A security system for SRAM chips

Abstract

The present invention relates to a safety system for SRAM chips, which belongs to the field of SRAM memory technology, and solves the problem that the prior art cannot accurately measure the aging degree of SRAM chips and cannot give a safety warning of the aging degree. The system includes: an imprinting force detection module, which is used to automatically detect the imprinting force of the SRAM chip to be tested after startup, judge whether its safety performance meets the standard, and output an imprinting over-threshold signal to a control module when it does not meet the standard; a control module, which is used to control the startup of the imprinting force detection module at a fixed time; and, according to the received imprinting over-threshold signal, automatically generate matching verification information to the host, and judge whether the verification is successful according to the reply information of the host; if successful, reject all erase instructions to the SRAM issued by the host after the verification; if failed, use the electric energy provided by the parasitic power module to erase the storage information of the SRAM chip; the parasitic power module is used to provide electric energy for the above-mentioned erasing operation of the control module.

Description

Technical Field

[0001] The present invention relates to the technical field of SRAM memory, and in particular to a security system for SRAM chips. Background Art

[0002] At present, the existing security systems for SRAM chips are only designed for data residue. When the anti-attack detection and control circuit detects a threat, it will erase or rewrite the data in the SRAM chip. However, the circuit structure of the security system is relatively complex, with many control signals, and the use of a self-built power supply leads to high surface cost and power consumption. At the same time, it is not possible to detect the threat posed by aging to the security of SRAM.

[0003] In order to protect data security, the existing security system for SRAM chips will cut off the power supply of the SRAM chip once unauthorized illegal access is detected to prevent attackers from stealing data. However, SRAM chips have the problem of information residue. The reason is that the two symmetrical MOS tubes in the storage array will experience different degrees of aging effects, resulting in permanent threshold voltage mismatch, resulting in a certain probability (about 10% to 20%) of reading the power-on initial value opposite to the original storage value after the storage unit is powered on. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a safety system for an SRAM chip, so as to solve the problem that the prior art cannot accurately measure the aging degree of the SRAM chip and cannot provide a safety warning of the aging degree.

[0005] On the one hand, an embodiment of the present invention provides a security system for an SRAM chip, comprising an imprint force detection module, a control module, and a parasitic power supply module connected in sequence;

[0006] The stamping force detection module is used to automatically detect the stamping force of the SRAM chip to be tested after startup to determine whether its safety performance meets the standard. If it does not meet the standard, it outputs a stamping over-threshold signal to the control module;

[0007] A control module is used to control the start of the imprint force detection module at a fixed time; and automatically generate matching verification information to the host according to the received imprint over-threshold signal, and judge whether the verification is successful according to the reply information of the host; if successful, reject all erase instructions of the SRAM chip issued by the host after the verification; if failed, use the power provided by the parasitic power module to erase the storage information of the SRAM chip;

[0008] The parasitic power module is used to provide power for the above-mentioned erasing operation of the control module.

[0009] The beneficial effects of the above technical solution are as follows: a system is proposed to judge the safety performance of the SRAM chip by quantitatively detecting the stamping force of the SRAM chip, and then automatically erase the data when the safety performance of the SRAM chip does not meet the standard. The use of this system no longer requires comparing the blurriness of the picture to judge the aging condition by naked eyes, which solves the problem that the aging stamping force is difficult to quantitatively evaluate. The use of a parasitic power module can save the design area of ​​the system circuit board, and at the same time, it can still perform unfinished erase operations after the system is powered off, thereby improving system safety, reducing system power consumption, and extending the use time. The results have been verified by a large number of experiments and are credible.

[0010] Based on the further improvement of the above system, the control module further comprises:

[0011] The enabling submodule is used to control the start of the imprint force detection module at a timing; and, receives the imprint over-threshold signal sent by the imprint force detection module, forwards it to the handshake submodule, and analyzes the reply information fed back by the handshake submodule. If the matching check succeeds, all erase instructions for the SRAM chip sent by the host after the check are rejected. If the matching check fails, an erase signal is sent to the erase submodule;

[0012] The handshake submodule is used to start the handshake with the host after receiving the imprinting over-threshold signal sent by the enabling submodule, automatically generate matching verification information to the host according to the effective value of the imprinting over-threshold signal; and receive the reply information fed back by the host and forward it to the enabling submodule;

[0013] The erasing submodule is used to perform data erasing operation on the SRAM using the electric energy provided by the parasitic power module after receiving the erasing signal.

[0014] The beneficial effect of the above further improvement scheme is: by enabling the submodule to control the startup of the stamping force detection module, the power consumption of the system in standby mode is reduced. At the same time, a handshake module is introduced, which can determine whether the SRAM chip is in a dangerous environment by requesting a handshake. If the use environment is credible, unnecessary erase operations can be excluded under the premise that the stamping force exceeds the standard, saving operating costs.

[0015] Furthermore, the stamping force detection module further includes:

[0016] The pre-processing submodule is used to export and format the existing data in the SRAM chip to be tested;

[0017] The test submodule is used to power on the formatted SRAM chip and initialize the back gate voltage of its storage array to obtain the first power-on initial value after initialization; and write unified data to the SRAM chip, and then re-power on the SRAM chip to obtain the second power-on initial value after re-powering on; repeat the above process to obtain the first power-on initial value and the second power-on initial value after multiple power-ons; input the first power-on initial value and the second power-on initial value after multiple power-ons into the aging imprint force model to obtain the aging imprint force of the SRAM chip, and output it to the output module;

[0018] The output module is used to judge whether the safety performance of the SRAM chip to be tested meets the standard according to the above-mentioned aging stamping force, and output a stamping over-threshold signal to the control module if it does not meet the standard.

[0019] The beneficial effect of the above further improvement scheme is that the aging imprint strength of the SRAM chip to be tested can be quantitatively determined through a specific aging imprint model, and the current aging state of the SRAM chip to be tested can be analyzed more accurately, thereby making the output imprint over-threshold signal more credible.

[0020] The beneficial effects of the above further improvement scheme are: it solves the problem of single variable when testing SRAM chip aging in the prior art, and at the same time, through the test measurement data and the customized aging imprint force model, it is no longer necessary to judge the aging condition by comparing the blurriness of the picture with the naked eye, which solves the problem that the aging imprint force is difficult to quantitatively evaluate. By comparing the anti-aging imprint ability of the SRAM chip to be tested in multiple tests, while taking into account the influencing factors of multiple variables such as back gate and irradiation, the final evaluation results of whether the safety performance of the SRAM chip to be tested meets the standards are more comprehensive and reliable. The above method can be directly applied to SRAM chips that have been put into use, quantitatively analyze whether their safety performance meets the standards, and evaluate whether the corresponding security system has security vulnerabilities. After a large number of experimental verifications, the results are credible.

[0021] Further, the unified data is all 0 or all 1; and the power-on at least includes:

[0022] The NMOS transistor is negatively biased and the PMOS transistor is negatively biased once;

[0023] The NMOS transistor is negatively biased and the PMOS transistor is forward biased once;

[0024] The NMOS transistor is zero biased and the PMOS transistor is zero biased once;

[0025] The NMOS transistor is forward biased and the PMOS transistor is negatively biased once;

[0026] And, the NMOS transistor is forward biased once and the PMOS transistor is forward biased once.

[0027] The beneficial effect of the above further improved scheme is: by setting multiple groups of back gate bias conditions, all bias conditions of NMOS transistors and PMOS transistors are taken into account at the same time to determine the worst back gate bias condition for aging stamping, making the aging stamping result more comprehensive and accurate, laying the foundation for accurate erasure later.

[0028] Further, the test submodule performs the following steps to obtain the first power-on initial value after initialization:

[0029] Power on the SRAM chip;

[0030] The back gate voltages of all NMOS transistors and PMOS transistors in the memory array of the SRAM chip are set to 0V, and the number and ratio of 1s and 0s in the memory cells after initialization are counted;

[0031] Repeat the above process n times, calculate Rate1 according to the following formula, and use Rate1 as the first power-on initial value after initialization;

[0032]

[0033] Where N 1i is the number of cells with storage cells set to 1 in the i-th test, N 0i is the number of cells with storage cells set to 0 in the i-th test, n is the number of repeated power-on initialization times, and n≥3.

[0034] The beneficial effects of the above further improved solution are: controlling the back gate voltage of all NMOS transistors and PMOS transistors in the storage array of the SRAM chip to eliminate the interference caused by voltage fluctuations, and repeatedly counting the initial power-on value to reduce the impact of strong jitter nodes.

[0035] Further, the test submodule performs the following steps to obtain a second power-on initial value after powering on again:

[0036] After initialization is completed, all 0s or all 1s are written to the SRAM chip and maintained for a predetermined time in a preset irradiation environment;

[0037] Re-power on the SRAM chip and count the second power-on initial value after the power-on;

[0038] The above process is repeated to obtain the second power-on initial value after power-on again under various irradiation environments.

[0039] The beneficial effects of the above further improvement scheme are: introducing the radiation factor, considering the influence of multiple variables on the aging stamping, making the aging stamping result more comprehensive and accurate, and solving the problem of single variable when testing the aging of SRAM chips in the prior art.

[0040] Furthermore, the aging imprint force model is:

[0041]

[0042] Where Φ() is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the first power-on initial value after initialization, Ratio3 is the ratio of 1 to 0 in the second power-on initial value, σ noise is the noise impact factor, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth test j , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

[0043] The beneficial effect of the above further improvement scheme is: the aging imprint force is calculated by the above aging imprint force model, which comprehensively considers multiple variables such as back gate voltage, radiation dose, power-on initial value and noise, so that the obtained aging imprint force result is more complete and reliable.

[0044] Further, the output submodule performs the following steps to determine whether the safety performance of the SRAM chip meets the standards:

[0045] The aging stamping force F of the SRAM chip tested n times under the same radiation environment j The average is taken as the aging imprint strength of the SRAM chip in the corresponding radiation environment;

[0046] According to the aging imprint strength of the SRAM chip under different radiation environments, the final aging imprint strength F of the SRAM chip is obtained. total ;

[0047] If the final aging stamping force F total If the test result is within the preset range, the test result indicating that the safety performance of the SRAM chip meets the standard is output; if the test result is not within the preset range, an over-threshold signal is output to the control module.

[0048] The beneficial effect of the above further improvement scheme is: selecting the aging imprint strength of M groups of SRAM chips as the final aging imprint strength evaluation index improves the credibility of the evaluation result and can eliminate the interference of accidental situations.

[0049] Furthermore, the F total Obtained by the following formula

[0050]

[0051] Where M is the number of radiation environment types.

[0052] The beneficial effect of the above further improvement scheme is: the final aging imprint strength evaluation index of the SRAM chip is calculated in an average manner, which simplifies the calculation process and saves computing resources while ensuring the credibility of the data.

[0053] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0055] Figure 1 This is a schematic diagram of the composition of a security system for an SRAM chip according to Embodiment 1 of the present invention;

[0056] Figure 2 Schematic diagram of the composition of the security system for SRAM chip according to Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0057] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0058] Example 1

[0059] A specific embodiment of the present invention discloses a security system for SRAM chips, such as Figure 1 As shown, it includes an imprint force detection module, a control module, and a parasitic power supply module.

[0060] Among them, the detection end of the imprint force detection module is connected to the SRAM chip, the control end is connected to the output end 1 of the control module, and the output end is connected to the input end of the control module; the output end 2 of the control module is connected to the host, the output end 3 is connected to the control end of the parasitic power supply module, and the power supply end is connected to the output end of the parasitic power supply module.

[0061] The imprint force detection module is used to automatically detect the imprint force of the SRAM chip to be tested after startup, determine whether its safety performance meets the standard, and output an imprint over-threshold signal to the control module if it does not meet the standard.

[0062] The control module is used to control the start of the imprint force detection module at a fixed time; and automatically generate matching verification information to the host according to the received imprint over-threshold signal, and judge whether the verification is successful according to the reply information of the host; if successful, reject all erase instructions to the SRAM chip issued by the host after the verification; if failed, use the power provided by the parasitic power module to erase the storage information of the SRAM chip.

[0063] The parasitic power module is used to provide power for the above-mentioned erasing operation of the control module.

[0064] During implementation, the imprinting force of the SRAM chip to be tested is regularly detected by the imprinting force detection module, and the obtained imprinting force is compared with the upper and lower limits of the preset range; when the imprinting force is within the preset range, it is determined that the safety performance of the SRAM chip to be tested meets the standard, and the result of the SRAM to be tested meeting the standard is pushed to the user; when the imprinting force exceeds the preset range, it is determined that the safety performance of the SRAM chip to be tested does not meet the standard, and the imprinting over-threshold signal is transmitted to the host through handshake, and the user determines on the host whether the SRAM chip to be tested is in a dangerous environment. If the use environment is credible, unnecessary erasing operations can be excluded under the premise that the imprinting force exceeds the standard, that is, if the verification is successful, no erasure is performed, otherwise, erasure is performed, thereby repeatedly saving operation time and cost.

[0065] Compared with the prior art, the security system provided by this embodiment automatically erases the data in the SRAM chip after detecting that the SRAM chip to be tested has been used for too long and its safety has been reduced, thereby improving the safety of the SRAM chip. The use of this system no longer requires judging the aging condition by comparing the blurriness of the picture with the naked eye, thus solving the problem that it is difficult to quantitatively evaluate the aging stamping force. The use of a parasitic power module can save the design area of ​​the system circuit board, and at the same time, it can still perform unfinished erase operations after the system is powered off, thereby improving system safety, reducing system power consumption, and extending the use time. The results have been verified by a large number of experiments and are credible.

[0066] Example 2

[0067] Based on the optimization of Example 1, the control module includes an enabling submodule, a handshake submodule, and an erasing submodule that are further connected, such as Figure 2 shown.

[0068] The enabling submodule is used to control the start-up of the imprint force detection module at a timing; and to receive the imprint over-threshold signal sent by the imprint force detection module, and forward it to the handshake submodule, and analyze the reply information fed back by the handshake submodule. If the matching verification is successful, all erase instructions for the SRAM chip sent by the host after the verification are rejected. If the matching verification fails, an erase signal is sent to the erase submodule.

[0069] The handshake submodule is used to start the handshake with the host after receiving the imprinting over-threshold signal sent by the enabling submodule, and automatically generate specific matching verification information to the host according to the effective value of the imprinting over-threshold signal; and receive the reply information fed back by the host and forward it to the enabling submodule.

[0070] The effective value of the over-threshold signal λ = the peak value of the over-threshold signal /

[0071] The specific matching verification information generated according to the effective value includes: the ratio α of the effective amplitude λ of the over-threshold signal and the threshold (preset range upper limit) λ0, and the ratio β of the effective amplitude λ of the over-threshold signal and the threshold (preset range lower limit) λ0′

[0072]

[0073] Only when α≤1 and β≥1 are satisfied at the same time, it means that the safety performance of the SRAM chip meets the standard, and the host feedbacks the matching verification success information.

[0074] Otherwise, when α is greater than 1, the larger it is, the worse the security performance of the SRAM chip is, and the greater the probability of host feedback matching verification failure. When β is less than 1, the smaller it is, the worse the security performance of the SRAM chip is, and the greater the probability of host feedback matching verification failure.

[0075] It is worth noting that the smaller the effective value of the imprinted super-threshold signal, the higher the probability of successful matching verification; conversely, the larger the effective value of the imprinted super-threshold signal, the lower the probability of successful matching.

[0076] The erasing submodule is used to perform data erasing operation on the SRAM chip using the power provided by the parasitic power module after receiving the erasing signal. The parasitic power module is used to supply power to the erasing submodule.

[0077] Preferably, the security system is connected to an SRAM storage cell array with suitable capacity. When the number of storage cells in the storage array that have been affected by data imprinting and data changes due to long-term use of the SRAM chip or other circumstances accumulates to a certain extent, the imprint force detection module outputs a signal.

[0078] Preferably, the control module also includes a charging control submodule. No control enable signal is required, and the parasitic power module is automatically charged as long as the output voltage of the parasitic power module is detected to be at a high level. After the power supply voltage of the detection system is powered off, the erasing submodule can continue to be powered to avoid the failure of data erasure due to insufficient power supply.

[0079] The charging control submodule is used to periodically detect the output level of the parasitic power module, and automatically charge the parasitic power module if the output level is high.

[0080] Preferably, the stamping force detection module performs the following steps to detect the stamping force of the SRAM chip and determine whether its safety performance meets the standard:

[0081] S1. The existing data in the SRAM chip to be tested is exported and formatted, the formatted SRAM chip is powered on, and the back gate voltage of the storage array is initialized to obtain the first power-on initial value after initialization;

[0082] S2. Write unified data to the SRAM chip, then re-power on the SRAM chip, and count the second power-on initial value after re-powering on; specifically, the unified data is all 0 or all 1;

[0083] S3. Repeat the above process to obtain the first power-on initial value and the second power-on initial value after multiple power-ons;

[0084] S4. Input the first power-on initial value and the second power-on initial value after multiple power-ons into the aging imprint force model to obtain the aging imprint force of the SRAM chip.

[0085] S5. Based on the above aging stamping force, output the test result of whether the safety performance of the SRAM chip meets the standard.

[0086] Correspondingly, the imprint force detection module further includes a preprocessing submodule, a testing submodule, and an output module which are connected in sequence.

[0087] The pre-processing submodule is used to export the existing data in the SRAM chip to be tested to the spare storage module and then format it.

[0088] The test submodule is used to power on the formatted SRAM chip and initialize the back gate voltage of its storage array to obtain the first power-on initial value after initialization; and write unified data to the SRAM chip, and then re-power on the SRAM chip to count the second power-on initial value after re-powering on; repeat the above process to obtain the first power-on initial value and the second power-on initial value after multiple power-ons; input the first power-on initial value and the second power-on initial value after multiple power-ons into the aging imprint force model to obtain the aging imprint force of the SRAM chip to be tested; and output to the output module.

[0089] The output module is used to judge whether the safety performance of the SRAM chip to be tested meets the standard according to the above-mentioned aging stamping force, and output a stamping over-threshold signal to the control module if it does not meet the standard.

[0090] Preferably, the power-on includes at least the following five times: the NMOS transistor is negatively biased and the PMOS transistor is negatively biased once; the NMOS transistor is negatively biased and the PMOS transistor is positively biased once; the NMOS transistor is zero biased and the PMOS transistor is zero biased once; the NMOS transistor is forward biased and the PMOS transistor is negatively biased once; the NMOS transistor is forward biased and the PMOS transistor is forward biased once.

[0091] Preferably, the test submodule performs the following steps to obtain the first power-on initial value after initialization:

[0092] S11. Export the existing data in the SRAM chip and format it, and power on the formatted SRAM chip;

[0093] S12. The back gate voltages of all NMOS transistors and PMOS transistors in the memory array of the SRAM chip are set to 0V, and the number and ratio of 1 and 0 in the memory cell after initialization are counted;

[0094] S13. Repeat the above process n times, calculate Rate1 according to the following formula, and use Rate1 as the first power-on initial value after initialization

[0095]

[0096] Where N 1i is the number of cells with storage cells set to 1 in the i-th test, N 0i is the number of cells with storage cells set to 0 in the i-th test, n is the number of repeated power-on initialization times, and n≥3.

[0097] The test submodule performs the following steps to obtain the second power-on initial value after power-on again:

[0098] S21. After initialization is completed, write all 0s or all 1s to the SRAM chip and keep it in the preset irradiation environment for a predetermined time;

[0099] S22. Re-power on the SRAM chip and count the second power-on initial value after re-powering on;

[0100] S23. Repeat the above process to obtain the second power-on initial value after re-powering on in multiple radiation environments. That is, multiple power-ons also include power-ons in different radiation environments. If there are M radiation environments, the number of tests is M×n times.

[0101] Preferably, the aging imprint force model is

[0102]

[0103] Where Φ() is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the first power-on initial value, Ratio3 is the ratio of 1 to 0 in the second power-on initial value, and σ noise is the noise impact factor, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth test j , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

[0104] Preferably, the output submodule performs the following steps to determine whether the safety performance of the SRAM chip meets the standards:

[0105] S31. The aging stamping force F of the SRAM chip tested n times under the same radiation environment j The average is taken as the aging imprint strength of the SRAM chip in the corresponding radiation environment;

[0106] S32. Obtain the final aging stamping force F of the SRAM chip according to the aging stamping force of the SRAM chip under different radiation environments total ;

[0107] S33. According to the final aging stamping force F total Determine whether the safety performance of the SRAM chip meets the standard. If the final aging stamping force F total If the test result is within the preset range, the test result indicating that the safety performance of the SRAM chip meets the standard is output; otherwise, the test result indicating that the safety performance of the SRAM chip does not meet the standard is output.

[0108] The F total Obtained by the following formula

[0109]

[0110] Where M is the number of radiation environment types.

[0111] Compared with Example 1, the system provided in this embodiment takes into account the time, back gate voltage and total dose effects at the same time, can test the aging imprint strength of the SRAM chip more comprehensively, and analyze from multiple angles which factors will affect the aging imprint strength; the method of writing all "0" or all "1" is used to count the changes in the data of the SRAM after aging imprinting, which can quantitatively analyze the aging imprint strength and facilitate subsequent erasure processing.

[0112] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0113] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A security system for an SRAM chip, characterized in that: include: The stamping force detection module is used to automatically detect the stamping force of the SRAM chip to be tested after startup to determine whether its safety performance meets the standard. If it does not meet the standard, it outputs a stamping over-threshold signal to the control module; A control module is used to control the start of the imprint force detection module at a fixed time; and automatically generate matching verification information to the host according to the received imprint over-threshold signal, and judge whether the verification is successful according to the reply information of the host; if successful, reject all erase instructions issued by the host to the SRAM chip after the verification; If it fails, the stored information of the SRAM chip is erased using the power provided by the parasitic power module; A parasitic power module, used for providing power for the above-mentioned erasing operation of the control module; The control module further comprises: The enabling submodule is used to control the start of the imprint force detection module at a timing; and, receives the imprint over-threshold signal sent by the imprint force detection module, forwards it to the handshake submodule, and analyzes the reply information fed back by the handshake submodule. If the matching check succeeds, all erase instructions for the SRAM chip sent by the host after the check are rejected. If the matching check fails, an erase signal is sent to the erase submodule; The handshake submodule is used to start the handshake with the host after receiving the imprinting over-threshold signal sent by the enabling submodule, automatically generate matching verification information to the host according to the effective value of the imprinting over-threshold signal; and receive the reply information fed back by the host and forward it to the enabling submodule; The erasing submodule is used to perform data erasing operation on the SRAM using the electric energy provided by the parasitic power module after receiving the erasing signal.

2. The security system for SRAM chip according to claim 1, characterized in that: The control module further includes a charging control submodule; The charging control submodule is used to start according to the control timing of the enabling module, detect the output level of the parasitic power module, and automatically charge the parasitic power module if the output level is high.

3. The security system for SRAM chip according to claim 2, characterized in that: The stamping force detection module further includes: The pre-processing submodule is used to export and format the existing data in the SRAM chip to be tested; The test submodule is used to power on the formatted SRAM chip and initialize the back gate voltage of its storage array to obtain the first power-on initial value after initialization; And, writing unified data into the SRAM chip, and then re-powering on the SRAM chip to obtain a second power-on initial value after re-powering on; Repeat the above process to obtain the first power-on initial value and the second power-on initial value after multiple power-ons; input the first power-on initial value and the second power-on initial value after multiple power-ons into the aging imprint force model to obtain the aging imprint force of the SRAM chip; Output to output module; The output module is used to judge whether the safety performance of the SRAM chip to be tested meets the standard according to the above-mentioned aging stamping force, and output a stamping over-threshold signal to the control module if it does not meet the standard.

4. The security system for SRAM chip according to claim 3, characterized in that: The unified data is all 0 or all 1; Furthermore, the powering on at least includes: The NMOS transistor is negatively biased and the PMOS transistor is negatively biased once; The NMOS transistor is negatively biased and the PMOS transistor is forward biased once; The NMOS transistor is zero biased and the PMOS transistor is zero biased once; The NMOS transistor is forward biased and the PMOS transistor is negatively biased once; And, the NMOS transistor is forward biased once and the PMOS transistor is forward biased once.

5. The security system for SRAM chip according to claim 4, characterized in that: The test submodule performs the following steps to obtain the first power-on initial value after initialization: Power on the SRAM chip; The back gate voltages of all NMOS transistors and PMOS transistors in the memory array of the SRAM chip are set to 0V, and the number and ratio of 1s and 0s in the memory cells after initialization are counted; Repeat the above process n times, calculate Rate1 according to the following formula, and use Rate1 as the first power-on initial value after initialization; Where N 1i is the number of storage units that are 1 in the i-th test, N 0i is the number of storage cells that are 0 in the i-th test, and n is the number of repeated power-on initialization times.

6. The security system for SRAM chip according to claim 5, characterized in that: The test submodule performs the following steps to obtain a second power-on initial value after powering on again: After initialization is completed, all 0s or all 1s are written to the SRAM chip and maintained for a predetermined time in a preset irradiation environment; Re-power on the SRAM chip and count the second power-on initial value after the power-on; The above process is repeated to obtain the second power-on initial value after power-on again under various irradiation environments.

7. The security system for SRAM chip according to claim 6, characterized in that: The aging imprint force model is: Where Φ( ) is the standard normal cumulative distribution function, Ratio1 is the ratio of 1 to 0 in the first power-on initial value after initialization, Ratio3 is the ratio of 1 to 0 in the second power-on initial value, σ noise is the noise impact factor, T is the scheduled time; F j represents the aging imprint strength F obtained in the jth test j , α is the radiation environment coefficient, dose is the radiation dose in the irradiation environment, V p 、V n They are the back gate voltages of the PMOS transistor and the NMOS transistor during the test.

8. The security system for SRAM chip according to claim 7, characterized in that: The output module performs the following steps to determine whether the safety performance of the SRAM chip meets the standards: The aging stamping force F of the SRAM chip tested n times under the same radiation environment j The average is taken as the aging imprint strength of the SRAM chip in the corresponding radiation environment; According to the aging imprint strength of the SRAM chip under different radiation environments, the final aging imprint strength F of the SRAM chip is obtained. total ; If the final aging stamping force F total If the test result is within the preset range, the test result indicating that the safety performance of the SRAM chip meets the standard is output; if the test result is not within the preset range, an over-threshold signal is output to the control module.

9. The security system for SRAM chip according to claim 8, characterized in that: The F total Obtained by the following formula Where M is the number of radiation environment types.

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