Deep Learning-Based Program-Verification Modeling and Voltage Estimation for Memory Devices

Abstract

The present disclosure describes an apparatus, system, and method for improving the performance of a memory device. An exemplary method includes: obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device; generating at least one 1 count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages based on the plurality of cell counts and the plurality of read voltages; determining an updated value for the at least one read voltage based on an output of a deep neural network, the input of the deep neural network including the at least one 1 count, the at least one checksum, and the plurality of samples; and applying the updated value for the at least one read voltage to the memory device to retrieve information from the memory device.

Description

Technical Field

[0001] This patent document relates generally to memory devices and, more particularly, to robustness and reliable access in memory devices. Background Art

[0002] Data integrity is crucial for data storage and data transmission. In solid-state memory devices (e.g., NAND flash memory), information is stored within cells using varying charge levels within the cells. During write and read operations, program disturb errors and inter-cell charge leakage cause voltage distribution and levels to degrade over time, introducing noise. Generating accurate read voltages improves the reliability and lifespan of memory devices. Summary of the Invention

[0003] Embodiments of the disclosed technology relate to using a deep neural network to estimate read voltage thresholds during operation of a memory device, which improves the performance of the memory device. These and other features and benefits are achieved, at least in part, by using a 1s count, a checksum, and samples from a skewed normal distribution as inputs to the deep neural network.

[0004] In an exemplary aspect, a method for improving performance of a memory device is described. The method includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device; generating at least one 1-count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages based on the plurality of cell counts and the plurality of read voltages; determining an updated value for the at least one read voltage based on an output of a deep neural network (DNN), wherein inputs to the DNN include the at least one 1-count, the at least one checksum, and the plurality of samples; and applying the updated value for the at least one read voltage to the memory device to retrieve information from the memory device.

[0005] In another exemplary aspect, the above method may be implemented by a video encoder device or a video decoder device including a processor.

[0006] In another exemplary aspect, the methods may be implemented in the form of processor-executable instructions and stored on a computer-readable program medium.

[0007] The subject matter described in this patent document can be implemented in a specific way that provides one or more of the following features. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 An example of a memory system is shown.

[0009] Figure 2is a diagram of an exemplary nonvolatile memory device.

[0010] Figure 3 is an exemplary diagram illustrating a cell voltage level distribution (Vth) of a nonvolatile memory device.

[0011] Figure 4 is another exemplary diagram illustrating a cell voltage level distribution (Vth) of a nonvolatile memory device.

[0012] Figure 5 is an exemplary diagram illustrating cell voltage level distribution (Vth) of a nonvolatile memory device before and after program disturbance.

[0013] Figure 6 is an exemplary diagram illustrating a cell voltage level distribution (Vth) of a nonvolatile memory device as a function of a reference voltage.

[0014] Figure 7 The operation of an exemplary eBoost algorithm for read voltage estimation in a non-volatile memory device is shown.

[0015] Figure 8A and Figure 8B is a block diagram illustrating an exemplary deep neural network (DNN) configured in training mode and inference mode, respectively.

[0016] Figure 9 is a block diagram illustrating an exemplary architecture of a DNN.

[0017] Figure 10 Exemplary operation and analysis of a DNN are shown.

[0018] Figure 11 A flow chart illustrating an exemplary method for improving performance of a memory device. DETAILED DESCRIPTION

[0019] Semiconductor memory devices can be either volatile or nonvolatile. Volatile semiconductor memory devices perform read and write operations at high speeds, but the stored content may be lost when power is removed. Nonvolatile semiconductor memory devices retain their stored content even when power is removed. Nonvolatile semiconductor memory devices are used to store content that must be retained regardless of power supply.

[0020] As demand for high-capacity memory devices increases, multi-level cell (MLC) or multi-bit memory devices that store multiple bits of data per cell are becoming increasingly common. However, memory cells in MLC non-volatile memory devices must have threshold voltages corresponding to four or more distinguishable data states within a limited voltage window. To improve data integrity in non-volatile memory devices, the level and distribution of the read voltages used to distinguish data states must be adjusted throughout the life of the memory device to maintain optimal values during read operations and / or read attempts.

[0021] Figures 1 to 6 A non-volatile memory system (eg, flash-based memory, NAND flash) in which embodiments of the disclosed technology may be implemented is outlined.

[0022] Figure 1 1 is a block diagram of an example of a memory system 100 that can be used to implement some embodiments of the disclosed technology. Memory system 100 includes a memory module 110 that can be used to store information for use by other electronic devices or systems. Memory system 100 can be incorporated into other electronic devices and systems (e.g., located on a circuit board). Alternatively, memory system 100 can be implemented as an external storage device such as a USB flash drive and a solid-state drive (SSD).

[0023] The memory module 110 included in the memory system 100 may include memory regions (e.g., memory arrays) 102, 104, 106, and 108. Each of the memory regions 102, 104, 106, and 108 may be included in a single memory die or in multiple memory dies. The memory dies may be included in an integrated circuit (IC) chip.

[0024] Each of the memory regions 102, 104, 106, and 108 includes a plurality of memory cells. A read operation, a program operation, or an erase operation can be performed based on a group of memory cells. Thus, each memory cell group can include a predetermined number of memory cells. The memory cells in the memory regions 102, 104, 106, and 108 can be included in a single memory die or in multiple memory dies.

[0025] The memory cells in each of the memory regions 102, 104, 106, and 108 can be arranged in rows and columns in memory cell groups. Each memory cell group can be a physical cell group. For example, a group of multiple memory cells can form a memory cell group. Each memory cell group can also be a logical cell group. For example, a memory cell group can be a block or a page, each of which can be identified by a unique address such as a block address or a page address. For another example, where the memory regions 102, 104, 106, and 108 can include a computer memory that includes a repository as a logical unit of data storage, the memory cell group can be a repository that can be identified by a repository address. During a read operation or a write operation, a unique address associated with a particular memory cell group can be used to access the particular memory cell group. Based on the unique address, information can be written to or retrieved from one or more memory cells in the particular memory cell group.

[0026] The memory cells in memory regions 102, 104, 106, and 108 may include nonvolatile memory cells. Examples of nonvolatile memory cells include flash memory cells, phase-change random access memory (PRAM) cells, magnetoresistive random access memory (MRAM) cells, or other types of nonvolatile memory cells. In an exemplary embodiment where the memory cells are configured as NAND flash memory cells, read operations or write operations may be performed on a page basis. However, erase operations in NAND flash memory are performed on a block basis.

[0027] Each of the non-volatile memory cells may be configured as a single-level cell (SLC) or a multi-level memory cell. A single-level cell may store one bit of information per cell. A multi-level memory cell may store more than one bit of information per cell. For example, each memory cell in the memory regions 102, 104, 106, and 108 may be configured as a multi-level cell (MLC) storing two bits of information per cell, a triple-level cell (TLC) storing three bits of information per cell, or a quad-level cell (QLC) storing four bits of information per cell. In another example, each memory cell in the memory regions 102, 104, 106, and 108 may be configured to store at least one bit of information (e.g., one bit of information or multiple bits of information), and each memory cell in the memory regions 102, 104, 106, and 108 may be configured to store more than one bit of information.

[0028] like Figure 1As shown, memory system 100 includes a controller module 120. Controller module 120 includes a memory interface 121 for communicating with memory module 110; a host interface 126 for communicating with a host (not shown); a processor 124 for executing firmware layer code; and a cache 123 and a memory 122 for temporarily or permanently storing executable firmware / instructions and associated information, respectively. In some embodiments, controller module 120 may include an error correction engine 125 to perform error correction operations on information stored in memory module 110. Error correction engine 125 may be configured to detect / correct single-bit errors or multiple-bit errors. In another embodiment, error correction engine 125 may be located within memory module 110.

[0029] The host may be a device or system including one or more processors that operate to retrieve data from the memory system 100 or store or write data to the memory system 100. In some embodiments, examples of hosts may include personal computers (PCs), portable digital devices, digital cameras, digital multimedia players, televisions, and wireless communication devices.

[0030] In some embodiments, the controller module 120 may further include a host interface 126 for communicating with a host. The host interface 126 may include a component that complies with at least one of the host interface specifications, including but not limited to Serial Advanced Technology Attachment (SATA), Serial Small Computer System Interface (SAS), and Peripheral Component Interconnect Express (PCIe).

[0031] Figure 2 An example of a memory cell array is shown that can be used to implement at least some embodiments of the disclosed technology.

[0032] In some embodiments, the memory cell array may include a NAND flash memory array that is divided into a number of blocks, each block including a number of pages, each block including a plurality of memory cell strings, and each memory cell string including a plurality of memory cells.

[0033] In some embodiments where the memory cell array is a NAND flash memory array, read operations and write (program) operations are performed on a page basis, and erase operations are performed on a block basis. All memory cells within the same block must be erased simultaneously before a programming operation can be performed on any page included in the block. In an embodiment, the NAND flash memory can use an even / odd bit line structure. In another embodiment, the NAND flash memory can use an all-bit line structure. In the even / odd bit line structure, even bit lines and odd bit lines are interleaved along each word line and are accessed alternately so that each pair of even bit lines and odd bit lines can share peripheral circuits such as page buffers. In the all-bit line structure, all bit lines are accessed simultaneously.

[0034] Figure 3 An example of a threshold voltage distribution curve in a multi-level cell device is shown, where the number of cells in each programmed / erased state is plotted as a function of threshold voltage. Figure 3 As shown, the threshold voltage distribution curve includes an erased state (denoted as "ER" and corresponding to "11") having the lowest threshold voltage, and three programmed states (denoted as "P1," "P2," and "P3," corresponding to "01," "00," and "10," respectively) with read voltages between the states (denoted by dashed lines). In some embodiments, due to differences in the material properties of the memory array, each of the threshold voltage distributions for the programmed / erased states has a finite width.

[0035] although Figure 3 A multi-level cell device is shown by way of example, but each of the memory cells can be configured to store any number of bits per cell. In some embodiments, each of the memory cells can be configured as a single-level cell (SLC) storing one bit of information per cell, or as a triple-level cell (TLC) storing three bits of information per cell, or as a quad-level cell (QLC) storing four bits of information per cell.

[0036] When writing more than one data bit to a memory cell, the distance between adjacent distributions decreases, requiring careful placement of the threshold voltage levels of the memory cells. This is achieved by using incremental step pulse programming (ISPP), a programming and verification method that applies stepped programming voltages to the word line, repeatedly programming the memory cells on the same word line. Each programmed state is associated with a verification voltage used in the verification operation, setting the target position of each threshold voltage distribution window.

[0037] Threshold voltage distribution distortion or overlap may cause read errors. The ideal memory cell threshold voltage distribution may be severely distorted or overlapped due to, for example, program and erase (P / E) cycles, inter-cell interference, and data retention errors (which will be discussed below), and in most cases, these read errors can be managed by using error correction code (ECC).

[0038] Figure 4 Shown are an example of an ideal threshold voltage distribution curve 410 and an example of a distorted threshold voltage distribution curve 420. The vertical axis represents the number of memory cells having a particular threshold voltage represented on the horizontal axis.

[0039] For n-bit multi-level cell NAND flash memory, the threshold voltage of each cell can be programmed to 2 n In an ideal multi-level cell NAND flash memory, each value corresponds to a non-overlapping threshold voltage window.

[0040] Flash memory P / E cycles damage the tunnel oxide of the floating gate of the charge-trapping layer of the cell transistor, causing threshold voltage shifts and gradually reducing the noise margin of the memory device. As P / E cycles increase, the margin between adjacent distributions of different programming states decreases, and eventually the distributions begin to overlap. Data bits stored in memory cells whose threshold voltages are programmed into the overlapping range of adjacent distributions may be misinterpreted as values different from the original target value.

[0041] Figure 5 An example of inter-cell interference in NAND flash memory is shown. Inter-cell interference can also cause distortion of the threshold voltage of flash memory cells. The threshold voltage shift of one memory cell transistor can affect the threshold voltage of its adjacent memory cell transistor through the parasitic capacitance coupling effect between the interfering cell and the victim cell. The amount of inter-cell interference may be affected by the bit line structure of the NAND flash memory. In the even / odd bit line structure, the memory cells on a word line are alternately connected to even and odd bit lines, and in the same word line, even cells are programmed before odd cells. Therefore, even cells and odd cells are subject to different degrees of inter-cell interference. Cells in the all-bit line structure are subject to less inter-cell interference than even cells in the even / odd bit line structure, and the all-bit line structure can effectively support high-speed current sensing to improve memory read and verification speeds.

[0042] Figure 5 The dashed line in represents the nominal distribution of the P / E states (before program disturb) of the cell under consideration, and the "neighboring state value" represents the value to which the neighboring state has been programmed. Figure 5As shown, if the adjacent state is programmed to P1, the threshold voltage distribution of the cell under consideration shifts by a specific amount. However, if the adjacent state is programmed to P2, which has a higher threshold voltage than P1, this results in a larger shift than when the adjacent state is P1. Similarly, when the adjacent state is programmed to P3, the threshold voltage distribution shifts the most.

[0043] Figure 6 An example of retention errors in NAND flash memory is shown, comparing a normal threshold voltage distribution with a shifted threshold voltage distribution. Data stored in NAND flash memory tends to become corrupted over time, which is called a data retention error. Retention errors are caused by the loss of charge stored in the floating gate or charge trapping layer of the cell transistor. Memory cells with more program-erase cycles are more likely to experience retention errors due to wear and tear of the floating gate or charge trapping layer. Figure 6 In the example of , comparison of the voltage distribution of the top row (before damage) and the distribution of the bottom row (corrupted by hold errors) shows a leftward shift.

[0044] In NAND flash memory devices (e.g., Figures 1 to 6 (As shown in Figure 2), after receiving a read command, a series of data recovery steps are performed with the goal of retrieving noise-free data from the NAND flash memory. The first attempt is called a historical read, which uses the voltage (Vt) threshold used in the previous successful read. The previous successful read is a read in which the decoder successfully recovered noise-free data from the NAND flash memory. In a typical embodiment, a historical read is maintained separately for each physical block, and this historical read is updated if decoding fails and a different Vt is used in a subsequent step in the data recovery operation that results in a decoder success.

[0045] However, if a historical read fails, a historical read retry (HRR) operation is performed. An HRR operation involves a series of predetermined Vt thresholds that remain constant over time and do not vary with NAND conditions or the physical location of the data. Typically, 5 to 10 HRR operations (or read attempts) are performed before proceeding to the next step in the data recovery operation.

[0046] If all scheduled HRR read attempts fail, the data recovery operation will perform an eBoost process, which implements soft read and soft decode operations to attempt to retrieve the optimal value for the read voltage. In other words, the eBoost process will perform multiple reads to find the optimal center Vt for the soft read operation. The eBoost process can be based on one or more of the Gaussian model (GM) algorithm, the cumulative cell-count search (CCS) algorithm, or the advanced valley search (AVA) algorithm.

[0047] The GM algorithm assumes that each of the program-verify (PV) states (e.g., Figures 3 to 6 (shown) follows a Gaussian distribution with a known (or constant) variance and an unknown mean. It reads all the least significant bits (LSB), center significant bits (CSB), and most significant bits (MSB) pages on the same word line (WL) to obtain a pattern count, which enables the number of cells in each Vt interval between adjacent read thresholds to be determined. The mean of each PV state can then be determined by inverting the Q function, which is a tail distribution function of the standard normal distribution, and is defined as:

[0048]

[0049] like Figure 7 As shown, the GM algorithm uses two Gaussian distributions with means μ1 and μ2, and the Vt determined for the GM algorithm is the average of the two means of the two Gaussian distributions.

[0050] The CCS algorithm attempts to determine Vt so that the number of cells on either side of the selected Vt is equal. The AVA algorithm attempts to find the minimum point of the overall distribution in the valley between adjacent PV states. However, if Figure 7 As shown, these eBoost algorithms can lead to biased Vt estimates when one of the PV states is asymmetric, having a larger tail than the adjacent PV state.

[0051] The shortcomings of the GM, CCS, and AVA algorithms can be overcome by using a parameter framework for PV modeling and Vt estimation based on a deep neural network (DNN). This embodiment applies some additional reads and uses noisy measurements of cell counts from the additional reads to estimate model parameters, which are used to estimate the intersection points of adjacent PV states. However, this method is prone to loss of accuracy when the size (or complexity) of the DNN is limited, DNN pruning is applied, or the precision of the multiply-accumulate (MAC) operation is low. DNN pruning and low-precision MAC operations are often used to reduce the latency of Vt estimation. For example, DNN pruning can be applied to remove 50% of the DNN weights, which reduces latency but at the expense of accuracy.

[0052] Embodiments of the disclosed technology, among other features and advantages, improve the parametric framework of DNN-based PV modeling and Vt estimation methods by using additional information derived from additional reads, which advantageously improves the accuracy of Vt estimation without increasing latency or the number of MAC operations during the inference phase. In an example, the additional information includes 1 counts, e.g., the number of 1s on a particular page, and a checksum. That is, the DNN performs Vt estimation using the 1 counts, checksums, and noise samples from the cumulative distribution function (CDF) or inverse cumulative distribution function (ICDF) of the parametric model. Figure 7 In the example shown, the Vt to be estimated is labeled OPT.

[0053] In some embodiments, the underlying distribution is assumed to be a skewed normal distribution, defined by three parameters: location (ξ), size (ω), and shape (α). The cumulative distribution function (CDF) of the skewed normal distribution is:

[0054]

[0055] Here, Φ(x) is the CDF of a standard normal random variable, and T(h, a) is Owen's T function, which is defined as:

[0056]

[0057] Experimental results have verified the effectiveness of using the skewed normal distribution to model the PV state distribution in NAND memory devices.

[0058] Figure 8A 810 is a block diagram illustrating an exemplary DNN 810 configured in training mode. As shown, the input of the DNN 810 (in Figure 8AThe DNN 810 (denoted as "DNN1") includes a 1 count, a checksum, and a training data sample, and the output of the DNN 810 is the estimated read voltage threshold. The training data sample input to the DNN 810 is generated using a synthetic model 830 of the underlying distribution of PV states. Figure 8A As shown, the input of the synthetic model 830 includes probability distributions corresponding to four related PV distributions (denoted as p A 、p B 、p C 、p D ), and the output of the synthetic model 830 includes two samples, one of which is denoted as x and corresponds to the Vt used to read the corresponding PV distribution, and the other is denoted as CDF(x).

[0059] In some embodiments, the synthetic model is a skewed normal model (SNM), and the 1 count and checksum are provided for three reads. In other embodiments, the synthetic model is a modified Gaussian model (GM), and the 1 count and checksum are provided for two reads, wherein the modified GM includes a Gaussian distribution with an unknown mean and an unknown variance. In other embodiments, the synthetic model is a non-central T model (NCTM), and the 1 count and checksum are provided for four reads.

[0060] continue Figure 8A As described in the embodiment of the present invention, the DNN 810 configured in the training mode further includes the output of the DNN 810 being input to the loss function module 850, which also receives the parameter framework of the synthetic model. In the training mode, the loss function module 850 is configured to compare the estimated read voltage threshold output by the DNN 810 with the expected read voltage threshold based on the synthetic model, and feed back the difference (or error) to the DNN 810, which can then adjust its weights to ensure that the internal processing better conforms to the provided training data samples.

[0061] Figure 8B 810 is a block diagram illustrating an exemplary DNN 810 configured in inference mode. As shown, the inputs to the DNN 810 include x (Vt for reading PV) and CDF(x) of four PV distributions and 1 counts and checksums from three additional measurements. The DNN 810 is configured to use Figure 8A The invention also provides a method for performing an inference operation based on the weights determined during the training phase described in the context of FIG. 1 and outputting an estimated read voltage threshold for performing a read operation in the memory device.

[0062] Figure 9 is a diagram showing DNN 910 (e.g., Figure 8A and Figure 8B917 is a block diagram of an exemplary architecture of a DNN 1 shown in FIG. As shown, the exemplary DNN includes a first DNN 914 that processes input information including a 1 count and a checksum (CS) for an additional read. The output of the first DNN 914 is one of the inputs of a second DNN 917 that also processes the additional read x (Vt for reading PV) and CDF(x) and outputs an updated read threshold voltage.

[0063] In some embodiments, the first DNN 914 is a floating-point DNN having higher precision than the second DNN which is a fixed-point DNN because the 1 count and checksum have a larger dynamic range (compared to x and CDF(x)) and are more sensitive to quantization loss, thus requiring higher precision to better preserve information.

[0064] for Figure 9 In the example shown, the first floating-point DNN 914 can operate using a 32-bit floating-point data type, and the second fixed-point DNN 917 can operate using a 16-bit integer (fixed-point) data type. For another example, the first fixed-point DNN 914 can be configured to use a 128-bit integer data type, and the second fixed-point DNN 917 can be configured to use a 16-bit integer data type. It will be understood that the precision shown is an example, and other precisions can be implemented in the embodiments described herein.

[0065] In some embodiments, Figure 9 The DNN architecture shown can be implemented in firmware or system-on-chip (SoC) form. Whether the implementation is in firmware or SoC form can be based in part on the size of the DNN implemented, which is the size of the first DNN and the second DNN (respectively Figure 9 A function of the data type used in the operation of 914 and 917).

[0066] In some embodiments, Figure 9 The architecture shown can be used to estimate a read voltage threshold based on the 1 count and checksum from a previously failed read attempt without relying on any additional reads. In this case, the first DNN 914 can be configured to process the 1 count and checksum and output an estimated read voltage threshold, and the second DNN 917 is not used. Here, the size and weights of the first DNN1 914 are reconfigured, but this can be performed using firmware and does not require any SoC modifications.

[0067] In some embodiments, when the 1 count and checksum noise are too large to be used reliably, the second DNN 917 (with different weights) can use only x and CDF(x) to estimate the updated read voltage threshold. In this case, the first DNN 914 is not used.

[0068] Figure 10 An exemplary operation and analysis of a DNN for determining an optimal read voltage threshold for the least significant bit (LSB) page is shown. As shown, each of the PV distributions corresponds to a specific combination of the most significant bit (MSB) page, the center significant bit (CSB) page, and the least significant bit (LSB) page. For example, the PV distribution in partition 1 corresponds to a "0" MSB, a "1" CSB, and a "1" LSB. In this example, the optimal (updated) read voltage threshold shown for each PV distribution can be derived using the following implementation.

[0069] Step 1 : Read the LSB page, MSB page, and CSB page to generate a PV status count. Based on the PV status count, generate a first set of inverse cumulative mass function (ICMF) samples of the PV distribution associated with partitions 2, 3, 6, and 7. Then determine a set of 1 counts and a checksum for the LSB.

[0070] Step 2 : A predetermined number of additional reads are performed for the LSB and CSB pages to generate a second set of ICMF samples for the PV distribution associated with partitions 2, 3, 6, and 7. Two sets of 1 counts and checksums are then determined for the LSB pages.

[0071] In one example, one additional read is performed for the modified Gaussian model. In another example, two additional reads are performed for the skewed normal model. In another example, three additional reads are performed for the non-central T distribution model.

[0072] Step 3 : Input 1 count, checksum and ICMF samples into DNN (e.g. Figure 9 DNN 910 shown in FIG. Figure 10 The updated (optimal) read voltage threshold is indicated by the vertical line in .

[0073] Figure 11A flow chart of a method 1100 for improving performance of a memory device is shown. The method 1100 includes obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device at operation 1110. Herein, each of the plurality of read voltages corresponds to a program verify (PV) state, and each of the plurality of cell counts represents a number of cells having a cell voltage value within a voltage band corresponding to the read voltage applied thereto.

[0074] The method 1100 includes generating at least one 1 count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages based on the plurality of cell counts and the plurality of read voltages at operation 1120 .

[0075] The method 1100 includes, at operation 1130 , determining an updated value of at least one read voltage based on an output of a deep neural network whose inputs include at least one 1 count, at least one checksum, and a plurality of samples.

[0076] The method 1100 includes, at operation 1140 , applying an updated value of at least one read voltage to the memory device to retrieve information from the memory device.

[0077] In some embodiments, the DNN includes a first DNN and a second DNN, wherein the input of the first DNN includes at least one 1 count and at least one checksum, the input of the second DNN includes the output of the first DNN and multiple samples, and the output of the second DNN includes an updated value of at least one read voltage.

[0078] In some embodiments, the first DNN comprises a floating-point DNN and the second DNN comprises a fixed-point DNN.

[0079] In some embodiments, the first DNN operates using a 32-bit floating point data type and the second DNN operates using a 16-bit fixed point data type.

[0080] In some embodiments, obtaining a plurality of cell counts includes obtaining a first plurality of cell counts corresponding to an LSB page, a CSB page, and an MSB page, and obtaining a second plurality of cell counts corresponding to at least two of the LSB page, the CSB page, and the MSB page.

[0081] In some embodiments, method 1100 further includes the following operations: generating a first set of inverse cumulative mass function (ICMF) samples based on the first plurality of unit counts, and generating a second set of ICMF samples based on the second plurality of unit counts, wherein the input of the second DNN further includes the first set of ICMF samples and the second set of ICMF samples.

[0082] In some embodiments, a distribution function is used to model the at least one read voltage, and wherein the distribution function is a skewed normal distribution.

[0083] In some embodiments, the skewed normal distribution comprises an asymmetric Gaussian distribution characterized by a location parameter, a scale parameter, and a shape parameter.

[0084] The embodiments and functional operations of the subject matter described in this patent document can be implemented in various systems, digital electronic circuits, or computer software, firmware, or hardware including the structures disclosed in this specification and their equivalent structures, or a combination of one or more of them. The embodiments of the subject matter described in this specification can be implemented as one or more computer program products, that is, one or more modules of computer program instructions encoded on a tangible and non-transitory computer-readable medium for execution by a data processing device or for controlling the operation of the data processing device. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a material composition that affects a machine-readable propagated signal, or a combination of one or more of them. The term "data processing unit" or "data processing device" covers all devices, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or computers. In addition to hardware, the device may also include code that creates an operating environment for the computer program in question, for example, code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0085] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language (including compiled or interpreted languages) and can be deployed in any form, including as a stand-alone program suitable for use in a computing environment, or as a module, component, subroutine, or other unit. A computer program does not necessarily correspond to a file in a file system. A program can be stored as part of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., a file that stores a portion of one or more modules, subroutines, or code). A computer program can be deployed to run on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communications network.

[0086] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating data. The processes and logic flows can also be performed by, and apparatus can be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

[0087] Processors suitable for running computer programs include, for example, both general-purpose and special-purpose microprocessors, as well as any one or more processors of any type of digital computer. Typically, a processor will receive instructions and data from read-only memory or random access memory, or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Typically, a computer will also include one or more mass storage devices (e.g., magneto-optical or optical disks) for storing data, or be operably coupled to receive data from or transfer data to one or more mass storage devices (e.g., magneto-optical or optical disks) for storing data, or both. However, a computer need not have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and storage devices, including, by way of example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices. The processor and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0088] Although this patent document contains many details, these details should not be construed as limitations on the scope of any invention or any invention that may be claimed, but rather as descriptions of specific features that may be performed on specific embodiments of a particular invention. Certain features described in this patent document in the context of separate embodiments may also be implemented in combination with a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any applicable subcombination. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed as such, in some cases one or more features of the claimed combination may be excluded from the combination, and the claimed combination may involve subcombinations or variations of subcombinations.

[0089] Similarly, while operations are depicted in a particular order in the drawings, this should not be understood as requiring that these operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, in order to achieve desired results. Furthermore, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0090] This patent document describes only a few embodiments and examples, and other embodiments, improvements, and variations can be made based on what is described and illustrated in this patent document.

Claims

1. A method for improving performance of a memory device, comprising: obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, wherein each of the plurality of read voltages corresponds to a program verify state (PV state), and wherein each of the plurality of cell counts represents a number of cells having a cell voltage value within a voltage band corresponding to the read voltage applied thereto; generating, based on the plurality of cell counts and the plurality of read voltages, at least one 1's count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages; determining an updated value for the at least one read voltage based on an output of a deep neural network (DNN), wherein inputs to the DNN include the at least one ones count, the at least one checksum, and the plurality of samples; and An updated value of the at least one read voltage is applied to the memory device to retrieve information from the memory device.

2. The method of claim 1 , wherein the DNN comprises a first DNN and a second DNN, wherein an input of the first DNN comprises the at least one 1 count and the at least one checksum, wherein an input of the second DNN comprises an output of the first DNN and the plurality of samples, and wherein the output of the second DNN comprises an updated value of the at least one read voltage.

3. The method of claim 2, wherein the first DNN comprises a floating-point DNN, and wherein the second DNN comprises a fixed-point DNN.

4. The method of claim 2, wherein the first DNN operates using a 32-bit floating point data type, and wherein the second DNN operates using a 16-bit fixed point data type.

5. The method of claim 2, wherein obtaining the plurality of cell counts comprises: obtaining a first plurality of cell counts corresponding to a least significant bit page (LSB), a center significant bit page (CSB), and a most significant bit page (MSB); and A second plurality of cell counts corresponding to at least two of the LSB page, the CSB page, and the MSB page is obtained.

6. The method according to claim 5, further comprising: generating a first set of inverse cumulative mass function samples (ICMF samples) based on the first plurality of unit counts; and generating a second set of ICMF samples based on the second plurality of cell counts, The input of the second DNN further includes the first group of ICMF samples and the second group of ICMF samples. The method of claim 1 , wherein the at least one read voltage is modeled using the distribution function, and wherein the distribution function is a skewed normal distribution.

8. The method of claim 7, wherein the skewed normal distribution comprises an asymmetric Gaussian distribution characterized by a location parameter, a scale parameter, and a shape parameter.

9. A system for improving performance of a memory device, comprising: A processor and a memory, the memory comprising instructions stored on the memory, wherein the instructions, when executed by the processor, cause the processor to: obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, wherein each of the plurality of read voltages corresponds to a program verify state (PV state) and each of the plurality of cell counts represents a number of cells having a cell voltage value within a voltage band corresponding to the read voltage applied thereto; generating, based on the plurality of cell counts and the plurality of read voltages, at least one 1's count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages; determining an updated value for the at least one read voltage based on an output of a deep neural network (DNN), wherein inputs to the DNN include the at least one ones count, the at least one checksum, and the plurality of samples; as well as An updated value of the at least one read voltage is applied to the memory device to retrieve information from the memory device.

10. The system of claim 9, wherein the DNN comprises a first DNN and a second DNN, wherein an input to the first DNN comprises the at least one 1 count and the at least one checksum, wherein an input to the second DNN comprises an output of the first DNN and the plurality of samples, and wherein the output of the second DNN comprises an updated value of the at least one read voltage.

11. The system of claim 10, wherein the first DNN comprises a floating-point DNN, and wherein the second DNN comprises a fixed-point DNN.

12. The system of claim 10, wherein the first DNN operates using a 32-bit floating point data type, and wherein the second DNN operates using a 16-bit fixed point data type.

13. The system of claim 9, wherein the at least one read voltage is modeled using the distribution function, and wherein the distribution function is a skewed normal distribution comprising an asymmetric Gaussian distribution and characterized by a location parameter, a scale parameter, and a shape parameter.

14. A non-transitory computer-readable storage medium storing instructions for improving performance of a memory device, comprising: instructions for obtaining a plurality of cell counts for each of a plurality of read voltages applied to the memory device, wherein each of the plurality of read voltages corresponds to a program verify state (PV state), and each of the plurality of cell counts represents a number of cells having a cell voltage value within a voltage band corresponding to the read voltage applied thereto; instructions to generate, based on the plurality of cell counts and the plurality of read voltages, at least one ones count, at least one checksum, and a plurality of samples corresponding to a distribution function of at least one of the plurality of read voltages; instructions to determine an updated value for the at least one read voltage based on an output of a deep neural network (DNN), wherein inputs to the DNN include the at least one ones count, the at least one checksum, and the plurality of samples; as well as Instructions to apply an updated value of the at least one read voltage to the memory device to retrieve information from the memory device.

15. The non-transitory computer-readable storage medium of claim 14, wherein the DNN comprises a first DNN and a second DNN, wherein an input to the first DNN comprises the at least one 1 count and the at least one checksum, wherein an input to the second DNN comprises an output of the first DNN and the plurality of samples, and wherein the output of the second DNN comprises an updated value of the at least one read voltage.

16. The non-transitory computer-readable storage medium of claim 15, wherein the first DNN comprises a floating-point DNN, and wherein the second DNN comprises a fixed-point DNN.

17. The non-transitory computer-readable storage medium of claim 15, wherein the first DNN operates using a 32-bit floating point data type, and wherein the second DNN operates using a 16-bit fixed point data type.

18. The non-transitory computer-readable storage medium of claim 15, wherein the instructions to obtain the plurality of cell counts comprise: an instruction to obtain a first plurality of cell counts corresponding to a least significant bit page (LSB), a center significant bit page (CSB), and a most significant bit page (MSB); as well as An instruction to obtain a second plurality of cell counts corresponding to at least two of the LSB page, the CSB page, and the MSB page.

19. The non-transitory computer-readable storage medium of claim 18, further comprising: instructions for generating a first set of inverse cumulative mass function samples (ICMF samples) based on the first plurality of cell counts; as well as instructions for generating a second set of ICMF samples based on the second plurality of cell counts, The input of the second DNN further includes the first group of ICMF samples and the second group of ICMF samples.

20. The non-transitory computer-readable storage medium of claim 14, wherein the at least one read voltage is modeled using the distribution function, and wherein the distribution function is a skewed normal distribution comprising an asymmetric Gaussian distribution and characterized by a location parameter, a scale parameter, and a shape parameter.

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