Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming the same are provided. A semiconductor structure according to the present invention includes at least one first semiconductor element and at least one second semiconductor element located above a substrate; a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element; a first work function metal layer wrapping each of the at least one first semiconductor element and continuously extending from the at least one first semiconductor element to a top surface of the dielectric fin; and a second work function metal layer disposed above the at least one second semiconductor element and the first work function metal layer.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this shrinkage also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate channel coupling, reducing off-state current, and reducing short-channel effect (SCE). Multi-gate devices generally refer to devices having gate structures or portions thereof disposed above more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. A FinFET has a raised channel surrounded by gates on more than one side (e.g., the top and sidewalls of a “fin” of semiconductor material extending from the substrate). An MBC transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel region, an MBC transistor can also be called a gate-all-around (SGT) transistor or a gate-all-around (GAA) transistor.

[0004] As IC devices shrink in size, chip density increases, and the spacing between adjacent active regions decreases. One limiting factor for successful scaling is mask coverage in the photolithography process. While existing methods for forming multi-gate devices are sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0005] Some embodiments of this application provide a semiconductor structure including: at least one first semiconductor element and at least one second semiconductor element located above a substrate; a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element; a first power function metal layer encapsulating each of the at least one first semiconductor element, the first power function metal layer extending continuously from the at least one first semiconductor element to the top surface of the dielectric fin; and a second power function metal layer disposed above the at least one second semiconductor element and the first power function metal layer.

[0006] Other embodiments of this application provide a semiconductor structure including: a first plurality of channel members disposed above a first device region of a substrate; a second plurality of channel members disposed above a second device region of the substrate; dielectric fins disposed between the first plurality of channel members and the second plurality of channel members along a first direction; and a gate structure disposed above the dielectric fins and enclosing each of the first plurality of channel members and each of the second plurality of channel members, wherein the gate structure includes: a first power function metal layer extending continuously from the top surface of the dielectric fins to the surface of the first plurality of channel members, and a second power function metal layer enclosing each of the second plurality of channel members and disposed above the first power function metal layer.

[0007] Some embodiments of this application provide a method for forming a semiconductor structure, comprising: receiving a workpiece including: a first active region and a second active region, and dielectric fins disposed between the first active region and the second active region; forming a gate dielectric layer over the first active region, the dielectric fins, and the second active region; after forming the gate dielectric layer, depositing a capping layer over the dielectric fins, the first active region, and the second active region; etching back the capping layer until the dielectric fins divide the capping layer into a first portion over the first active region and a second portion over the second active region; after the etching back, selectively removing the first portion of the capping layer over the first active region; forming a first metal layer over the first active region, and forming the dielectric fins and the capping layer over the second active region; selectively removing the first metal layer and the capping layer over the second active region; and forming a second metal layer over the second active region and forming the first metal layer over the first active region. Attached Figure Description

[0008] The invention is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various components are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of the present invention is shown.

[0010] Figures 2 to 32 It is shown that one or more aspects of the invention are in Figure 1 Partial cross-sectional views of the workpiece during each manufacturing stage in the method.

[0011] Figure 33 An alternative semiconductor structure comprising different active region configurations is shown according to one or more aspects of the present invention. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, as understood by those skilled in the art, the term is intended to cover values ​​within a reasonable range that takes into account inherent variations during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing parts having numerically related characteristics, a numerical value or range of values ​​covers a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer with a thickness of "about 5 nm" can cover a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] In IC design, multiple devices can be combined together as cells or standard cells to implement certain circuit functions. These cells or standard cells can implement logic operations such as NAND, AND, OR, NOR, or inverters, or serve as memory cells, such as static random access memory (SRAM) cells. Cell dimensions (such as cell height) become a benchmark for measuring device scaling. One factor limiting cell height reduction is the overlay window used in the photolithography process to pattern adjacent metal gates. For example, devices with different gate structures can be placed adjacent to each other. Forming such devices requires forming a patterned hard mask layer. Unsatisfactory mask overlay can lead to incomplete removal of the hard mask layer. Residual hard mask layers can hinder the deposition of different power function layers, resulting in significant deviations from the design threshold voltage level.

[0016] This invention provides a method for forming semiconductor structures with different work function metal layers. An exemplary method of this invention includes: forming a protective layer over different active regions and dielectric fins; forming a capping layer over the protective layer; and forming a hard mask layer over the capping layer. The capping layer introduces self-alignment in the patterning process, while the protective layer serves as an etch stop layer or etch delay layer to protect the active regions. Because the capping layer can be selectively etched away while the hard mask layer is substantially not etched, the active regions can be selectively exposed for work function metal layer deposition even when the patterning of the hard mask layer is inaccurate due to a lack of satisfactory mask coverage. The capping layer can also be referred to as a sacrificial layer. The method of this invention expands the capping process window and improves the formation of satisfactory different work function metal layers.

[0017] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. Figure 1A flowchart of a method 100 for forming a semiconductor structure is shown. Method 100 is merely an example and is not intended to limit the scope of the invention to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 32 Description method 100, Figures 2 to 32 Partial cross-sectional views of workpiece 200 at different manufacturing stages according to an embodiment of method 100 are shown. Because a semiconductor structure or semiconductor device will be formed from workpiece 200, workpiece 200 may be referred to as semiconductor structure 200 or semiconductor device 200 depending on the context. Throughout the invention, the same reference numerals are used to denote the same components. Figures 2 to 32 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this paper.

[0018] refer to Figure 1 , Figure 2 and Figure 3 Method 100 includes a frame 102, in which a workpiece 200 is received. (See reference) Figure 2 The workpiece 200 includes a first active region 204-1 and a second active region 204-2 above the substrate 202. Depending on the design of the semiconductor device 200, the first active region 204-1 and the second active region 204-2 can be active regions of a FinFET or an MBC transistor. When the first active region 204-1 or the second active region 204-2 is an active region for a FinFET, it may include fin elements, such as... Figure 33 The third active region 204-3 is shown. When the first active region 204-1 or the second active region 204-2 is an active region for an MBC transistor, it may include a vertical stack of channel members 208, such as... Figures 2 to 32 The first active region 204-1 and the second active region 204-2 are shown. The channel component 208 is a nanostructure and may take the shape of a nanowire or nanosheet. Each of the channel component 208 and the fin element (such as the third active region 204-3) can generally be referred to as a semiconductor element.

[0019] Substrate 202 may be a silicon (Si) substrate. In some other embodiments, substrate 202 may include other semiconductor materials, such as germanium (Ge), silicon germanium (SiGe), or group III-V semiconductor materials. Exemplary group III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GeOI) structure. In some embodiments, substrate 202 may include one or more well regions for forming different types of devices, such as n-type well regions doped with n-type dopants (i.e., phosphorus (P) or arsenic (As)) or p-type well regions doped with p-type dopants (i.e., boron (B)). Doped n-type wells and p-type wells may be formed using ion implantation or thermal diffusion. The semiconductor elements in the first active region 204-1 and the second active region 204-2 can be formed of semiconductor materials, such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). Figure 2 In the illustrated embodiment, the channel member 208 comprises silicon (Si).

[0020] An interface layer 210 is disposed on the semiconductor device of the first active region 204-1 and the second active region 204-2. The interface layer 210 comprises silicon oxide and may be formed due to a pre-cleaning process or an oxidation process. An exemplary pre-cleaning process may include the use of RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed semiconductor surfaces of the channel member 208 and the substrate 202 to form the interface layer 210.

[0021] The first active region 204-1 and the second active region 204-2 rise from the substrate 202 and extend through the isolation member 203 disposed on the substrate 202. The isolation member 203 may also be referred to as a shallow trench isolation (STI) member 203. In some embodiments, the isolation member 203 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0022] refer to Figure 2 The workpiece 200 includes dielectric fins 214 disposed on the isolation member 203. For example... Figure 2As shown, dielectric fins 214 are disposed along the Y direction between the first active region 204-1 and the second active region 204-2. The top surface of the dielectric fins 214 is higher than the top surfaces of the first active region 204-1 and the second active region 204-2. The dielectric fins 214 may include silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, hafnium oxide, silicon oxide, silicon oxynitride, silicon carbonitride, or suitable dielectric materials. The dielectric fins 214 may be single-layered or multi-layered. Single-layer dielectric fins 214 are... Figure 2 As shown in the figure, and the exemplary multilayer dielectric fin 214 in Figure 27 As shown in the diagram. When the dielectric fin 214 is as follows... Figure 27 The multilayer shown may include an inner layer 236 and an outer layer 238 surrounding the inner layer 236. The dielectric constant of the outer layer 238 is greater than that of the inner layer 236. In some cases, the dielectric constant of the outer layer 238 is equal to or greater than 7, while the dielectric constant of the inner layer 236 is less than 7. The outer layer 238 with the higher dielectric constant serves as an etch-resistant layer, while the inner layer 236 with the lower dielectric constant is used to reduce parasitic capacitance. In some cases, the outer layer 238 may be formed of silicon, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, zirconium alumina, or hafnium oxide. The inner layer 236 may be formed of silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or a suitable dielectric material.

[0023] Still referencing Figure 2 The gate dielectric layer 212 is disposed on the surface of the interface layer 210, the top surface of the dielectric fin 214, and the sidewalls of the dielectric fin 214. For example... Figure 2As shown, interface layer 210 and gate dielectric layer 212 enclose each of the channel members 208 in the first active region 204-1 and the second active region 204-2. Gate dielectric layer 212 is formed of a high-k dielectric material having a dielectric constant greater than that of silicon dioxide (~3.9). In one embodiment, gate dielectric layer 212 may comprise hafnium oxide (HfO2). In some other embodiments, the gate dielectric layer 212 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials.

[0024] Still referencing Figure 2 The first active region 204-1 can be disposed in the n-type device region 20N of the substrate 202, and the second active region 204-2 can be disposed in the p-type device region 20P. In some embodiments, although not in Figure 2 As explicitly shown, however, the n-type device region 20N of substrate 202 may include a p-type well doped with a p-type dopant (such as boron (B2)), and the p-type device region 20P of substrate 202 may include an n-type well doped with an n-type dopant (such as phosphorus (P) or arsenic (As)). Figure 3 Partial cross-sectional views of section I-I' passing through the first active region 204-1 and section II-II' passing through the second active region 204-2 are shown. Figure 6 , Figure 8 , Figure 10 , Figure 12 , Figure 14 , Figure 16 , Figure 18 , Figure 20 , Figure 22 , Figure 24 , Figure 26 The middle shows the span Figure 5 , Figure 7 , Figure 9 , Figure 11 , Figure 13 , Figure 15 , Figure 17 , Figure 19 , Figure 21, Figure 23 , Figure 25 Comparable local cross-sectional views of the first active region 204-1 and the second active region 204-2 in the image.

[0025] refer to Figure 3 The channel members 208 in the n-type device region 20N and the p-type device region 20P are interleaved by a plurality of internal spacer members 217. The plurality of internal spacer members 217 may comprise silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, or combinations thereof. In one embodiment, the plurality of internal spacer members 217 are formed of silicon nitride. The channel members 208 in the n-type device region 20N are sandwiched between two n-type source / drain members 214N. In some embodiments, the two n-type source / drain members 214N comprise silicon (Si) and at least one n-type dopant, such as phosphorus (P) or arsenic (As). The channel members 208 in the p-type device region 20P are sandwiched between two p-type source / drain members 214P. In some embodiments, the two p-type source / drain members 214P comprise silicon germanium (SiGe) and at least one p-type dopant, such as boron (B). The n-type source / drain component 214N and the p-type source / drain component 214P are formed using epitaxial processes, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Therefore, the n-type source / drain component 214N can also be referred to as the n-type epitaxial component 214N, and the p-type source / drain component 214P can also be referred to as the p-type epitaxial component 214P.

[0026] Workpiece 200 also includes a contact etch stop layer (CESL) 218 ​​and an interlayer dielectric (ILD) layer 220 disposed above the n-type source / drain components 214N and p-type source / drain components 214P. CESL 218 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. ILD layer 220 comprises materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. Figure 3 As shown, CESL 218 is disposed on the top surfaces of the n-type source / drain component 214N and the p-type source / drain component 214P, and on the sidewalls of the gate spacer layer 216. In a post-gate or replacement gate process, the gate spacer layer 216 is formed above the sidewalls of a dummy gate stack that serves as a placeholder for the functional gate structure. After removing the dummy gate stack and releasing the channel component 208, Figure 3The gate spacer layer 216 shown defines a gate opening for exposing the channel member 208. The gate spacer layer 216 may be a single layer or multiple layers and may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride and / or combinations thereof.

[0027] refer to Figure 1 and Figure 4 Method 100 may optionally include frame 104, wherein a protective layer 222 is deposited over workpiece 200. For example... Figure 4 As shown, a protective layer 222 is deposited over the surface of the gate dielectric layer 212 to cover each of the channel members 208 and over the dielectric fins 214. The protective layer 222 may comprise a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or silicon titanium nitride (TiSiN). In one embodiment, the protective layer 222 is formed of titanium nitride (TiN). In some embodiments, the protective layer 222 may be deposited using ALD or CVD. The protective layer 222 protects the gate dielectric layer 212 and the channel members 208 from damage in subsequent processes. The protective layer 222 may be omitted if the capping layer 224 can be selectively removed without substantially damaging the gate dielectric layer 212 (described below).

[0028] refer to Figure 1 , Figure 5 and Figure 6 Method 100 includes frame 106, wherein a capping layer 224 is deposited over workpiece 200. (Example) Figure 5 and Figure 6 As shown, a capping layer 224 is deposited over the workpiece 200 to fill the spacing between and around the channel members 208, including the spacing along the Y direction between the channel members 208 and the dielectric fins 214. The capping layer 224 comprises silicon (Si) and can be deposited using ALD, CVD, or a suitable method. As described below, the capping layer 224 can be selectively removed (when exposed in a patterned hard mask layer) without damaging the protective layer 222. Figure 6 As shown, the protective layer 222 and the cover layer 224 completely fill the gaps between the channel members 208 (i.e., member-to-member gaps), but they do not completely fill the gaps between the gate spacer layers 216. Figure 6 In this configuration, the protective layer 222 and the capping layer 224 extend along the sidewalls of the gate spacer layer 216, leaving a gap 225. After depositing the capping layer 224, block 106 may include a post-deposition annealing process to improve the quality of the interface between the capping layer 224 and the protective layer 222. In some embodiments, the post-deposition annealing process may include an annealing temperature between about 700°C and about 950°C in a nitrogen-containing environment (such as a nitrogen (N2) environment or an ammonia (NH3) environment).

[0029] refer to Figure 1 , Figure 7 and Figure 8 Method 100 includes block 108, in which the overlay 224 is pulled back. In some embodiments, the pull-back in block 108 may include a selective wet etching process or an anisotropic dry etching process. Example selective wet etching processes may include using ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), or diluted hydrofluoric acid (DHF). When using an oxidizing agent (such as hydrogen peroxide (H2O2) or diluted hydrofluoric acid (DHF)), digital etching techniques may be used. Exemplary dry etching processes may include using oxygen, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. In one embodiment, the pull-back in block 108 includes a selective wet etching process. Figure 7 As shown, the pullback in implementation block 108 removes sufficient capping layer 224, causing the dielectric fin 214 to rise above the capping layer 224 along with the gate dielectric layer 212 and the guard layer 222. In other words, the pullback in implementation block 108 continues until the dielectric fin 214 separates the first portion above the n-type device region 20N from the second portion above the p-type device region 20P. (See reference...) Figure 8 The pullback in frame 108 removes all the capping layer 224 disposed on the sidewalls of the gate spacer layer 216, thereby exposing the protective layer 222 on the sidewalls of the gate spacer layer 216. The member-to-member spacing between the channel members 208 remains filled with the capping layer 224. Figure 8 In some of the embodiments shown, a small portion of the cover layer may still be disposed above the topmost channel member 208.

[0030] refer to Figure 1 , Figure 9 and Figure 10Method 100 includes block 110, wherein a hard mask layer 226 is deposited over workpiece 200. As described below, the hard mask layer 226 serves as an etching mask to selectively remove the overlay layer 224 over n-type device region 20N or p-type device region 20P. In some embodiments, the hard mask layer 226 can be conformally deposited using CVD, ALD, or a suitable deposition method. The hard mask layer 226 may include alumina (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), zirconium oxide (ZrO), zirconium nitride (ZrN), aluminum zirconium oxide (ZrAlO), hafnium oxide (HfO), zinc oxide (ZnO), yttrium oxide (YO), titanium oxide (TiO), other metal oxides, or suitable dielectric materials. In some other embodiments, the hard mask layer 226 may be multilayered. Figure 9 As shown, a hard mask layer 226 is conformally deposited on the top surface of the capping layer 224 and on the surface of the protective layer 222 located on the portion of the dielectric fin 214 protruding from the capping layer 224. (See reference...) Figure 10 Hard mask layer 226 is deposited on the top surface of CESL 218, ILD layer 220, gate spacer layer 216 and protective layer 222 extending along the sidewall of gate spacer layer 216.

[0031] refer to Figure 1 , Figure 11 , Figure 12 , Figure 13 and Figure 14 Method 100 includes a frame 112, wherein a patterned hard mask layer 226 is used to expose the n-type device region 20N of the workpiece 200. (First refer to...) Figure 11 and Figure 12 A first bottom antireflective coating (BARC) layer 228 is deposited and patterned using photolithography over a workpiece 200 to expose a hard mask layer 226 over an n-type device region 20N. The first BARC layer 228 may comprise polysulfone, polyurea, polyurea sulfone, polyacrylate, poly(vinylpyridine), or a silicon-containing polymer. The first BARC layer 228 can be deposited over the workpiece 200 using spin coating or FCVD. According to the invention, at least a portion of the hard mask layer 226 above the dielectric fins 214 remains covered by the patterned first BARC layer 228. This arrangement allows the subsequently formed patterned hard mask layer 226 and dielectric fins to form a protective shell of a cover layer 224 in the p-type device region 20P. In the depicted embodiment, a portion of the patterned first BARC layer 228 remains disposed above the portion of the hard mask layer 226 above the n-type device region 20N. Then refer to... Figure 13 and Figure 14The patterned first BARC layer 228 serves as an etch mask to etch the hard mask layer 226 to form the patterned hard mask layer 226. In the depicted embodiment, a portion of the patterned hard mask layer 226 is disposed on the portion of the cover layer 224 located above the n-type device region 20N. Figure 14 As shown, after selectively removing the hard mask layer 226 above the n-type device region 20N, the protective layer 222 on the sidewalls of the gate spacer layer 216 and the cover layer 224 in the n-type device region 20N is exposed.

[0032] refer to Figure 1 , Figure 15 and Figure 16 Method 100 includes block 114, in which a capping layer 224 is removed from a first device region 20N. The capping layer 224 over the n-type device region 20N is selectively removed as a patterned hard mask layer 226 is formed in block 112. In some embodiments, selective wet etching or selective dry etching is used to selectively remove the capping layer 224 over the n-type device region 20N, the selective wet etching or selective dry etching being selective to the capping layer 224 and etching the protective layer 222 at a much slower rate. Example selective wet etching processes in block 114 may include using ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), or suitable wet etchants. Example selective dry etching processes in block 114 may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), methane (CH4), hydrogen bromide (HBr), hydrogen fluoride (HF), carbon tetrafluoride (CF4), or mixtures thereof. like Figure 15 and Figure 16 As shown, the capping layer 224 above the n-type device region 20N is selectively removed to expose the protective layer 222 above the n-type device region 20N. After removing the capping layer 224, the patterned first BARC layer 228 is removed by ashing or selective etching.

[0033] refer to Figure 1 , Figure 17 and Figure 18Method 100 includes block 116, in which a patterned hard mask layer 226 is removed. After selectively removing the overlay layer 224 over the n-type device region 20N, the patterned hard mask layer 226 over the dielectric fins 214 and the p-type device region 20P is selectively removed by selective etching. Because the hard mask layer 226 is formed of a metal oxide, the selective etching in block 116 can be performed using dry etching or wet etching that is selective to the metal oxide. Example selective wet etching processes may include using hydrofluoric acid, ammonium fluoride, RCA SC-1 (ammonia, hydrogen peroxide, and water), RCA SC-2 (hydrochloric acid and hydrogen peroxide), or combinations thereof. Example selective dry etching processes may include using oxygen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), or combinations thereof.

[0034] refer to Figure 1 , Figure 19 and Figure 20 Method 100 includes box 118, wherein the protective layer 222 not covered by the overlay layer 224 is removed. Figure 19 and Figure 20 As shown, the exposed protective layer 222 is removed by selective dry etching or selective wet etching. Examples of selective wet etching for removing the protective layer 222 may include a mixture of nitric acid and hydrofluoric acid, RCA SC-1 (ammonia, hydrogen peroxide, and water), RCA SC-2 (hydrochloric acid and hydrogen peroxide), or buffered hydrofluoric acid (a mixture of hydrofluoric acid and ammonium fluoride). Removing the exposed protective layer 222 may expose the dielectric fins 214 in the n-type device region 20N and the gate dielectric layer 212 above the channel member 208.

[0035] refer to Figure 1 , Figure 19 and Figure 20 Method 100 includes frame 120, in which a first work function metal layer 230 is deposited. After removing the exposed protective layer 222, frame 120 deposits the first work function metal layer 230 over the workpiece 200. In some embodiments, the first work function metal layer 230 may be an n-type work function metal layer and may include titanium (Ti), aluminum (Al), titanium aluminide (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), titanium aluminum aluminum aluminum nitride (TiAlN), tantalum silicon aluminum (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaC), or hafnium carbide (HfC). Figure 19 and Figure 20As shown, the deposited first power-function metal layer 230 is in direct contact with the gate dielectric layer 212 on the dielectric fin 214 and around the channel member 208 in the n-type device region 20N. It should be noted that the first power-function metal layer 230 is allowed to fill the gap between the dielectric fin 214 and the channel member 208 in the n-type device region 20N, as indicated by the hollow arrow. The gap between the dielectric fin 214 and the channel member 208 can be referred to as the end-cap gap. Satisfactory metal filling in the end-cap gap is important for gate structure integrity, threshold voltage, and gate resistance.

[0036] exist Figure 19 In some embodiments shown, the first function metal layer 230 deposited between adjacent channel members 208 in the n-type device region 20N is allowed to merge, thereby filling the member-to-member spacing. Figure 28 In some alternative embodiments shown, the first functional metal layer 230 is not merged to seal the member-to-member spacing and allows the subsequently deposited second functional metal layer 234 (described below) to enter the member-to-member spacing.

[0037] refer to Figure 1 , Figure 21 , Figure 22 , Figure 23 and Figure 24 Method 100 includes block 122, wherein a first function metal layer 230, a capping layer 224, and a protective layer 222 are selectively removed over the p-type device region 20P. The operation in block 122 may include forming a patterned second BARC layer 232. Figure 21 and Figure 22 (as shown) and etching the first work function metal layer 230, the cover layer 224 using a patterned second BARC layer 232 as an etching mask ... Figure 23 and Figure 24 As shown), and the patterned second BARC layer 232 (as shown). Figure 23 and Figure 24 (As shown in the illustration). In an exemplary process, the second BARC layer 232 is first deposited on the first work function metal layer 230 on the workpiece 200, and then the second BARC layer 232 is patterned using photolithography to form a patterned second BARC layer 232, as shown in the illustration. Figure 21 and Figure 22 As shown. In Figure 21 In some embodiments shown, a patterned second BARC layer 232 covers and protects the first power function metal layer 230 above the n-type device region 20N and the first power function metal layer 230 on the top surface and sidewalls of the dielectric fin 214. For example... Figure 21 and Figure 22 As shown, the patterned second BARC layer 232 exposes the first functional metal layer 230 above the p-type device region 20P.

[0038] Now for reference Figure 23 and Figure 24 Box 122 also includes etching the first function metal layer 230 and the capping layer 224 over the p-type device region 20P using the second patterned BARC layer 232 as an etching mask. Box 122 further includes removing the patterned second BARC layer 232 and removing the protective layer 222 over the p-type device region 20P. In some embodiments, the etching of the first function metal layer 230, the etching of the capping layer 224, and the etching of the protective layer 222 are performed in different etching processes. For example, the first function metal layer 230 can be etched using a selective wet etching process using phosphoric acid, acetic acid, nitric acid, RCA SC-1 (ammonia, hydrogen peroxide, and water) or RCA SC-2 (hydrochloric acid and hydrogen peroxide) or a selective dry etching process using chlorine, carbon tetrachloride, silicon tetrachloride, and boron chloride. Selective wet etching can be used to selectively etch the capping layer 224 using ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), ammonium fluoride (NH4F), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), dilute hydrofluoric acid (DHF), or a suitable wet etchant. Figure 23 As shown, the wet etching of the capping layer 224 is isotropic and can undercut the patterned second BARC layer 232 and the underlying first functional metal layer 230. Selective removal of the capping layer 224 at finite intervals introduces a self-aligned element into method 100. Even when the patterning of the patterned second BARC layer 232 is less than ideal due to unsatisfactory mask coverage, the capping layer 224 can still be satisfactorily removed as long as it is partially exposed.

[0039] After removing the capping layer 224 over the p-type device region 20P, the patterned second BARC layer 232 is removed by ashing or selective etching. After removing the patterned second BARC layer 232, the protective layer 222 over the p-type device region 20P is selectively removed using a selective wet etching process. Example selective wet etching processes for removing the protective layer 222 may include a mixture of nitric acid and hydrofluoric acid, RCA SC-1 (ammonia, hydrogen peroxide, and water), RCA SC-2 (hydrochloric acid and hydrogen peroxide), or buffered hydrofluoric acid (a mixture of hydrofluoric acid and ammonium fluoride). Removing the exposed protective layer 222 in block 122 may expose the gate dielectric layer 212 over the dielectric fins 214 in the n-type device region 20N and the sidewalls of the channel member 208.

[0040] Optionally, after patterning the first functional metal layer 230 using the patterned second BARC layer 232, the patterned second BARC layer 232 can be removed. The patterned first functional metal layer 230 can be used as an etching mask in removing the cover layer 224 in the p-type device region.

[0041] refer to Figure 1 , Figure 25 and Figure 26 Method 100 includes block 124, wherein a second power function metal layer 234 is deposited over workpiece 200. After removing the protective layer 222 over the p-type device region 20P, block 124 deposits the second power function metal layer 234 over workpiece 200. In some embodiments, the second power function metal layer 234 may be a p-type power function metal layer and may include cobalt (Co), titanium nitride (TiN), tungsten carbonitride (WCN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), molybdenum (Mo), or combinations thereof. Figure 25 and Figure 26 As shown, a deposited second functional metal layer 234 surrounds each of the channel members 208 in the p-type device region 20P and is disposed on the first functional metal layer 230 in the n-type device region 20N. In the depicted embodiment, the second functional metal layer 234 fills the end-cap space between the channel members 208 and the dielectric fins 214 in the p-type device region 20P. The second functional metal layer 234 may also extend into the end-cap space between the channel members 208 and the dielectric fins 214 in the n-type device region 20N. It should be noted that the top surface of the dielectric fins 214 is covered by the first functional metal layer 230 and spaced apart from the second functional metal layer 234 by the first functional metal layer 230. In some embodiments, the top surface of the dielectric fins 214 may not be completely covered by the first functional metal layer 230. The second functional metal layer 234 is in direct contact with the gate dielectric layer 212 on the sidewalls of the dielectric fins 214 and around the channel members 208 in the p-type device region 20P. Figure 25 and Figure 26An example is shown where the first power function metal layer 230 and the second power function metal layer 234 are not divided into two separate gate structures by the dielectric fin 214 or gate dicing features. Although not explicitly shown in the figures, after depositing the second power function metal layer 234, the workpiece 200 may undergo a planarization process, such as a chemical mechanical polishing (CMP) process, to provide a flat top surface. At the end of the operation in block 124, an n-type MBC transistor 300 is formed over the n-type device region 20N and a p-type MBC transistor 400 is formed over the p-type device region 20P. Because the first power function metal layer 230 and the second power function metal layer 234 include connection portions across the dielectric fin 214, they together form a common gate structure controlling the n-type MBC transistor 300 and the p-type MBC transistor 400. As described elsewhere in the invention, further processes may be implemented to divide the common gate structure into different gate structures (or different gate segments).

[0042] exist Figure 29 In some alternative embodiments shown, a third power function metal layer 235 is deposited in block 124 instead of the second power function metal layer 234. In these alternative embodiments, for ease of reference, the n-type device region 20N may be referred to as the first n-type device region 20N. Figure 29 In this embodiment, the p-type device region 20P is replaced by a second n-type device region 30N. Like the first n-type device region 20N, the second n-type device region 30N can also be disposed above the p-type well. The third power function metal layer 235 is an n-type power function metal layer, but it differs from the first power function metal layer 230 in composition. For example, the first power function metal layer 230 may include titanium aluminum (TiAl), while the third power function metal layer 235 includes titanium (Ti). In these alternative embodiments, the n-type MBC transistors formed in the first n-type device region 20N and the n-type MBC transistors formed in the second n-type device region 30N can have different threshold voltages.

[0043] Still in Figure 30 In some alternative embodiments shown, the second function metal layer 234 is conformally deposited over the workpiece 200 but does not completely fill the space around the dielectric fins 214. In these alternative embodiments, method 100 may include a further process to deposit a metal filler layer 240 over the second function metal layer 234.

[0044] refer to Figure 1 Method 100 includes block 126, in which a further process is performed. This further process may include, for example, depositing a metal filler layer 240. Figure 30 As shown in the figure, the second work function metal layer 234 and the first work function metal layer 230 are etched back. Figure 31 As shown in the figure, or a gate dicing member 244 is formed above the dielectric fin 214. Figure 32 (As shown in the image). First refer to Figure 30 In some alternative embodiments, the second function metal layer 234 does not fill the gate opening defined between the gate spacer layers. In those alternative embodiments, method 100 may include a metal fill process to deposit a metal fill layer 240 over the second function metal layer 234. Figure 30 As shown, the metal filler layer 240 may extend into the end cap space between the channel member 208 and the dielectric fin 214 above the p-type device region 20P. The metal filler layer 240 may include tungsten (W), ruthenium (Ru), cobalt (Co), or copper (Cu). In one embodiment, the metal filler layer 240 may include tungsten (W). Although not explicitly shown in the figures, after depositing the metal filler layer 240, the workpiece 200 may undergo a planarization process, such as a chemical mechanical polishing (CMP) process, to provide a flat top surface.

[0045] Then refer to Figure 31 When the first active region 204-1 and the second active region 204-2 need to be activated individually, a dry etching process can be used to etch back the second power function metal layer 234, the first power function metal layer 230, and the gate dielectric layer 212 until they are separated into a first gate structure 250-1 above the n-type device region 20N and a second gate structure 250-2 above the p-type device region 20P. The dry etching process may include the use of oxygen, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBR3), iodine-containing gases, other suitable gases, and / or plasma and / or combinations thereof. Figure 31 As shown, etching back the first power function metal layer 230 can leave the first power function metal component 2300 as part of the second gate structure 250-2. The first power function metal component 2300 is in contact with the gate dielectric layer 212 but is spaced apart from the dielectric fins 214 by the gate dielectric layer 212.

[0046] Now for reference Figure 32When the first active region 204-1 and the second active region 204-2 are to be activated individually, a gate dicing member 244 can be formed over the dielectric fin 214. The gate dicing member 244 cuts off the connection portion between the second function metal layer 234 and the first function metal layer 230 and separates them into a first gate structure 250-1 and a second gate structure 250-2. In an exemplary process, after planarizing the second function metal layer 234, a dielectric layer 242 can be deposited over the second function metal layer 234. A gate dicing opening is then formed through the dielectric layer 242, the second function metal layer 234, the first function metal layer 230, and the gate dielectric layer 212 to expose the top surface of the dielectric fin 214. Subsequently, dielectric material is deposited into the gate dicing opening to form the gate dicing member 244. In some embodiments, the composition and formation process of the dielectric layer 242 can be similar to those of the ILD layer 220. The gate dicing component 244 may include a dielectric material such as silicon oxide, silicon oxynitride, silicon carbonitride, hafnium oxide, zirconium oxide, or aluminum oxide.

[0047] Figure 33 An alternative embodiment is shown where workpiece 200 includes a first active region 204-1 and a third active region 204-3. Unlike the first active region 204-1 and the second active region 204-2 of a vertically stacked assembly including a channel member 208, the third active region 204-3 includes a fin element 2082 to serve as a channel region for a FinFET. The fin element 2082 may be formed of silicon and may extend from the substrate 202. Figure 32 The semiconductor device 200 in the process can be referred to as a hybrid device because it includes at least one n-type MBC transistor 300 and at least one p-type FinFET 500. Except for the fact that the third active region 204-3 does not have a vertically stacked structure of channel members and does not have member-to-member spacing, method 100 can be used to form... Figure 33 The semiconductor device shown.

[0048] Based on the above discussion, it can be seen that the present invention provides advantages over existing processes. However, it should be understood that other embodiments may provide additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. For example, the process disclosed in this invention deposits a protective layer over an active region, a capping layer over the protective layer, and a hard mask layer over the capping layer. The protective layer serves as an etch delay layer. The capping layer serves as a sacrificial layer that can be selectively removed without substantially damaging the protective layer. Combined with dielectric fins disposed between two adjacent active regions, this three-layer arrangement allows for self-alignment and controlled removal of the capping layer over an active region, even when the patterning of the hard mask layer is less than satisfactory. The process of the present invention can reduce mask coverage requirements and improve process yield.

[0049] In one exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: at least one first semiconductor element and at least one second semiconductor element, located above a substrate; a dielectric fin disposed between the at least one first semiconductor element and the at least one second semiconductor element; a first power function metal layer encapsulating each of the at least one first semiconductor element, the first power function metal layer extending continuously from the at least one first semiconductor element to the top surface of the dielectric fin; and a second power function metal layer disposed above the at least one second semiconductor element and the first power function metal layer.

[0050] In some embodiments, the semiconductor structure may further include: a gate dielectric layer disposed above the surfaces of at least one first semiconductor element and at least one second semiconductor element. A second power function metal layer contacts the gate dielectric layer disposed on the at least one second semiconductor element, and the second power function metal layer is spaced apart from the gate dielectric layer disposed on the at least one first semiconductor element by a first power function metal layer. In some embodiments, the gate dielectric layer is disposed above the sidewalls and top surface of the dielectric fin. In some embodiments, at least one first semiconductor element includes a first plurality of channel members stacked on top of each other, and at least one second semiconductor element includes a second plurality of channel members stacked on top of each other. In some cases, at least one first semiconductor element includes a plurality of channel members stacked on top of each other, and at least one second semiconductor element includes semiconductor fins rising from the substrate. In some embodiments, the first power function metal layer is an n-type power function metal layer, and the second power function metal layer is a p-type power function metal layer. In some embodiments, the first function metal layer comprises titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN), and the second function metal layer comprises cobalt (Co), titanium nitride (TiN), or tungsten carbonitride (WCN). In some cases, the semiconductor structure may further include a gate dicing member disposed above the dielectric fins. The gate dicing member divides the first function metal layer and the second function metal layer into a first gate segment disposed above at least one first semiconductor element and a second gate segment disposed above at least one second semiconductor element. In some cases, the gate dicing member extends through the first function metal layer, such that the second gate segment includes a portion of the first function metal layer.

[0051] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a first plurality of channel members disposed over a first device region of a substrate; a second plurality of channel members disposed over a second device region of the substrate; dielectric fins disposed along a first direction between the first plurality of channel members and the second plurality of channel members; and a gate structure disposed over the dielectric fins and enclosing each of the first plurality of channel members and each of the second plurality of channel members. The gate structure includes: a first power function metal layer extending continuously from the top surface of the dielectric fins to the surface of the first plurality of channel members; and a second power function metal layer enclosing each of the second plurality of channel members and disposed over the first power function metal layer.

[0052] In some embodiments, a first plurality of channel members are sandwiched between two n-type source / drain members along a second direction perpendicular to the first direction, and a second plurality of channel members are sandwiched between two p-type source / drain members along the second direction. In some embodiments, a first function metal layer does not extend between a second function metal layer and the second plurality of channel members. In some cases, a second function metal layer extends between adjacent first plurality of channel members. In some embodiments, the first function metal layer comprises titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN), and the second function metal layer comprises cobalt (Co), titanium nitride (TiN), or tungsten carbonitride (WCN).

[0053] In another exemplary aspect, the present invention relates to a method. The method includes: receiving a workpiece including: a first active region and a second active region, and dielectric fins disposed between the first active region and the second active region; forming a gate dielectric layer over the first active region, the dielectric fins, and the second active region; after forming the gate dielectric layer, depositing a capping layer over the dielectric fins, the first active region, and the second active region; etching back the capping layer until the dielectric fins divide the capping layer into a first portion over the first active region and a second portion over the second active region; after etching back, selectively removing the first portion of the capping layer over the first active region; forming a first metal layer over the first active region, and forming the dielectric fins and the capping layer over the second active region; selectively removing the capping layer over the first metal layer and the second active region; and forming a second metal layer over the second active region and forming a first metal layer over the first active region.

[0054] In some embodiments, the capping layer comprises silicon. In some embodiments, the method may further include depositing a protective layer over a first active region, a second active region, and a dielectric fin before depositing the capping layer. In some embodiments, the protective layer comprises titanium nitride. In some cases, after selectively removing the capping layer over the first metal layer and the second active region, a portion of the first metal layer remains disposed over the top surface of the dielectric fin. In some cases, after forming the second metal layer over the second active region, the top surface of the dielectric fin is spaced apart from the second metal layer by the first metal layer.

[0055] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: At least one first semiconductor element and at least one second semiconductor element are located above the substrate; Dielectric fins are disposed between the at least one first semiconductor element and the at least one second semiconductor element; A gate dielectric layer is disposed above the surfaces of the at least one first semiconductor element and the at least one second semiconductor element; A first power function metal layer is provided to enclose each of the at least one first semiconductor element, the first power function metal layer extending continuously from the at least one first semiconductor element to the top surface of the dielectric fin; as well as A second power-function metal layer is disposed above the at least one second semiconductor element and the first power-function metal layer, wherein the second power-function metal layer is in contact with the gate dielectric layer disposed on the at least one second semiconductor element, and is spaced apart from the gate dielectric layer disposed on the at least one first semiconductor element by the first power-function metal layer. The dielectric fin includes a first sidewall facing the at least one first semiconductor element and a second sidewall facing the at least one second semiconductor element. The first functional metal layer is disposed along the top of the second sidewall of the dielectric fin.

2. The semiconductor structure according to claim 1, wherein, The gate dielectric layer is formed of a high-k dielectric material.

3. The semiconductor structure according to claim 2, wherein, The gate dielectric layer is disposed above the sidewalls and top surface of the dielectric fin.

4. The semiconductor structure according to claim 1, in, The at least one first semiconductor element includes a plurality of first channel components stacked on top of each other. The at least one second semiconductor element includes a second plurality of channel components stacked on top of each other.

5. The semiconductor structure according to claim 1, in, The at least one first semiconductor element includes a plurality of channel components stacked on top of each other. The at least one second semiconductor element includes a semiconductor fin that rises from the substrate.

6. The semiconductor structure according to claim 1, in, The first work function metal layer is an n-type work function metal layer. The second work function metal layer is a p-type work function metal layer.

7. The semiconductor structure according to claim 1, in, The first function metal layer includes titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN). The second work function metal layer includes cobalt (Co), titanium nitride (TiN), or tungsten carbonitride (WCN).

8. The semiconductor structure according to claim 1, further comprising: A gate dicing component is disposed above the dielectric fin, wherein the gate dicing component divides the first power function metal layer and the second power function metal layer into a first gate segment disposed above the at least one first semiconductor element and a second gate segment disposed above the at least one second semiconductor element.

9. The semiconductor structure according to claim 8, wherein, The gate dicing member extends through the first power function metal layer, such that the second gate segment includes a portion of the first power function metal layer.

10. A semiconductor structure comprising: The first plurality of channel components are disposed above the first device region of the substrate; A second plurality of channel components are disposed above the second device region of the substrate; Dielectric fins are disposed between the first plurality of channel members and the second plurality of channel members along a first direction; as well as A gate structure is disposed above the dielectric fins and encloses each of the first plurality of channel members and each of the second plurality of channel members. The gate structure includes: a gate dielectric layer; a first power function metal layer extending continuously from the top surface of the dielectric fins to the surface of the first plurality of channel members; and a second power function metal layer enclosing each of the second plurality of channel members and disposed above the first power function metal layer. The second power function metal layer is in contact with the gate dielectric layer disposed on the second plurality of channel members and is spaced apart from the gate dielectric layer disposed on the first plurality of channel members by the first power function metal layer. The dielectric fin includes a first sidewall facing the first plurality of channel members and a second sidewall facing the second plurality of channel members. The first functional metal layer is disposed along the top of the second sidewall of the dielectric fin.

11. The semiconductor structure according to claim 10, in, The first plurality of channel components are sandwiched between two n-type source / drain components along a second direction perpendicular to the first direction. The second plurality of channel components are sandwiched between two p-type source / drain components along the second direction.

12. The semiconductor structure according to claim 10, wherein, The first functional metal layer does not extend between the second functional metal layer and the second plurality of channel components.

13. The semiconductor structure according to claim 10, wherein, The second functional metal layer extends between adjacent first plurality of channel members.

14. The semiconductor structure according to claim 10, in, The first function metal layer includes titanium (Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), or titanium aluminum nitride (TiAlN). The second work function metal layer includes cobalt (Co), titanium nitride (TiN), or tungsten carbonitride (WCN).

15. A method for forming a semiconductor structure, comprising: The workpiece is received, the workpiece comprising: a first active region and a second active region, and dielectric fins disposed between the first active region and the second active region; A gate dielectric layer is formed over the first active region, the dielectric fin, and the second active region; After the gate dielectric layer is formed, a capping layer is deposited over the dielectric fin, the first active region, and the second active region; The capping layer is etched back until the dielectric fins divide the capping layer into a first portion above the first active region and a second portion above the second active region; After the back etch, the first portion of the cover layer located above the first active region is selectively removed; A first metal layer is formed over the capping layer above the first active region, the dielectric fin, and the second active region; Selectively remove the capping layer above the first metal layer and the second active region; and A second metal layer is formed above the first metal layer above the second active region and above the first active region, wherein the second metal layer is in contact with the gate dielectric layer disposed on the second active region, and is spaced apart from the gate dielectric layer disposed on the first active region by the first metal layer. The dielectric fin includes a first sidewall facing the first active region and a second sidewall facing the second active region. The first metal layer is disposed along the top of the second sidewall of the dielectric fin.

16. The method according to claim 15, wherein, The capping layer comprises silicon.

17. The method of claim 15, further comprising: Before depositing the capping layer, a protective layer is deposited over the first active region, the second active region, and the dielectric fin.

18. The method according to claim 17, wherein, The protective layer comprises titanium nitride.

19. The method according to claim 15, wherein, After selectively removing the capping layer above the first metal layer and the second active region, a portion of the first metal layer remains disposed above the top surface of the dielectric fin.

20. The method of claim 15, wherein, After the second metal layer is formed above the second active region, the top surface of the dielectric fin is separated from the second metal layer by the first metal layer.

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