Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate; a gate structure separated on the substrate, comprising a gate contact region for contacting a gate plug; a source-drain doped region, comprising a source-drain contact region and a source-drain connection region; a dielectric structure layer, located on the substrate at the side of the gate structure and covering the source-drain doped region and the gate structure; a source-drain contact structure, contacting the source-drain doped region, the source-drain contact structure being an integrated structure, comprising a source-drain plug penetrating through the dielectric structure layer at the source-drain contact region, and a source-drain contact layer in the dielectric structure at the source-drain connection region, the top surface of the source-drain contact layer being lower than the top surface of the source-drain plug, the source-drain contact structure and the dielectric structure layer surrounding a spacing opening; a spacing dielectric layer, filling in the spacing opening; and the gate plug, located on the top of the gate structure at the gate contact region and contacting the gate structure. The source-drain contact structure of the embodiment is an integrated structure, which improves the electrical connection performance between the source-drain plug and the source-drain contact layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped regions for connecting the source / drain doped regions to external circuitry.

[0004] Currently, to further reduce transistor area, the ContactOver Active Gate (COAG) process has been introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area.

[0005] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0006] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0007] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; a plurality of gate structures discretely disposed on the substrate, each gate structure including a gate contact region for contacting a gate plug; source / drain doped regions located within the substrate on both sides of the gate structures, each source / drain doped region including a source / drain contact region for contacting a source / drain plug, the remaining region serving as a source / drain connection region; a dielectric structure layer located on the substrate on the side of the gate structures and covering the source / drain doped regions, the dielectric structure layer also covering the top of the gate structures; a source / drain contact structure in contact with the source / drain doped regions, the source / drain contact structure being an integral structure including a source / drain plug penetrating the dielectric structure layer through the source / drain contact region, and a source / drain contact layer located in the dielectric structure of the source / drain connection region, the top surface of the source / drain contact layer being lower than the top surface of the source / drain plug, the source / drain contact structure and the dielectric structure layer forming a spaced opening; a spacer dielectric layer filling the spaced opening; and a gate plug located on top of the gate structures in the gate contact regions and in contact with the gate structures.

[0008] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a plurality of discrete gate structures are formed on the substrate, each gate structure including a gate contact region for contacting a gate plug, source / drain doped regions are formed in the substrate on both sides of the gate structures, each source / drain doped region including a source / drain contact region for contacting a source / drain plug, the remaining region serving as a source / drain connection region, a bottom dielectric layer is formed on the substrate on the side of the gate structures, covering the source / drain doped regions; a top dielectric layer is formed on the bottom dielectric layer; and source / drain contact materials are formed penetrating the top of the source / drain doped regions through the bottom dielectric layer and the top dielectric layer. Material is applied to the source / drain doped region; a portion of the source / drain contact material in the source / drain connection region is removed, and the remaining source / drain contact material in the source / drain connection region is used as a source / drain contact layer. The source / drain contact material in the source / drain contact region is used as a source / drain plug. The source / drain plug and the source / drain contact layer together form a source / drain contact structure. The source / drain contact structure, the bottom dielectric layer, and the top dielectric layer form a spacer opening. A spacer dielectric layer is filled into the spacer opening. After forming the spacer dielectric layer, a gate plug is formed that penetrates the top dielectric layer above the gate contact region and contacts the top of the gate structure in the gate region.

[0009] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0010] In the semiconductor structure provided by this invention, the source-drain contact structure is an integral structure, including a source-drain plug that penetrates the dielectric structure layer of the source-drain contact region, and a source-drain contact layer located in the dielectric structure of the source-drain connection region. The top surface of the source-drain contact layer is lower than the top surface of the source-drain plug. The integral structure of the source-drain contact structure is beneficial to reducing the resistance between the source-drain plug and the source-drain contact layer, as well as the contact resistance between the source-drain plug and the source-drain contact layer, thereby improving the electrical connection performance between the source-drain plug and the source-drain contact layer. This, in turn, helps to improve the subsequent RC (resistance-capacitance) delay, reduce power consumption, and improve the circuit response speed, thus improving the performance of the semiconductor structure.

[0011] In the semiconductor structure formation method provided by the embodiments of the present invention, the source-drain contact material is first formed, and then a portion of the source-drain contact material located in the source-drain connection region is removed to form a source-drain contact layer and a source-drain plug located in the source-drain contact region. Thus, the embodiments of the present invention form the source-drain plug and the source-drain contact layer in the same step, which not only simplifies the process but also eliminates the need for alignment between the source-drain plug and the source-drain contact layer. This reduces the process difficulty of forming the source-drain plug and increases the process window for forming the source-drain plug. Furthermore, the source-drain contact structure formed by the source-drain plug and the source-drain contact layer is an integral structure, which helps to reduce the resistance of the source-drain plug and the source-drain contact layer, as well as the contact resistance between the source-drain plug and the source-drain contact layer. This improves the electrical connection performance between the source-drain plug and the source-drain contact layer, thereby improving the subsequent RC (resistance-capacitance) delay, reducing power consumption, and increasing circuit response speed. The performance of the semiconductor structure is thus improved.

[0012] In an optional embodiment, the remaining area outside the gate contact region in the gate structure is used as a gate spacer region. After providing the substrate and before forming the top dielectric layer, the formation method further includes: removing a portion of the thickness of the gate structure located in the gate spacer region, so that the gate structure located in the gate contact region is not etched. Compared with the gate structure in the gate spacer region, the top surface height of the gate structure in the gate contact region is higher, which is beneficial to reduce the formation height of the subsequent gate plug, thereby reducing the formation difficulty of the gate plug, increasing the process window for forming the gate plug, and also beneficial to reduce the resistance of the gate plug.

[0013] In an optional embodiment, after providing the substrate and before removing the portion of the gate structure located in the gate spacer region, the formation method further includes: forming an etch barrier structure covering the top of the gate structure in the gate contact region. The etch barrier structure is located on top of the gate structure in the gate contact region and is also used to pre-occupy a space for forming a gate plug. During the subsequent formation of the gate plug, the gate plug passes through the etch barrier structure. Since the etch barrier structure has etch selectivity with the top dielectric layer, the spacer dielectric layer, and the bottom dielectric layer, it is beneficial to achieve self-alignment between the formation position of the gate plug and the etch barrier structure, thereby reducing the probability of short circuit between the gate plug and the source / drain contact structure. Moreover, the etch barrier structure also serves as an etch barrier during the subsequent formation of the source / drain contact material, preventing the source / drain contact material from forming on the gate structure in the gate contact region and short-circuiting with the gate structure, thus improving the reliability of the semiconductor structure. Attached Figure Description

[0014] Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] Figures 7 to 9 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0016] Figures 10 to 37 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0017] As the background technology shows, the performance of current semiconductor structures needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 6 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0018] refer to Figure 1 A substrate 10 is provided, on which a gate structure 20 is formed. A gate capping layer 25 is formed on the top surface of the gate structure 20. Source and drain doped regions 30 are formed in the substrate 10 on both sides of the gate structure 20. A bottom dielectric layer 40 covering the source and drain doped regions 30 is formed on the substrate 10 on the side of the gate structure 20. The bottom dielectric layer 40 is exposed on the top surface of the gate capping layer 25.

[0019] refer to Figure 2 A source / drain contact layer 50 is formed that penetrates the bottom dielectric layer 40 at the top of the source / drain doped region 30 and is in contact with the source / drain doped region 30; a portion of the source / drain contact layer 50 is removed, and a source / drain capping layer 55 is formed on top of the remaining source / drain contact layer 50.

[0020] refer to Figure 3A top dielectric layer 60 is formed on the bottom dielectric layer 40, covering the source / drain cap layer 55 and the gate cap layer 25.

[0021] refer to Figures 4 to 6 , Figure 4 This is a top view. Figure 5 for Figure 4 Cross-sectional view along the x1-x1 direction. Figure 6 for Figure 4 A cross-sectional view along the x2-x2 direction shows a gate contact plug 70 forming through the gate cap layer 25 and the top dielectric layer 60 of the gate structure 20, and in contact with the gate structure 20; and a source drain contact plug 80 forming through the source drain cap layer 55 and the top dielectric layer 60 of the source drain contact layer 50, and in contact with the source drain contact layer 50.

[0022] In the method described above, a source / drain contact layer 50 and a source / drain capping layer 55 located on top of the source / drain contact layer 50 are first formed. Then, the source / drain capping layer 55 is etched to form a source / drain contact plug 80 that contacts the source / drain contact layer 50. During the formation of the source / drain contact plug 80, the source / drain contact plug 80 needs to be aligned with the source / drain contact layer 50, which can easily lead to overlay shift. This can reduce the process window for forming the source / drain contact plug 80, increase the process difficulty of forming the source / drain contact plug 80, and also easily lead to a large contact resistance between the source / drain contact plug 80 and the source / drain contact layer 50, resulting in poor electrical connection performance of the semiconductor structure. In addition, the process flow of the method is also relatively complex.

[0023] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure in which the source-drain contact structure is an integral structure, including a source-drain plug penetrating a dielectric structure layer through the source-drain contact region, and a source-drain contact layer located in the dielectric structure of the source-drain connection region. The top surface of the source-drain contact layer is lower than the top surface of the source-drain plug. The integral structure of the source-drain contact structure is beneficial for reducing the resistance between the source-drain plug and the source-drain contact layer, as well as the contact resistance between the source-drain plug and the source-drain contact layer, thereby improving the electrical connection performance between the source-drain plug and the source-drain contact layer. This, in turn, helps to improve the subsequent RC (resistance-capacitance) delay, reduce power consumption, and increase circuit response speed, thus improving the performance of the semiconductor structure.

[0024] To make the above-mentioned objects, features, and advantages of the embodiments of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. (Reference) Figures 7 to 9 A schematic diagram of an embodiment of the semiconductor structure of the present invention is shown. Figure 7 This is a top view. Figure 8 yes Figure 7Cross-sectional view along the X1-X1 direction. Figure 9 yes Figure 7 Cross-sectional view along the X2-X2 direction.

[0025] In this embodiment, the semiconductor structure includes: a substrate 100; a plurality of gate structures 110 discretely disposed on the substrate 100, each gate structure 110 including a gate contact region 110a for contacting a gate plug 410; source / drain doped regions 120 located within the substrate 100 on both sides of the gate structures 110, each source / drain doped region 120 including a source / drain contact region 120a for contacting a source / drain plug 310, the remaining region serving as a source / drain connection region 120b; and a dielectric structure layer 200 located on the substrate 100 on the side of the gate structures 110 and covering the source / drain doped regions 120a. 0, and the dielectric structure layer 200 also covers the top of the gate structure 110; the source / drain contact structure 300 contacts the source / drain doped region 120. The source / drain contact structure 300 is an integral structure, including a source / drain plug 310 penetrating the dielectric structure layer 200 through the source / drain contact region 120a, and a source / drain contact layer 320 located in the dielectric structure 200 of the source / drain connection region 120b. The top surface of the source / drain contact layer 320 is lower than the top surface of the source / drain plug 310. The source / drain contact structure 300 and the dielectric structure layer 200 form a spaced opening 340 (e.g., Figure 25 and Figure 26 (as shown); a spacer dielectric layer 350, filling the spacer opening 340; a gate plug 410, located on top of the gate structure 110 of the gate contact region 110a and in contact with the gate structure 110.

[0026] The substrate 100 is used to provide a process platform for the formation of semiconductor structures. In this embodiment, the substrate 100 is used to form a fin field-effect transistor (FinFET). Accordingly, the substrate 100 is a three-dimensional substrate, including a substrate (not shown) and fins 100a discretely disposed on the substrate.

[0027] Fin 100a is used to provide a conductive channel for the field-effect transistor. In this embodiment, the substrate is a silicon substrate, and the fin 100a is made of the same material as the substrate. In other embodiments, the substrate and fin may be made of other suitable semiconductor materials.

[0028] In this embodiment, there are multiple fins 100a, and the multiple fins 100a are arranged laterally (e.g., ...). Figure 7 Extending in the X direction (as shown in the middle), and along the longitudinal direction (as shown in the middle X direction) Figure 7 The elements are arranged at intervals (as shown in the Y direction), with the lateral and longitudinal directions perpendicular to each other. In this embodiment, both the lateral and longitudinal directions are parallel to the surface of the substrate 100.

[0029] In other embodiments, depending on the type of transistor to be formed, the substrate may also be other types of three-dimensional substrates. For example, when forming a gate-all-around (GAA) transistor, the substrate includes a substrate and a channel structure layer on the substrate, the channel structure layer including one or more spaced-apart channel layers. In other embodiments, when forming a planar field-effect transistor, the substrate is correspondingly planar.

[0030] When the device is in operation, the gate structure 110 is used to control the opening or closing of the conductive channel. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin 100a and covers part of the top surface and part of the sidewall of the fin 100a. The gate structure 110 extends longitudinally accordingly.

[0031] In this embodiment, the gate structure 110 is a metal gate structure, including a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer. In other embodiments, depending on actual process requirements, the gate structure may also be a polysilicon gate structure.

[0032] The gate structure 110 of the gate contact region 110a is used to contact the gate plug 410, thereby bringing out the electrical properties of the gate structure 110. The remaining area of ​​the gate structure 110 outside the gate contact region 110a is used as the gate spacer region 110b.

[0033] In this embodiment, the semiconductor structure further includes: a gate cap layer 160, located between the top of the gate structure 110 of the gate spacer region 110b and the dielectric structure layer 200; the top surface of the gate structure 110 of the gate contact region 110a is higher than the top surface of the gate structure 110 of the gate spacer region 110b.

[0034] In this embodiment, compared with the gate structure 110 of the gate spacer region 110b, the top surface height of the gate structure 110 of the gate contact region 110a is higher, which is beneficial to reduce the height of the gate plug 410, thereby reducing the difficulty of forming the gate plug 410, increasing the process window for forming the gate plug 410, and also helping to reduce the resistance of the gate plug 410.

[0035] The gate cap layer 160 is used to protect the top of the gate structure 110 during the formation of the semiconductor structure, for example, during the formation of the source-drain contact structure 300, to protect the top of the gate structure 110 and prevent short circuit between the source-drain contact structure 300 and the gate structure 110.

[0036] The gate cap layer 160 is made of a material that is etch-selective with the dielectric structure layer 200. The material of the gate cap layer 160 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the material of the gate cap layer 160 is silicon nitride.

[0037] In this embodiment, the semiconductor structure further includes a sidewall 115 located on the sidewall of the gate structure 110. The sidewall 115 defines the formation region of the source / drain doped region 120 and also protects the sidewall of the gate structure 110. In this embodiment, the material of the sidewall 115 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, and low-k dielectric materials.

[0038] In this embodiment, the gate structure 110 is formed by a process of forming a high-k last metal gate last after forming a high-k gate dielectric layer. Therefore, the semiconductor structure further includes a high-k gate dielectric layer 220, located between the gate structure 110 and the sidewall 115, and between the gate structure 110 and the substrate 100. The high-k gate dielectric layer 220 is used to achieve insulation between the gate structure 110 and the channel. The material of the high-k gate dielectric layer 220 is a high-k dielectric material.

[0039] The source / drain doped regions 120 are used to provide carrier sources. In this embodiment, the source / drain doped regions 120 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 120 are located in the fins 100a on both sides of the gate structure 110.

[0040] In this embodiment, when forming an NMOS transistor, the source / drain doped region 120 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 120 includes a stress layer doped with P-type ions.

[0041] The source / drain doped region 120 of the source / drain contact region 120a is used to contact the source / drain plug 310, thereby bringing out the electrical properties of the source / drain doped region 120. The source / drain doped region 120 of the source / drain connection region 120b is used to contact the source / drain contact layer 320, which is used to realize the electrical connection between the source / drain doped regions 120 located in the plurality of fins 100a.

[0042] The dielectric structure layer 200 is used to achieve isolation between adjacent devices and also to achieve electrical isolation between the source / drain plug 310 and the gate plug 410.

[0043] In this embodiment, the dielectric structure layer 200 is a stacked structure, and the dielectric structure layer 200 includes: a bottom dielectric layer 130, which is located on the substrate 100 on the side of the gate structure 110 and covers the source and drain doped regions 120; and a top dielectric layer 140, which is located on the bottom dielectric layer 130.

[0044] The bottom dielectric layer 130 is used to achieve isolation between adjacent devices. The material of the bottom dielectric layer 130 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, and silicon carbonitride. The top dielectric layer 140 is used to achieve electrical isolation between the gate plug 410 and the source-drain contact structure 300. The material of the top dielectric layer 140 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0045] In this embodiment, the semiconductor structure further includes: an etch barrier structure 210 located on top of the gate structure 110 of the gate contact region 110a; the dielectric structure layer 200 covering the sidewall of the etch barrier structure 210; and the gate plug 410 penetrating the etch barrier structure 210.

[0046] In this embodiment, the top surface of the gate structure 110 of the gate spacer region 110b is lower than the top surface of the gate structure 110 of the gate contact region 110a because a portion of the thickness of the gate structure 110 in the gate spacer region 110b is removed during the formation of the semiconductor structure. The etching barrier structure 210 serves as a mask for removing the portion of the thickness of the gate structure 110 in the gate spacer region 110b. Moreover, the etching barrier structure 210 is located on top of the gate structure 110 in the gate contact region 110a and is also used to pre-occupy a space for forming the gate plug 410. In addition, the etching barrier structure 210 also serves to act as an etching barrier during the formation of the source / drain contact structure 300, preventing the source / drain contact structure 300 from being formed on the gate structure 110 in the gate contact region 110a and short-circuiting with the gate structure 110.

[0047] In this embodiment, the etching barrier structure 210 also extends to cover part of the top surface of the bottom dielectric layer 130 located on both sides of the gate structure 110, thereby increasing the area of ​​the etching barrier structure 210, which is beneficial to further improve the effect of the etching barrier structure 210 as an etching mask and etching barrier.

[0048] In this embodiment, the top dielectric layer 140 covers the sidewall of the etching barrier structure 210, and the top surface of the top dielectric layer 140 is flush with the top surface of the etching barrier structure 210.

[0049] Therefore, the etch barrier structure 210 is selected from a material that has etch selectivity with the dielectric structure layer 200, and the material of the etch barrier structure 210 has an etch selectivity ratio with the material of the gate cap layer 160. The material of the etch barrier structure 210 includes one or more of AlN, Al2O3, SiCN, SiON, SiOC, AlON, Si, Ge, C, and SiO2. As an example, the material of the etch barrier structure 210 is aluminum oxide.

[0050] The thickness of the etch barrier structure 210 should not be too small, otherwise it may lead to poor performance as an etch mask and etch barrier. Conversely, the thickness of the etch barrier structure 210 should not be too large, otherwise the height of the source / drain plug 310 may be too large, increasing the difficulty of forming the source / drain contact structure 30 and potentially causing excessive resistance in the source / drain contact structure 300. Therefore, in this embodiment, the thickness of the etch barrier structure 210 is 50% to 150% of the thickness of the gate cap layer 160.

[0051] As an example, the thickness of the etch barrier structure 210 is the same as the thickness of the gate cap layer 160. Specifically, the thickness of the etch barrier structure 210 is 3 nanometers to 10 nanometers.

[0052] The source / drain contact structure 300 is used to electrically lead out the source / drain doped regions 120. The source / drain contact layer 320 is used to electrically connect the source / drain doped regions 120 located in the plurality of fins 100a, and the source / drain contact plug 310 is used to electrically connect with the metal interconnect.

[0053] Spacing opening 340 (e.g.) Figure 27 (As shown) is used to provide spatial location for forming the spacer dielectric layer.

[0054] In this embodiment, the source / drain contact structure 300 is an integral structure, including a source / drain plug 310 with a higher top surface height and a source / drain contact layer 320 with a lower top surface height. This is because the formation steps of the source / drain contact structure 300 include: forming source / drain contact material, and then removing a portion of the source / drain contact material located in the source / drain connection region 120b. Therefore, the source / drain plug 310 and the source / drain contact layer 320 are formed in the same step, which not only simplifies the process but also eliminates the need for aligning the source / drain plug 310 and the source / drain contact layer 320, correspondingly reducing the formation cost of the source / drain plug 310. The increased process difficulty of 10 increases the process window for forming the source / drain plug 310. Furthermore, the source / drain contact structure 300 formed by the source / drain plug 310 and the source / drain contact layer 320 is an integral structure, which helps to reduce the resistance of the source / drain plug 310 and the source / drain contact layer 320, as well as the contact resistance between the source / drain plug 310 and the source / drain contact layer 320. This correspondingly improves the electrical connection performance between the source / drain plug 310 and the source / drain contact layer 320, thereby improving the subsequent RC (resistance-capacitance) delay, reducing power consumption, and increasing the circuit response speed. The performance of the semiconductor structure is thus improved.

[0055] In this embodiment, the top surface of the source / drain contact layer 320 is lower than the top surface of the source / drain plug 310, thereby reducing the height of the top surface of the source / drain contact layer 320, which in turn reduces the probability of a short circuit between the gate plug 410 and the source / drain contact layer 320, and improves the reliability of the semiconductor structure.

[0056] In this embodiment, the top surface of the source / drain contact layer 320 is lower than the top surface of the bottom dielectric layer 130. Specifically, as an example, the top surface of the source / drain contact layer 320 is lower than the top surface of the gate structure 110 of the gate spacer region 110b, thereby further reducing the height of the top surface of the source / drain contact layer 320, increasing the distance between the top surface of the source / drain contact layer 320 and the bottom surface of the gate plug 410, which in turn helps to significantly reduce the probability of a short circuit between the gate plug 410 and the source / drain contact layer 320.

[0057] In this embodiment, the source / drain contact structure 300 is a strip structure, and the source / drain contact structure 300 is along the longitudinal direction (e.g., Figure 7 Extending in the Y direction (as shown in the middle), the direction perpendicular to the longitudinal direction is the transverse direction (as shown in the middle Y direction). Figure 7 (As shown in the X direction).

[0058] The source / drain contact structure 300 is made of a conductive material. The source / drain contact structure 300 can be a single-layer or multi-layer structure. As an example, the source / drain contact structure 300 includes a main contact structure (not shown) and source / drain contact diffusion barrier layers (not shown) located on the sidewalls and bottom of the main contact structure.

[0059] The source / drain contact diffusion barrier layer is used to improve the adhesion between the main contact structure and the dielectric structure layer 200. In addition, the source / drain contact diffusion barrier layer is also used to prevent the material of the main contact structure from diffusing into the dielectric structure layer 200, thereby improving the problem of electromigration (EM). Furthermore, the source / drain contact diffusion barrier layer is also used to prevent impurities such as carbon atoms and oxygen atoms in the dielectric structure layer 200 from diffusing into the main contact structure, thereby improving the reliability of the semiconductor structure.

[0060] In this embodiment, the main contact structure includes one or more of W, Co, Ru, Cu and Al, and the source / drain contact diffusion barrier layer includes one or more of TiN, Ti, TaN and Ta.

[0061] The spacer dielectric layer 350 is used to fill the spacer opening 340, thereby providing a flat surface for the process, and the spacer dielectric layer 350 is also used to achieve isolation between adjacent devices.

[0062] The material of the spacer dielectric layer 350 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric material, and ultra-low-k dielectric material.

[0063] The gate plug 410 is used to bring out the electrical properties of the gate structure 110, thereby realizing the electrical connection between the gate structure 110 and external circuits or other interconnection structures.

[0064] In this embodiment, the gate plug 410 is located above the gate structure 110 of the active area (AA). The gate plug 410 is a contact over active gate (COAG), which helps to save chip area and thus achieve further reduction in chip size.

[0065] In this embodiment, compared with the gate structure 110 of the gate spacer region 110b, the top surface of the gate structure 110 of the gate contact region 110a is higher, which helps to reduce the height of the gate plug 410, thereby reducing the difficulty of forming the gate plug 410, increasing the process window for forming the gate plug 410, and also helping to reduce the resistance of the gate plug 410. In particular, the gate plug 410 is an active gate contact hole plug, which is more difficult to form. This embodiment helps to significantly reduce the difficulty of the COAG process. Specifically, the height of the gate plug 410 is the same as the thickness of the top dielectric layer 140.

[0066] In this embodiment, the gate plug 410 penetrates the etch barrier structure 210.

[0067] In this embodiment, the gate plug 410 is made of a conductive material. The gate plug 410 has a single-layer or multi-layer structure. As an example, the gate plug 410 includes a main gate plug (not shown) and a gate plug diffusion barrier layer (not shown) located at the bottom and sidewalls of the main gate plug.

[0068] The gate plug diffusion barrier layer is used to improve the adhesion between the main gate plug and the etch barrier structure 210. Furthermore, the gate plug diffusion barrier layer is also used to prevent the material of the main gate plug from diffusing into the etch barrier structure 210 or the dielectric structure layer 200, thereby improving the electromigration problem. In addition, the gate plug diffusion barrier layer is also used to prevent impurities such as carbon atoms and oxygen atoms in the etch barrier structure 210 or the dielectric structure layer 200 from diffusing into the main gate plug, thereby improving the reliability of the semiconductor structure.

[0069] In this embodiment, the material of the main gate plug includes one or more of W, Co, Ru, Cu and Al, and the material of the gate plug diffusion barrier layer includes one or more of TiN, Ti, TaN and Ta.

[0070] In this embodiment, the formation step of the gate plug 410 includes: forming a gate contact hole; and forming the gate plug 410 in the gate contact hole. The material of the etch barrier structure 210 has etch selectivity with the material of the dielectric structure layer 200. Therefore, during the formation of the gate contact hole, there is a high etch selectivity ratio between the etch barrier structure 210 and the top dielectric layer 140, and between the etch barrier structure 210 and the bottom dielectric layer 130. This makes it less likely to cause accidental etching of the top dielectric layer 140 or the bottom dielectric layer 130, thereby enabling self-alignment of the etching. This reduces the process difficulty of forming the gate contact hole, increases the process window for forming the gate contact hole, and facilitates precise control of the shape and position of the gate contact hole. Furthermore, the gate contact hole is less likely to expose the source / drain plug 310.

[0071] Accordingly, the shape, position, and cross-sectional morphology of the gate plug 410 can be controlled, and the probability of bridging between the gate plug 410 and the source / drain plug 310 is low, which is beneficial to improving the reliability of the semiconductor structure. In particular, in this embodiment, the gate plug 410 is an active gate contact hole plug, and the distance between the gate plug 410 and the source / drain plug 310 is closer. This embodiment is beneficial to significantly reduce the probability of bridging between the gate plug 410 and the source / drain plug 310.

[0072] It should be noted that in this embodiment, the gate plug 410 penetrates the etch barrier structure 210, and a portion of the etch barrier structure 210 is retained on the sidewall of the gate plug 410. In other embodiments, depending on the actual process, the etch barrier structure may be completely removed during the formation of the gate plug, and the sidewall of the gate plug may then contact the top dielectric layer.

[0073] In this embodiment, the semiconductor structure further includes: an interconnect dielectric layer 380 (referring to a reference). Figure 33 and Figure 34 A gate interconnect 400 is located on the dielectric structure layer 200 and covers the top surface of the spacer dielectric layer 350 and the source / drain plug 310; a metal interconnect 400 extends through the interconnect dielectric layer 380, the metal interconnect 400 extends laterally and is spaced apart along the longitudinal direction, and the metal interconnect 400 respectively contacts the gate plug 410 and the source / drain plug 310.

[0074] The interconnect dielectric layer 380 is used to achieve electrical isolation between the metal interconnects 400. The interconnect dielectric layer 380 is a metal interlayer dielectric (IMD), and the material of the interconnect dielectric layer 380 is a dielectric material. For a description of the material of the interconnect dielectric layer 380, please refer to the preceding description of the top dielectric layer 140; it will not be repeated here.

[0075] The metal interconnect 400 is used to realize the electrical connection between the gate plug 410 and the source / drain plug 310 and the external circuit.

[0076] In this embodiment, the metal interconnect 400 and the gate plug 410 are integrally formed. This helps to reduce the contact resistance between the gate plug 410 and the metal interconnect 400, improves the electrical connection performance between the gate plug 410 and the metal interconnect 400, and thus optimizes the performance of the semiconductor structure.

[0077] In this embodiment, the material of the metal interconnect 400 is the same as the material of the gate plug 410.

[0078] It should be noted that, in this embodiment, for ease of illustration and explanation, only the dielectric structure layer 200, the interconnect dielectric layer 380, the high-k gate dielectric layer 220, and the sidewall 115 are shown in the cross-sectional view.

[0079] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 10 to 37 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. The semiconductor structure formation method of this embodiment will be described in detail below with reference to the accompanying drawings.

[0080] refer to Figures 10 to 11, Figure 10 This is a top view. Figure 11 yes Figure 10 A cross-sectional view along the X1-X1 direction shows a substrate 100 on which a plurality of discrete gate structures 110 are formed. Each gate structure 110 includes a gate contact region 110a for contacting a gate plug. Source-drain doped regions 120 are formed in the substrate 100 on both sides of the gate structure 110. Each source-drain doped region 120 includes a source-drain contact region 120a for contacting a source-drain plug, and the remaining region serves as a source-drain connection region 120b. A bottom dielectric layer 130 is formed on the substrate 100 on the side of the gate structure 110, covering the source-drain doped regions 120.

[0081] The substrate 100 is used to provide a process platform for subsequent process fabrication. In this embodiment, the substrate 100 is used to form a fin field-effect transistor (FinFET), and the substrate 100 is a three-dimensional substrate, including a substrate (not shown) and fins 100a discretely disposed on the substrate.

[0082] Fin 100a is used to provide a conductive channel for the field-effect transistor. In this embodiment, the substrate is a silicon substrate, and the fin 100a is made of the same material as the substrate. In other embodiments, the substrate and fin may be made of other suitable semiconductor materials.

[0083] In this embodiment, there are multiple fins 100a, and the multiple fins 100a are arranged laterally (e.g., ...). Figure 10 Extending in the X direction (as shown in the middle), and along the longitudinal direction (as shown in the middle X direction) Figure 10 The elements are arranged at intervals (as shown in the Y direction), with the lateral and longitudinal directions perpendicular to each other. In this embodiment, both the lateral and longitudinal directions are parallel to the surface of the substrate 100.

[0084] In other embodiments, the substrate may also be other types of three-dimensional substrates, depending on the type of transistor to be formed. For example, when forming a gate-all-around (GAA) transistor, the substrate includes a substrate and a channel structure layer on the substrate, the channel structure layer including one or more spaced-apart channel layers. In other embodiments, when forming a planar field-effect transistor, the substrate is correspondingly planar.

[0085] When the device is in operation, the gate structure 110 is used to control the opening or closing of the conductive channel. In this embodiment, the gate structure 110 is located on the substrate, and the gate structure 110 spans the fin 100a and covers part of the top surface and part of the sidewall of the fin 100a. The gate structure 110 extends longitudinally accordingly.

[0086] In this embodiment, the gate structure 110 is a metal gate structure, including a work function layer (not shown) and a gate electrode layer (not shown) located on the work function layer. In other embodiments, depending on actual process requirements, the gate structure may also be a polysilicon gate structure.

[0087] The gate structure 110 of the gate contact region 110a is used for subsequent contact with the gate plug, thereby bringing out the electrical properties of the gate structure 110. The remaining area of ​​the gate structure 110 outside the gate contact region 110a is used as the gate spacer region 110b.

[0088] In this embodiment, a sidewall 115 is also formed on the sidewall of the gate structure 110. The sidewall 115 is used to define the formation region of the source / drain doped region 120 and to protect the sidewall of the gate structure 110. In this embodiment, the material of the sidewall 115 includes one or more of silicon nitride, silicon carbonitride, silicon carbide, silicon carbide, and low-k dielectric materials.

[0089] In this embodiment, the gate structure 110 is formed by a process of forming a high-k last metal gate last after forming a high-k gate dielectric layer. A high-k gate dielectric layer 220 is also formed between the gate structure 110 and the sidewall 115, and between the gate structure 110 and the substrate 100. The high-k gate dielectric layer 220 is used to achieve insulation between the gate structure 110 and the channel. The material of the high-k gate dielectric layer 220 is a high-k dielectric material.

[0090] The source / drain doped regions 120 are used to provide carrier sources. In this embodiment, the source / drain doped regions 120 are also used to provide stress to the channel during device operation to improve carrier mobility. In this embodiment, the source / drain doped regions 120 are located in the fins 100a on both sides of the gate structure 110.

[0091] In this embodiment, when forming an NMOS transistor, the source / drain doped region 120 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doped region 120 includes a stress layer doped with P-type ions.

[0092] The source / drain doped region 120 of the source / drain contact region 120a is used to contact the subsequent source / drain plug, thereby bringing out the electrical properties of the source / drain doped region 120. Subsequently, a source / drain contact layer is formed to contact the source / drain doped region 120 of the source / drain connection region 120b. The source / drain contact layer is used to realize the electrical connection between the source / drain doped regions 120 located on the plurality of fins 100a.

[0093] The bottom dielectric layer 130 is used to achieve isolation between adjacent devices. The material of the bottom dielectric layer 130 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride.

[0094] It should be noted that, in this embodiment, for ease of illustration and explanation, only the bottom dielectric layer 140, the high-k gate dielectric layer 220, and the sidewall 115 are shown in the cross-sectional view.

[0095] Reference Figures 12 to 14 , Figure 12 This is a top view. Figure 13 for Figure 12 Cross-sectional view along the X1-X1 direction, Figure 14 for Figure 12 A cross-sectional view along the X2-X2 direction shows that, after providing the substrate 100, the formation method further includes: forming an etch barrier structure 210 covering the top of the gate structure 110 of the gate contact region 110a.

[0096] Subsequent steps include: removing a portion of the thickness of the gate structure 110 located in the gate spacer region 110b, forming a top dielectric layer on the bottom dielectric layer 130; forming source / drain contact material that penetrates the top of the source / drain doped region 120 and the bottom dielectric layer and the top dielectric layer, and contacting the source / drain doped region 120.

[0097] The etching barrier structure 210 serves as a mask for removing a portion of the thickness of the gate structure 110 located in the gate spacer region 110b. Furthermore, the etching barrier structure 210 is located on top of the gate structure 110 in the gate contact region 110a and is also used to pre-occupy a space for forming a gate plug. In addition, the etching barrier structure 210 also serves to act as an etching barrier during the subsequent formation of source and drain contact materials, preventing the source and drain contact materials from forming on the gate structure 110 in the gate contact region 110a and short-circuiting with the gate structure 110.

[0098] In this embodiment, the etching barrier structure 210 also extends to cover part of the top surface of the bottom dielectric layer 130 located on both sides of the gate structure 110, thereby increasing the area of ​​the etching barrier structure 210, which is beneficial to improving the effect of the etching barrier structure 210 as an etching mask and etching barrier.

[0099] Therefore, the etching barrier structure 210 is made of a material that has etching selectivity for both the bottom dielectric layer 130 and the top dielectric layer. Furthermore, after removing a portion of the thick gate structure 110 located in the gate spacer region 110b, the process includes forming a gate capping layer on top of the gate spacer region 110b. Forming the gate capping layer includes an etching process for the gate capping layer material. The material of the etching barrier structure 210 needs to have an etching selectivity ratio with the material of the gate capping layer.

[0100] The material of the etching barrier structure 210 includes one or more of AlN, Al2O3, SiCN, SiON, SiOC, AlON, Si, Ge, C, and SiO2. As an example, the material of the etching barrier structure 210 is Al2O3.

[0101] The thickness of the etch barrier structure 210 should not be too small, otherwise it may result in poor performance as an etch mask and etch barrier. Conversely, the thickness of the etch barrier structure 210 should not be too large, otherwise it may lead to excessive height of the subsequent source / drain contact material, increasing the difficulty of forming the source / drain contact material and causing excessively high resistance in the source / drain contact structure. Therefore, in this embodiment, the thickness of the etch barrier structure 210 is 50% to 150% of the thickness of the subsequent gate cap layer.

[0102] As an example, the thickness of the etch barrier structure 210 is the same as the thickness of the subsequent gate cap layer. Specifically, the thickness of the etch barrier structure 210 is 3 nanometers to 20 nanometers.

[0103] In this embodiment, the etch barrier structure 210 is located on top of the gate structure 110 in the gate contact region 110a, and is used to pre-occupy a space for forming the gate plug. Therefore, the position of the etch barrier structure 210 corresponds to the position of the gate plug. The etch barrier structure 210 can be formed using the photomask used when forming the gate plug, so that no additional photomask is needed, which is beneficial to saving costs and can also improve compatibility with existing processes.

[0104] As an example, the step of forming the etch barrier structure 210 includes: forming an etch barrier material (not shown) on the bottom dielectric layer 130 to cover the gate structure 110; patterning the etch barrier material, and retaining the etch barrier material located on top of the gate structure 110 in the gate contact region 110a for use as the etch barrier structure 210. The etch barrier material is patterned using a photomask used when forming the gate plug.

[0105] Reference Figures 12 to 19 The method for forming the semiconductor structure further includes: removing a portion of the thickness of the gate structure 110 located in the gate spacer region 110b, so that the remaining gate structure 110 and the bottom dielectric layer 140 form a gate recess 150; and forming a gate cap layer 160 in the gate recess 150.

[0106] The gate recess 150 is used to provide space for the formation of the gate cap layer 160.

[0107] In this embodiment, a portion of the thick gate structure 110 located in the gate spacer region 110b is removed, so that the gate structure 110 located in the gate contact region 110a is not etched. Compared with the gate structure 110 in the gate spacer region 110b, the top surface of the gate structure 110 in the gate contact region 110a is higher, which is beneficial to reduce the height of the subsequent gate plug, thereby reducing the difficulty of forming the gate plug, increasing the process window for forming the gate plug, and also helping to reduce the resistance of the gate plug.

[0108] Specifically, using the etching barrier structure 210 as a mask, a portion of the thickness of the gate structure 110 located in the gate spacer region 110b is removed.

[0109] In this embodiment, a dry etching process is used to remove a portion of the gate structure 110 located in the gate spacer region 110b. The gate structure 110 is made of metal. The dry etching process is easy to implement for etching metal materials, and it is also beneficial for achieving a high etching selectivity and etching profile control, thereby facilitating precise control of the etching thickness of the gate structure 110.

[0110] The gate cap layer 160 is used to protect the top of the gate structure 110 in subsequent processes, for example, during the formation of the source-drain contact structure, to protect the top of the gate structure 110 and prevent short circuits between the source-drain contact structure and the gate structure 110.

[0111] Therefore, the gate cap layer 160 is made of a material that has etch selectivity for the bottom dielectric layer 130. At the same time, the material of the gate cap layer 160 also has etch selectivity with the etch barrier structure 210, so as to ensure that the etch barrier structure 210 can be retained during the formation of the gate cap layer 160.

[0112] The gate cap layer 160 is made of one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. As an example, the gate cap layer 160 is made of silicon nitride.

[0113] The steps for forming the gate cap layer 160 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0114] like Figure 15 and Figure 16 As shown, Figure 15 Based on Figure 13 Cross-sectional view, Figure 16 Based on Figure 14The cross-sectional view shows a gate cap material layer 155 formed, filling the gate recess 150 and covering the bottom dielectric layer 130 and the etch barrier structure 210. The gate cap material layer 155 is formed using a deposition process (e.g., chemical vapor deposition, atomic layer deposition, etc.).

[0115] like Figures 17 to 19 As shown, Figure 17 This is a top view. Figure 18 for Figure 17 Cross-sectional view along the X1-X1 direction, Figure 19 for Figure 17 A cross-sectional view along the X2-X2 direction shows that an etching process is used to remove the gate cap material layer 155 located on the top surface of the bottom dielectric layer 130 and the etching barrier structure 210. The remaining gate cap material layer 155 located in the gate recess 150 is used as the gate cap layer 160.

[0116] In this embodiment, there is an etching selectivity ratio between the gate cap material layer 155 and the etch barrier structure 210, thereby reducing the probability of the etching process causing accidental etching of the etch barrier structure 210 and allowing the etch barrier structure 210 to be retained. Specifically, the etching process includes an isotropic dry etching process, which enables isotropic etching and removes the gate cap material layer 155 located on the bottom surface and sidewalls of the etch barrier structure 210, as well as on the top surface of the bottom dielectric layer 130.

[0117] refer to Figures 20 to 21 , Figure 20 Based on Figure 18 Cross-sectional view, Figure 21 Based on Figure 19 The cross-sectional view shows that a top dielectric layer 140 is formed on the bottom dielectric layer 130.

[0118] The bottom dielectric layer 130 and the top dielectric layer 140 are used to form the dielectric structure layer 200.

[0119] The top dielectric layer 140 is used to achieve electrical isolation between the gate plug and the source / drain contact structure. The material of the top dielectric layer 140 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, low-k dielectric materials, and ultra-low-k dielectric materials.

[0120] In this embodiment, the top dielectric layer 140 covers the sidewall of the etching barrier structure 210.

[0121] In this embodiment, for ease of illustration and explanation, only the top dielectric layer 140 is shown in the cross-sectional view.

[0122] refer to Figures 22 to 24, Figure 22 This is a top view. Figure 23 for Figure 22 Cross-sectional view along the X1-X1 direction, Figure 24 for Figure 22 In a cross-sectional view along the X2-X2 direction, a source / drain contact material 370 is formed, penetrating the bottom dielectric layer 130 and the top dielectric layer 140 of the source / drain doped region 120, and is in contact with the source / drain doped region 120. The source / drain contact material 370 is used to form a source / drain contact structure to bring out the electrical properties of the source / drain doped region 120.

[0123] In this embodiment, the source / drain contact material 370 has a strip-shaped structure and extends along the longitudinal direction.

[0124] Therefore, the source / drain contact material 370 is made of a conductive material. The source / drain contact material 370 has a single-layer or multi-layer structure. As an example, the source / drain contact material 370 includes a main contact material (not shown) and source / drain contact diffusion barrier materials (not shown) located on the sidewalls and bottom of the main contact material.

[0125] In this embodiment, the main contact material includes one or more of W, Co, Ru, Cu and Al, and the source / drain contact diffusion barrier material includes one or more of TiN, Ti, TaN and Ta.

[0126] In this embodiment, the step of forming the source / drain contact material 370 includes: forming a source / drain contact opening (not shown) that penetrates the dielectric structure layer 200 to expose the source / drain doped region 120; and forming the source / drain contact material 370 in the source / drain contact opening.

[0127] refer to Figures 25 to 27 , Figure 25 This is a top view. Figure 26 for Figure 25 Cross-sectional view along the X1-X1 direction, Figure 27 for Figure 25 In a cross-sectional view along the X2-X2 direction, after the source / drain contact material 370 is formed and before removing a portion of the thickness of the source / drain contact material 370 located in the source / drain connection region 120b, the forming method further includes: forming a hard mask layer 355 on top of the source / drain contact material 370 in the source / drain contact region 120b.

[0128] The hard mask layer 355 serves as a mask for subsequent removal of a portion of the source-drain contact material 370 located in the source-drain connection region 120b. The position of the hard mask layer 355 corresponds to the formation position of the source-drain plug.

[0129] Therefore, the hard mask layer 355 is selected from materials that have etching selectivity with the source / drain contact material 370 to ensure the etching masking function of the hard mask layer 355. In this embodiment, the material of the hard mask layer 355 includes one or more of AlN, Al2O3, SiCN, SiON, SiOC, AlON, Si, Ge, C, and SiO2. As an example, the material of the hard mask layer 355 is AlN.

[0130] In this embodiment, the hard mask layer 355 is positioned corresponding to the formation position of the source / drain plug. Therefore, the hard mask layer 355 can be formed using the photomask used when forming the source / drain plug, thus eliminating the need for an additional photomask and saving costs.

[0131] As an example, the step of forming the hard mask layer 355 includes: forming a hard mask material layer (not shown) on the top dielectric layer 140, covering the source / drain contact material 370; patterning the hard mask material layer, and retaining the hard mask material layer located on the source / drain contact region 120a as the hard mask layer 355. The hard mask material layer is patterned using a photomask used when forming the source / drain plugs.

[0132] Continue to refer to Figures 25 to 27 , Figure 25 This is a top view. Figure 26 for Figure 25 Cross-sectional view along the X1-X1 direction, Figure 27 for Figure 25 A cross-sectional view along the X2-X2 direction shows that a portion of the source / drain contact material 370 in the source / drain connection region 120b is removed. The remaining source / drain contact material 370 in the source / drain connection region 120b is used as a source / drain contact layer. The source / drain contact material 370 in the source / drain contact region 120a is used as a source / drain plug 310. The source / drain plug 310 and the source / drain contact layer 320 are used to form a source / drain contact structure 300. The source / drain contact structure 300, the bottom dielectric layer 130, and the top dielectric layer 140 form a spaced opening 340.

[0133] The source / drain contact structure 300 is used to electrically bring out the source / drain doped regions 120. The source / drain contact layer 320 is used to electrically connect the source / drain doped regions 120 located in the plurality of fins 100a, and the source / drain contact plug 310 is used to electrically connect with the subsequently formed metal interconnects.

[0134] The spacer opening 340 is used to provide space for forming the spacer medium layer.

[0135] In this embodiment, the source / drain contact material 370 is formed first, and then a portion of the source / drain contact material 370 located in the source / drain connection region 120b is removed to form the source / drain contact layer 320 and the source / drain plug 310 located in the source / drain contact region 120a. This allows the source / drain plug 310 and the source / drain contact layer 320 to be formed in the same step, simplifying the process and eliminating the need for alignment between the source / drain plug 310 and the source / drain contact layer 320. This helps prevent alignment misalignment (overlay) between the source / drain plug 310 and the source / drain contact layer 320. The problem is that the process difficulty of forming the source-drain plug 310 is reduced and the process window for forming the source-drain plug 310 is increased. Furthermore, the source-drain contact structure 300 formed by the source-drain plug 310 and the source-drain contact layer 320 is an integral structure, which helps to reduce the resistance of the source-drain plug 310 and the source-drain contact layer 320, as well as the contact resistance between the source-drain plug 310 and the source-drain contact layer 320. This improves the electrical connection performance between the source-drain plug 310 and the source-drain contact layer 320, thereby improving the subsequent RC (resistance-capacitance) delay, reducing power consumption, and increasing the circuit response speed. The performance of the semiconductor structure is thus improved.

[0136] Accordingly, the top surface of the source / drain contact layer 320 is lower than the top surface of the source / drain plug 310.

[0137] In this embodiment, by removing a portion of the source / drain contact material 370 located in the source / drain connection region 120b, the top surface height of the source / drain contact layer 320 is reduced, thereby reducing the probability of a short circuit between the subsequent gate plug and the source / drain contact layer 320 and improving the reliability of the semiconductor structure.

[0138] In this embodiment, the top surface of the source / drain contact layer 320 is lower than the top surface of the bottom dielectric layer 130. Specifically, as an example, the top surface of the source / drain contact layer 320 is lower than the top surface of the gate structure 110 of the gate spacer region 110b, thereby further reducing the height of the top surface of the source / drain contact layer 320, increasing the distance between the top surface of the source / drain contact layer 320 and the bottom surface of the gate plug, which in turn helps to significantly reduce the probability of a short circuit between the gate plug and the source / drain contact layer 320.

[0139] In this embodiment, after removing a portion of the source / drain contact material 370 located in the source / drain connection region 120b, the source / drain contact structure 300 includes a main contact structure (not shown) and source / drain contact diffusion barrier layers (not shown) located on the sidewalls and bottom of the main contact structure.

[0140] The source / drain contact diffusion barrier layer is used to improve the adhesion between the main contact structure and the dielectric structure layer 200. In addition, the source / drain contact diffusion barrier layer is also used to prevent the material of the main contact structure from diffusing into the dielectric structure layer 200, thereby improving the electromigration problem. Furthermore, the source / drain contact diffusion barrier layer is also used to prevent impurities such as carbon atoms and oxygen atoms in the dielectric structure layer 200 from diffusing into the main contact structure, thereby improving the reliability of the semiconductor structure.

[0141] For a description of the material of the source-drain contact structure 300, please refer to the aforementioned detailed description of the material of the source-drain contact material 370, which will not be repeated here.

[0142] In this embodiment, the hard mask layer 355 is used as a mask to remove a portion of the source / drain contact material 370 located in the source / drain connection region 120b.

[0143] In this embodiment, a dry etching process is used to remove a portion of the source / drain contact material 370 located in the source / drain connection region 120b. Specifically, the dry etching process is an anisotropic dry etching process. Anisotropic dry etching has the characteristics of anisotropic etching, which is beneficial for precise control of the removal thickness of the source / drain contact material 370 and also helps to improve the cross-sectional morphology quality of the spacer opening 340. The etching gas used in the dry etching process includes etching gases such as SF6 used for etching metallic materials.

[0144] In this embodiment, both the gate structure 110 and the source / drain contact structure 300 are along the longitudinal direction (e.g., Figure 25 Extending in the Y direction (as shown in the middle), the direction perpendicular to the longitudinal direction is the transverse direction (as shown in the middle Y direction). Figure 25 (As shown in the X direction).

[0145] refer to Figures 28 to 32 The spacer medium layer 350 is filled in the spacer opening 340.

[0146] The spacer dielectric layer 350 is used to fill the spacer opening 340, thereby providing a flat surface for subsequent process manufacturing. The spacer dielectric layer 350 is also used to achieve isolation between adjacent devices.

[0147] The material of the spacer dielectric layer 350 is a dielectric material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, silicon carbonitride, low-k dielectric material, and ultra-low-k dielectric material.

[0148] In this embodiment, the step of forming the spacer dielectric layer 340 includes the following steps.

[0149] like Figures 28 to 29 As shown, Figure 28 For based on Figure 26Cross-sectional view, Figure 29 For based on Figure 27 The cross-sectional view shows that the spaced openings 340 are filled with dielectric material 360, which is also formed on the top dielectric layer 140. In this embodiment, the dielectric material 360 is also formed on the hard mask layer 355.

[0150] In this embodiment, the process of filling the spacer opening 340 with the medium material 360 includes one or more of the following: flowable chemical vapor deposition (FCVD), spin coating, and atomic layer deposition.

[0151] As an example, the dielectric material 360 is formed using a flow-through chemical vapor deposition (FCVD) process. The FCVD process has good filling capabilities and is suitable for filling openings with high aspect ratios. This improves the filling quality of the dielectric material 360 within the spacer openings 340, reduces the probability of voids or other defects forming within the dielectric material 360, and consequently improves the formation quality of the spacer dielectric layer.

[0152] like Figures 30 to 32 As shown, Figure 30 This is a top view. Figure 31 for Figure 30 Cross-sectional view along the X1-X1 direction, Figure 32 for Figure 30 A cross-sectional view along the X2-X2 direction shows that, using a planarization process, the dielectric material 360 above the top surface of the top dielectric layer 140 is removed, and the remaining dielectric material 360 located in the spacer opening 340 is used as the spacer dielectric layer 350.

[0153] In this embodiment, the forming method further includes removing the hard mask layer 355 during the process of removing the dielectric material 360 above the top surface of the top dielectric layer 140, thereby simplifying the process steps and improving process compatibility.

[0154] In this embodiment, the planarization process includes chemical mechanical planarization (CMP). CMP is a global planarization process that facilitates the comprehensive planarization of various materials with different properties. This allows for the removal of dielectric material 360 and hard mask layer 355 above the top surface of the top dielectric layer 140 in the same step, and also improves the flatness of the top surfaces of the spacer dielectric layer 350, the top dielectric layer 140, and the source / drain plug 310.

[0155] refer to Figures 33 to 34 , Figure 33 For based on Figure 31 Cross-sectional view, Figure 34 For based on Figure 32The cross-sectional view shows that, after forming the spacer dielectric layer 350, the forming method further includes: forming an interconnect dielectric layer 380 on the top dielectric layer 140 and the spacer dielectric layer 350, covering the source / drain plug 310.

[0156] Subsequent steps also include: metal interconnects in the interconnect dielectric layer 380, the interconnect dielectric layer 380 being used to achieve electrical isolation between the metal interconnects.

[0157] The interconnect dielectric layer 380 is a metal interlayer dielectric (IMD) layer, and the material of the interconnect dielectric layer 380 is a dielectric material. For a description of the material of the interconnect dielectric layer 380, please refer to the preceding description of the top dielectric layer 140; it will not be repeated here.

[0158] It should be noted that, in this embodiment, before forming the interconnect dielectric layer 380, the forming method further includes: forming an etch stop layer 390 on the top dielectric layer 140 and the spacer dielectric layer 350.

[0159] The etch stop layer 390 is used to temporarily define the etch stop position during the subsequent formation of the gate plug, so as to improve the consistency of the etch position and help reduce damage to the source-drain plug 310.

[0160] In this embodiment, for ease of illustration and explanation, only the interconnect dielectric layer 380 and the etch stop layer 390 are shown in the cross-sectional view.

[0161] refer to Figures 35 to 37 , Figure 35 This is a top view. Figure 36 for Figure 35 Cross-sectional view along the X1-X1 direction, Figure 37 for Figure 35 In the cross-sectional view along the X2-X2 direction, after the spacer dielectric layer 350 is formed, a gate plug 410 is formed that penetrates the top dielectric layer 140 above the gate contact region 110a and contacts the top of the gate structure 110 of the gate contact region 110a.

[0162] The gate plug 410 is used to bring out the electrical properties of the gate structure 110, thereby realizing the electrical connection between the gate structure 110 and external circuits or other interconnection structures.

[0163] In this embodiment, the gate plug 410 is in contact with the gate structure 110 of the active region. The gate plug 410 is a contact over active gate (COAG) plug, which helps to save chip area and thus achieve further reduction in chip size.

[0164] In this embodiment, before forming the top dielectric layer 140, a portion of the gate structure 110 located in the gate spacer region 110b is removed, while the gate structure 110 located in the gate contact region 110a is not etched. This results in a higher top surface of the gate structure 110 in the gate contact region 110a, which helps reduce the height of the gate plug 410, thereby reducing the difficulty of forming the gate plug 410, increasing the process window for forming the gate plug 410, and also helping to reduce the resistance of the gate plug 410. In particular, in this embodiment, the gate plug 410 is an active gate contact hole plug, which is more difficult to form. Therefore, this embodiment significantly reduces the difficulty of the COAG process.

[0165] Specifically, the height of the gate plug 410 is the same as the thickness of the top dielectric layer 140.

[0166] In this embodiment, the gate plug 410 penetrates the etch barrier structure 210.

[0167] In this embodiment, the gate plug 410 is made of a conductive material. The gate plug 410 has a single-layer or multi-layer structure. As an example, the gate plug 410 includes a main gate plug (not shown) and a gate plug diffusion barrier layer (not shown) located at the bottom and sidewalls of the main gate plug.

[0168] The gate plug diffusion barrier layer is used to improve the adhesion between the main gate plug and the etch barrier structure 210. Furthermore, the gate plug diffusion barrier layer is also used to prevent the material of the main gate plug from diffusing into the etch barrier structure 210 or the dielectric structure layer 200, thereby improving the electromigration problem. In addition, the gate plug diffusion barrier layer is also used to prevent impurities such as carbon atoms and oxygen atoms in the etch barrier structure 210 or the dielectric structure layer 200 from diffusing into the main gate plug, thereby improving the reliability of the semiconductor structure.

[0169] In this embodiment, the material of the main gate plug includes one or more of W, Co, Ru, Cu and Al, and the material of the gate plug diffusion barrier layer includes one or more of TiN, Ti, TaN and Ta.

[0170] In this embodiment, the step of forming the gate plug 410 includes: forming a gate contact hole (not shown) through the etch barrier structure 210 to expose the top of the gate structure 110 of the gate contact region 110a; and forming the gate plug 410 in the gate contact hole.

[0171] The material of the etching barrier structure 210 has etching selectivity with the material of the top dielectric layer 140 or the bottom dielectric layer 130. Therefore, during the formation of the gate contact hole, there is a high etching selectivity between the etching barrier structure 210 and the top dielectric layer 140, and between the etching barrier structure 210 and the bottom dielectric layer 130. It is not easy to cause mis-etching of the top dielectric layer 140 or the bottom dielectric layer 130. Correspondingly, self-alignment of etching can be achieved, which reduces the process difficulty of forming the gate contact hole, increases the process window for forming the gate contact hole, and is conducive to precise control of the shape and position of the gate contact hole. Moreover, the gate contact hole is not easy to expose the source / drain plug 310.

[0172] Accordingly, after the gate plug 410 is formed in the gate contact hole, the shape, position, and cross-sectional morphology of the gate plug 410 can be controlled, and the probability of bridging between the gate plug 410 and the source / drain plug 310 is low, which is beneficial to improving the reliability of the semiconductor structure. The gate plug 410 correspondingly penetrates the etch barrier structure 210. In particular, in this embodiment, the gate plug 410 is an active gate contact hole plug, and the distance between the gate plug 410 and the source / drain plug 310 is closer. This embodiment is beneficial to significantly reduce the probability of bridging between the gate plug 410 and the source / drain plug 310.

[0173] It should be noted that in this embodiment, the gate plug 410 penetrates the etch barrier structure 210, and a portion of the etch barrier structure 210 is retained on the sidewall of the gate plug 410. In other embodiments, depending on the actual process, the etch barrier structure can be completely removed during the formation of the gate plug, and the sidewall of the gate plug will then contact the top dielectric layer.

[0174] In this embodiment, the gate plug 410 is formed after the interconnect dielectric layer 380 is formed.

[0175] In the step of forming the gate plug 410, the method of forming the semiconductor structure further includes: forming a laterally (e.g., ...) structure in the interconnect dielectric layer 380. Figure 35 Extending in the X direction and along the longitudinal direction (as shown in the middle X direction) Figure 35 Metal interconnects 400 are arranged at intervals (as shown in the Y direction), and the metal interconnects 400 are respectively in contact with the gate plug 410 and the source / drain plug 310.

[0176] The metal interconnect 400 is used to realize the electrical connection between the gate plug 410 and the source / drain plug 310 and the external circuit. In this embodiment, by forming the metal interconnect 400 and the gate plug 410 in the same step, the processes of forming the metal interconnect 400 and forming the gate plug 410 are integrated, which improves the process integration and process compatibility, and also simplifies the process steps.

[0177] In this embodiment, the steps of forming the metal interconnect 400 and the gate plug 410 include: forming a plurality of interconnect trenches (not shown) that extend laterally and penetrate the interconnect dielectric layer 380; on a projection plane parallel to the substrate 100, the interconnect trenches respectively span the top of the source / drain plug 310 and the top of the gate structure 110 of the gate contact region 110a; forming a gate contact hole (not shown) in the top dielectric layer 140 above the top of the gate structure 110, which communicates with the interconnect trenches; filling the gate contact hole and the interconnect trenches with conductive material to form the gate plug 410 located in the gate contact hole and the metal interconnect 400 located in the interconnect trenches.

[0178] Accordingly, in this embodiment, during the formation of the interconnect trench, the extension direction of the interconnect trench is perpendicular to the extension direction of the gate structure 110 and the source / drain contact structure 300, and the interconnect trench exposes the top of the source / drain plug 310 and the top of the etch barrier structure 210, respectively.

[0179] In this embodiment, conductive material is filled into the gate contact hole and interconnect trench in the same step to form a gate plug 410 and a metal interconnect 400. The gate plug 410 and the metal interconnect 400 are respectively integral structures, which helps to reduce the contact resistance between the gate plug 410 and the metal interconnect 400, improve the electrical connection performance between the gate plug 410 and the metal interconnect 400, and thus optimize the performance of the semiconductor structure. Accordingly, the material of the metal interconnect 400 is the same as the material of the gate plug 410.

[0180] In this embodiment, the metal interconnect 200 also penetrates the etch stop layer 390.

[0181] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; Multiple gate structures discretely disposed on the substrate, each gate structure including a gate contact region for contacting a gate plug; The source / drain doped regions are located in the substrate on both sides of the gate structure. The source / drain doped regions include source / drain contact regions for contacting the source / drain plugs, and the remaining regions serve as source / drain connection regions. A dielectric structure layer is located on a substrate on the side of the gate structure and covers the source and drain doped regions, and the dielectric structure layer also covers the top of the gate structure; A source / drain contact structure is in contact with the source / drain doped region. The source / drain contact structure is an integral structure, including a source / drain plug that penetrates the dielectric structure layer of the source / drain contact region and a source / drain contact layer in the dielectric structure of the source / drain connection region. The top surface of the source / drain contact layer is lower than the top surface of the source / drain plug. The source / drain contact structure and the dielectric structure layer form a spaced opening. A spacer medium layer is used to fill the spacer opening; The material of the spacer dielectric layer is a dielectric material; A gate plug is located on top of the gate structure in the gate contact area and is in contact with the gate structure.

2. The semiconductor structure as described in claim 1, characterized in that, The dielectric structure layer includes: a bottom dielectric layer located on the substrate on the side of the gate structure and covering the source / drain doped regions; and a top dielectric layer located on the bottom dielectric layer.

3. The semiconductor structure as described in claim 2, characterized in that, The top surface of the source / drain contact layer is lower than the top surface of the bottom dielectric layer.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a gate cap layer, located between the top of the gate structure in the gate spacer region and the dielectric structure layer; The top surface of the gate structure in the gate contact region is higher than the top surface of the gate structure in the gate spacer region.

5. The semiconductor structure as described in claim 4, characterized in that, The top surface of the source / drain contact layer is lower than the top surface of the gate structure of the gate spacer region.

6. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: an etch barrier structure located on top of the gate structure in the gate contact region; the dielectric structure layer covering the sidewalls of the etch barrier structure; and the gate plug penetrating the etch barrier structure.

7. The semiconductor structure as described in claim 6, characterized in that, The material of the etching barrier structure includes one or more of AlN, Al2O3, SiCN, SiON, SiOC, AlON, Si, Ge, C, and SiO2.

8. The semiconductor structure as described in claim 6, characterized in that, The thickness of the etch barrier structure is 50% to 150% of the thickness of the gate cap layer.

9. The semiconductor structure as described in claim 1, characterized in that, Both the gate structure and the source / drain contact structure extend longitudinally, and the direction perpendicular to the longitudinal direction is the transverse direction. The semiconductor structure further includes: an interconnect dielectric layer located on the dielectric structure layer and covering the top surface of the spacer dielectric layer and the source / drain plug; Metal interconnects extend through the interconnect dielectric layer, the metal interconnects extend laterally and are spaced apart longitudinally, and the metal interconnects respectively contact the gate plug and the source / drain plug.

10. The semiconductor structure as described in claim 9, characterized in that, The metal interconnect and the gate plug are an integral structure.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a plurality of discrete gate structures are formed. Each gate structure includes a gate contact region for contacting a gate plug. Source and drain doped regions are formed in the substrate on both sides of the gate structure. Each source and drain doped region includes a source and drain contact region for contacting a source and drain plug. The remaining region serves as a source and drain connection region. A bottom dielectric layer is formed on the substrate on the side of the gate structure to cover the source and drain doped regions. A top dielectric layer is formed on the bottom dielectric layer; A source / drain contact material is formed that penetrates the bottom dielectric layer and the top dielectric layer of the source / drain doped region and contacts the source / drain doped region; A portion of the source / drain contact material of a certain thickness is removed from the source / drain connection area. The remaining source / drain contact material in the source / drain connection area is used as a source / drain contact layer. The source / drain contact material in the source / drain contact area is used as a source / drain plug. The source / drain plug and the source / drain contact layer are used to form a source / drain contact structure. The source / drain contact structure, the bottom dielectric layer, and the top dielectric layer form a spaced opening. The spacer opening is filled with a spacer dielectric layer; The material of the spacer dielectric layer is a dielectric material; After the spacer dielectric layer is formed, a gate plug is formed that extends through the top dielectric layer above the gate contact region and contacts the top of the gate structure of the gate region.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The remaining area outside the gate contact region in the gate structure is called the gate spacer region. After providing the substrate and before forming the top dielectric layer, the method for forming the semiconductor structure further includes: removing a portion of the thickness of the gate structure located in the gate spacing region, so that the remaining gate structure and the bottom dielectric layer form a gate recess; A gate cap layer is formed in the gate groove.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After providing the substrate, and before removing a portion of the thickness of the gate structure located in the gate spacer region, the method of forming the semiconductor structure further includes: forming an etch barrier structure covering the top of the gate structure covering the gate contact region; Using the etching barrier structure as a mask, a portion of the gate structure with a certain thickness located in the gate spacer region is removed; During the formation of the top dielectric layer, the top dielectric layer covers the sidewalls of the etching barrier structure; In the step of forming the gate plug, the gate plug penetrates the etch barrier structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of forming the gate capping layer includes: forming a gate capping material layer that fills the gate recess and covers the bottom dielectric layer and the etch barrier structure; using an etching process to remove the gate capping material layer located on the top surface of the bottom dielectric layer and the etch barrier structure, and using the remaining gate capping material layer in the gate recess as the gate capping layer.

15. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the etch barrier structure, the etch barrier structure further extends to cover a portion of the top surface of the bottom dielectric layer located on both sides of the gate structure.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the source / drain contact material, and before removing a portion of the thickness of the source / drain contact material located in the source / drain connection region, the method for forming the semiconductor structure further includes: forming a hard mask layer on top of the source / drain contact material in the source / drain contact region; Using the hard mask layer as a mask, a portion of the source / drain contact material of a certain thickness located in the source / drain connection region is removed.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The step of forming the spacer dielectric layer includes: filling the spacer opening with dielectric material, the dielectric material also being formed on the top dielectric layer; and using a planarization process to remove the dielectric material above the top surface of the top dielectric layer, the remaining dielectric material in the spacer opening being used as the spacer dielectric layer. The method for forming the semiconductor structure further includes removing the hard mask layer during the process of removing the dielectric material above the top surface of the top dielectric layer.

18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process of filling the spacer opening with a dielectric material includes one or more of the following: flow chemical vapor deposition, spin coating, and atomic layer deposition.

19. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the source-drain contact structure, the top surface of the source-drain contact layer is lower than the top surface of the bottom dielectric layer.

20. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of forming the source-drain contact structure, the top surface of the source-drain contact layer is lower than the top surface of the gate structure of the gate spacer region.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, Both the gate structure and the source / drain contact structure extend longitudinally, and the direction perpendicular to the longitudinal direction is the transverse direction. After forming the spacer dielectric layer and before forming the gate plug, the method for forming the semiconductor structure further includes: forming an interconnect dielectric layer on the top dielectric layer and the spacer dielectric layer to cover the source / drain plug; After the interconnect dielectric layer is formed, the gate plug is formed; In the step of forming the gate plug, the method of forming the semiconductor structure further includes: forming metal interconnects that extend laterally and are spaced apart longitudinally in the interconnect dielectric layer, wherein the metal interconnects respectively contact the gate plug and the source / drain plug.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The steps of forming the metal interconnect and the gate plug include: forming a plurality of interconnect trenches that extend laterally and penetrate the interconnect dielectric layer, wherein on a projection plane parallel to the substrate, the interconnect trenches respectively cross the top of the source / drain plug and the top of the gate structure of the gate contact region; A gate contact hole is formed in the top dielectric layer above the top of the gate structure, and communicates with the interconnect trench; Conductive material is filled into the gate contact hole and the interconnect trench to form a gate contact plug in the gate contact hole and a metal interconnect in the interconnect trench.

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