Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device with reduced breakdown voltage and a method for manufacturing the semiconductor device are provided. The IGBT region (10) has: an n-type carrier accumulation layer (2), which is connected to an n-type carrier accumulation layer (2). ‑ Type drift layer (1) is contacted and set on n ‑ The first principal surface (1a) side of the drift layer (1) is adjacent to n ‑ The p-type drift layer (1) has a higher impurity concentration than the n-type layer; the p-type base layer (15) is disposed between the n-type carrier accumulation layer (2) and the 1-type main surface (1a); + The emitter layer (13) is selectively disposed on the surface portion of the p-type base layer (15); and the gate electrode (11a) is disposed between the p-type base layer (15) and the n-type base layer (15) separated by an insulating film. + The n-type emitter layer (13) and the p-type base layer (15) are opposite each other, and the diode region (20) has a p-type anode layer (25), which is disposed on the n-type base layer. ‑ Between the n-type drift layer (1) and the first main surface (1a), and disposed at a depth from the first main surface (1a) that is greater than that of the n-type carrier accumulation layer (2) and the n-type carrier accumulation layer (3). ‑ The position is up to the boundary depth of the drift layer (1).

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a manufacturing method of a semiconductor device. BACKGROUND

[0002] An RC-IGBT (Reverse Conducting Insulated Gate Bipolar Transistor) in which an IGBT region and a diode region are provided in one semiconductor device is known. In addition, a semiconductor device in which a carrier accumulation layer of a first conductivity type having a higher impurity concentration than a drift layer is provided between the drift layer of the first conductivity type and a base layer of a second conductivity type in the IGBT region is known.

[0003] In the conventional semiconductor device, the carrier accumulation layer is not provided in the diode region, the carrier accumulation layer is provided in the IGBT region, and a second carrier accumulation layer is provided on the boundary side of the IGBT region with the diode region, the second carrier accumulation layer being formed shallower than a first carrier accumulation layer on the central side of the IGBT region. Thus, in the conventional semiconductor device, the field plate effect at the boundary of the IGBT region and the diode region is easily exhibited to increase the withstand voltage (for example, refer to Patent Literature 1).

[0004] Patent Literature 1: International Publication No. 2017 / 141998

[0005] However, in the conventional semiconductor device, since the action is performed in a manner that the electric field is concentrated in the second carrier accumulation layer formed shallower than the first carrier accumulation layer, there is a problem that the withstand voltage is decreased due to the electric field being concentrated in a part of the carrier accumulation layer. SUMMARY

[0006] The present application has been made to solve the above-described problems, and has an object to provide a semiconductor device and a manufacturing method of a semiconductor device in which the electric field concentration toward the carrier accumulation layer is suppressed, and the decrease in the withstand voltage is suppressed.

[0007] The semiconductor device according to the present application includes a semiconductor substrate having an IGBT region and a diode region arranged in a first direction along a first main surface, the semiconductor substrate having a drift layer of a first conductivity type between the first main surface and a second main surface opposite to the first main surface, the IGBT region having a collector layer of a second conductivity type provided between the drift layer and the second main surface, a carrier accumulation layer of the first conductivity type provided on the first main surface side of the drift layer in contact with the drift layer and having a higher impurity concentration of the first conductivity type than the drift layer, a base layer of the second conductivity type provided between the carrier accumulation layer and the first main surface, an emitter layer of the first conductivity type selectively provided in a surface layer portion of the base layer and having a portion of the first main surface, and a gate electrode provided opposite to the emitter layer and the base layer with an insulating film interposed therebetween, and the diode region having a cathode layer of the first conductivity type provided between the drift layer and the second main surface, and an anode layer of the second conductivity type provided between the drift layer and the first main surface and provided to a position deeper than a boundary between the carrier accumulation layer and the drift layer.

[0008] Further, the manufacturing method of the semiconductor device according to the present application includes the steps of preparing a semiconductor substrate of a first conductivity type having a first main surface, the semiconductor substrate having a first region in which an IGBT region is formed by being arranged in a first direction along the first main surface and a second region in which a diode region is formed, forming a first resist mask having a first opening on the first main surface of the first region, implanting impurity ions of the first conductivity type from the first opening to form a carrier accumulation layer of the first conductivity type, implanting impurity ions of a second conductivity type from the first opening to form a base layer of the second conductivity type between the first main surface and the carrier accumulation layer, forming a second resist mask having a first opening on a second main surface of the second region, and implanting impurity ions of the second conductivity type from the second opening to form an anode layer of the second conductivity type from a position deeper than a position at which the carrier accumulation layer is formed to the first main surface.

[0009] Effects of the Invention

[0010] According to the semiconductor device according to the present application, it is possible to provide a semiconductor device in which concentration of electric field toward the carrier accumulation layer is suppressed and reduction in withstand voltage is suppressed.

[0011] Further, according to the manufacturing method of the semiconductor device according to the present application, it is possible to provide a manufacturing method of a semiconductor device in which concentration of electric field toward the carrier accumulation layer is suppressed and reduction in withstand voltage is suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 is a plan view showing a semiconductor device in Embodiment 1.

[0013] Figure 2 is a plan view showing the structure of the semiconductor device in Embodiment 1.

[0014] Figure 3 is a partial enlarged plan view showing the structure of the IGBT region of the semiconductor device in Embodiment 1.

[0015] Figure 4 is a sectional view showing the structure of the IGBT region of the semiconductor device in Embodiment 1.

[0016] Figure 5 is a sectional view showing the structure of the IGBT region of the semiconductor device in Embodiment 1.

[0017] Figure 6 is a partial enlarged plan view showing the structure of the diode region of the semiconductor device in Embodiment 1.

[0018] Figure 7 is a sectional view showing the structure of the diode region of the semiconductor device in Embodiment 1.

[0019] Figure 8 is a sectional view showing the structure of the diode region of the semiconductor device in Embodiment 1.

[0020] Figure 9 is a sectional view showing the structure of the boundary between the IGBT region and the diode region of the semiconductor device in Embodiment 1.

[0021] Figure 10 is a sectional view showing the structure of the boundary between the IGBT region and the diode region of another semiconductor device in Embodiment 1.

[0022] Figure 11 is a sectional view showing the structure of the end region of the semiconductor device in Embodiment 1.

[0023] Figure 12 is a diagram showing a manufacturing method of the semiconductor device in Embodiment 1.

[0024] Figure 13 is a diagram showing a manufacturing method of the semiconductor device in Embodiment 1.

[0025] Figure 14 is a diagram showing a manufacturing method of the semiconductor device in Embodiment 1.

[0026] Figure 15 is a diagram showing a manufacturing method of the semiconductor device in Embodiment 1.

[0027] Figure 16is a view showing a manufacturing method of a semiconductor device in Embodiment 1.

[0028] Figure 17 is a view showing a manufacturing method of a semiconductor device in Embodiment 1.

[0029] Figure 18 is a view showing a manufacturing method of a semiconductor device in Embodiment 1.

[0030] Figure 19 is a view showing a manufacturing method of a semiconductor device in Embodiment 1.

[0031] Figure 20 is a partial enlarged plan view showing a structure of a boundary portion of an IGBT region and a diode region of a semiconductor device in Embodiment 2.

[0032] Figure 21 is a sectional view showing a structure of an IGBT region, a boundary region, and a diode region of a semiconductor device in Embodiment 2.

[0033] Figure 22 is a sectional view showing a structure of an IGBT region, a boundary region, and a diode region of a semiconductor device in Embodiment 2.

[0034] Figure 23 is a sectional view showing a structure of an IGBT region, a boundary region, and a diode region of a semiconductor device in Embodiment 2.

[0035] Figure 24 is a sectional view showing a structure of an IGBT region, a boundary region, and a diode region of a semiconductor device in Embodiment 2.

[0036] Figure 25 is a sectional view showing a structure of a boundary of an IGBT region and a diode region of a semiconductor device in Embodiment 3. DETAILED DESCRIPTION

[0037] Embodiment 1

[0038] First, a structure of a semiconductor device in Embodiment 1 will be described. Figure 1 is a plan view showing a semiconductor device in Embodiment 1.

[0039] In the following description, n and p represent conductive types of a semiconductor, and in the present application, a first conductive type is described as n type and a second conductive type is described as p type. In addition, n - represents a concentration lower than n, and n + represents a concentration higher than n. Similarly, p - represents a concentration lower than p, and p +Indicates a concentration higher than the impurity concentration ratio p.

[0040] Figure 1 The illustrated semiconductor device 100 is an RC-IGBT in which the IGBT region 10 and the diode region 20 are arranged in a strip shape, and can be referred to as a "strip-shaped" RC-IGBT.

[0041] In Figure 1 , the semiconductor device 100 has the IGBT region 10 and the diode region 20 in one semiconductor device. The IGBT region 10 and the diode region 20 are arranged in a strip shape in the first direction (the up-down direction on the paper) along the first main surface of the semiconductor substrate constituting the semiconductor device 100. The IGBT region 10 and the diode region 20 extend from one end side to the other end side of the semiconductor device 100, and are alternately arranged in the direction orthogonal to the extending direction of the IGBT region 10 and the diode region 20. In Figure 1 , three IGBT regions 10 and two diode regions are shown, and the structure in which all the diode regions 20 are sandwiched by the IGBT regions 10, but the number of the IGBT regions 10 and the diode regions 20 is not limited thereto. The number of the IGBT regions 10 can be greater than or equal to three or less than or equal to three, and the number of the diode regions 20 can be greater than or equal to two or less than or equal to two. In addition, it can be a structure in which the positions of the IGBT region 10 and the diode region 20 are exchanged, and it can also be a structure in which all the IGBT regions 10 are sandwiched by the diode regions 20. In addition, the IGBT region 10 and the diode region 20 can be a structure in which one of each is arranged adjacent to each other. Figure 1

[0042] As Figure 1 ​As shown, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the paper. The pad region 40 is a region in which control pads 41 for controlling the semiconductor device 100 are provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. In order to maintain the withstand voltage of the semiconductor device 100, a terminal region 30 is provided around a region in which the cell region and the pad region 40 are combined. A well-known withstand voltage maintaining structure can be appropriately and selectively provided in the terminal region 30. The withstand voltage maintaining structure can be, for example, a structure in which a FLR (Field Limiting Ring) that surrounds the cell region with a p-type terminal well layer of a p-type semiconductor, or a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type terminal well layer having a concentration gradient, is provided on the surface side, i.e., the first main surface side, of the semiconductor device 100. The number of annular p-type terminal well layers used in the FLR and the concentration distribution used in the VLD can be appropriately selected in accordance with the withstand voltage design of the semiconductor device 100. In addition, the p-type terminal well layer can be provided throughout substantially the entire region of the pad region 40, or IGBT cells and diode cells can be provided in the pad region 40.

[0043] The control pads 41 can be, for example, a current sense pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, and temperature sense diode pads 41d, 41e. The current sense pad 41a is a control pad for detecting a current flowing in the cell region of the semiconductor device 100, and is a control pad that is electrically connected to a part of the IGBT cells or the diode cells of the cell region. When a current flows in the cell region of the semiconductor device 100, the current sense pad 41a flows a current that is several one-thousandths to several ten-thousandths of the current flowing in the entire cell region.

[0044] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a gate drive voltage for on-off control of the semiconductor device 100 is applied. The Kelvin emitter pad 41b is electrically connected to a p-type base layer of the IGBT cells, and the gate pad 41c is electrically connected to a gate trench electrode of the IGBT cells. The Kelvin emitter pad 41b and the p-type base layer can also be electrically connected via a p-type contact layer. The temperature sense diode pads 41d, 41e are control pads that are electrically connected to an anode and a cathode of a temperature sense diode provided in the semiconductor device 100. The voltage between the anode and the cathode of a temperature sense diode not shown that is provided in the cell region is measured, and the temperature of the semiconductor device 100 is measured. +

[0045] Figure 2 is a plan view showing another structure of the semiconductor device according to Embodiment 1. Figure 2 ​The illustrated semiconductor device 101 is an RC-IGBT in which a plurality of diode regions 20 are provided in the longitudinal and lateral directions, and IGBT regions 10 are provided around the diode regions 20, which can be referred to simply as an "island type" RC-IGBT.

[0046] In Figure 2 , the semiconductor device 101 has IGBT regions 10 and diode regions 20 in one semiconductor device. The IGBT regions 10 and diode regions 20 are arranged in a first direction (up-down direction on the paper) along a first main surface of a semiconductor substrate that constitutes the semiconductor device 101. The diode regions 20 are arranged in a plurality of rows in the longitudinal direction and in a plurality of columns in the lateral direction in the semiconductor device, and the diode regions 20 are surrounded by the IGBT regions 10. That is, the diode regions 20 are provided in an island shape within the IGBT regions 10. In Figure 2 , a structure is illustrated in which the diode regions 20 are arranged in a matrix shape having four columns in the lateral direction on the paper and two rows in the up-down direction on the paper, but the number and arrangement of the diode regions 20 are not limited thereto, and as long as one or a plurality of diode regions 20 are dispersed within the IGBT regions 10 and each diode region 20 is surrounded by the IGBT regions 10.

[0047] The semiconductor device 101 is the same as the semiconductor device 100 illustrated in Figure 1 , in that a region in which the IGBT regions 10 and diode regions 20 are combined is a unit region. Around a region in which the unit region and the land region 40 are combined, an end region 30 is provided, which has the same structure as the end region 30 of the semiconductor device 100 illustrated in Figure 1 .

[0048] Figure 3 is a partial enlarged plan view that shows the structure of the IGBT region of the RC-IGBT, that is, the semiconductor device. In addition, Figure 4 and Figure 5 are cross-sectional views that show the structure of the IGBT region of the RC-IGBT, that is, the semiconductor device. Figure 3 The region surrounded by the broken line 82 in the semiconductor device 100 illustrated in Figure 1 or the semiconductor device 101 illustrated in Figure 2 is shown in an enlarged manner. Figure 4 is a cross-sectional view at the broken line A-A of the semiconductor device 100 or the semiconductor device 101 illustrated in Figure 3 , Figure 5 is a cross-sectional view at the broken line B-B of the semiconductor device 100 or the semiconductor device 101 illustrated in Figure 3 .

[0049] As Figure 3As shown, in the IGBT region 10, the active trench gate 11 and the dummy trench gate 12 are provided in a strip shape. In the semiconductor device 100 and the semiconductor device 101, the active trench gate 11 and the dummy trench gate 12 extend in a second direction (a direction of the paper surface) orthogonal to a first direction in which the IGBT region 10 and the diode region 20 are arranged.

[0050] The active trench gate 11 is configured by providing the gate trench electrode 11a inside the trench formed in the semiconductor substrate with the gate trench insulating film 11b interposed therebetween. The dummy trench gate 12 is configured by providing the dummy trench electrode 12a inside the trench formed in the semiconductor substrate with the dummy trench insulating film 12b interposed therebetween. The gate trench electrode 11a and the dummy trench electrode 12a are IGBT trench electrodes provided in the IGBT region 10. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 41c, and is a gate electrode that switches the ON state and the OFF state of the IGBT cell of the IGBT region 10. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to the emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0051] n + The n-type emitter layer 13 is provided to contact the gate trench insulating film 11b on both sides in the width direction of the active trench gate 11. + The n-type emitter layer 13 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) or the like as an n-type impurity, and the concentration of the n-type impurity is 1.0 x 10 17 / cm 3 ~ 1.0 x 10 20 / cm 3 . + The n-type emitter layer 13 is alternately provided with the p + type contact layer 14 in the extension direction of the active trench gate 11. The p + type contact layer 14 is also provided between adjacent two dummy trench gates 12. The p + type contact layer 14 is a semiconductor layer having, for example, boron (B) or aluminum (Al) or the like as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 15 / cm 3 ~ 1.0 x 10 20 / cm 3 .

[0052] The p + type contact layer 14 is a semiconductor layer having a higher p-type impurity concentration than the p-type base layer, which is formed in a surface layer portion of the p-type base layer in order to improve the electrical connection between the emitter electrode and the p-type base layer. In the present application, the p + type contact layer 14 is described as a part of the p-type base layer. It is not necessarily required that the p+ Contact layer 14 can also be in Figure 3 In the top view, a p-type base layer is set instead of p. + The structure of contact layer 14.

[0053] like Figure 3 As shown, the IGBT region 10 of semiconductor device 100 or semiconductor device 101 has the following structure: three dumb trench gates 12 are arranged next to three side-by-side active trench gates 11, and three active trench gates 11 are arranged next to the three side-by-side dumb trench gates 12. The IGBT region 10 is configured such that groups of active trench gates 11 and groups of dumb trench gates 12 are arranged alternately as described above. Figure 3 In this configuration, a group of active trench gates 11 may contain three active trench gates 11, but any group containing one or more active trench gates is acceptable. Similarly, a group of dumb trench gates 12 may contain one or more dumb trench gates 12, or the number of dumb trench gates 12 may be zero. That is, all trenches in the IGBT region 10 may be active trench gates 11. In other words, all IGBT trench electrodes may be gate trench electrodes 11a of active trench gates 11.

[0054] Figure 4 It is semiconductor device 100 or semiconductor device 101 Figure 3 The cross-sectional view at the dashed line AA is a cross-sectional view of the IGBT region 10. Semiconductor device 100 or semiconductor device 101 has an n-shaped structure made of a semiconductor substrate. - Type 1 drift layer. - The n-type drift layer 1 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity, with an n-type impurity concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 15 / cm 3 Semiconductor substrates in Figure 4 The middle is from n + Type 13 emitter layer and p + The range from the p-type contact layer 14 to the p-type collector layer 16. (The text abruptly ends here.) Figure 4 n + Type 13 emitter layer and p +The upper end of the paper surface of the p-type contact layer 14 is referred to as a first main surface la of the semiconductor substrate, and the lower end of the paper surface of the p-type collector layer 16 is referred to as a second main surface lb of the semiconductor substrate. The first main surface la of the semiconductor substrate is a main surface on the surface side of the semiconductor device 100, and the second main surface lb of the semiconductor substrate is a main surface on the back surface side of the semiconductor device 100. The semiconductor device 100 has, in the cell region, that is, the IGBT region 10, an n - type drift layer 1.

[0055] As Figure 4 indicated, in the IGBT region 10, an n - type drift layer 1, an n-type carrier accumulation layer 2 having a higher concentration of n-type impurities than the n - type drift layer 1 is provided in contact with the n - type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer having, for example, arsenic (As) or phosphorus (P) or the like as n-type impurities, and has a concentration of n-type impurities of 1.0 x 10 13 / cm 3 ~ 1.0 x 10 17 / cm 3 By providing the n-type carrier accumulation layer 2, it is possible to reduce the energization loss when a current flows in the IGBT region 10.

[0056] The n-type carrier accumulation layer 2 is formed by implanting n-type impurity ions into a semiconductor substrate constituting the n - type drift layer 1, and then diffusing the implanted n-type impurities into the n - type drift layer 1, that is, the semiconductor substrate, by annealing. Therefore, in the vicinity of the boundary between the n - type drift layer 1 and the n-type carrier accumulation layer 2, the concentration of n-type impurities gradually increases. In the present application, in a case where the concentration of n-type impurities in the n - type drift layer 1 toward the n-type carrier accumulation layer 2 is measured by a spreading resistance method (SR method), a position where the concentration of n-type impurities in the n - type drift layer 1 toward the n-type carrier accumulation layer 2 is higher than the average impurity concentration of the n - type drift layer 1 by 2% or more is defined as the boundary between the n - type drift layer 1 and the n-type carrier accumulation layer 2.

[0057] A p-type base layer 15 is provided on the first main surface la side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer having, for example, boron (B) or aluminum (Al) or the like as p-type impurities, and has a concentration of p-type impurities of 1.0 x 10 12 / cm3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. An n-type base layer 15 is formed by contacting the gate trench insulating film 11b of the active trench gate 11 on its first main surface side. + Type emitter layer 13, with p in the remaining region + Type contact layer 14. + Type 13 emitter layer and p + The contact layer 14 forms the first main surface 1a of the semiconductor substrate. Furthermore, p... + The p-type contact layer 14 is a portion of the p-type base layer where the concentration of p-type impurities is higher than that of the p-type base layer 15, as described above. In this invention, in addition to the p-type contact layer 14, the p-type base layer 15 is a portion of the p-type base layer where the concentration of p-type impurities is higher than that of the p-type base layer 15. + Except where the p-type contact layer 14 and the p-type base layer 15 are specifically distinguished, the p-type base layer 15 will be... + The p-type contact layer 14 and the p-type base layer 15 are combined and referred to as the p-type base layer.

[0058] Additionally, in semiconductor device 100 or semiconductor device 101, in n - The second main surface 1b of the drift layer 1 has a concentration ratio of n-type impurities to n - The n-type buffer layer 3 is a high-density n-type drift layer 1. The n-type buffer layer 3 is provided to suppress depletion layer breakdown extending from the p-type base layer 15 to the second main surface when the semiconductor device 100 is in an off state. The n-type buffer layer 3 can be, for example, implanted phosphorus (P) or protons (H). + It can be formed by either injecting phosphorus or protons. The concentration of n-type impurities in n-type buffer layer 3 is 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 18 / cm 3 Furthermore, semiconductor device 100 or semiconductor device 101 may also omit the n-type buffer layer 3, and instead... Figure 4 The area of ​​the n-type buffer layer 3 shown also has n... - The structure of type n drift layer 1. Alternatively, type n buffer layer 3 and type n... - The drift layers 1 are collectively referred to as drift layers.

[0059] Semiconductor device 100 or semiconductor device 101 has a p-type collector layer 16 disposed on the second main surface 1b side of the n-type buffer layer 3. That is, on the n-type buffer layer 3... - A p-type collector layer 16 is disposed between the p-type drift layer 1 and the second main surface 1b. The p-type collector layer 16 is a semiconductor layer having a p-type impurity such as boron (B) or aluminum (Al), and the concentration of the p-type impurity is 1.0 × 10⁻⁶. 16 / cm3 ~1.0×10 20 / cm 3 The p-type collector layer 16 forms the second main surface 1b of the semiconductor substrate. The p-type collector layer 16 is disposed not only in the IGBT region 10 but also in the terminal region 30, and the portion of the p-type collector layer 16 disposed in the terminal region 30 constitutes a p-type terminal collector layer. Alternatively, the p-type collector layer 16 may also be configured such that a portion extends from the IGBT region 10 into the diode region 20.

[0060] like Figure 4 As shown, in semiconductor device 100 or semiconductor device 101, a p-type base layer 15 and an n-type carrier accumulation layer 2 are formed through the first main surface 1a of the semiconductor substrate to reach n - The trench of the drift layer 1. An active trench gate 11 is formed by providing a gate trench electrode 11a within the trench, separated by a gate trench insulating film 11b. The gate trench electrode 11a is separated from the n by the gate trench insulating film 11b. - The drift layer 1 is opposite to the type. Furthermore, a dumb trench gate 12 is formed by providing a dumb trench electrode 12a within the trench, separated by a dumb trench insulating film 12b. The dumb trench electrode 12a is separated from the n by the dumb trench insulating film 12b. - The drift layer 1 is opposite to the active trench gate 11. The gate trench insulating film 11b of the active trench gate 11 is opposite to the p-type base layer 15 and the n-type base layer 15. + The p-type emitter layer 13 is in contact. If a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 that is in contact with the gate trench insulating film 11b of the active trench gate 11.

[0061] like Figure 4 As shown, an interlayer insulating film 4 is disposed on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not disposed and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi alloyed from titanium and silicon (Si). Figure 4 As shown, the blocking metal 5 and n + Type 13 emitter layer, p + The contact layer 14 and the dummy trench electrode 12a make ohmic contact with n. + Type 13 emitter layer, p + The contact layer 14 and the dumb groove electrode 12a are electrically connected.

[0062] The emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy), or can be an electrode composed of a multilayer metal film formed by plating on an electrode formed of an aluminum alloy. The plating film formed by plating can be, for example, a nickel (Ni) plating film or a copper (Cu) plating film. In the case where there is a minute region such as a minute region of the interlayer insulating film 4 adjacent to each other and the emitter electrode 6 cannot be embedded well, a tungsten electrode having a good embedding property compared to the emitter electrode 6 can be provided in the minute region, and the emitter electrode 6 can be provided on the tungsten electrode.

[0063] Further, the barrier metal 5 can not be provided, and the n + type emitter layer 13, the p + type contact layer 14, and the dummy trench electrode 12a. Further, the barrier metal 5 can be provided only on the n + type semiconductor layer such as the n Figure 4 structure in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12 is shown, but the interlayer insulating film 4 can be formed on the dummy trench electrode 12a of the dummy trench gate 12. In the case where the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a can be electrically connected in a cross section different from that shown in FIG. 6. Figure 4

[0064] The collector electrode 7 is provided on the side of the second main surface 1b of the p-type collector layer 16. The collector electrode 7 can be composed of an aluminum alloy, an aluminum alloy and a plating film, like the emitter electrode 6. Further, the collector electrode 7 can be a structure different from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0065] Figure 5 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 or the semiconductor device 101. Figure 3 is a cross-sectional view at a dotted line B-B in the semiconductor device 100 or the semiconductor device 101. Figure 4 is different from the cross-sectional view at the dotted line A-A shown in FIG. 1 in that the n Figure 5 type emitter layer 13 provided on the side of the first main surface of the semiconductor substrate is not observed in the cross section at the dotted line B-B of the active trench gate 11. That is, as shown in FIG. 6, the n + type emitter layer 13 is provided on the side of the first main surface of the semiconductor substrate. Figure 3 + ​​The p-type emitter layer 13 is selectively provided on the side of the first main surface la of the p-type base layer. Here, the p-type base layer refers to the p-type base layer 15 and the p + type contact layer 14 collectively.

[0066] Figure 6 is a partial enlarged plan view showing the structure of the diode region of the RC-IGBT, i.e., the semiconductor device. In addition, Figure 7 and Figure 8 is a sectional view showing the structure of the diode region of the RC-IGBT, i.e., the semiconductor device. Figure 6 The region surrounded by the broken line 83 in the semiconductor device 100 or the semiconductor device 101 shown in Figure 1 is shown in an enlarged manner. Figure 7 is a sectional view of the semiconductor device 100 at the broken line C-C shown in Figure 6 . Figure 8 is a sectional view of the semiconductor device 100 at the broken line D-D shown in Figure 6 .

[0067] The diode trench gate 21 extends along the first main surface la of the semiconductor device 100 or the semiconductor device 101 in a second direction (the left-right direction of the paper) orthogonal to the first direction in which the IGBT region 10 and the diode region 20 are arranged. The diode trench gate 21 is configured by providing the diode trench electrode 21a inside the trench formed in the semiconductor substrate of the diode region 20 through the diode trench insulating film 21b. The diode trench electrode 21a is electrically connected to the p - type drift layer 1 opposite.

[0068] The p + type contact layer 24 and the p-type anode layer 25 are provided between the two adjacent diode trench gates 21. The p + type contact layer 24 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 15 / cm 3 ~ 1.0 x 10 20 / cm 3 . The p-type anode layer 25 is a semiconductor layer having, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 12 / cm 3 ~ 1.0 x 10 19 / cm 3 . The p + type contact layer 24 and the p-type anode layer 25 are alternately provided in the length direction of the diode trench gate 21, i.e., the second direction.

[0069] Figure 7It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the dashed line CC is a cross-sectional view of diode region 20. Semiconductor device 100 or semiconductor device 101, like IGBT region 10, also has an n-shaped structure made of a semiconductor substrate in diode region 20. - Type drift layer 1. Diode region 20 n - n-type drift layer 1 and IGBT region 10 - The drift layer 1 is continuously integrally formed from the same semiconductor substrate. Figure 7 The semiconductor substrate is from p + Type contact layer 24 to n + The range up to the cathode layer 26. Figure 7 Lieutenant General P + The upper end of the contact layer 24 on the paper is called the first main surface 1a of the semiconductor substrate, and n + The lower end of the cathode layer 26 is called the second main surface 1b of the semiconductor substrate. The first main surface 1a of the diode region 20 and the first main surface 1a of the IGBT region 10 are the same surface, and the second main surface 1b of the diode region 20 and the second main surface 1b of the IGBT region 10 are the same surface.

[0070] like Figure 7 As shown, diode region 20 differs from IGBT region 10 in that, in n - A p-type anode layer 25 is disposed on the first main surface 1a side of the p-type drift layer 1. The p-type anode layer 25 is disposed on the n-type drift layer 1. - The p-type drift layer 25 is disposed between the first main surface 1a and the first main surface 1a. The p-type anode layer 25 is positioned at a depth greater than that of the n-type carrier accumulation layer 2 and the n-type carrier storage layer 1a in the IGBT region 10. - The distance extends to the boundary depth of the p-type drift layer 1. That is, the p-type anode layer 25 and the n-type anode layer 25. - The depth of the boundary of the n-type drift layer 1 from the first principal surface 1a is greater than that of the n-type carrier accumulation layer 2 and the n-type drift layer 1. - The boundary of the p-type drift layer 1 is located at a depth greater than that of the first main surface 1a. In this way, by forming the p-type anode layer 25 at a depth greater than that of the n-type carrier accumulation layer 2, the semiconductor device 100 or semiconductor device 101 can suppress the concentration of electric field toward the n-type carrier accumulation layer 2 and suppress the reduction of breakdown voltage.

[0071] The p-type anode layer 25 is a semiconductor layer containing, for example, boron (B) or aluminum (Al) as p-type impurities, with a p-type impurity concentration of 1.0 × 10⁻⁶. 12 / cm 3 ~1.0×10 19 / cm 3The p-type impurity concentration in the p-type anode layer 25 is higher than the n-type impurity concentration in the n-type carrier accumulation layer 2 of the IGBT region 10. Alternatively, the p-type impurity concentration in the p-type anode layer 25 can be set to the same concentration as that in the p-type base layer 15 of the IGBT region 10. Alternatively, the p-type impurity concentration in the p-type anode layer 25 can be set to be lower than that in the p-type base layer 15 of the IGBT region 10, thereby reducing the amount of holes injected into the diode region 20 during diode operation. By reducing the amount of holes injected during diode operation, the recovery loss during diode operation can be reduced.

[0072] A p-type anode layer 25 is provided on the first main surface 1a side. + Type contact layer 24. p can be used as a contact layer. + The concentration of p-type impurities in the contact layer 24 is set to be the same as that in the IGBT region 10. + The concentration of p-type impurities in the contact layer 14 can be the same, or different. + The contact layer 24 forms the first main surface 1a of the semiconductor substrate. Furthermore, p... + The contact layer 24 is a region where the concentration of p-type impurities is higher than that of the p-type anode layer 25, where it is necessary to distinguish between p-type and p-type impurities. + In the case of p-type contact layer 2414 and p-type anode layer 25, they can be referred to separately, or p can be referred to as p-type anode layer 25. + The p-type contact layer 24 and the p-type anode layer 25 are combined and referred to as the p-type anode layer.

[0073] In addition, such as Figure 7 As shown, similarly to the IGBT region 10, in the diode region 20 of semiconductor device 100 or semiconductor device 101, in n - An n-type buffer layer 3 is disposed on the second main surface 1b side of the n-type drift layer 1. The n-type buffer layer 3 of the diode region 20 can be integrally formed with the n-type buffer layer 3 of the IGBT region 10. - The type 1 drift layer and the type 3 buffer layer are combined and referred to as the drift layer.

[0074] In diode region 20, an n-type buffer layer 3 is provided on the second main surface 1b side. + Type 26 cathode layer. + Type 26 cathode layer is disposed in n - Between drift layer 1 and the second principal surface 1b. + The n-type cathode layer 26 is a semiconductor layer containing, for example, arsenic (As) or phosphorus (P) as an n-type impurity, with an n-type impurity concentration of 1.0 × 10⁻⁶. 16 / cm 3 ~1.0×10 21 / cm 3 n +The cathode layer 26 is disposed in part or all of the diode region 20. + The p-type cathode layer 26 constitutes the second main surface 1b of the semiconductor substrate. Furthermore, although not shown, p-type impurities can be selectively implanted into the n-type cathode layer formed as described above. + The region of the type cathode layer 26 will form n + A portion of the region of the cathode layer 26 is configured as a p-type semiconductor. + Type-n cathode layer. For example, n layers can be alternately arranged along the second main surface 1b of the semiconductor substrate. + Type Cathode Layer and p + A type of cathode layer, a diode with this structure is known to be an RFC (Relaxed Field of Cathode) diode.

[0075] like Figure 7 As shown, in the diode region 20 of semiconductor device 100 or semiconductor device 101, a p-type anode layer 25 is formed that extends from the first main surface 1a of the semiconductor substrate to reach n. - The trench of the drift layer 1. A diode trench electrode 21a is formed by providing a diode trench electrode 21a within the trench of the diode region 20, separated by a diode trench insulating film 21b. The diode trench electrode 21a is separated from the diode trench insulating film 21b by the n... - Type drift layer 1 relative.

[0076] like Figure 7 As shown, in the diode trench electrode 21a and p + A barrier metal 5 is disposed above the contact layer 24. The barrier metal 5 is connected to the diode trench electrode 21a and p. + The contact layer 24 forms an ohmic contact with the diode trench electrode 21a and p. + The contact layer 24 is electrically connected. The barrier metal 5 can have the same structure as the barrier metal 5 in the IGBT region 10. The emitter electrode 6 is disposed on the barrier metal 5. The emitter electrode 6 disposed in the diode region 20 is formed continuously with the emitter electrode 6 disposed in the IGBT region 10. Alternatively, similar to the case of the IGBT region 10, the barrier metal 5 can be omitted, and the diode trench electrode 21a and p can be made... + The p-type contact layer 24 and the emitter electrode 6 make ohmic contact. Alternatively, a barrier metal 5 can be provided in the IGBT region 10, but not in the diode region 20. In this case, the p-type impurity concentration of the p-type anode layer of the diode region 20 can be set to be lower than the p-type impurity concentration of the p-type base layer of the IGBT region 10.

[0077] In addition, Figure 7The diagram shows a structure where the interlayer insulating film 4 is not formed on the diode trench electrode 21a of the diode trench gate 21, but it is also possible to form the interlayer insulating film 4 on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, it is compatible with... Figure 7 Other cross-sections, different from the one shown, can be used to electrically connect the emitter electrode 6 and the diode trench electrode 21a.

[0078] In n + A collector electrode 7 is disposed on the second main surface side of the cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is continuously formed with the collector electrode 7 disposed in the IGBT region 10. The collector electrode 7 and n + The cathode layer 26 makes an ohmic contact with n. + Type 26 cathode layer is electrically connected.

[0079] Figure 8 It is semiconductor device 100 or semiconductor device 101 Figure 6 The cross-sectional view at the dashed line DD is a cross-sectional view of diode region 20. (And...) Figure 7 The difference in the cross-sectional view shown at the dashed line CC is that no p-type anode layer 25 is provided between the p-type anode layer 25 and the barrier metal 5. + The p-type contact layer 24 and the p-type anode layer 25 constitute the first main surface of the semiconductor substrate. That is, Figure 7 p shown + The p-type contact layer 24 is selectively disposed on the first main surface side of the p-type anode layer 25.

[0080] Figure 9 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of an RC-IGBT, i.e., a semiconductor device. Figure 9 yes Figure 1 The semiconductor device 100 shown or Figure 2 A cross-sectional view of the semiconductor device 101 shown at the dashed line GG.

[0081] like Figure 9 As shown, semiconductor device 100 or semiconductor device 101 has a boundary region 50 between IGBT region 10 and diode region 20. The boundary region 50 is disposed between the IGBT trench electrode closest to diode region 20 among the gate trench electrode 11a and dumb trench electrode 12a of IGBT region 10, and the diode trench electrode closest to IGBT region 10 among the diode trench electrodes 21a of diode region 20.

[0082] In this invention, the IGBT trench electrode is formed by penetrating the p-type base layer 15 through the first main surface 1a of the semiconductor substrate to reach the n-type base layer 15. - The trench electrodes of the IGBT trench electrodes are disposed within the trenches of the drift layer 1, separated by an insulating film. The two opposite sides of the IGBT trench electrodes are separated from the p-type base layer 15 by the insulating film. The IGBT trench electrodes are gate trench electrodes 11a or dumb trench electrodes 12a. When not distinguishing between gate trench electrodes 11a and dumb trench electrodes 12a, they are referred to as IGBT trench electrodes in this invention.

[0083] Furthermore, in this invention, the diode trench electrode 21a is formed by penetrating the p-type anode layer 25 from the first main surface 1a of the semiconductor substrate to reach the n-type anode layer 21a. - The trench electrodes of the p-type drift layer 1 are disposed within the trenches separated by an insulating film. The two opposing sides of the diode trench electrodes 21a are separated by an insulating film and face the p-type anode layer 25. Additionally, as... Figure 9 As shown, the diode trench electrode 21a is n + The cathode layer 26 is located on the second main surface 1b side of the p-type anode layer 25, which is opposite to the side of the diode trench electrode 21a, separated by an insulating film.

[0084] like Figure 9 As shown, the boundary region 50 is in n - A p-type collector layer 16 is present between the p-type drift layer 1 and the second main surface 1b. The boundary between the boundary region 50 and the diode region 20 can be defined as the p-type collector layer 16 disposed on the second main surface 1b side and the n-type collector layer 16. + The boundary of the p-type cathode layer 26. Thus, by providing the p-type collector layer 16 in the boundary region 50 between the IGBT region 10 and the diode region 20, it is possible to [contain] the n-type collector layer 20. + The distance between the cathode layer 26 and the active trench gate 11 of the IGBT region 10 is set to be large, so that even when a gate drive voltage is applied to the gate trench electrode 11a when the freewheeling diode is operating, current can flow from the channel formed adjacent to the active trench gate 11 in the IGBT region 10 to the n + The cathode layer 26 is used for suppression.

[0085] Figure 10 It is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of other RC-IGBTs, i.e., semiconductor devices. Figure 10 and Figure 9 Similarly, is Figure 1 The semiconductor device 100 shown or Figure 2 A cross-sectional view at the dashed line GG in the semiconductor device 101 shown. Figure 9 In the boundary region 50, no trench electrodes are provided, but as... Figure 10As shown, it is also possible to set a boundary region 50 extending from the first principal surface 1a to n - One or more boundary trench electrodes 51a are disposed within the trenches of the drift layer, separated by an insulating film. The width U1 of the boundary region 50 can be, for example, 100 μm. Furthermore, depending on the application of the RC-IGBT, i.e., semiconductor device 100 or semiconductor device 101, the width U1 of the boundary region 50 can be a distance smaller than 100 μm, or it can be the same width as the distance between adjacent trenches.

[0086] like Figure 9 and Figure 10 As shown, in semiconductor device 100 or semiconductor device 101, the n-type carrier accumulation layer 2 and the p-type anode layer 25 are in contact in the boundary region 50. Furthermore, the p-type anode layer 25 and the n... - The boundary of the n-type drift layer 1 is set at a depth greater than that of the first principal surface 1a than that of the n-type carrier accumulation layer 2 and the n-type drift layer 1. - The p-type anode layer 25 is located at a depth deeper than the boundary of the n-type carrier accumulation layer 2. In the semiconductor device 100 or semiconductor device 101 of the present invention, by providing the p-type anode layer 25 at a depth deeper than the n-type carrier accumulation layer 2, the concentration of the electric field towards the n-type carrier accumulation layer 2 is suppressed, thereby suppressing the decrease in breakdown voltage. Figure 10 In this configuration, the contact position between the n-type carrier accumulation layer 2 and the p-type anode layer 25 is set between the IGBT trench electrode closest to the diode region 20, i.e., the dumb trench electrode 12a, and the boundary trench electrode 51a. However, there are no special restrictions on the contact position between the n-type carrier accumulation layer 2 and the p-type anode layer 25 if they are within the boundary region 50.

[0087] In addition, Figure 9 and Figure 10 In this design, the IGBT trench electrode closest to the diode region 20 is set as a dumb trench electrode 12a electrically connected to the emitter electrode 6. However, the IGBT trench electrode closest to the diode region 20 can also be set as a gate trench electrode 11a electrically connected to the gate pad 41c. Figure 9 and Figure 10 As shown, by setting the IGBT trench electrode closest to the diode region 20 as a dumb trench electrode 12a electrically connected to the emitter electrode 6, the boundary region 50 can be prevented from contributing to the switching operation. Therefore, the influence of the boundary region 50 on the switching operation can be suppressed, and the voltage drop can be suppressed.

[0088] Figure 11 This is a cross-sectional view showing the structure of the end region of an RC-IGBT, i.e., a semiconductor device. Figure 11 (a) is Figure 1 or Figure 2 The cross-sectional view at the dashed line EE is a cross-sectional view from IGBT region 10 to end region 30. Additionally,Figure 11 (b) is Figure 1 a cross-sectional view at the dotted line F-F in (b), is a cross-sectional view from the diode region 20 to the termination region 30.

[0089] As Figure 11 (a) and Figure 11 (b) show, the termination region 30 of the semiconductor device 100 has an n - type drift layer 1 between the first main surface la and the second main surface lb of the semiconductor substrate. The first main surface la and the second main surface lb of the termination region 30 are the same surfaces as the first main surface la and the second main surface lb of the IGBT region 10 and the diode region 20, respectively. In addition, the n - type drift layer 1 of the termination region 30 is the same structure as the n - type drift layer 1 of the IGBT region 10 and the diode region 20, and is continuously formed as one body.

[0090] On the first main surface la side of the n - type drift layer 1, that is, between the first main surface la of the semiconductor substrate and the n - type drift layer 1, a p-type termination well layer 31 is provided. The p-type termination well layer 31 is a semiconductor layer having, for example, boron (B) or aluminum (Al) or the like as a p-type impurity, and the concentration of the p-type impurity is 1.0 x 10 14 / cm 3 ~ 1.0 x 10 19 / cm 3 . The p-type termination well layer 31 is provided so as to surround the unit region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is formed at a position deeper than the n-type carrier accumulation layer, and is formed at a position deeper than the trench formed in the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a plurality of annular shapes, and the number of p-type termination well layers 31 is appropriately selected in accordance with the withstand voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, an n + type channel stop layer 32 is provided on the more edge side of the p-type termination well layer 31, and the n + type channel stop layer 32 surrounds the p-type termination well layer 31.

[0091] On the n - type drift layer 1 and the second main surface lb of the semiconductor substrate, a p-type termination collector layer 16a is provided. The p-type termination collector layer 16a is continuously formed as one body with the p-type collector layer 16 provided in the unit region. Therefore, it can be referred to as the p-type collector layer 16 including the p-type termination collector layer 16a. In addition, in a structure in which the diode region 20 is provided adjacent to the termination region 30 as shown in Figure 1 , the p-type termination collector layer 16a is provided in the termination region 30. In addition, in a structure in which the diode region 20 is provided adjacent to the termination region 30 as shown in Figure 11(b) shown, the p-type end collector layer 16a is provided so that the end portion on the diode region 20 side protrudes toward the diode region 20 by a distance U2. In this way, by providing the p-type end collector layer 16a so as to protrude to the diode region 20, it is possible to increase the distance between the n-type cathode layer 26 and the p-type end well layer 31 of the diode region 20, and it is possible to suppress the p-type end well layer 31 from functioning as the anode of the diode. The distance U2 may, for example, be 100 μm. + (b) shown, the p-type end collector layer 16a is provided so that the end portion on the diode region 20 side protrudes toward the diode region 20 by a distance U2. In this way, by providing the p-type end collector layer 16a so as to protrude to the diode region 20, it is possible to increase the distance between the n-type cathode layer 26 and the p-type end well layer 31 of the diode region 20, and it is possible to suppress the p-type end well layer 31 from functioning as the anode of the diode. The distance U2 may, for example, be 100 μm.

[0092] The collector electrode 7 is provided on the second main surface lb of the semiconductor substrate. The collector electrode 7 is formed continuously in one piece from the unit region including the IGBT region 10 and the diode region 20 to the end region 30. On the other hand, the emitter electrode 6 that is continuous from the unit region, and the end electrode 6a that is separate from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the end region 30.

[0093] The emitter electrode 6 and the end electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may, for example, be a sin SiN (semi-insulating Silicon Nitride). The end electrode 6a and the p-type end well layer 31 and the n-type cathode layer 26 of the diode region 20 are electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the end region 30. + The emitter electrode 6 and the end electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may, for example, be a sin SiN (semi-insulating Silicon Nitride). The end electrode 6a and the p-type end well layer 31 and the n-type cathode layer 26 of the diode region 20 are electrically connected via a contact hole formed in the interlayer insulating film 4 provided on the first main surface of the end region 30.

[0094] Next, the method of manufacturing the semiconductor device 100 or the semiconductor device 101 of the present application will be described.

[0095] Figures 12-19 is a view showing the method of manufacturing the semiconductor device. Figures 12-17 is a view showing the process of forming the surface side of the semiconductor device 100 or the semiconductor device 101, Figure 18 and Figure 19 is a view showing the process of forming the back surface side of the semiconductor device 100 or the semiconductor device 101.

[0096] First, as shown in Figure 12 (a), an n -The semiconductor substrate is a type-floating layer 1. The semiconductor substrate can be, for example, an FZ wafer fabricated using the FZ (Floating Zone) method, or an MCZ wafer fabricated using the MCZ (Magnetic-field-applied Czochralski) method, and can be an n-type wafer containing n-type impurities. The concentration of n-type impurities in the semiconductor substrate is appropriately selected according to the breakdown voltage of the semiconductor device being manufactured. For example, in a semiconductor device with a breakdown voltage of 1200V, the concentration of n-type impurities is adjusted so that the n-type impurities constituting the semiconductor substrate... - The relative resistivity of drift layer 1 is approximately 40–120 Ω·cm. For example... Figure 12 As shown in (a), in the process of preparing the semiconductor substrate, the entire semiconductor substrate is n - A p-type or n-type semiconductor layer is formed by implanting p-type or n-type impurity ions from the first main surface 1a side or the second main surface 1b side of such a semiconductor substrate, and then diffusing them into the semiconductor substrate through heat treatment or the like, thereby manufacturing a semiconductor device 100 or semiconductor device 101.

[0097] like Figure 12 As shown in (a), n constitutes - The semiconductor substrate of the drift layer 1 has regions that form IGBT region 10, diode region 20, and boundary region 50. Additionally, although not shown, a region forming end region 30 surrounds the regions that form IGBT region 10, diode region 20, and boundary region 50. The following mainly describes the manufacturing method of the structure of IGBT region 10, diode region 20, and boundary region 50 of semiconductor device 100 or semiconductor device 101; however, the end region 30 of semiconductor device 100 or semiconductor device 101 can be fabricated using known manufacturing methods. For example, when forming an FLR with a p-type end well layer 31 in the end region 30 as a breakdown voltage holding structure, it can be formed by implanting p-type impurity ions before processing the IGBT region 10 and diode region 20 of semiconductor device 100 or semiconductor device 101, or it can be formed by simultaneously implanting p-type impurity ions when implanting them into the IGBT region 10 or diode region 20 of semiconductor device 100.

[0098] Next, as Figure 12(b) shows that a first resist mask, i.e., a resist mask 60, is formed on the first main surface la of the region of the semiconductor substrate that becomes the diode region 20, and a mask process is performed. In the present application, the mask process is a process for applying a resist to the semiconductor substrate, forming an opening in a prescribed region of the resist using a photolithography technique, performing ion implantation in the prescribed region of the semiconductor substrate through the opening or performing etching, and forming a mask on the semiconductor substrate. As shown in Figure 12 (b) shows that the resist mask 60 has a first opening, i.e., an opening 60a, in the region that becomes the IGBT region 10. The resist mask 60 is provided in such a manner that the end portion of the resist mask 60 protrudes from the region of the semiconductor substrate that becomes the diode region 20 on the first main surface la to the region that becomes the boundary region 50. That is, the resist mask 60 has the opening 60a in the region of the semiconductor substrate that becomes the IGBT region 10 on the first main surface la and in a portion of the region that becomes the boundary region 50, and the end portion of the opening 60a of the resist mask 60 is located at a position that is separated by a distance a from the boundary between the region that becomes the IGBT region 10 and the region that becomes the boundary region 50 toward the diode region 20.

[0099] After the resist mask 60 is formed on the first main surface la of the semiconductor substrate, n-type impurities such as phosphorus (P) are implanted from the first main surface la side of the semiconductor substrate, as shown in Figure 12 (b) shows that an n-type carrier accumulation layer 2 is formed in a portion of the IGBT region 10 and the boundary region 50. The n-type carrier accumulation layer 2 is formed at a position shallower than the boundary between the p-type anode layer 25 and the n - type drift layer 1. As shown in Figure 12 (b) shows that the end portion of the n-type carrier accumulation layer 2 on the diode region 20 side has a depth from the first main surface la that is shallower than the n-type carrier accumulation layer 2 in the IGBT region 10.

[0100] Next, as shown in Figure 13 (a), p-type impurities such as boron (B) are implanted from the first main surface la side of the semiconductor substrate to form a p-type base layer 15. Since the p-type base layer 15 is formed by a mask process using the resist mask 60 used when forming the n-type carrier accumulation layer 2, the p-type base layer 15 is formed in a portion of the IGBT region 10 and the boundary region 50. After the n-type carrier accumulation layer 2 and the p-type base layer 15 are formed by implanting impurity ions into the IGBT region 10 and the portion of the boundary region 50 of the semiconductor substrate, the semiconductor substrate is subjected to a heat treatment to diffuse the impurity ions implanted into the n-type carrier accumulation layer 2 and the p-type base layer 15 within the semiconductor substrate.

[0101] Next, as shown in Figure 13As shown in (b), a second resist mask, i.e., a resist mask 61, is formed on the first main surface 1a of the semiconductor substrate, which is the IGBT region 10, and a masking process is performed. P-type impurity ions are implanted from the first main surface 1a side of the semiconductor substrate to form a p-type anode layer 25. Figure 13 As shown in (b), the resist mask 61 has a second opening, namely opening 61a, in the region that becomes the diode region 20. The resist mask 61 is arranged such that the end of the resist mask 61 extends a distance b from the region that becomes the IGBT region 10 on the first main surface 1a of the semiconductor substrate toward the region that becomes the boundary region 50. That is, the resist mask 61 has an opening 61a in a part of the region that becomes the diode region 20 and the region that becomes the boundary region 50 on the first main surface 1a of the semiconductor substrate, and the end of the opening 61a of the resist mask 61 is located at a distance b away from the boundary between the region that becomes the IGBT region 10 and the region that becomes the boundary region 50 toward the diode region 20.

[0102] Figure 13 (b) The distance b shown is a ratio Figure 13 (a) The smaller distance a is set to the portion of the end of the diode region 20 side of the n-type carrier accumulation layer 2 that is shallower than the depth of the first main surface 1a, located in the opening 61a of the resist mask 61. That is, the opening 60a of the resist mask 60 and the opening 61a of the resist mask 61 are formed to partially overlap in the boundary region 50. Therefore, the end of the IGBT region 10 side of the p-type anode layer 25 is formed to overlap with the region of the end of the diode region 20 side where the n-type carrier accumulation layer 2 and the p-type base layer 15 are formed. By setting the p-type impurity concentration of the p-type anode layer 25 to be higher than the n-type impurity concentration of the n-type carrier accumulation layer 2, the region where n-type impurity ions are implanted to form the n-type carrier accumulation layer 2 and the region where p-type impurity ions are implanted to form the p-type anode layer 25 overlap, becoming a p-type semiconductor layer and part of the p-type anode layer 25. As a result, a structure can be formed in which the n-type carrier accumulation layer 2 and the p-type anode layer 25 are in contact at the boundary region 50. In addition, by using p-type impurities with a higher concentration than the n-type impurities in the n-type carrier accumulation layer 2, the portion of the end of the n-type carrier accumulation layer 2 on the diode region 20 side that is shallower than the depth of the first main surface 1a is offset and the p-type anode layer 25 is formed. Therefore, the concentration of electric field at the end of the n-type carrier accumulation layer 2 can be suppressed, and the voltage drop can be suppressed.

[0103] After forming a p-type anode layer 25 by implanting p-type impurity ions into a portion of the diode region 20 and the boundary region 50 of the semiconductor substrate, the semiconductor substrate is heat-treated to allow the impurity ions implanted into the p-type anode layer 25 to diffuse within the semiconductor substrate. Furthermore, the heat treatment for diffusing impurity ions in the n-type carrier accumulation layer 2 and the p-type base layer 15 can be performed simultaneously with the heat treatment for diffusing impurity ions in the p-type anode layer 25. By simultaneously performing heat treatments for diffusing impurity ions in the n-type carrier accumulation layer 2, the p-type base layer 15, and the p-type anode layer 25, the number of diffusion cycles of impurity ions in the n-type carrier accumulation layer 2, whose impurity concentration is lower than that in the p-type base layer 15 and the p-type anode layer 25, can be reduced, making it easier to form an n-type carrier accumulation layer 2 of a specified thickness.

[0104] Alternatively, as another method for forming the n-type carrier accumulation layer 2 and the p-type anode layer 25, the p-type anode layer 25 may be formed before the n-type carrier accumulation layer 2. Figure 14 This diagram illustrates a manufacturing method where a p-type anode layer 25 is formed before the n-type carrier accumulation layer 2. It can replace... Figure 12 (b) Figure 13 (a) and Figure 13 (b) The process shown in the diagram is applied Figure 14 (a) and Figure 14 The process shown in (b)

[0105] In such Figure 12 (a) shows the preparation of n - After the semiconductor substrate with drift layer 1, such as Figure 14 As shown in (a), a photoresist mask 61 is formed on the first main surface 1a of the semiconductor substrate, which is the IGBT region 10, to perform masking treatment. P-type impurity ions are implanted from the first main surface 1a side of the semiconductor substrate to form a p-type anode layer 25. The photoresist mask 61 and... Figure 13 (b) Similarly, the end is arranged such that it extends a distance b from the region that becomes the IGBT region 10 to the region that becomes the boundary region 50. After a p-type anode layer 25 is formed by implanting p-type impurity ions into a portion of the diode region 20 and the boundary region 50 of the semiconductor substrate, the semiconductor substrate is heated to cause the impurity ions implanted into the p-type anode layer 25 to diffuse within the semiconductor substrate.

[0106] Next, as Figure 14 As shown in (b), a resist mask 60 is formed on the first main surface 1a of the semiconductor substrate, which is the diode region 20, and a masking process is performed. Figure 14(b) shown, the resist mask 60 is provided to have an opening in a manner that an end portion of the IGBT region 10 side of the p-type anode layer 25 is exposed to the first main surface la. The resist mask 60 has an opening over the region of the semiconductor substrate that becomes the IGBT region 10 and a portion of the region that becomes the boundary region 50 on the first main surface la, and an end portion of the opening of the resist mask 60 is located at a position that is apart from the boundary between the region that becomes the IGBT region 10 and the region that becomes the boundary region 50 by a distance a in the diode region 20 side. Figure 14 The distance a shown in (b) is larger than Figure 14 The distance b shown in (a) is larger than

[0107] After the resist mask 60 is formed over the first main surface la of the semiconductor substrate, n-type impurity ions are implanted from the first main surface la side of the semiconductor substrate to form the n-type carrier accumulation layer 2, and p-type impurity ions are implanted to form the p-type base layer 15. The n-type carrier accumulation layer 2 is formed at a position shallower than the boundary of the p-type anode layer 25 and the n - The ion implantation for forming the n-type carrier accumulation layer 2 and the ion implantation for forming the p-type base layer 15 can be performed in either order. The n-type impurity ions for forming the n-type carrier accumulation layer 2 are also implanted to the end portion of the p-type anode layer 25 located at the opening of the resist mask 60, but since the p-type impurity concentration of the p-type anode layer 25 is higher than the n-type impurity concentration of the n-type carrier accumulation layer 2, the end portion of the p-type anode layer 25 will remain a p-type semiconductor layer even if the n-type impurity ions are implanted to the end portion of the p-type anode layer 25. As a result, it is possible to provide a structure in which the n-type carrier accumulation layer 2 and the p-type anode layer 25 are in contact at the boundary region 50. Further, since it is possible to cause the n-type impurity to be implanted only to the end portion of the n-type carrier accumulation layer 2 on the diode region 20 side that is shallower than the n-type carrier accumulation layer 2 of the IGBT region 10 to be embedded in the p-type anode layer 25, it is possible to suppress the formation of a portion of the n-type carrier accumulation layer 2 that is shallow in depth from the first main surface la, and it is possible to suppress the concentration of an electric field at the end portion of the n-type carrier accumulation layer 2, and to suppress a reduction in the withstand voltage.

[0108] After the n-type carrier accumulation layer 2 and the p-type base layer 15 are formed, the semiconductor substrate is subjected to a heat treatment to diffuse the impurity ions implanted to the n-type carrier accumulation layer 2 and the p-type base layer 15 within the semiconductor substrate. In this way, by performing the implantation of the impurity ions for forming the p-type anode layer 25 before the implantation of the impurity ions for forming the n-type carrier accumulation layer, it is possible to diffuse the impurity ions within the semiconductor substrate only by a heat treatment of the p-type anode layer 25, it is possible to reduce the number of times of diffusion of the impurity ions caused by the heat treatment of the n-type carrier accumulation layer 2, and it is easy to form the n-type carrier accumulation layer 2 in accordance with the design.

[0109] Furthermore, the p-type end-well layer 31 formed in the end region 30 of the semiconductor device 100 or semiconductor device 101 can also be implanted with p-type impurity ions simultaneously with the p-type anode layer 25. In this case, the depth and p-type impurity concentration of the p-type end-well layer 31 and the p-type anode layer 25 are the same. Additionally, during the masking process for forming the p-type end-well layer 31 and the p-type anode layer 25, by setting the mask formed in the region where the p-type end-well layer 31 is formed or the region where the p-type anode layer 25 is formed as a grid-shaped mask, the aperture ratio can be changed. Therefore, even if p-type impurity ions are implanted into the p-type end-well layer 31 and the p-type anode layer 25 simultaneously, the p-type impurity concentrations of the p-type end-well layer 31 and the p-type anode layer 25 can be set to different concentrations. Furthermore, by using masking processes to implant p-type impurity ions into the p-type end-well layer 31 and the p-type anode layer 25 separately, the depths of the p-type end-well layer 31 and the p-type anode layer 25 can be different, thus also resulting in different p-type impurity concentrations.

[0110] Next, as Figure 15 As shown in (a), n-type impurities are selectively implanted into the first main surface 1a side of the p-type base layer 15 of the IGBT region 10 through masking to form n-type impurities. + The n-type emitter layer 13. The implanted n-type impurity can be, for example, arsenic (As) or phosphorus (P). Additionally, through masking, p-type impurities are selectively implanted into the first main surface 1a side of the p-type base layer 15 of the IGBT region 10 to form a p-type base layer 13. + The p-type contact layer 14 selectively implants p-type impurities into the first main surface 1a side of the p-type anode layer 25 of the diode region 20 to form a p-type contact layer 14. + Type contact layer 24. The implanted p-type impurities can be, for example, boron (B) or aluminum (Al).

[0111] Next, as Figure 15 (b) Forming a p-type base layer 15 and a p-type anode layer 25 penetrating from the first main surface side of the semiconductor substrate to reach n - The trench 8 of the drift layer 1. In Figure 15 In (b), no trench 8 is formed in the boundary region 50, but one or more trenches 8 may be formed in the boundary region 50. In the IGBT region 10, through n... + The sidewalls of the trench 8 of the type emitter layer 13 constitute n + A portion of the emitter layer 13. After depositing an oxide film such as SiO2 on a semiconductor substrate, an opening is formed in the oxide film at the portion where the trench 8 is formed through mask processing. The semiconductor substrate is then etched using the oxide film with the opening as a mask, thereby forming the trench 8. Figure 15In (b), the trenches 8 are formed with the same spacing in the IGBT region 10 and the diode region 20, but the spacing of the trenches 8 can also be different in the IGBT region 10 and the diode region 20. The pattern of the trench spacing when viewed from above can be appropriately changed according to the mask pattern of the masking process.

[0112] Next, as Figure 16 As shown in (a), an oxide film 9 is formed on the inner wall of the trench 8 and the first main surface 1a of the semiconductor substrate by heating in an oxygen-containing atmosphere. Among the oxide films 9 formed on the inner wall of the trench 8, the oxide films 9 formed in the trench 8 of the IGBT region 10 are the gate trench insulating film 11b of the active trench gate 11 and the dumb trench insulating film 12b of the dumb trench gate 12. Additionally, the oxide film 9 formed in the trench 8 of the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface 1a of the semiconductor substrate is removed by a subsequent process.

[0113] Next, as Figure 16 As shown in (b), polysilicon doped with n-type or p-type impurities is deposited in the trench 8, in which an oxide film 9 is formed on the inner wall, by means of CVD (Chemical Vapor Deposition) or the like, to form a gate trench electrode 11a, a dumb trench electrode 12a and a diode trench electrode 21a.

[0114] Next, as Figure 17 As shown in (a), after forming an interlayer insulating film 4 on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10, the oxide film 9 formed on the first main surface 1a of the semiconductor substrate is removed. The interlayer insulating film 4 can be, for example, SiO2. Then, contact holes are formed on the interlayer insulating film 4 deposited through a mask process. The contact holes are formed on n + Above the type emitter layer 13, p + Above the contact layer 14, p + Above the contact layer 24, above the dumb trench electrode 12a, and above the diode trench electrode 21a.

[0115] Next, as Figure 17 As shown in (b), a barrier metal 5 is formed on the first main surface 1a of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by forming a film of titanium nitride using PDV (Physical Vapor Deposition) and CVD.

[0116] For example, an aluminum-silicon alloy (Al-Si alloy) can be deposited onto the barrier metal 5 by PVD processes such as sputtering or vapor deposition to form the emitter electrode 6. Alternatively, a nickel alloy (Ni alloy) or a copper alloy (Cu alloy) can be further formed on the formed aluminum-silicon alloy by electroless plating or electroplating to serve as the emitter electrode 6. If the emitter electrode 6 is formed by electroplating, a thick metal film can be easily formed as the emitter electrode 6, thereby increasing the heat capacity of the emitter electrode 6 and improving its heat resistance. Furthermore, if the emitter electrode 6 made of aluminum-silicon alloy is formed by PVD, and a nickel alloy or copper alloy is further formed by electroplating, the electroplating process for forming the nickel alloy or copper alloy can be performed after processing the second main surface of the semiconductor substrate.

[0117] Next, as Figure 18 (a) shows the second main surface 1b of the semiconductor substrate being ground to thin the semiconductor substrate to the designed thickness. The thickness of the semiconductor substrate after grinding can be, for example, 80 μm to 200 μm.

[0118] Next, as Figure 18 As shown in (b), an n-type buffer layer 3 is formed by implanting an n-type impurity from the second main surface 1b side of the semiconductor substrate. Furthermore, a p-type collector layer 16 is formed by implanting a p-type impurity from the second main surface 1b side of the semiconductor substrate. The n-type buffer layer 3 can be formed in the IGBT region 10, the diode region 20, the boundary region 50, and the end region 30, or it can be formed only in the IGBT region 10 or the diode region 20.

[0119] The n-type buffer layer 3 can be formed, for example, by implanting phosphorus (P) ions. Alternatively, it can be formed by implanting protons (H) ions. + It can be formed by injecting protons or phosphorus. Protons can be injected to a deep location from the second main surface 1b of the semiconductor substrate with relatively low acceleration energy. In addition, the depth of proton injection can be easily changed by changing the acceleration energy. Therefore, if multiple injections are performed while changing the acceleration energy when forming the n-type buffer layer 3 by protons, a wider n-type buffer layer 3 can be formed in the thickness direction of the semiconductor substrate compared to formation by phosphorus.

[0120] Furthermore, compared to protons, phosphorus can increase the activation rate of n-type impurities. Therefore, by using phosphorus to form an n-type buffer layer 3, even a thinned semiconductor substrate can more reliably suppress depletion layer breakdown. To further thin the semiconductor substrate, it is preferable to implant both protons and phosphorus to form the n-type buffer layer 3, in which case protons are implanted to a deeper position from the second main surface 1b compared to phosphorus.

[0121] The p-type collector layer 16 can be formed, for example, by implanting boron (B). The p-type collector layer 16 is also formed in the end region 30, and the p-type collector layer 16 in the end region 30 is called the p-type end collector layer 16a. After ion implantation from the second main surface 1b of the semiconductor substrate, laser annealing is performed by irradiating the second main surface 1b with a laser, thereby activating the implanted boron and forming the p-type collector layer 16. At this time, the phosphorus used to implant from the second main surface 1b of the semiconductor substrate to a relatively shallow position is also activated simultaneously. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken to prevent the entire semiconductor substrate from reaching a temperature higher than 350°C to 500°C, except for the process of activating protons after implantation. Since laser annealing can only raise the temperature near the second main surface 1b of the semiconductor substrate, it can also be used to activate n-type and p-type impurities after proton implantation.

[0122] Next, as Figure 19 As shown in (a), n is formed in diode region 20. + Type 26 cathode layer. + The cathode layer 26 can be formed, for example, by implanting phosphorus (P). Figure 19 As shown in (a), with p-type collector layer 16 and n + The boundary of the cathode layer 26 is located at a distance U1 from the boundary between the IGBT region 10 and the boundary region 50 toward the diode region 20, and phosphorus is selectively implanted from the second main surface side through a mask process. This is used to form n + The amount of n-type impurities implanted in the p-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. Figure 19 In (a), the p-type collector layer 16 and n are shown. + The cathode layer 26 is at the same depth as the second main surface 1b, but n + The depth of the n-type cathode layer 26 is greater than or equal to the depth of the p-type collector layer 16. This is due to the formation of the n-type cathode layer 26. + The region of the p-type cathode layer 26 needs to be implanted with n-type impurities to become an n-type semiconductor, thus forming an n-type semiconductor. + The concentration of n-type impurities injected into the entire region of the cathode layer 26 is set to be higher than the concentration of p-type impurities.

[0123] Next, as Figure 19(b) A collector electrode 7 is formed over the second main surface lb of the semiconductor substrate as shown. The collector electrode 7 is formed over the entire surface of the IGBT region 10, the boundary region 50, the diode region 20, and the terminal region 30 of the second main surface lb. Alternatively, the collector electrode 7 can be formed over the entire surface of the second main surface lb of the semiconductor substrate, i.e., the n-type wafer. The collector electrode 7 can be formed by depositing an aluminum-silicon alloy (Al-Si-based alloy), titanium (Ti), or the like by sputtering, vapor deposition, or the like (PVD). Alternatively, the collector electrode 7 can be formed by laminating a plurality of metals such as aluminum-silicon alloy, titanium, nickel, or gold. Further, the collector electrode 7 can be formed by further forming a metal film by electroless plating or electroplating on a metal film formed by PVD.

[0124] The semiconductor device 100 or the semiconductor device 101 is manufactured by the above-described process. In the semiconductor device 100 or the semiconductor device 101, since a plurality of semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix form from one n-type wafer, the semiconductor device 100 or the semiconductor device 101 is completed by being divided into each semiconductor device 100 or semiconductor device 101 by laser cutting or blade cutting.

[0125] As described above, in the semiconductor device 100 or the semiconductor device 101 of the present application, since the depth of the p-type anode layer 25 of the diode region 20 from the first main surface la of the semiconductor substrate is set to be deeper than the depth of the n-type carrier accumulation layer 2 provided in the IGBT region 10 from the first main surface la, the concentration of the electric field toward the n-type carrier accumulation layer 2 is suppressed, and thus the reduction in the withstand voltage of the semiconductor device 100 or the semiconductor device 101 can be suppressed.

[0126] Further, since the p-type impurity concentration of the p-type anode layer 25 is set to be higher than the n-type impurity concentration of the n-type carrier accumulation layer 2, and the p-type anode layer 25 is formed so as to overlap with the portion of the n-type carrier accumulation layer 2 in the diode region 20 of the IGBT region 10, which is shallow in depth from the first main surface la, the portion of the n-type carrier accumulation layer 2, which is shallow in depth from the first main surface la, at the end portion can be eliminated, the concentration of the electric field toward the n-type carrier accumulation layer 2 can be suppressed, and the reduction in the withstand voltage can be suppressed.

[0127] Further, the structure in which the boundary region 50 is provided between the IGBT region 10 and the diode region 20, and the n-type carrier accumulation layer 2 and the p-type anode layer 25 are in contact at the boundary region 50, and thus the boundary of the n-type carrier accumulation layer 2 and the p-type anode layer 25 is provided so as to be away from the trench electrode where the electric field is easily concentrated, and thus the concentration of the electric field toward the end portion of the diode region 20 of the n-type carrier accumulation layer 2 can be suppressed, and the reduction in the withstand voltage can be suppressed.

[0128] Further, since the boundary between the n-type carrier accumulation layer 2 and the p-type anode layer 25 is located in a structure between the two trench electrodes electrically connected to the emitter electrode 6, the influence of the boundary between the n-type carrier accumulation layer 2 and the p-type anode layer 25 on the on-off operation of the semiconductor device 100 or the semiconductor device 101 can be suppressed, and the reduction in the withstand voltage can be suppressed.

[0129] Further, since the boundary region 50 is provided with one or more boundary trench electrodes 51a at the boundary between the n-type carrier accumulation layer 2 and the p-type anode layer 25, the width of the boundary region 50, which does not contribute to the on-off operation of the semiconductor device 100 or the semiconductor device 101, can be increased, and the influence of the boundary between the n-type carrier accumulation layer 2 and the p-type anode layer 25 on the on-off operation can be further suppressed, and the reduction in the withstand voltage can be suppressed.

[0130] Embodiment 2

[0131] Next, the structure of the semiconductor device in Embodiment 2 will be described. Figure 20 is a partial enlarged plan view showing the structure of the boundary portion of the IGBT region and the diode region of the RC-IGBT, i.e., the semiconductor device, in Embodiment 2. Figure 20 Figure 1 or Figure 2 The other structure of the region surrounded by the dotted line 84 in the semiconductor device shown in the structure of

[0132] As shown in Figure 20 , the semiconductor device of Embodiment 2 has a boundary region 50 between the IGBT region 10 and the diode region 20, and a plurality of boundary trench electrodes 51a are provided in the boundary region 50. The boundary region 50 is provided between the IGBT electrode, i.e., the dummy trench electrode 12a, of the IGBT region 10 on the side closest to the diode region 20 and the diode trench electrode 21a of the diode region 20 on the side closest to the IGBT region 10.

[0133] The p + -type contact layer 14 provided on the side of the first main surface la of the IGBT region 10 is different from the semiconductor device 100 or the semiconductor device 101 of Embodiment 1 in that it is sandwiched by the p-type base layer 15 in the region sandwiched by the IGBT electrode composed of the gate trench electrode 11a or the dummy trench electrode 12a. Further, the n + -type emitter layer 13 of the IGBT region 10 on the side closest to the diode region 20 is not in contact with the IGBT trench electrode through an insulating film at the end portion on the side of the diode region 20, and the n + ​The p-type base layer 15 is provided between the p-type emitter layer 13 and the IGBT trench electrode, i.e., the dummy trench electrode 12a. In addition, the p + The p-type contact layer 24 is different from the semiconductor device 100 or the semiconductor device 101 of Embodiment 1 in that it is sandwiched by the p-type anode layer 25 in the region sandwiched by the diode trench electrode 21a.

[0134] Further, Figure 20 The p + The p + The configuration of the p-type contact layer 24 and the p-type anode layer 25 is not limited to this, and can be the configuration of Embodiment 1. Figure 3 Or Figure 6 The configuration shown in Embodiment 1, the semiconductor device 100 or the semiconductor device 101, the p + The p + The configuration of the p-type contact layer 24 and the p-type anode layer 25 is not limited to this, and can be the configuration of Embodiment 1. Figure 20 The configuration shown in Embodiment 1, the semiconductor device 100 or the semiconductor device 101, the p + The p + The configuration of the p-type contact layer 24 and the p-type anode layer 25 is not limited to this, and can be the configuration of Embodiment 1. Figure 20 The configuration shown in Embodiment 1, the semiconductor device 100 or the semiconductor device 101, the p

[0135] As Figure 20 shown, the p-type base layer 15 or the p-type anode layer 25 in the boundary region 50 opposes the boundary trench electrode 51a through the insulating film. In Figure 20 shown, the p-type base layer 15 or the p-type anode layer 25 in the boundary region 50 opposes the boundary trench electrode 51a through the insulating film. In - The n-type carrier accumulation layer 2 is provided between the p-type base layer 15 and the n - The n-type carrier accumulation layer 2 is provided between the p-type base layer 15 and the n

[0136] As Figure 20 shown, the p-type base layer 15 or the p-type anode layer 25 in the boundary region 50 opposes the boundary trench electrode 51a through the insulating film. In + The n-type carrier accumulation layer 2 is provided between the p-type base layer 15 and the n + The n-type impurity concentration of the n-type carrier accumulation layer 53 can be the same as the n + The n-type impurity concentration of the n-type carrier accumulation layer 53 can be the same as the n + The n-type impurity concentration of the n-type carrier accumulation layer 53 can be the same as the n Figure 20In the direction (vertical direction on the paper) where IGBT region 10 and diode region 20 are arranged, n + Type 13 and n emitter layers + The carrier injection suppression layer 53 is arranged in a relative manner, but n + Type 53 carrier injection suppression layer 53 can be combined with n + The configuration of the emitter layer 13 is set independently. That is, in Figure 20 The n-th electrode will be disposed in the length direction (left-right direction on the paper) of the gate trench electrode 11a and the boundary trench electrode 51a. + The number of emitter layers 13 and n + The number of carrier injection suppression layers 53 is set to the same number, but n can be changed. + The number of emitter layers 13 and n + The number of carrier injection suppression layers 53 is set to different numbers.

[0137] like Figure 20 As shown, n is set in the boundary region 50. + The p-type carrier injection suppression layer 53 is configured such that it is sandwiched between the p-type base layer 15 or the p-type anode layer 25 in the direction (up and down on paper) where the IGBT region 10 and the diode region 20 are arranged. That is, n + The p-type carrier injection suppression layer 53 is not in contact with the insulating film that is in contact with the boundary trench electrode 51a, but is opposite to the trench where the boundary trench electrode 51a is provided, separated by the p-type base layer 15 or the p-type anode layer 25.

[0138] exist Figure 20 In the semiconductor device of Embodiment 2 shown, n electrodes are provided that are adjacent to each other in the extension direction of the boundary trench electrode 51a. + p-type carrier injection suppression layers 53 are provided between them + Type contact layer 14 or p + The structure of contact layer 24 is similar, but p may not necessarily be provided. + Type contact layer 14 or p + Type contact layer 24 can also replace p + Type contact layer 14 or p + A p-type base layer 15 or a p-type anode layer 25 is provided in the n-type contact layer 24. Additionally, in the n-type contact layer 24... + A p-type base layer 15 or a p-type anode layer 25 is disposed between the p-type carrier injection suppression layer 53 and the trench where the boundary trench electrode 51a is provided. However, a p-type base layer 15 or a p-type anode layer 25 can be disposed instead of the p-type base layer 15 or the p-type anode layer 25. + Type contact layer 14 or p + Type 24 contact layer.

[0139] Figures 21-24This is a cross-sectional view showing the structure of the IGBT region, boundary region, and diode region of the RC-IGBT, i.e., semiconductor device, in Embodiment 2. Figure 21 It is in IGBT region 10 Figure 20 The cross-sectional view shown at the dashed line HH. Figure 22 It is in the boundary region 50 Figure 20 The cross-sectional view at the dashed line II. Figure 23 It is in the boundary region 50 Figure 20 The cross-sectional view shown at the dashed line JJ. Figure 24 It is in diode region 20 Figure 20 The cross-sectional view shown at the dashed line KK. Figures 21-24 All are cross-sectional views orthogonal to the direction in which the IGBT region 10 and the diode region 20 are arranged (vertical direction on the paper), and are cross-sectional views orthogonal to the extension direction of the gate trench electrode 11a, the dumb trench electrode 12a and the boundary trench electrode 51a.

[0140] like Figure 21 As shown, in the IGBT region 10, a p-type base layer 15 is provided on the first main surface 1a side of the semiconductor substrate, and an n-type base layer is selectively provided on the surface portion of the p-type base layer 15. + Type 13 emitter layer and p + Type contact layer 14. p + The contact layer 14 can be set at a depth ratio n from the first main surface 1a. + The location is deep within the p-type emitter layer 13. Between the p-type base layer 15 and the n-type emitter layer 13. - An n-type carrier accumulation layer 2 is disposed between the n-type drift layers 1. Additionally, in the n-type drift layers 1... - An n-type buffer layer 3 is provided on the second main surface 1b side of the n-type drift layer 1, and a p-type collector layer 16 is provided between the n-type buffer layer 3 and the second main surface 1b.

[0141] like Figure 22 and Figure 23 As shown, in the boundary region 50, a p-type base layer 15 is provided on the first main surface 1a side of the semiconductor substrate in the region near the IGBT region 10, and a p-type anode layer 25 is provided on the first main surface 1a side of the semiconductor substrate in the region near the diode region 20. Furthermore, in the boundary region 50 where the p-type base layer 15 is provided, a p-type anode layer 25 is provided on the first main surface 1a side of the semiconductor substrate in the region near the diode region 20. - An n-type carrier accumulation layer 2 is disposed between the n-type drift layers 1.

[0142] As described in Embodiment 1, the p-type base layer 15 of the boundary region 50 is a p-type semiconductor layer that is continuous from the p-type base layer 15 of the IGBT region 10, the n-type carrier accumulation layer 2 of the boundary region 50 is an n-type semiconductor layer that is continuous from the n-type carrier accumulation layer 2 of the IGBT region 10, and the p-type anode layer 25 of the boundary region 50 is a p-type semiconductor layer that is continuous from the p-type anode layer 25 of the diode region 20. The depth of the n-type carrier accumulation layer 2 disposed in the IGBT region 10 and the boundary region 50 from the first main surface 1a of the semiconductor substrate is greater than that of the p-type anode layer 25 disposed in the diode region 20 and the n-type anode layer 25 disposed in the boundary region 50. - The boundary of drift layer 1 is shallow. Figure 22 and Figure 23 Although not illustrated, as described in Embodiment 1, the n-type carrier accumulation layer 2 and the p-type anode layer 25 are in contact at the boundary region 50.

[0143] like Figure 22 and Figure 23 As shown, in the boundary region 50, an n-type impurity concentration higher than that of the n-type carrier accumulation layer 2 is selectively provided on the surface of the p-type base layer 15 or the p-type anode layer 25. + Type 53 carrier injection suppression layer. In adjacent n... + p-type carrier injection suppression layers 53 are provided between them + Type contact layer 14 or p + Type contact layer 24. p + Type contact layer 14 or p + The contact layer 24 can be set at a depth ratio n from the first main surface 1a. + The location of the carrier injection suppression layer 53 is at its depth. Furthermore, it may not be necessary to set p... + Type contact layer 14 or p + Type 24 contact layer can also replace p + Type contact layer 14 or p + A p-type base layer 15 or a p-type anode layer 25 is provided in the contact layer 24. In the boundary region 50, an n-type buffer layer 3 is provided on the second main surface 1b side of the semiconductor substrate, and a p-type collector layer 16 is provided between the n-type buffer layer 3 and the second main surface 1b.

[0144] like Figure 24 As shown, in diode region 20, a p-type anode layer 25 is provided on the first main surface 1a side of the semiconductor substrate, and a p-type anode layer is provided on the surface portion of the p-type anode layer 25. + Type contact layer 24. P-type anode layer 25 can be selectively provided on the surface portion of the p-type anode layer 25. + Type contact layer 24. Type p anode layer 25 and n - Type drift layer 1 contact, p-type anode layer 25 and n- The boundary of the n-type drift layer 1 is located at a depth deeper than that where the n-type carrier accumulation layer 2 is located. Furthermore, in the n... - An n-type buffer layer 3 is provided on the second main surface 1b side of the n-type drift layer 1, and an n-type buffer layer is provided between the n-type buffer layer 3 and the second main surface 1b. + Type 26 cathode layer.

[0145] The semiconductor device of Embodiment 2 is configured as described above. In the semiconductor device of Embodiment 2, since an n-type base layer 15 or a p-type anode layer 25 is provided on the surface portion of the boundary region 50, + The carrier injection suppression layer 53 reduces the supply of holes from the first main surface 1a side of the boundary region 50, thus reducing the hole injection efficiency into the diode region 20. Therefore, it is possible to suppress the voltage drop of the semiconductor device and reduce the recovery loss during diode operation.

[0146] Implementation Method 3

[0147] Figure 25 This is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of the RC-IGBT, i.e., the semiconductor device, in Embodiment 3. Figure 25 yes Figure 1 The semiconductor device 100 shown or Figure 2 The cross-sectional view at the dashed line GG in the semiconductor device 101 shown is the same as that described in Embodiment 1. Figure 9 or Figure 10 The cross-sectional view shown is different; it is a cross-sectional view of a semiconductor device with a structure that does not have a boundary region 50 between the IGBT region 10 and the diode region 20.

[0148] like Figure 25 As shown, in Embodiment 3, the semiconductor device is arranged such that the IGBT region 10 and the diode region 20 are adjacent to each other. A gate trench electrode 11a, serving as an IGBT trench electrode, is provided at the boundary between the IGBT region 10 and the diode region 20. Figure 25 In this design, the IGBT trench electrode located at the boundary between the IGBT region 10 and the diode region 20 is designated as the gate trench electrode 11a, but it can also be designated as the dumb trench electrode 12a.

[0149] The semiconductor device in Embodiment 3 is similar to the semiconductor device 100 or semiconductor device 101 described in Embodiment 1, in that an n-type carrier accumulation layer 2 is provided in the IGBT region 10. The n-type carrier accumulation layer 2 is provided at a depth from the first main surface 1a that is greater than that of the p-type anode layer 25 and n-type anode layer 25 provided in the diode region 20. -a shallow position of the boundary of the p-type drift layer 1. That is, the p-type anode layer 25 is provided at a depth from the first main surface la of the semiconductor substrate deeper than the n-type carrier accumulation layer 2 and the n-type emitter layer 3 provided in the IGBT region 10. - a deep position of the boundary of the p-type drift layer 1.

[0150] The semiconductor device of Embodiment 3, like the semiconductor device described in Embodiment 1, since the depth of the p-type anode layer 25 of the diode region 20 from the first main surface la of the semiconductor substrate is set deeper than the depth of the n-type carrier accumulation layer 2 from the first main surface la provided in the IGBT region 10, concentration of the electric field toward the n-type carrier accumulation layer 2 is suppressed, and thus reduction in the withstand voltage of the semiconductor device can be suppressed.

[0151] Further, in the above-described Embodiments 1 to 3, the trench-type semiconductor device in which a trench is formed in the IGBT region 10 and the diode region 20 of the semiconductor device, and an electrode is provided in the trench through an insulating film is described, but the semiconductor device of the present application can also be a planar-type semiconductor device in which no trench is formed and an electrode is provided on the first main surface la of the semiconductor substrate through an insulating film. Also, it can be a semiconductor device in which a trench is formed only in the IGBT region 10, and no trench is formed in the diode region 20 or the boundary region 50.

[0152] Further, appropriate combination, modification, and omission of each of the embodiments are included in the scope of the present application.

[0153] Explanation of Reference Numerals

[0154] 1 n - p-type drift layer, la first main surface, lb second main surface

[0155] 2 n-type carrier accumulation layer

[0156] 6 emitter electrode

[0157] 10 IGBT region

[0158] 11 active trench gate, 11a gate trench electrode (IGBT trench electrode), 11b gate trench insulating film

[0159] 12 dummy trench gate, 12a dummy trench electrode (IGBT trench electrode), 12b dummy trench insulating film

[0160] 13 n + p-type emitter layer

[0161] 15 p-type base layer

[0162] 16 p-type collector layer, 16a p-type terminal collector layer

[0163] 20 diode region

[0164] 21 diode trench gate, 21a diode trench electrode, 21b diode trench insulating film

[0165] 25 p-type anode layer

[0166] 26 n + type cathode layer

[0167] 30 end region

[0168] 31 p-type end well layer

[0169] 50 boundary region

[0170] 51a boundary trench electrode

[0171] 53 n + type carrier injection suppression layer

[0172] 60, 61 resist mask

[0173] 100, 101 semiconductor device

Claims

1. A semiconductor device having an IGBT region and a diode region on a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, the IGBT region and the diode region being arranged in a first direction along the first main surface, the semiconductor device comprising: the IGBT region having: a collector layer of a second conductivity type provided between the drift layer and the second main surface; a carrier accumulation layer of the first conductivity type provided on the first main surface side of the drift layer in contact with the drift layer, the impurity concentration of the first conductivity type being higher than that of the drift layer; a base layer of the second conductivity type provided between the carrier accumulation layer and the first main surface; an emitter layer of the first conductivity type selectively provided in a surface portion of the base layer, the emitter layer having a portion of the first main surface; and a gate electrode provided opposite to the emitter layer and the base layer with an insulating film interposed therebetween, the diode region having: a cathode layer of the first conductivity type provided between the drift layer and the second main surface; and an anode layer of the second conductivity type provided between the drift layer and the first main surface to a position deeper than a boundary between the carrier accumulation layer and the drift layer, the collector layer and the cathode layer being provided in contact with each other in the first direction.

2. The semiconductor device according to claim 1, wherein the impurity concentration of the second conductivity type of the anode layer is higher than the impurity concentration of the first conductivity type of the carrier accumulation layer.

3. The semiconductor device according to claim 1 or 2, wherein the IGBT region has a plurality of IGBT trench electrodes extending in a second direction orthogonal to the first direction along the first main surface, the IGBT trench electrodes being provided in trenches reaching the drift layer from the first main surface through the base layer with the insulating film interposed therebetween, the diode region has a plurality of diode trench electrodes extending in the second direction, the diode trench electrodes being provided in trenches reaching the drift layer from the first main surface through the anode layer with the insulating film interposed therebetween, and at least a portion of the plurality of IGBT trench electrodes are the gate electrodes.

4. A semiconductor device having an IGBT region and a diode region on a semiconductor substrate having a drift layer of a first conductivity type between a first main surface and a second main surface opposite to the first main surface, the IGBT region and the diode region being arranged in a first direction along the first main surface, the semiconductor device comprising: the IGBT region having: a collector layer of a second conductivity type provided between the drift layer and the second main surface; a carrier accumulation layer of the first conductivity type provided on the first main surface side of the drift layer in contact with the drift layer, the impurity concentration of the first conductivity type being higher than that of the drift layer; a base layer of the second conductivity type provided between the carrier accumulation layer and the first main surface; and an emitter layer of the first conductivity type selectively provided in a surface portion of the base layer, the emitter layer having a portion of the first main surface, the diode region having: a cathode layer of the first conductivity type provided between the drift layer and the second main surface; and an anode layer of the second conductivity type provided between the drift layer and the first main surface to a position deeper than a boundary between the carrier accumulation layer and the drift layer, the collector layer and the cathode layer being provided in contact with each other in the first direction. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ an emitter layer of a first conductivity type selectively provided in a surface layer portion of the base layer, having a portion of the first main surface; and a gate electrode provided opposite the emitter layer and the base layer with an insulating film interposed therebetween, the diode region has: a cathode layer of the first conductivity type provided between the drift layer and the second main surface; and an anode layer of a second conductivity type provided between the drift layer and the first main surface, and provided to a position deeper than a boundary between the carrier accumulation layer and the drift layer, the IGBT region has a plurality of IGBT trench electrodes extending in a second direction orthogonal to the first direction along the first main surface, provided in a trench reaching the drift layer from the first main surface through the base layer with an insulating film interposed therebetween, the diode region has a plurality of diode trench electrodes extending in the second direction, provided in a trench reaching the drift layer from the first main surface through the anode layer with an insulating film interposed therebetween, at least a portion of the plurality of IGBT trench electrodes is the gate electrode, a boundary region having the drift layer is present between the IGBT trench electrode of the plurality of IGBT trench electrodes closest to the diode region and the diode trench electrode of the plurality of diode trench electrodes closest to the IGBT region, the boundary region has the collector layer between the drift layer and the second main surface, the carrier accumulation layer and the anode layer are in contact at the boundary region.

5. The semiconductor device according to claim 4, wherein an emitter electrode electrically connected to the emitter layer, the base layer, and the anode layer is present on the first main surface, the IGBT trench electrode closest to the diode region and the diode trench electrode closest to the IGBT region are electrically connected to the emitter electrode.

6. The semiconductor device according to claim 5, wherein the boundary region has a boundary trench electrode extending in the second direction, provided in a trench reaching the drift layer from the first main surface with an insulating film interposed therebetween, the boundary trench electrode is electrically connected to the emitter electrode.

7. The semiconductor device according to any one of claims 4 to 6, wherein the boundary region has the base layer or the anode layer between the drift layer and the first main surface, a carrier injection suppression layer of a first conductivity type is selectively provided in a surface layer portion of the base layer or the anode layer included in the boundary region, having a higher impurity concentration of the first conductivity type than the carrier accumulation layer.

8. A method of manufacturing a semiconductor device, comprising the steps of: A semiconductor substrate of a first conductivity type is prepared, the semiconductor substrate of the first conductivity type having a first main surface and a second main surface opposite to the first main surface, having a first region in which IGBT regions are arranged in a first direction along the first main surface and a second region in which diode regions are formed; A first resist mask having a first opening over the first main surface of the first region is formed; Impurity ions of the first conductivity type are implanted from the first opening to form a carrier storage layer of the first conductivity type; Impurity ions of a second conductivity type are implanted from the first opening to form a base layer of the second conductivity type between the first main surface and the carrier storage layer; A second resist mask having a second opening over the first main surface of the second region is formed; Impurity ions of the second conductivity type are implanted from the second opening to form an anode layer of the second conductivity type from a position deeper than a depth at which the carrier storage layer is formed to the first main surface; In the IGBT regions, impurities of the second conductivity type are implanted from the second main surface side of the semiconductor substrate to form a collector layer of the second conductivity type; and In the diode regions, impurities of the first conductivity type are selectively implanted from the second main surface side by a mask process to form a cathode layer of the first conductivity type, the collector layer and the cathode layer are formed to be in contact with each other in the first direction.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the first opening and the second opening partially overlap each other, the carrier storage layer and the anode layer are formed by implanting impurity ions in a manner that they partially overlap each other.

10. The method of manufacturing a semiconductor device according to claim 8, wherein the step of forming the anode layer is performed before the step of forming the carrier storage layer.

11. The method of manufacturing a semiconductor device according to claim 10, wherein a heating step of diffusing impurity ions of the anode layer within the semiconductor substrate is performed after the step of forming the anode layer, the step of forming the carrier storage layer is performed after the heating step.

12. The method of manufacturing a semiconductor device according to any one of claims 8 to 11, wherein the semiconductor substrate has a third region that is a terminal region formed around the first region and the second region, the second resist mask has a third opening over the first main surface of the third region, in the step of forming the anode layer, impurity ions of the second conductivity type are simultaneously implanted from the second opening and the third opening to form the anode layer and a terminal well layer of the second conductivity type. ​

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