Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate having a plurality of first and second fins separated from each other, the first fin including a first isolation region and the second fin including a second isolation region; a plurality of first source-drain doped layers within the first fin, the first source-drain doped layers having first source-drain ions; a plurality of second source-drain doped layers within the second fin, the second source-drain doped layers having second source-drain ions, the first source-drain ions and the second source-drain ions being of opposite electrical types; a first isolation structure within the first isolation region, the first isolation structure providing a first stress for the first fin; and a second isolation structure within the second isolation region, the second isolation structure providing a second stress for the second fin, the first stress and the second stress being of opposite stress types. By using the first and second stresses of opposite stress types, the stress requirements of different types of transistor structures are simultaneously met, thereby improving the performance of the resulting semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the integration density of semiconductor devices increases, the critical dimensions of transistors continue to shrink. However, as transistor dimensions decrease dramatically, the gate dielectric thickness and operating voltage cannot be adjusted accordingly, making it more difficult to suppress the short channel effect and increasing the channel leakage current of the transistor.

[0003] The gate of the Fin Field-Effect Transistor (FinFET) is a forked 3D structure similar to a fish fin. The channel of the FinFET protrudes from the surface of the substrate to form a fin, and the gate covers the top surface and sidewalls of the fin, so that an inversion layer is formed on each side of the channel, which can control the connection and disconnection of the circuit on both sides of the fin. This design can increase the control of the gate over the channel region, thereby effectively suppressing the short channel effect of the transistor. However, the short channel effect still exists in the Fin Field-Effect Transistor.

[0004] Furthermore, to further reduce the impact of the short channel effect on semiconductor devices and lower channel leakage current, strained silicon technology has been introduced into the field of semiconductor technology. The strained silicon technology method includes: forming grooves in the fins on both sides of the gate structure; and forming source and drain doped regions in the grooves through an epitaxial growth process.

[0005] In order to prevent the source and drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fin. At the same time, in order to reduce the area of ​​the isolation layer and improve the integration of the formed semiconductor structure, the existing technology introduces SDB (Single Diffusion Break) technology.

[0006] However, existing methods still have many problems in the process of forming semiconductor structures. Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate, having a plurality of mutually separate first fins and second fins, the first fins including a first isolation region, and the second fins including a second isolation region; a plurality of first source-drain doped layers located in the first fins, the first source-drain doped layers having first source-drain ions; a plurality of second source-drain doped layers located in the second fins, the second source-drain doped layers having second source-drain ions, the first source-drain ions and the second source-drain ions having opposite electrical types; a first isolation structure located in the first isolation region, the first isolation structure providing a first stress for the first fin; a second isolation structure located in the second isolation region, the second isolation structure providing a second stress for the second fin, the first stress and the second stress having opposite stress types.

[0009] Optionally, it also includes: a plurality of second gate structures located on the substrate, the second gate structure spanning the first fin and the second fin; the first source-drain doped layer located between adjacent first isolation structures and second gate structures, or between adjacent second gate structures; the second source-drain doped layer located between adjacent second isolation structures and second gate structures, or between adjacent second gate structures; and a dielectric layer located on the substrate, the dielectric layer covering the sidewalls of the second gate structure.

[0010] Optionally, the first source and drain ions include N-type ions or P-type ions; and the second source and drain ions include P-type ions or N-type ions.

[0011] Optionally, when the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress; when the first source and drain ions are P-type ions and the second source and drain ions are N-type ions, the first stress is compressive stress and the second stress is tensile stress.

[0012] Optionally, the material of the first isolation structure is different from the material of the second isolation structure.

[0013] Optionally, the material of the first isolation structure includes silicon oxide or silicon nitride.

[0014] Optionally, the material of the second isolation structure includes silicon oxide or silicon nitride.

[0015] Correspondingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually discrete first fins and a plurality of mutually discrete second fins, the first fins including a first isolation region, and the second fins including a second isolation region; forming a plurality of first source-drain doping layers in the first fins, the first source-drain doping layers having first source-drain ions; forming a plurality of second source-drain doping layers in the second fins, the second source-drain doping layers having second source-drain ions, the first source-drain ions and the second source-drain ions having opposite electrical types; forming a first isolation structure in the first isolation region, the first isolation structure providing a first stress for the first fins; forming a second isolation structure in the second isolation region, the second isolation structure providing a second stress for the second fins, the first stress and the second stress having opposite stress types.

[0016] Optionally, the method for forming the first isolation structure and the second isolation structure includes: forming a first gate structure on the substrate, the first gate structure spanning the first isolation region and the second isolation region; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first gate structure; removing the first gate structure and a portion of the first isolation region located on the first fin, forming a first opening in the dielectric layer and the first isolation region; forming the first isolation structure in the first opening; removing the first gate structure and a portion of the second isolation region located on the second fin, forming a second opening in the dielectric layer and the second isolation region; and forming the second isolation structure in the second opening.

[0017] Optionally, in the process of forming the first gate structure, it also includes: forming a plurality of second gate structures on the substrate, the second gate structure spanning the first fin and the second fin; the first source-drain doped layer is located between adjacent first gate structures and second gate structures, or between adjacent second gate structures; the second source-drain doped layer is located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

[0018] Optionally, before forming the first gate structure and the second gate structure, it also includes: forming a first dummy gate structure on the substrate, the first dummy gate structure spanning the first isolation region and the second isolation region; forming a plurality of second dummy gate structures on the substrate, the second dummy gate structures spanning the first fin and the second fin.

[0019] Optionally, the method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening.

[0020] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doping layer, the second source-drain doping layer, the first dummy gate structure and the second dummy gate structure; and flattening the initial dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form the dielectric layer.

[0021] Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming a first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

[0022] Optionally, the first source and drain ions include N-type ions or P-type ions; and the second source and drain ions include P-type ions or N-type ions.

[0023] Optionally, when the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress; when the first source and drain ions are P-type ions and the second source and drain ions are N-type ions, the first stress is compressive stress and the second stress is tensile stress.

[0024] Optionally, the material of the first isolation structure is different from the material of the second isolation structure.

[0025] Optionally, the material of the first isolation structure includes silicon oxide or silicon nitride.

[0026] Optionally, the material of the second isolation structure includes silicon oxide or silicon nitride.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the structure of the technical solution of the present invention, a first isolation structure located within the first isolation region provides a first stress to the first fin; a second isolation structure located within the second isolation region provides a second stress to the second fin, wherein the first stress and the second stress are of opposite stress types. The first and second stresses of opposite stress types can simultaneously meet the stress requirements of different types of transistor structures, thereby improving the performance of the resulting semiconductor structure.

[0029] In the formation method of the technical solution of the present invention, a first isolation structure is formed within the first isolation region, providing a first stress to the first fin; a second isolation structure is formed within the second isolation region, providing a second stress to the second fin, wherein the first stress and the second stress are of opposite stress types. The first and second stresses of opposite stress types can simultaneously meet the stress requirements of different types of transistor structures, thereby improving the performance of the resulting semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 3 It is a structural diagram of a semiconductor structure;

[0031] Figures 4 to 18 It is a schematic structural diagram of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0032] As described in the background art, existing methods still have many problems in the process of forming semiconductor structures, which will be described in detail below with reference to the accompanying drawings.

[0033] Figures 1 to 3 It is a structural diagram of a semiconductor structure.

[0034] Please refer to Figures 1 to 3 , Figure 1 It is a top view of the semiconductor structure omitting the dielectric layer and isolation layer. Figure 2 yes Figure 1 Schematic diagram of the cross section along the AA direction, Figure 3 yes Figure 1The cross-sectional schematic diagram along the BB direction includes: a substrate 100, the substrate 100 including a first region I and a second region II, the first region I having a plurality of mutually discrete first fins 101, the first fins 101 including a first isolation region 102, the second region II having a plurality of mutually discrete second fins 103, the second fins 103 including a second isolation region 104; a plurality of first source-drain doped layers 108 located within the first fins 101, the first source-drain doped layers 108 having first source-drain ions therein; a plurality of second source-drain doped layers 105 located within the second fins 103, the second source-drain doped layers 105 having second source-drain ions therein, the first source-drain ions and the second source-drain ions having opposite electrical types; a first isolation structure 106 located within the first isolation region 102, the first isolation structure 106 providing a first stress for the first fin 101; a second isolation structure 107 located within the second isolation region 104, the second isolation structure 107 providing a second stress for the second fin 103, the first stress and the second stress having the same stress type.

[0035] In this embodiment, by forming the first isolation structure 106 and the second isolation structure 107, it is possible to effectively prevent short circuits between the first source-drain doped layers 108 formed in the first fin 101 and short circuits between the second source-drain doped layers 105 formed in the second fin 103, thereby achieving an isolation effect.

[0036] In this embodiment, since the electrical types of the first source and drain ions are opposite to those of the second source and drain ions, the first fin 101 is used to form a PMOS transistor structure (NMOS transistor structure), and the second fin 103 is used to form an NMOS transistor structure (PMOS transistor structure). Since the PMOS transistor structure and the NMOS transistor structure have different stress requirements for the fins, the PMOS transistor structure needs to provide compressive stress for the first fin 101, and the compressive stress is generated by the first isolation structure 106 acting on the first fin 101, while the NMOS transistor structure needs to provide tensile stress for the second fin 103, and the tensile stress is generated by the second isolation structure 107 acting on the second fin 103.

[0037] However, in this embodiment, since the first isolation structure 106 and the second isolation structure 107 are formed simultaneously using the same process step, the materials of the first isolation structure 106 and the second isolation structure 107 are the same, and the corresponding first isolation structure 106 provides the first fin 101 with the same stress type as the second isolation structure 107 provides the second fin 103. Therefore, the stress requirements of the PMOS transistor structure and the NMOS transistor structure cannot be met at the same time, thereby reducing the performance of the finally formed semiconductor structure.

[0038] Based on this, the present invention provides a semiconductor structure and a method for forming the same. A first isolation structure located within the first isolation region provides a first stress to the first fin; a second isolation structure located within the second isolation region provides a second stress to the second fin. The first and second stresses are of opposite types. These structures simultaneously meet the stress requirements of different transistor types, thereby improving the performance of the resulting semiconductor structure.

[0039] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0040] Figures 4 to 18 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0041] Please refer to Figures 4 to 6 , Figure 4 It is a top view of the semiconductor structure omitting the dielectric layer and isolation layer. Figure 5 yes Figure 4 Schematic diagram of the cross section along the CC direction, Figure 6 yes Figure 4 A schematic cross-sectional view along the DD direction; providing a substrate 200 having a plurality of mutually discrete first fins 201 and a plurality of mutually discrete second fins 202 thereon, wherein the first fins 201 include a first isolation region A1, and the second fins 202 include a second isolation region A2.

[0042] In this embodiment, the method for forming the substrate 200, the first fin 201 and the second fin 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, wherein the patterned layer exposes a portion of the top surface of the initial substrate; and etching the initial substrate using the patterned layer as a mask to form the substrate 200, the first fin 201 and the second fin 202.

[0043] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0044] In this embodiment, the material of the first fin 201 and the second fin 202 is silicon; in other embodiments, the material of the first fin and the second fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] Please refer to Figure 7 and Figure 8 , Figure 7 and Figure 5 The view direction is consistent, Figure 8 and Figure 6 In the same viewing direction, an isolation layer 203 is formed on the substrate 200 , the isolation layer 203 covers part of the sidewalls of the first fin 201 and the second fin 202 , and the top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202 .

[0046] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching and removing a portion of the initial isolation layer to form the isolation layer 203, wherein the top surface of the isolation layer 203 is lower than the top surface of the first fin 201 and the second fin 202.

[0047] The isolation layer 203 is made of an insulating material, which includes silicon oxide or silicon oxynitride. In this embodiment, the isolation layer 203 is made of silicon oxide.

[0048] After forming the isolation layer 203, the method further includes: forming a plurality of first source-drain doped layers in the first fin 201, wherein the first source-drain doped layers have first source-drain ions; forming a plurality of second source-drain doped layers in the second fin 202, wherein the second source-drain doped layers have second source-drain ions, wherein the first source-drain ions and the second source-drain ions have opposite electrical types. For the specific formation process of the first source-drain doped layers and the second source-drain doped layers, please refer to Figures 9 to 12 .

[0049] Please refer to Figure 9 and Figure 10 , a first dummy gate structure 204 is formed on the substrate 200, and the first dummy gate structure 204 spans the first isolation region A1 and the second isolation region A2; and a plurality of second dummy gate structures 205 are formed on the substrate 200, and the second dummy gate structures 205 span the first fin 201 and the second fin 202.

[0050] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously using the same photomask. The first dummy gate structure 204 and the second dummy gate structure 205 are formed simultaneously through a global process, which can effectively improve production efficiency.

[0051] In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 both include: a dummy gate dielectric layer, a dummy gate layer located on the dummy gate dielectric layer, and sidewalls (not marked) located on the sidewalls of the dummy gate dielectric layer and the dummy gate layer.

[0052] In this embodiment, the material of the dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the dummy gate dielectric layer may also be silicon oxynitride.

[0053] In this embodiment, the material of the dummy gate layer is polysilicon.

[0054] Please continue to refer to Figure 9 and Figure 10 After forming the first dummy gate structure 204 and the second dummy gate structure 205 , a first sidewall (not labeled) is formed on the sidewall of the first dummy gate structure 204 ; a second sidewall (not labeled) is formed on the sidewall of the second dummy gate structure 205 .

[0055] In this embodiment, the method for forming the first side wall and the second side wall includes: forming an initial side wall layer (not shown) on the side walls and top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205, and the surface of the isolation layer; etching back the initial side wall layer until the first dummy gate structure 204, the second dummy gate structure 205 and the top surface of the isolation layer 203 are exposed, thereby forming the first side wall and the second side wall.

[0056] In this embodiment, the initial spacer layer is formed by an atomic layer deposition process.

[0057] In this embodiment, the first sidewall spacer and the second sidewall spacer are made of silicon nitride.

[0058] Please refer to Figure 11 and Figure 12 The first fin 201 and the second fin 202 are etched using the first dummy gate structure 204 and the second dummy gate structure 205 as masks to form a plurality of first source-drain openings (not marked) in the first fin 201; a plurality of second source-drain openings (not marked) are formed in the second fin 202; the first source-drain doped layer 206 is formed in the first source-drain openings; and the second source-drain doped layer 207 is formed in the second source-drain openings.

[0059] In this embodiment, the method for forming the first source-drain doped layer 206 in the first source-drain opening includes: forming a first epitaxial layer (not marked) in the first source-drain opening using an epitaxial growth process; in-situ doping the first epitaxial layer during the epitaxial growth process, and introducing first source-drain ions into the first epitaxial layer to form the first source-drain doped layer 206.

[0060] In this embodiment, the method for forming the second source-drain doped layer 207 in the second source-drain opening includes: forming a second epitaxial layer (not marked) in the second source-drain opening using an epitaxial growth process; in-situ doping the second epitaxial layer during the epitaxial growth process, and introducing second source-drain ions into the second epitaxial layer to form the second source-drain doped layer 207.

[0061] In this embodiment, the first source and drain ions and the second source and drain ions are of different electrical types; the first source and drain ions are P-type ions, and the second source and drain ions are N-type ions. In other embodiments, the first source and drain ions may be N-type ions, and the second source and drain ions may be P-type ions.

[0062] After forming the first source-drain doped layer 206 and the second source-drain doped layer 207, the method further includes: forming a first isolation structure in the first isolation region A1, the first isolation structure providing a first stress for the first fin 201; forming a second isolation structure in the second isolation region A2, the second isolation structure providing a second stress for the second fin 202, the first stress and the second stress being of opposite stress types. For the specific formation process of the first isolation structure and the second isolation structure, please refer to Figures 13 to 18 .

[0063] Please refer to Figure 13 and Figure 14 , a dielectric layer 208 is formed on the substrate 200 , and the dielectric layer 208 covers the sidewalls of the first dummy gate structure 204 and the second dummy gate structure 205 .

[0064] In this embodiment, the method for forming the dielectric layer 208 includes: forming an initial dielectric layer (not shown) on the substrate 200, the initial dielectric layer covering the first source-drain doping layer 206, the second source-drain doping layer 207, the first dummy gate structure 204 and the second dummy gate structure 205; and flattening the initial dielectric layer until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed, thereby forming the dielectric layer 208.

[0065] In this embodiment, the material of the dielectric layer 208 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0066] Please refer to Figure 15 and Figure 16 , remove the first dummy gate structure 204, and form a first gate opening in the dielectric layer 208; remove the second dummy gate structure 205, and form a second gate opening in the dielectric layer 208; form a first gate structure 209 in the first gate opening; and form the second gate structure 210 in the second gate opening.

[0067] In this embodiment, the first source-drain doped layer 206 is located between adjacent first gate structures 209 and second gate structures 210, or between adjacent second gate structures 210; the second source-drain doped layer 207 is located between adjacent first gate structures 209 and second gate structures 210, or between adjacent second gate structures 210.

[0068] In this embodiment, the first gate structure 209 and the second gate structure 210 are formed simultaneously, and the first gate structure 209 and the second gate structure 210 respectively include: a gate dielectric layer, a gate layer located on the gate dielectric layer, and a protection layer (not marked) located on the gate layer.

[0069] In this embodiment, the gate dielectric layer is made of a high-K dielectric material.

[0070] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0071] In this embodiment, the material of the protective layer is silicon nitride.

[0072] Please refer to Figure 17 and Figure 18 , the first gate structure 209 and a portion of the first isolation region A1 located on the first fin 201 are removed, and a first opening (not shown) is formed in the dielectric layer 208 and the first isolation region A1; the first isolation structure 211 is formed in the first opening; the first gate structure 209 and a portion of the second isolation region A2 located on the second fin 202 are removed, and a second opening (not shown) is formed in the dielectric layer 208 and the second isolation region A2; and the second isolation structure 212 is formed in the second opening.

[0073] In this embodiment, since the first source and drain ions are P-type ions, the corresponding first stress is compressive stress F1; and since the second source and drain ions are N-type ions, the corresponding second stress F2 is tensile stress. In other embodiments, when the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress.

[0074] In this embodiment, a first isolation structure 211 is formed within the first isolation region A1 to provide a first stress F1 for the first fin 201. A second isolation structure 212 is formed within the second isolation region A2 to provide a second stress F2 for the second fin 202. The first stress F1 and the second stress F2 are of opposite stress types. The first stress F1 and the second stress F2 can simultaneously meet the stress requirements of different types of transistor structures, thereby improving the performance of the resulting semiconductor structure.

[0075] In this embodiment, different stress types are generated in the first isolation structure 211 and the second isolation structure 212 by using different materials for the first isolation structure 211 and the second isolation structure 212 .

[0076] In this embodiment, the material of the first isolation structure 211 is silicon oxide, and the pressure and temperature of the silicon oxide material are adjusted so that the finally formed first isolation structure 211 provides the first stress F1 for the first fin 201; in other embodiments, the material of the first isolation structure may also be silicon nitride, and the pressure and temperature of the silicon nitride material are adjusted so that the finally formed first isolation structure provides the first stress for the first fin.

[0077] In this embodiment, the material of the second isolation structure 212 is silicon nitride, and the pressure and temperature of the silicon nitride material are adjusted so that the finally formed second isolation structure 212 provides the second stress F2 for the second fin 202; in other embodiments, the material of the second isolation structure may also be silicon oxide, and the pressure and temperature of the silicon oxide material are adjusted so that the finally formed second isolation structure provides the second stress for the second fin.

[0078] Accordingly, the embodiment of the present invention further provides a semiconductor structure, please continue to refer to Figure 17 and Figure 18, including: a substrate 200, on which are provided a plurality of mutually separate first fins 201 and second fins 202, the first fin 201 including a first isolation region A1, and the second fin 202 including a second isolation region A2; a plurality of first source-drain doped layers 206 located in the first fin 201, the first source-drain doped layers 206 having first source-drain ions; a plurality of second source-drain doped layers 207 located in the second fin 202, the second source-drain doped layers 207 having second source-drain ions, the first source-drain ions and the second source-drain ions having opposite electrical types; a first isolation structure 211 located in the first isolation region A1, the first isolation structure 211 providing a first stress F1 for the first fin 201; a second isolation structure 212 located in the second isolation region A2, the second isolation structure 212 providing a second stress F2 for the second fin 202, the first stress F1 and the second stress F2 having opposite stress types.

[0079] In this embodiment, a first isolation structure 211 located within the first isolation region A1 provides a first stress F1 to the first fin 201. A second isolation structure 212 located within the second isolation region A2 provides a second stress F2 to the second fin 202. The first stress F1 and the second stress F2 are of opposite stress types. These structures simultaneously meet the stress requirements of different types of transistor structures, thereby improving the performance of the resulting semiconductor structure.

[0080] In this embodiment, it also includes: a plurality of second gate structures 210 located on the substrate 200, the second gate structure 210 spanning the first fin 201 and the second fin 202; the first source-drain doped layer 206 located between adjacent first isolation structures 211 and second gate structures 210, or between adjacent second gate structures 210; the second source-drain doped layer 207 located between adjacent second isolation structures 212 and second gate structures 210, or between adjacent second gate structures 210; and a dielectric layer 208 located on the substrate 200, the dielectric layer 208 covering the sidewalls of the second gate structure 210.

[0081] In this embodiment, the first source and drain ions are P-type ions, and the second source and drain ions are N-type ions; in other embodiments, the first source and drain ions may also be N-type ions, and the second source and drain ions may be P-type ions.

[0082] In this embodiment, when the first source and drain ions are P-type ions and the second source and drain ions are N-type ions, the first stress F1 is compressive stress and the second stress F2 is tensile stress. In other embodiments, when the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress.

[0083] In this embodiment, the material of the first isolation structure 211 and the material of the second isolation structure 212 are different.

[0084] In this embodiment, the material of the first isolation structure 211 is silicon oxide, and the pressure and temperature of the silicon oxide material are adjusted so that the finally formed first isolation structure 211 provides the first stress F1 for the first fin 201; in other embodiments, the material of the first isolation structure may also be silicon nitride, and the pressure and temperature of the silicon nitride material are adjusted so that the finally formed first isolation structure provides the first stress for the first fin.

[0085] In this embodiment, the material of the second isolation structure 212 is silicon nitride, and the pressure and temperature of the silicon nitride material are adjusted so that the finally formed second isolation structure 212 provides the second stress F2 for the second fin 202; in other embodiments, the material of the second isolation structure may also be silicon oxide, and the pressure and temperature of the silicon oxide material are adjusted so that the finally formed second isolation structure provides the second stress for the second fin.

[0086] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate having a plurality of first fins and second fins separated from each other, wherein the first fins include a first isolation region, and the second fins include a second isolation region; a plurality of first source-drain doped layers located in the first fin, wherein the first source-drain doped layers have first source-drain ions; a plurality of second source-drain doped layers located in the second fin, wherein the second source-drain doped layers have second source-drain ions, and the first source-drain ions and the second source-drain ions are of opposite electrical types; a first isolation structure located in the first isolation region, wherein the first isolation structure provides a first stress for the first fin; a second isolation structure located in the second isolation region, the second isolation structure providing a second stress for the second fin, wherein the first stress and the second stress are of opposite stress types; a plurality of second gate structures located on the substrate, wherein the second gate structures span the first fin and the second fin; The first source-drain doped layer is located between adjacent first isolation structures and second gate structures, or between adjacent second gate structures; The second source-drain doped layer is located between adjacent second isolation structures and second gate structures, or between adjacent second gate structures.

2. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric layer is located on the substrate, and the dielectric layer covers the sidewalls of the second gate structure.

3. The semiconductor structure according to claim 1, wherein: The first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

4. The semiconductor structure according to claim 3, wherein: When the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress; when the first source and drain ions are P-type ions and the second source and drain ions are N-type ions, the first stress is compressive stress and the second stress is tensile stress.

5. The semiconductor structure according to claim 1, wherein: The material of the first isolation structure is different from the material of the second isolation structure.

6. The semiconductor structure according to claim 5, wherein: The material of the first isolation structure includes silicon oxide or silicon nitride.

7. The semiconductor structure according to claim 5, wherein: The material of the second isolation structure includes silicon oxide or silicon nitride.

8. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of mutually separate first fins and a plurality of mutually separate second fins, wherein the first fins include a first isolation region, and the second fins include a second isolation region; forming a plurality of first source-drain doped layers in the first fin, wherein the first source-drain doped layers contain first source-drain ions; forming a plurality of second source-drain doped layers in the second fin, wherein the second source-drain doped layers have second source-drain ions, and the first source-drain ions and the second source-drain ions are of opposite electrical types; forming a first isolation structure in the first isolation region, wherein the first isolation structure provides a first stress for the first fin; forming a second isolation structure in the second isolation region, wherein the second isolation structure provides a second stress for the second fin, and the first stress and the second stress are of opposite stress types; forming a plurality of second gate structures on the substrate, wherein the second gate structures span the first fin and the second fin; The first source-drain doped layer is located between adjacent first isolation structures and second gate structures, or between adjacent second gate structures; The second source-drain doped layer is located between adjacent second isolation structures and second gate structures, or between adjacent second gate structures.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming the first isolation structure and the second isolation structure includes: forming a first gate structure on the substrate, the first gate structure spanning the first isolation region and the second isolation region; forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first gate structure; removing the first gate structure and a portion of the first isolation region located on the first fin, forming a first opening in the dielectric layer and the first isolation region; forming the first isolation structure in the first opening; removing the first gate structure and a portion of the second isolation region located on the second fin, forming a second opening in the dielectric layer and the second isolation region; and forming the second isolation structure in the second opening.

10. The method for forming a semiconductor structure according to claim 9, wherein: The process of forming the first gate structure also includes: forming a plurality of second gate structures on the substrate; the first source-drain doped layer is located between adjacent first gate structures and second gate structures, or between adjacent second gate structures; the second source-drain doped layer is located between adjacent first gate structures and second gate structures, or between adjacent second gate structures.

11. The method for forming a semiconductor structure according to claim 10, wherein: Before forming the first gate structure and the second gate structure, the method further includes: forming a first dummy gate structure on the substrate, wherein the first dummy gate structure spans the first isolation region and the second isolation region; and forming a plurality of second dummy gate structures on the substrate, wherein the second dummy gate structures span the first fin and the second fin.

12. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first source-drain doped layer and the second source-drain doped layer includes: etching the first fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of first source-drain openings in the first fin; etching the second fin using the first dummy gate structure and the second dummy gate structure as a mask to form a plurality of second source-drain openings in the second fin; forming the first source-drain doped layer in the first source-drain opening; and forming the second source-drain doped layer in the second source-drain opening.

13. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source-drain doped layer, the second source-drain doped layer, the first dummy gate structure and the second dummy gate structure; and flattening the initial dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form the dielectric layer.

14. The method for forming a semiconductor structure according to claim 11, wherein: The method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure to form a first gate opening in the dielectric layer; removing the second dummy gate structure to form a second gate opening in the dielectric layer; forming a first gate structure in the first gate opening; and forming the second gate structure in the second gate opening.

15. The method for forming a semiconductor structure according to claim 8, wherein: The first source-drain ions include N-type ions or P-type ions; the second source-drain ions include P-type ions or N-type ions.

16. The method for forming a semiconductor structure according to claim 15, wherein: When the first source and drain ions are N-type ions and the second source and drain ions are P-type ions, the first stress is tensile stress and the second stress is compressive stress; when the first source and drain ions are P-type ions and the second source and drain ions are N-type ions, the first stress is compressive stress and the second stress is tensile stress.

17. The method for forming a semiconductor structure according to claim 8, wherein: The material of the first isolation structure is different from the material of the second isolation structure.

18. The method for forming a semiconductor structure according to claim 17, wherein: The material of the first isolation structure includes silicon oxide or silicon nitride.

19. The method for forming a semiconductor structure according to claim 17, wherein: The material of the second isolation structure includes silicon oxide or silicon nitride.

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