Single-particle transient pulse width measurement circuit

Abstract

The invention discloses a single particle transient pulse width measurement circuit, belonging to the technical field of basic electronic circuits. The circuit comprises a front-stage detection part and a rear-stage logic control part, wherein the front-stage detection part comprises a double-chain detection circuit composed of two delay chains and a PD detector and a logic device for calculating the rear-stage logic control signal, and the rear-stage logic control part comprises a counter for classifying and counting the partial pulses of the SET pulse that exceed the measurement range. The invention has the advantages of low area cost, high detection accuracy and wide measurement range.

Description

Technical Field

[0001] The invention discloses a single-particle transient pulse width measurement circuit, relates to aerospace integrated circuit technology, and belongs to the technical field of basic electronic circuits. Background Art

[0002] High-energy particles in the irradiation environment may hit the MOS tube in the integrated circuit to generate additional electron-hole pairs. The additional electron-hole pairs are collected at the drain end of the MOS tube. When the high-energy particles hit the sensitive device, the logic state of the sensitive device is reversed. For example, the "0" originally stored in the memory becomes "1", or "1" becomes "0", which can cause a single event upset (SEU) in the timing circuit or a single event transient (SET) effect in the combinational circuit. SET is actually a voltage / current pulse. When it is captured by a timing device such as a trigger, it may cause a soft error. The width of the SET pulse is an important feature of SET, which determines the probability of being captured. However, the SET width depends on many factors, including the nature of the ionized particles, the energy of the ionized particles linearly transferred, the layout structure of the ionized particles in the space and space, and the position and angle of the ionized particles hitting the target device. In the advanced nano-scale CMOS process, accurately describing the SET width distribution is an issue that has received increasing attention.

[0003] There are two common methods for measuring SET pulse width. The first is to measure the SET pulse width based on off-chip measuring instruments such as oscilloscopes. The SET pulse width in nano-level CMOS advanced technology is usually less than 100ps. The SET pulse distortion caused by the pads on the chip and the instrument probes easily affects the measurement accuracy of the SET pulse width. The other is to measure the SET pulse width using an on-chip measurement circuit. The on-chip measurement method uses the inverter propagation delay time as the measurement time unit. When the SET leading edge propagates in the chain and reaches the self-triggering node, the latch chain locks the voltage of each inverter output node to obtain a digital code similar to 10 "01010" 01. This measurement method is limited by the propagation delay time of the inverter. Common on-chip measurement circuits include linear pulse filter circuits and vernier delay line circuits. The linear pulse filter circuit has a simple structure and a small implementation area, but the detection accuracy of the circuit is limited by the delay of a single logic gate. The vernier delay line circuit can achieve sub-logic gate delay accuracy, but increases the circuit complexity and circuit area. On the other hand, the existing on-chip measurement circuit increases the pulse width measurement range by increasing the number of circuit stages, which increases the circuit area and power consumption and cannot meet the measurement requirements of single-particle transient pulse width. Summary of the invention

[0004] The purpose of the present invention is to provide a single-particle transient pulse width measurement circuit to address the shortcomings of the above-mentioned background technology, solve the technical problems of the existing on-chip measurement circuits with limited detection accuracy, large circuit area, and failure to meet the requirements of single-particle transient pulse width measurement, and achieve the purpose of the invention of a single-particle transient pulse width measurement circuit with high resolution and wide measurement range with small area consumption. .

[0005] The present invention adopts the following technical solutions to achieve the above-mentioned invention object:

[0006] The single-particle transient pulse width measurement circuit comprises a front-stage detection part and a rear-stage logic control part.

[0007] The front-stage detection part includes: a first multiplexer, a second multiplexer, a third multiplexer, a first OR gate, a second OR gate, a first buffer chain, a second buffer chain, an AND gate array, a pulse detector array, a fourth multiplexer, a fifth multiplexer, a first AND gate, and a drive tree.

[0008] The post-stage logic control circuit includes: a fourth inverter, a second AND gate, a first NAND gate, a fifth inverter, a D trigger, a delay device, a pulse generator, a first counter, and a second counter.

[0009] The output of the first multiplexer is connected to the "0" input of the second multiplexer and the third multiplexer at the same time, the "0" input of the first multiplexer is connected to the SET_PLUSE signal, and the "1" input of the first multiplexer is connected to the second trigger signal. The selection signal of the first multiplexer is the first trigger signal.

[0010] The output end of the second multiplexer is connected to an input end of the first buffer in the first buffer chain, the "1" input end of the second multiplexer is connected to the output end of the first inverter, the "0" input end of the second multiplexer is connected to the output end of the first multiplexer, and the selection signal of the second multiplexer is the enable signal RO_VF_EN.

[0011] The output end of the third multiplexer is connected to an input end of the first buffer of the second buffer chain, the "1" input end of the third multiplexer is connected to the output end of inverter 2, the "0" input end of the third multiplexer is connected to the output end of the first multiplexer, and the selection signal of the third multiplexer is the enable signal RO_VF_EN.

[0012] The first buffer chain is composed of a series of cascaded AND gates. One input end of each AND gate in the chain is connected to the output end of the AND gate of the previous stage, and the other input end is simultaneously connected to the fourth trigger signal. One input end of the first AND gate in the chain is connected to the output end of the second multiplexer, and the output end of the last AND gate is connected to the input end of the first inverter.

[0013] The second buffer chain is composed of a series of cascaded AND gates. One input end of each AND gate in the chain is connected to the output end of the AND gate of the previous stage, and the other input end is simultaneously connected to the fourth trigger signal. One input end of the first AND gate in the chain is connected to the output end of the third multiplexer, and the output end of the last AND gate is connected to the input end of the second inverter.

[0014] The number of stages of the AND gate array corresponds to the number of stages of the buffer chain, two input ends of the AND gate of each corresponding stage are connected to the AND gate input ends of the non-trigger signal in the first buffer chain and the second buffer chain, and the other input end is connected to the output end of the third inverter. The output ends of the AND gates in the AND gate array are respectively connected to the set end S of the pulse detector of the corresponding stage.

[0015] The pulse detector array is composed of an RS flip-flop, which has two input terminals S and R and one output terminal Q. The set terminal S of the pulse detector is connected to the output terminal of the AND gate of the corresponding stage in the AND gate array, and the other input terminal R is connected to the output terminal of the second OR gate. The output signal Q is the pulse detection output result.

[0016] The output ends of the fourth multiplexer and the fifth multiplexer are connected to the two input ends of the first AND gate, the "1" input ends of the fourth multiplexer and the fifth multiplexer are connected to the GND signal, the selection signals of the fourth multiplexer and the fifth multiplexer are the enable signal RO_VF_EN, and the "0" input ends of the fourth multiplexer and the fifth multiplexer are respectively connected to the output ends of the last level AND gates of the first buffer chain and the second buffer device chain.

[0017] The input end of the driving tree is connected to the output end of the first AND gate and the input end of the third inverter, and the output end of the driving tree is connected to the input end of the delay module, the input end of the pulse generator, an input end of the second AND gate, and an input end of the first NAND gate.

[0018] The output signals of the second multiplexer and the third multiplexer are connected to the first OR gate, and the output signal of the first OR gate is DS. Only when the width of the pulse signal output by the second multiplexer and the pulse signal output by the third multiplexer exceeds the length of the second buffer chain, DS=1. The DS signal is connected to one input terminal of the first NAND gate and the input terminal of the fourth inverter.

[0019] The first NAND gate outputs a fourth trigger signal, and the output end of the first NAND gate is connected to the input end of the fifth inverter, and the output end of the fifth inverter is connected to the input end of the second counter.

[0020] The output terminal of the second AND gate is connected to the input terminal of the first counter and the CLK terminal of the D flip-flop.

[0021] The input end of the delay device is connected to the output end of the driving tree, and the output is a second trigger signal. The second trigger signal is a pulse signal after the pulse delay processing of the part of the set pulse width that exceeds the measurement range. When the set pulse width exceeds the measurement range, the second trigger pulse is connected to the first multiplexer to indicate that the pulse exceeding the measurement range is re-sent to the double-chain detector, and the double-chain detector continues to detect the part of the pulse exceeding the measurement range.

[0022] The input end of the pulse generator is connected to the output end of the driving tree, and the output is a third pulse t signal. The third pulse signal is used to reset the pulse detector array. The pulse width of the third pulse signal is determined according to the reset time of the pulse detector array.

[0023] The input end of the first counter is connected to the output end of the driving tree, the reset end of the first counter is connected to the RESET signal, and the output of the first counter is the Q_VFM[3:0] signal.

[0024] The input end of the second counter is connected to the output end of the second AND gate, the reset end of the second counter is connected to the RESET signal, and the output of the second counter is the Q_VFS[1:0] signal.

[0025] The present invention adopts the above technical solution and has the following beneficial effects:

[0026] (1) The single-particle transient pulse width measurement circuit proposed in the present invention detects the time difference between the two buffer chains transmitting the SET pulse, triggers the PD detector according to the detected time difference, and uses a counter to classify and count the pulse widths that exceed the measurement range. Compared with the prior art vernier delay line circuit, linear pulse filter detector and the traditional method of increasing the measurement range, the present invention uses two buffer chains to achieve sub-logic gate delay accuracy while reducing the circuit area of ​​the PD detector, so that the detection circuit part of the single-particle transient pulse width measurement circuit of the present invention only requires half the area of ​​the vernier delay line circuit, and is suitable for evaluating the single-particle transient effect of integrated circuits in a space radiation environment.

[0027] (2) The present invention adopts a classification detection mode to achieve accurate measurement of a wide range of single-particle transient pulse widths, so that the measurement circuit of the present invention can detect the pulse width of pulse signals outside the measurement range. Compared with the method of improving measurement accuracy by increasing the number of circuit levels, the present invention only requires a smaller area cost and lower power consumption to improve the measurement range of single-particle transient pulse width. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a structural diagram of the single-particle transient pulse width measurement circuit proposed by the present invention.

[0029] Figure 2It is a structural diagram of the PD detector circuit proposed by the present invention.

[0030] Figure 3 Figure 2 is a block diagram of a ring oscillator circuit.

[0031] Figure 4 This is the working waveform of the ring oscillator.

[0032] Figure 5 A pulse propagation dual chain circuit consisting of two buffer chains operating in a closed loop.

[0033] Figure 6 Waveform diagram of the pulse propagation double chain circuit propagating SET pulse.

[0034] Figure 7 This is a single particle transient pulse width measurement circuit after the pulse detector array is activated.

[0035] Figure 8 This is a waveform diagram of the pulse detector array operation.

[0036] Explanation of the numbers in the figure: MUX1~MUX5 are the first to fifth multiplexers, AND1~AND2 are the first and second AND gates, OR1~OR2 are the first and second OR gates, INV1~INV5 are the first to fifth inverters, NAND1 is the first NAND gate, and Driven-tree is the drive tree. DETAILED DESCRIPTION

[0037] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0038] The present invention proposes a single-particle transient pulse width measurement circuit from the perspectives of time resolution, area consumption and measurement range, called a Vernier Linear Filter Detector (VLFD), such as Figure 1 As shown, a single-particle transient pulse width measurement circuit includes a front-stage detection circuit and a rear-stage logic control circuit. The front-stage detection circuit includes: a pulse detector array, an AND gate array, a first buffer chain, a second buffer chain, and a logic device that performs a logic operation on a logic control signal to obtain control signals of the pulse detector array, the AND gate array, the first buffer chain, and the second buffer chain. The rear-stage logic control circuit includes: a D trigger, a delay, a pulse generator, a first counter, a second counter, and a logic device that performs a logic operation on a delayed state signal of a detection part to obtain input signals of the D trigger, the delay, the pulse generator, the first counter, and the second counter.

[0039] The output end of the first multiplexer MUX1 is simultaneously connected to the "0" input ends of the second multiplexer MUX2 and the third multiplexer MUX3, the "0" input end of the first multiplexer MUX1 is connected to the SET pulse signal SET_PLUSE, the "1" input end of the first multiplexer MUX1 receives the second trigger signal trig2 output by the subsequent logic control circuit, and the selection signal end of the first multiplexer MUX1 receives the first trigger signal trig1 output by the subsequent logic control circuit.

[0040] The output end of the second multiplexer MUX2 is connected to the input end of the first buffer chain Chain1(t1), the "1" input end of the second multiplexer MUX2 receives the feedback signal of the first buffer chain Chain1(t1), the "0" input end of the second multiplexer MUX2 is connected to the output end of the first multiplexer MUX1, and the selection signal end of the second multiplexer MUX2 receives the enable signal RO_VF_EN.

[0041] The output end of the third multiplexer MUX3 is connected to the input end of the second buffer chain Chain2(t2), the "1" input end of the third multiplexer MUX3 receives the feedback signal of the second buffer chain Chain2(t2), the "0" input end of the third multiplexer MUX3 is connected to the output end of the first multiplexer MUX1, and the selection signal end of the third multiplexer MUX3 receives the enable signal RO_VF_EN.

[0042] The first buffer chain Chain1(t1) is composed of a series of cascaded AND gates, one input end of the first-stage AND gate in the chain is connected to the output end of the second multiplexer MUX2, one input end of each of the remaining AND gates is connected to the output end of the previous-stage AND gate, the other input ends of all the AND gates receive the fourth trigger signal trig4 output by the subsequent logic control circuit, the output end of the last-stage AND gate serves as the output end of the first buffer chain Chain1(t1), the output end of the first buffer chain Chain1(t1) is connected to the input end of the first inverter INV1, and the first inverter INV1 outputs the feedback signal of the first buffer chain Chain1(t1).

[0043] The second buffer chain Chain2(t2) is composed of a series of cascaded AND gates, wherein one input end of the first-stage AND gate in the chain is connected to the output end of the third multiplexer MUX3, and one input end of each of the remaining AND gates is connected to the output end of the AND gate of the previous stage, and the other input ends of all the AND gates receive the fourth trigger signal trig4 output by the subsequent logic control circuit, and the output end of the last-stage AND gate is the output end of the second buffer chain Chain2(t2), and the output end of the second buffer chain Chain2(t2) is connected to the input end of the second inverter INV2, and the second inverter INV2 outputs the feedback signal of the second buffer chain Chain2(t2).

[0044] The output ends of the fourth multiplexer MUX4 and the fifth multiplexer MUX5 are respectively connected to an input end of the first AND gate AND1, the "1" input ends of the fourth multiplexer MUX4 and the fifth multiplexer MUX5 are connected to the GND signal, the select communication ends of the fourth multiplexer MUX4 and the fifth multiplexer MUX5 both receive the enable signal RO_VF_EN, the "0" input end of the fourth multiplexer MUX4 is connected to the output end of the first buffer chain Chain1 (t1), and the "0" input end of the fifth multiplexer MUX5 is connected to the output end of the second buffer chain Chain2 (t2). The first AND gate outputs 0 when the SET pulse width does not exceed the lower limit of the measurement range, the first AND gate outputs a pulse with a pulse width equal to the difference between the SET pulse width and the lower limit of the measurement range when the SET pulse width is within the measurement range, and the first AND gate outputs a pulse with a pulse width equal to the difference between the SET pulse width and the upper limit of the measurement range when the SET pulse width exceeds the upper limit of the measurement range.

[0045] The input end of the drive tree Driven-tree is connected to the output end of the first AND gate AND1 and the input end of the third inverter INV3 to transmit the output signal of the first AND gate to the logic control part.

[0046] The number of stages of the AND gate array is the same as the number of stages of the two buffer chains. The two input ends of the AND gate of the current stage are connected to the non-trigger signal trig4 input ends of the two AND gates of the corresponding stage in the two buffer chains, and the other input ends of all the AND gates are connected to the output end of the third inverter INV3. The output ends of the AND gates in the AND gate array are respectively connected to the set end S of the pulse detector of the corresponding stage.

[0047] The pulse detector array is composed of a cascade of RS flip-flops, with the same number of stages as the AND gate array. The set terminal S of the current number of RS flip-flops is connected to the output terminal of the AND gate of the corresponding number of stages in the AND gate array. The reset terminals R of all RS flip-flops are connected to the output terminal of the second OR gate OR2. The output terminals Q of all RS flip-flops are connected together as the pulse detection output terminal, and the output pulse detection result is recorded as Q_VFA[31:0]. The second OR gate OR2 performs an OR operation on the reset signal RESET and the third trigger signal trig3 output by the subsequent logic control circuit. The circuit structure of the RS flip-flop is shown in FIG. Figure 2 shown.

[0048] An input terminal D of the D flip-flop is grounded, a clock terminal CLK is connected to an output terminal of the second AND gate AND2, a reset terminal R receives a reset signal RESET, and an output terminal Q outputs a first trigger pulse signal trig1.

[0049] The input end of the delay device is connected to the output end of the drive tree Driven-tree, and outputs the second trigger pulse signal trig2.

[0050] The input terminal of the pulse generator is connected to the output terminal of the drive tree Driven-tree, and outputs the third trigger pulse signal trig3.

[0051] The second AND gate AND2 performs an AND operation on the output signal of the drive tree Driven-tree and the inverted signal of the DS signal, and outputs the AND operation result to the input terminal C of the first counter. The reset terminal R of the first counter receives the reset signal RESET. The first counter outputs Q_VFM[3:0]. The DS signal is obtained by the first OR gate OR1 performing an OR operation on the output signal of the second multiplexer MUX2 and the output signal of the third multiplexer MUX3. DS is used to detect whether the width of SET is greater than N*t2. The output terminal signal of the first OR gate OR1 is. The inverted signal of the DS signal is obtained by inverting the DS signal at its input terminal by the fourth inverter INV4.

[0052] One input terminal of the first NAND gate NAND1 receives the DS signal, the other input terminal of the first NAND gate NAND1 is connected to the output terminal of the driving tree, and the first NAND gate NAND1 outputs a fourth trigger pulse signal trig4.

[0053] The input terminal C of the second counter receives the inverted signal of the fourth trigger pulse signal trig4, the reset terminal R of the second counter receives the reset signal RESET, the first counter outputs Q_VFS[1:0], and the inverted signal of the fourth trigger pulse signal trig4 is obtained by inverting the fourth trigger pulse signal trig4 at its input terminal through the fifth inverter INV5.

[0054] An input terminal of the fourth inverter INV4 receives the DS signal.

[0055] The working principle of the single particle transient measurement circuit proposed in the present invention is described below. The single particle transient measurement circuit sequentially undergoes a startup mode, a calibration mode, and a detection mode. The specific description of each mode is as follows.

[0056] 1. Circuit startup. RESET=1, SET_PLUSE=0, RO_VF_EN=0. The RESET signal passes through the second OR gate OR2, so the reset action is performed, Q_VFA[31:0]=0, Q_VFM[3:0]=0, Q_VFS[1:0]=0, trig1=0, trig2=0, trig3=0, trig4=1.

[0057] 2. The circuit enters the calibration mode. RO_VF_EN=1. At this time, the first buffer chain Chain1(t1) operates in a closed loop to form a ring oscillator RO1, and the second buffer chain Chain2(t2) operates in a closed loop to form a ring oscillator RO2. The periods of the ring oscillator RO1 and the ring oscillator RO2 are T1=2*(t1*N+t inv1 +t mux2 ), T2=2*(t2*N+t inv2 +t mux3 ), N is the number of levels of the two cache chains, t inv1 ,t inv2 is the delay time of the first and second inverters, t mux2 is the delay time of the second multiplexer, t mux3 is the delay time of the third multiplexer. Through the oscillation waveform, it can be obtained that the delay time of the two chains is t1 and t2. The circuit diagram and working waveform of the ring oscillator are shown in Figure 3 , Figure 4 At this time, Q_VFA[31:0]=0, Q_VFM[3:0]=0, Q_VFS[1:0]=0, trig1=0, trig2=0, trig3=0, trig4=1.

[0058] 3. The circuit enters the detection mode. RO_VF_EN=0. The SET_PULSE pulse signal passes through the first multiplexer MUX1, and enters the second multiplexer MUX2 and the third multiplexer MUX3 at the same time and enters the first buffer chain Chain1(t1) and the second buffer chain Chain2(t2). At the starting position Start of the two buffer chains, the pulses have the same starting point. As the pulse propagates in the buffer chain, it is affected by the different propagation times t1 and t2 of the two buffer chains. After each level, the positions of the two pulses with the same initial position change by Δt=t2-t1. The circuit diagram and working waveform of the pulse propagation double chain are as follows. Figure 5 and Figure 6 as shown

[0059] There are 3 types of circuit detection modes. Let T be the width of the SET pulse SET_PULSE, and N be the number of stages of the detection circuit part, that is, the number of stages of the buffer chain and the number of stages of the pulse detector array. Next, we will analyze the 3 circuit modes according to the size of T.

[0060] Mode 1:

[0061] When T < N*(t2 - t1), at this time, the width of the pulse does not exceed the measurement range of the detection circuit. At the termination position Stop of the two buffer chains, the signals in the two buffer chains are ANDed and then output 0, and the SET_PLUSE signal cannot enter the subsequent logic control circuit. The output of the third inverter INV3 is 1, the AND gate array opens the channel, and the single-event transient pulse width measurement circuit enters the pulse width measurement state. The circuit diagram and working waveform at this time are simplified as Figure 7 and Figure 8 shown. Q_VFA[31:0] is the pulse detection result, Q_VFM[3:0] = 0, Q_VFS[1:0] = 0, trig1 = 0, trig2 = 0, trig3 = 0, trig4 = 1.

[0062] Mode 2:

[0063] Front-stage detection circuit: When N*(t2 - t1) < T < t2*N, when the SET_PLUSE signal reaches the Stop position after passing through the N-stage buffer chain, since T exceeds the measurement range of the detection circuit, the first AND gate AND1 outputs a pulse T`, where T` = T - N*(t2 - t1). At this time, the output of the third inverter INV3 is 0, shielding the AND gate array. The T` signal does not trigger the PD detector until the T` signal completely leaves the buffer chain, and then the AND gate array will be opened.

[0064] Subsequent logic control circuit: The rising edge signal of T` triggers trig1 = 1, opens the "1" channel of the first multiplexer MUX1, and starts the pulse re-detection channel. After a delay unit, T` is sent back to the "1" channel of the first multiplexer MUX1 as the second trigger pulse signal trig2. The rising edge signal of T` triggers the pulse generator to output the third trigger pulse signal trig3, and the third trigger pulse signal trig3 triggers the reset of the pulse detector array after passing through the second OR gate OR2. The rising edge signal of T` also triggers the first counter to count once.. The pulse time generated by the pulse generator is determined by the reset requirement of the pulse detector array. The delay time t of the delay unit Delay satisfies: t Delay >(t PDreset , t DFF +tMUX1 ), t PDreset is the reset time of the pulse detector array, t DFF is the delay of the D flip-flop, t MUX1 is the delay of the first multiplexer. In mode 2, DS = 0 and the second counter does not work.

[0065] Working principle: When T` is generated, if T` meets mode 2, it enters mode 2 detection. The detection result Q_VFA[31:0] at this time is the detection result of T`, Q_VFM[3:0] = 1, Q_VFS[1:0] = 0, trig1 = 1, trig4 = 1. If T` continues to meet mode 2, it enters mode 2 detection again. At Stop, T`` = T` - N*(t2 - t1) = T - 2*[N*(t2 - t1)] is obtained, the detection circuit re-measures T``, the first counter counts once, and other signals repeat the actions of mode 2. Next, it is judged whether the circuit is in mode 1 or mode 2 according to the pulse width of T``. The final detection result is T = Q_VFA[31:0] + m*[N*(t2 - t1)], where m is the count of the first counter. In mode 2, the pulse width T < t2*N, so there is no SET pulse signal re-entering the detection circuit, and there is still a signal error at the start of the detection circuit.

[0066] Mode 3:

[0067] When T > t2*N, when the SET_PLUSE signal reaches the Stop position after passing through N-level buffer chains, at this time the first AND gate AND1 outputs a pulse T`. Since T exceeds the longest length t2*N of the second buffer chain at this time, T` = T - t2*N. Therefore, when T` appears, SET_PLUSE at Start has not completely disappeared, DS = 1, at this time the second counter starts to count, the first counter is blocked, trig1 = 0, trig4 = 0, and the other signals are the same as in mode 2.

[0068] Working principle:

[0069] When the rising edge of T` is generated, trig4 = 0 and the second counter counts once. One input terminal of the AND gates in the two chains is connected to 0, so the outputs of all AND gates are 0 at the same time. At this time, the original pulse T is equivalent to subtracting the length of the second buffer chain, T a = T - t2*N, T a is regarded as a new pulse T and added to the detection circuit. If T a is still greater than t2*N, the second counter counts again, T b = T a - t2*N, until the pulse T output by the first AND gate *The width of the first AND gate output pulse is within the measurement range [N*(t2-t1), t2*N]. When the width of the first AND gate output pulse is within the measurement range, jump to mode 2. The final detection result is T= Q_VFA[31:0]+m*[N*(t2-t1)]+n* t2*N. Among them, m is the count of the first counter and n is the count of the second counter.

[0070] The above embodiments are only for illustrating the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.

Claims

1. Single particle transient pulse width measurement circuit, including: The front-stage detection part and the rear-stage logic control part are characterized in that the front-stage detection part includes: A first multiplexer, whose "0" input terminal receives the SET pulse signal, whose "1" input terminal receives the second trigger signal output by the subsequent logic control part, and whose control terminal receives the first trigger signal output by the subsequent logic control part, wherein the second trigger signal is obtained according to the pulse signal of the SET pulse signal that exceeds the measurement range; A second multiplexer, whose "0" input terminal is connected to the output terminal of the first multiplexer, whose "1" input terminal receives the feedback signal of the first buffer chain, and whose control terminal receives the enable signal; A third multiplexer, whose "0" input terminal is connected to the output terminal of the first multiplexer, whose "1" input terminal receives the feedback signal of the second buffer chain, and whose control terminal receives the enable signal; A first OR gate, one input of which is connected to the output of the second multiplexer, and the other input of which is connected to the output of the third multiplexer, outputs a high level when the SET pulse width output by the second multiplexer and the SET pulse width output by the third multiplexer both exceed the delay time of the second buffer chain, otherwise outputs a low level; A second OR gate, one input terminal of which is connected to the reset signal, and another input terminal of which is connected to a third trigger signal output by the subsequent logic control part, wherein the third trigger signal is obtained according to the partial pulse signal of the SET pulse signal exceeding the measurement range and the reset time of the pulse detector array; A first buffer chain is formed by cascading N AND gates, wherein the first input end of the first-stage AND gate is connected to the output end of the second multiplexer, and the first input end of each of the remaining AND gates is connected to the output end of the previous-stage AND gate, and the second input ends of all the AND gates receive a fourth trigger signal output by a subsequent-stage logic control part, and the output end of the last-stage AND gate serves as the output end of the first buffer chain, and the fourth trigger signal is used to distinguish whether the SET pulse signal exceeds an upper limit or a lower limit of a measurement range; A second buffer chain is formed by cascading N AND gates, wherein the first input end of the first-stage AND gate is connected to the output end of the third multiplexer, and the first input end of each of the remaining AND gates is connected to the output end of the previous-stage AND gate, and the second input ends of all the AND gates receive the fourth trigger signal output by the subsequent-stage logic control part, and the output end of the last-stage AND gate is the output end of the second buffer chain; An AND gate array, comprising N AND gates, wherein two input terminals of the ith AND gate are respectively connected to the second input terminal of the ith AND gate in the first buffer chain, and a third input terminal of each AND gate is connected to the output terminal of the third inverter, and each AND gate sends a set signal to the pulse detector array when the output of the third inverter is valid, 1≤i≤N; A pulse detector array is formed by cascading N RS flip-flops, wherein the reset terminal of each RS flip-flop is connected to the output terminal of the second OR gate, and the output terminals of each RS flip-flop are connected together as the pulse detection output terminal; a fourth multiplexer, whose "0" input terminal is connected to the output terminal of the first buffer chain, whose "1" input terminal is grounded, and whose control terminal receives an enable signal; a fifth multiplexer, whose "0" input terminal is connected to the output terminal of the second buffer chain, whose "1" input terminal is grounded, and whose control terminal receives an enable signal; a first AND gate, one input terminal of which is connected to the output terminal of the fourth multiplexer, another input terminal of which is connected to the output terminal of the fifth multiplexer, and an output terminal of which is connected to the input terminal of the third inverter; and The driver tree has an input end connected to the output end of the first AND gate, and outputs a portion of the pulse signal sent to the two buffer chains that exceeds the measurement range to a subsequent logic control part.

2. The single-particle transient pulse width measurement circuit according to claim 1, characterized in that: The post-stage logic control part includes: a fourth inverter, an input end of which is connected to the output end of the first OR gate; A second AND gate, one input terminal of which is connected to the output terminal of the previous detection part, and the other input terminal of which is connected to the output terminal of the fourth inverter, outputting an enable signal of the first counter; A first NAND gate, one input end of which is connected to the output end of the first OR gate, and the other input end of which is connected to the output end of the preceding detection part, outputting a fourth pulse signal; a fifth inverter, whose input end is connected to the output end of the first NAND gate and outputs an enable signal of the second counter; A D flip-flop, whose input terminal is grounded, whose clock terminal is connected to the output terminal of the second AND gate, whose reset terminal is connected to the reset signal, and outputs a first trigger signal; A delayer, whose input end is connected to the output end of the preceding detection part, delays the pulse signal of the SET pulse signal that exceeds the measurement range, and outputs a second trigger signal; A pulse generator, whose input end is connected to the output end of the previous detection part, outputs a third pulse signal according to the reset time of the pulse detector array; A first counter, whose input end is connected to the output end of the second AND gate, whose reset end receives a reset signal, counts 1 when detecting that the SET pulse width is in [N*(t2-t1), t2*N], where t1 and t2 are the delays of each AND gate in the first buffer chain and the second buffer chain, and outputs the counting result; The second counter has its input end connected to the output end of the fifth inverter and its reset end connected to the reset signal. When detecting that the pulse signals sent to the two buffer chains exceed the upper limit of the measurement range, the counter counts 1 and outputs the counting result.

3. The single-particle transient pulse width measurement circuit according to claim 1, characterized in that: The feedback signal of the first buffer chain is obtained through a first inverter connected to an output end of the first buffer chain, and the feedback signal of the second buffer chain is obtained through a second inverter connected to an output end of the second buffer chain.

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