Data interface device, and data acquisition equipment and sensor system adapted thereto

Abstract

The application discloses a data interface device and a data acquisition device and a sensor system. The data interface device comprises a coupling input unit, a sampling unit, a clock recovery control unit, a clock generation unit and an output unit. The clock recovery control unit detects a received first digital signal in a preset number of clock half cycles to output a clock recovery control signal reflecting a phase deviation between a second analog signal and a clock signal. The clock recovery control signal uses a field to represent a phase value of an adjusted clock signal. The clock generation unit adjusts the clock signal by using the clock recovery control signal, so that the sampling unit can accurately sample the received analog signal to obtain various data provided by a sensor. The application adjusts a phase interval and a phase value in the phase interval to quickly recover the clock signal, thereby improving the clock recovery efficiency in a real-time data transmission process of the sensor.

Description

Technical Field

[0001] This application relates to data transmission technology, specifically to a data interface device and the applicable data acquisition equipment and sensor system. Background Technology

[0002] The data interface device includes a data interface device for transmitting analog signals, which converts received digital signals into analog signals based on the transmission medium, transmission path length, etc., for transmission over the transmission medium. The data interface device also includes a data interface device for receiving analog signals, which recovers the analog signals from the transmission medium into digital signals.

[0003] In some data transmission technologies, in order to recover digital signals from analog signals, each data interface device needs to select the transmitting and receiving circuit systems according to the transmission method of the analog signal. This ensures that the analog signal has recognizable signal changes at the level of circuit resolution after passing through the transmission medium, thus ensuring that the receiving data interface device can extract digital signals from the analog signal. Summary of the Invention

[0004] This application provides a data interface device and an applicable data acquisition device and sensor system to solve the problem of the long time consumed by the data interface device in recovering the clock signal used for sampling digital signals from analog signals and the technical problems caused thereto.

[0005] In a first aspect, this application provides a data interface device comprising: an input unit, coupled to a channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted; a sampling unit, coupled to the input unit, for sampling the received second analog signal according to a received clock signal to output a first digital signal and the clock signal; a clock recovery control unit, coupled to the sampling unit, for detecting the received first digital signal within a preset number of clock half-cycles and outputting a clock recovery control signal reflecting the phase deviation between the second analog signal and the clock signal; wherein the clock recovery control signal uses a field to represent the phase value of the adjusted clock signal; a clock generation unit, coupled to the clock recovery control unit and the sampling unit, for adjusting the generated clock signal according to the received clock recovery control signal and outputting the adjusted clock signal to the sampling unit; and an output unit, coupled to the sampling unit, for converting the corresponding acquired first digital signal into a second digital signal under the control of the received clock signal and outputting it.

[0006] Secondly, embodiments of this application provide a sensor system comprising: a first radar sensor, including a first data interface device; the first data interface device being used to transmit a measurement signal detected by the first radar sensor; wherein the measurement signal is used to reflect at least one of the following data: a baseband digital signal detected by the first radar sensor, at least one of the distance, velocity, and azimuth angle between the first radar sensor and a target, and target detection data of the target; a second radar sensor, including a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; the second data interface device is the data interface device as described in the first aspect, used to receive the measurement signal; and the third data interface device being used to forward the measurement signal.

[0007] Thirdly, this application also provides a sensor system comprising: a first radar sensor, including a first data interface device; the first data interface device being used to transmit a measurement signal detected by the first radar sensor; wherein the measurement signal is used to reflect at least one of the following data: a baseband digital signal detected by the first radar sensor, at least one of the distance, velocity, and azimuth angle between the first radar sensor and a target, and target detection data of the target; a second radar sensor, including a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; the second data interface device is the data interface device as described in the first aspect, used to receive the measurement signal; and the third data interface device being used to forward the measurement signal.

[0008] The data interface device, applicable data acquisition equipment, and sensor system provided in this application adjust the phase of the clock signal used for sampling by detecting the sampled digital signal, and achieve fast and accurate recovery of the sampling clock signal from the analog signal by adjusting the phase interval and the phase value within the phase interval, so as to meet the requirements of clock recovery efficiency in the real-time data transmission process of the sensor. Attached Figure Description

[0009] Figure 1 This is a hardware architecture block diagram of a data transmission interface device according to this application.

[0010] Figure 2 This is a schematic diagram of the circuit structure of a parallel-to-serial conversion unit according to this application.

[0011] Figure 3 This is a schematic diagram of a circuit structure for the first serial signal output device of this application.

[0012] Figure 4This is a schematic diagram of a circuit structure for the second serial signal output device of this application.

[0013] Figure 5 This is a schematic diagram of the circuit structure of an encoding unit according to this application.

[0014] Figure 6 This is a schematic diagram of the waveform of the third analog signal after equalization processing in this application.

[0015] Figure 7 This is a schematic diagram of a circuit structure for the output driving unit of this application.

[0016] Figure 8 This is a schematic diagram of another circuit structure for the output drive unit of this application.

[0017] Figure 9 For the purposes of this application Figure 2 and 8 The provided example provides a circuit structure diagram of a data transmission interface device.

[0018] Figure 10 This is a schematic diagram of the circuit structure of a data receiving interface device according to this application.

[0019] Figure 11 This is a schematic diagram of the circuit structure of an equalizer unit according to this application.

[0020] Figure 12 This is a schematic diagram of the spectrum in the equalizer unit of this application.

[0021] Figure 13 This is a schematic diagram of a circuit structure for an input unit in the data interface device of this application.

[0022] Figure 14 This is a schematic diagram of a calibration circuit in the data interface device of this application.

[0023] Figure 15 This is a schematic diagram of a detection sub-circuit in the correction circuit of this application.

[0024] Figure 16 A processing logic flowchart for processing at least one detection signal in the correction control sub-circuit of the correction circuit of this application.

[0025] Figure 17 This is a schematic diagram of another hardware architecture for the data receiving interface device of this application.

[0026] Figure 18 This is a schematic diagram of a circuit structure for a clock recovery control unit in the data receiving interface device of this application.

[0027] Figure 19This is a timing diagram of the phase-shift detection circuit structure in the data receiving interface device of this application.

[0028] Figure 20 This is a schematic diagram of a phase-shifting control circuit structure in the data receiving interface device of this application.

[0029] Figure 21 This is a schematic diagram of a circuit structure for the second shift decision circuit in the data receiving interface device of this application.

[0030] Figure 22 This is a schematic diagram of the condition-state transition for adjusting the phase interval in the second phase adjustment circuit of the data receiving interface device of this application.

[0031] Figure 23 This is a schematic diagram of the circuit structure of the clock recovery control unit in the data receiving interface device of this application.

[0032] Figure 24 This is a schematic diagram of the condition-state transition for adjusting the binary phase value in the first phase adjustment circuit of the data receiving interface device of this application.

[0033] Figure 25 This is a schematic diagram of the hardware structure of the sensor system in this application.

[0034] Figure 26 This is a schematic diagram of the hardware structure of the data acquisition device in this application. Detailed Implementation

[0035] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0036] In some data transmission technologies, a data interface device is coupled to a channel made of a signal-conducting material to transmit analog signals to another data interface device. Examples of such channels include microstrip lines, coaxial cables, or optical fibers.

[0037] The term "coupled" or "coupled" can have several different meanings depending on the context in which it is used. For example, the term "coupled" can mean mechanical coupling or electrical coupling. As used herein, the term "coupled" or "coupled" can mean that two elements or devices can be directly connected to each other or connected to each other via one or more intermediate elements or devices through electrical elements, electrical signals, or mechanical elements (e.g., but not limited to, wires or cables, depending on the specific application). Examples of coupling described herein include direct electrical connections, inductive connections, or optocoupler connections. For example, an electrical connection between two electrical devices is achieved using connection methods used in semiconductor manufacturing processes. Another example is a signal connection between two electrical devices achieved using non-contact connection methods such as optocoupler components or inductive components. Yet another example is the use of chip pin and socket connection methods to facilitate electrical or signal connections between two electrical devices.

[0038] For ease of description, in the embodiments of this application, the data interface device that emits analog signals is referred to as a data transmitting interface device, and the data interface that receives analog signals is referred to as a data receiving interface device.

[0039] In some data transmission technologies, data transmitting and receiving interface devices utilize channels to transmit analog signals represented by differential signals, thereby reducing the number of channels required for transmitting clock signals. Such data transmitting and receiving interface devices include LVDS interface devices or SerDes interface devices, etc. In the transmission of analog signals represented by differential signals, two channels are typically used to transmit the differential signal. When these two channels are long, high-frequency signal filtering and / or signal interference and attenuation can easily occur. This situation is particularly pronounced when transmitting analog signals at frequencies of 10 GHz and above.

[0040] Therefore, this application provides a data transmission interface device, intended for use in sensing systems such as those in which sensors are located. This device converts digital signals such as baseband digital signals, measurement data, or target detection data generated by the sensors into analog signals, and ensures that the corresponding analog signals are transmitted to the data receiving interface device via a channel, thus facilitating accurate parsing by the data receiving interface device. Its accuracy meets the error precision requirements of the sensing system. Taking a sensing system including sensors applied to an automotive automatic driving assistance system as an example, the channel length between the data processing device and the sensor in the sensing system is related to the sensor's installation position on the vehicle body and the vehicle's length. When the data transmission interface device transmits various digital signals generated by the sensor to the data receiving interface device via the channel (or via the channel and a repeater on the channel), the data receiving interface device can easily and accurately extract the digital signals from the received analog signals, thereby meeting the accuracy requirements of the automatic driving assistance system for the sensor's output data / signals.

[0041] For ease of description, the analog signal transmitted to the channel by the data transmission interface device in this application is referred to as the third analog signal, and the analog signal received by the data receiving interface device is referred to as the first analog signal. The first analog signal is an analog signal formed by attenuation of the third analog signal after transmission through the channel and the superposition of channel noise, etc.

[0042] Please see Figure 1 The diagram shows a hardware architecture block diagram of a data transmission interface device. The data transmission interface device 1 includes: a parallel-to-serial conversion unit 11, an encoding unit 112, and an output driving unit 13.

[0043] The parallel-to-serial conversion unit is used to convert the parallel digital signal generated in the sensor into a first serial digital signal and a second serial digital signal and output them.

[0044] Here, the parallel-to-serial conversion unit outputs a first serial digital signal and a second serial digital signal according to the bit order of the parallel digital signal from high to low or from low to high. The first and second serial digital signals have the same level change and exist with a predetermined time gap. In other words, the first and second serial digital signals are signals in the same direction (or opposite directions) with a predetermined delay between them. This delay period (also called the symbol time gap) is determined based on the pulse width of the operating clock signal of the parallel-to-serial conversion unit. For example, the delay period is half a cycle of the operating clock signal.

[0045] Please see Figure 2The diagram shows a circuit structure schematic of a parallel-to-serial conversion unit 11. The parallel-to-serial conversion unit 11 includes a parallel-to-serial converter 110, and cascaded first serial output unit 111 and second serial output unit 112. The parallel-to-serial converter 110 operates under the control of a first operating clock signal DIV_1, while the first serial output unit 111 and the second serial output unit 112 operate under the control of a second operating clock signal DIV_2. The first operating clock signal DIV_1 and the second operating clock signal DIV_2 have a frequency division / multiplication relationship. Taking the parallel-to-serial conversion unit 11 outputting a serial signal at full rate as an example, if the parallel-to-serial converter converts a 10-bit parallel digital signal into a 2-bit serial digital signal, and the first and second serial output units output this 2-bit serial digital signal, then the frequency ratio of the first operating clock signal DIV_1 to the second operating clock signal DIV_2 is 1:5.

[0046] The parallel-to-serial converter is used to convert the received parallel digital signal TXD <n:0>The signal is converted into two serial digital signals based on the parity of the bits. Here, n is an integer greater than 1, for example, n = 8 or 10.

[0047] The first serial signal output device is coupled to the parallel-to-serial converter and is used to output the received parity bit signals sequentially under the control of the received second working clock signal to form the first serial digital signal D_MAIN.

[0048] Here, under the control of the second operating clock signal DIV_2, the parallel-to-serial converter outputs the odd and even bits of the parallel digital signal in descending order (or descending order) through their respective odd signal output terminal EVEN and even signal output terminal ODD. Under the control of the second operating clock signal DIV_2, the first serial signal outputter sequentially outputs the received odd and even bits. Taking the first serial signal outputter outputting the first serial digital signal at full rate as an example, it outputs the serial digital signal according to the clock cycle of the second operating clock signal DIV_2 only in response to the rising or falling edge of the second operating clock signal DIV_2. Taking the first serial signal outputter outputting the first serial digital signal at half rate as an example, it outputs the serial digital signal according to half the clock cycle of the second operating clock signal DIV_2 in response to the rising and falling edges of the second operating clock signal DIV_2.

[0049] Please see Figure 3 The diagram shows a circuit structure diagram of a first serial signal output device. The first serial signal output device includes two flip-flops D11 and D12, a controller C1, and an output device P1. The input of flip-flop D11 is connected to the odd signal output terminal EVEN, and its control terminal (also called the enable terminal) receives the second working clock signal DIV_2. The output of flip-flop D11 is connected to the first input terminal of controller C1 and the second serial signal output device. The input of flip-flop D12 is connected to the even signal output terminal ODD, and its control terminal (also called the enable terminal) receives the inverted signal of the second working clock signal DIV_2. The output of flip-flop D12 is connected to the second input terminal of controller C1 and the second serial signal output device. The output device P1 can optionally be a comparator or an AND gate device to improve the level stability of the output signal. In some examples, such as... Figure 3 As shown in the dashed box, the first serial signal output device also includes a duty cycle calibration circuit DCC1 to improve the stability of the pulse width ratio in the second working clock signal DIV_2; correspondingly, the duty cycle calibration circuit DCC1 receives the second working clock signal DIV_2 and outputs it to the control terminal of the controller C1.

[0050] Under the control of the second working clock signal DIV_2, taking the half-rate transmission of serial digital signals as an example, within one clock cycle of the second working clock signal DIV_2: during the high-level active period of the second working clock signal DIV_2, the signal path formed by the flip-flop D11, the controller C1, and the output device P1 outputs an odd-bit signal; during the low-level active period of the second working clock signal DIV_2, the signal path formed by the flip-flop D12, the controller C1, and the output device P1 outputs an even-bit signal.

[0051] The second serial signal output device is cascaded with the first serial signal output device and is used to output the first serial digital signal D_MAIN transmitted by the first serial signal converter as the second serial digital signal D_POST according to the delay duration.

[0052] Under the control of the second working clock signal DIV_2, the second serial signal outputter sequentially outputs the received odd-bit and even-bit signals to form the second serial digital signal D_POST. Taking the second serial signal outputter at full rate as an example, it outputs the second serial digital signal D_POST according to the clock cycle of the second working clock signal DIV_2, responding only to the falling or rising edge of the second working clock signal DIV_2. Taking the second serial signal outputter at half rate as an example, it outputs the second serial digital signal D_POST according to half the clock cycle of the second working clock signal DIV_2, responding to both the falling and rising edges of the second working clock signal DIV_2. The second serial signal outputter is delayed by one symbol time interval (i.e., half the clock cycle of the second working clock signal DIV_2) compared to the first serial signal outputter.

[0053] Please see Figure 4 The diagram shows a circuit structure of a second serial signal output device. The second serial signal output device includes two flip-flops D21 and D22, a controller C2, and an output device P2. The input of flip-flop D21 is connected to the output D11_output of flip-flop D11 of the first serial signal output device. The control terminal (also called the enable terminal) of flip-flop D21 receives the inverted signal of the second working clock signal DIV_2. The output of flip-flop D21 is connected to the first input of controller C2. The input of flip-flop D22 is connected to the output D12_output of flip-flop D12 of the first serial signal output device. The control terminal (also called the enable terminal) of flip-flop D22 receives the second working clock signal DIV_2. The output of flip-flop D22 is connected to the second input of controller C2. The output device P2 can optionally be a comparator or an AND gate to improve the level stability of the output signal. In some examples, such as... Figure 4 As shown in the dashed box, the second serial signal output device also includes a duty cycle calibration circuit DCC2 to improve the stability of the pulse width ratio in the second working clock signal DIV_2; correspondingly, the duty cycle calibration circuit DCC2 receives the second working clock signal DIV_2 and outputs it to the control terminal of the controller C2. The duty cycle calibration circuit DCC2 and the duty cycle calibration circuit DCC1 are either the same device or two independent devices.

[0054] Under the control of the second working clock signal DIV_2, taking the half-rate transmission of serial digital signals as an example, within one clock cycle of the second working clock signal DIV_2: during the low-level active period of the second working clock signal DIV_2, the signal path formed by the flip-flop D21, the controller C2, and the output device P2 outputs an odd-bit signal; during the high-level active period of the second working clock signal DIV_2, the signal path formed by the flip-flop D22, the controller C2, and the output device P2 outputs an even-bit signal.

[0055] The aforementioned half-rate parallel-to-serial conversion unit first converts the received n-bit parallel digital signal into a two-bit (odd / even) digital signal, and then converts it into a one-bit serial digital signal via a controller (such as a 2-to-1 selector). Because of the half-rate structure, the required clock frequency is half the serial data rate. This reduces the clock requirement, but also makes it sensitive to the clock duty cycle due to the use of high and low clock levels. The clock duty cycle directly affects the jitter of the output serial data eye diagram. Therefore, DCC is added to the clock path to correct the clock duty cycle and keep its deviation within a certain range. In the diagram, D_MAIN is the final output first serial digital signal. D_POST is delayed by one symbol time interval compared to D_MAIN, mainly used for subsequent channel equalization. Signals P_0 and P_1 can control the polarity of D_MAIN and D_POST, respectively. The first serial digital signal D_MAIN and the second serial digital signal D_POST are output to the encoding unit of the data transmission interface device.

[0056] The encoding unit is coupled to the parallel-to-serial conversion unit and is used to encode the first serial data and the second serial data into a first drive control digital signal and a second drive control digital signal according to a preset equalization coefficient, and then output them. The equalization coefficient is intended to allow the output drive unit to adjust the voltage swing of a portion of the output third analog signal to improve its anti-filtering capability in the high-frequency section during channel transmission. Examples of equalization coefficients include equalization coefficients for pre-emphasis or de-emphasis. The equalization coefficient is preset based on the transmission distance between the data transmission interface device and the data receiving interface device, the channel medium, etc. For example, the encoding unit provides an editable equalization coefficient encoder, such as a thermometer encoder. This equalization coefficient encoder generates control signals according to externally input encoding instructions, allowing the encoding unit to perform encoding operations on the received first serial digital signal D_MAIN and second serial digital signal D_POST.

[0057] The encoding unit uses a multi-channel digital circuit encoding method to encode the first serial digital signal D_MAIN and the second serial digital signal D_POST, effectively utilizing semiconductor manufacturing processes to integrate the data transmission interface device and the sensor into a single chip within a limited size range.

[0058] Please see Figure 5 The diagram shows a circuit structure schematic of an encoding unit. The encoding unit includes two channels: differential converters SD1 and SD2, and an encoder group MUX1. <m:1>、MUX2 <m:1>Where m > 1, for example, m = 14. Differential converter SD1 converts the first serial digital signal D_MAIN into differential serial signals DP_MAIN and DN_MAIN. Differential converter SD2 converts the second serial digital signal D_POST into differential serial signals DP_POST and DN_POST. Taking the first and second serial digital signals D_MAIN and D_POST as identical signals with a delay duration as an example (for ease of description), serial signals DP_MAIN and DP_POST are identical signals with a delay duration, as are serial signals DN_MAIN and DN_POST; and serial signals DP_MAIN and DN_MAIN are synchronous inverse signals, and serial signals DP_POST and DN_POST are synchronous inverse signals.

[0059] Encoder group MUX1 <m:1>The system receives serial signals DP_MAIN and DN_POST, encodes them according to the control bits in the received control signals, and outputs the first drive control digital signal DP_INT. Each encoder group is controlled by the control signal output by the equalization coefficient encoder. Encoder group MUX2 <m:1>It receives serial signals DN_MAIN and DP_POST, encodes the serial signals DN_MAIN and DP_POST according to each control bit in the received control signal, and outputs the second drive control digital signal DN_INT.

[0060] Among them, the encoder group MUX1 <m:1>and encoder group MUX2 <m:1>They can have the same circuit structure. For example, encoder group MUX1. <m:1>Taking an encoder group consisting of m 2-to-1 selectors as an example, encoder group MUX1 <m:1>Each selector in the system selects the serial signals DP_MAIN and DN_POST based on the high or low level of the corresponding control bit in the received control signal, so as to output the m-bit first drive control digital signal DP_INT.

[0061] In this example, a thermometer decoder controls a 2-to-1 multiplexer to generate the control signals required by the output drive unit. For instance, signals D_MAIN and D_POST are converted to DP_MAIN and DN_MAIN, and DP_POST and DN_POSTN, respectively, via a single-ended to differential converter. These two sets of signals are then connected to 15 2-to-1 multiplexers, ultimately converting them into DP_INT and DN_INT outputs. The 2-to-1 multiplexers are controlled by the thermometer decoder. When the channel requires a high compensation level, the 2-to-1 multiplexer can select more DP_POST and DN_POST outputs. Furthermore, the equalization level can be increased incrementally through the thermometer decoder, achieving high precision.

[0062] Since the first drive control digital signal DP_INT and the second drive control digital signal DN_INT are respectively encoded into {DP_MAIN, DN_POST} and {DN_MAIN, DP_POST} using the same encoding method based on the received differential signals with delay durations, the first drive control digital signal DP_INT and the second drive control digital signal DN_INT contain control changes within one clock cycle that can be used by subsequent circuits for pre-emphasis (or pre-deduplication) processing according to the delay duration. Under the control of the first drive control digital signal DP_INT and the second drive control digital signal DN_INT, the output drive unit outputs a differential signal, i.e., the third analog signal, after equalization processing with constant voltage amplitude swing.

[0063] The output driving unit is coupled to the encoding unit and is used to select, under the driving control of the first driving control digital signal, to generate an analog signal representing either 0 or 1 in the first serial digital signal; or to select, under the driving control of the second driving control digital signal, to generate an analog signal representing either 0 or 1 in the first serial digital signal; and to output corresponding analog signals in a timing sequence to form a third analog signal. The energy amplitude of the third analog signal during the extended duration after the selection switch is processed by the pre-emphasis / de-emphasis equalization. For example, please refer to... Figure 6 The diagram shows the waveform of the third analog signal after equalization processing, where time slots T1 and T2 are the level signals output by the output drive unit after equalization processing of the differential signal.

[0064] Here, the output drive unit includes multiple controlled power supply circuits (e.g., digital-to-analog converter drivers, DAC drivers) to generate equalized differential analog signals under the control of the first and second drive control digital signals. By selecting multiple controlled power supply circuits to provide the large-swing signal output, the difficulty of integrating components in high-power drive circuits is reduced, and control accuracy is effectively improved. Each controlled power supply circuit can generate the same electrical signal or be configured to generate slightly different electrical signals. The output drive unit includes two sets of controlled power supply circuits: a first set and a second set. The number of circuits in each set corresponds to the maximum number of bits in the received first or second drive control digital signal. The first set of controlled power supply circuits is connected to the positive output terminal of the output drive unit; the second set is connected to the negative output terminal. This results in the output of a single-channel third analog signal represented by a differential signal.

[0065] To output a third analog signal with symmetrical energy amplitude swing, see some examples. Figure 7 The diagram shows a circuit structure of an output drive unit. The first and second controlled power supply circuit groups have the same circuit structure. Taking the first controlled power supply circuit group as an example, it contains m parallel first controlled power supply circuits. Each control bit in the first drive control digital signal controls a controlled switch in one of the first controlled power supply circuits. Under the control of two sets of first drive control digital signals DP_INT spaced apart by the specified delay time, the m parallel first controlled power supply circuits generate an equalized analog signal and output it to the positive output terminal TXP of the output drive unit 13. Unlike the first controlled power supply circuit group, the second controlled power supply circuit group generates an equalized analog signal and outputs it to the negative output terminal TXN of the output drive unit 13.

[0066] In other examples, please refer to Figure 8 The diagram shows another circuit structure of the output drive unit. The output drive unit includes a first controlled power supply circuit group 131, a second controlled power supply circuit group 132, and a swing compensation circuit 133.

[0067] and Figure 7 The example shown differs in that the swing compensation circuit is connected to the positive and negative output terminals of the output drive unit and is controlled by a first drive control digital signal and a second drive control digital signal. Specifically, a control bit in the first drive control digital signal and a control bit in the second drive control digital signal are respectively connected to the two control terminals of the swing compensation circuit. These two control bits are inverted signals, so that when the output analog signal level swings positively, the swing compensation circuit compensates for the voltage at the positive output terminal of the output drive unit, and when the output analog signal level swings negatively, the swing compensation circuit compensates for the voltage at the negative output terminal of the output drive unit.

[0068] like Figure 8 As shown, the swing compensation circuit 133 includes a power supply IS and two controlled switches connected in parallel. The control terminal of each controlled switch receives a control bit from the first drive control digital signal and a control bit from the second drive control digital signal, so that the two controlled switches are not turned on at the same time.

[0069] Please see Figure 9 It is displayed as a combination Figure 2 and 8 The provided example provides a circuit diagram of a data transmission interface device, wherein the output driver unit is a full-rate structure. This output driver only needs to generate differential serial signals under the control of the first and second drive control digital signals, without simultaneously processing clock and data, thus greatly simplifying the output driver structure. The output driver unit consists of two sets of DAC driver arrays connected as shown in the figure. Each DAC driver array consists of 15 DAC drivers, forming a 4-bit voltage-mode DAC driver. The relationship between the voltage divider resistor RU and the load resistor RT in the figure is: RU = n*RT.

[0070] For an N-bit voltage-mode DAC driver, the following relationship applies: n = 2 N -1. Since this example uses a 4-bit voltage-mode DAC driver, n can be calculated to be 15 using the above formula. RT is typically chosen to be 50 ohms, and RU can also be calculated to be 750 ohms. In addition to RU, the DAC driver also has two PMOS and NMOS transistors used as switches. Assuming the switch on-resistance is zero, the output differential peak-to-peak value of the DAC driver can be calculated to be VS. VS can be obtained through a regulator. By adjusting the output voltage of the regulator, the output swing of the driver is changed. Furthermore, to further increase the output swing, a swing enhancement module as shown in the figure is added, which can increase the output swing from VS to VS + IS * 2 * RT.

[0071] The differential signal output by the data transmission interface device provided in the above examples effectively solves the swing requirement for transmitting high-speed serial signals in the circuit system where the sensor is located.

[0072] This application also provides a data receiving interface device designed to accurately recover differential signals transmitted via a channel. Please refer to [link to relevant documentation]. Figure 10 The diagram shows a circuit structure of a data receiving interface device 2, which includes an input unit 21, a sampling unit 22, a clock recovery control unit 23, a clock generation unit 24, and an output unit 25.

[0073] The input unit is used to receive a first analog signal from the channel. The first analog signal is transmitted in the channel as a wave and is affected by the channel environment, the channel material, the channel length, etc., which makes its high-frequency components easily filtered out during transmission. In some examples, the data transmission interface device reduces the misinterpretation and other problems caused by this effect on the data receiving side by increasing the voltage swing of the transmitted first analog signal. In other examples, the input unit is configured with a compensation mechanism based on predetermined parameters / information related to the channel environment. For example, the input unit is configured with a feedback circuit for compensating the level of the first analog signal, wherein the electrical parameters of the reference signal in the feedback circuit are determined according to the channel material, length, etc. Furthermore, the feedback circuit in the input unit suppresses noise generated by the channel environment through feedback during the reception of the first analog signal, thus enabling the input unit to accurately output a second analog signal.

[0074] Taking the first analog signal as a differential signal as an example, the input unit includes: two signal leads and an equalization circuit connected to the signal leads. The two signal leads are used to couple with the channel to receive the first analog signal, represented by a differential signal, from the channel. The equalization circuit performs equalization processing on the received first analog signal to output the second analog signal. To easily distinguish the first equalization circuit (such as a DAC driver array) in the data transmission interface device, the equalization circuit in this data receiving interface device is referred to as the second equalization circuit.

[0075] The second equalization circuit includes at least one equalizer unit. The gate circuit devices in the equalizer unit respond to the voltage difference between two inverse signals in the received first analog signal, and accordingly output a differential signal, i.e., a second analog signal, that is inversely related to the first analog signal. When there are multiple equalizer units in the second equalization circuit, the equalizer units are cascaded together.

[0076] The equalizer unit, designed to output a differential signal that is inversely related to and compensated for by the first analog signal, includes switches M1 and M2 controlled by two inverse signals from the first analog signal. The equalizer unit is also connected to a constant voltage VDD. Circuit branch L1, containing switch M1, is connected to the positive output terminal, and circuit branch L2, containing switch M2, is connected to the negative output terminal. An isolation circuit branch connects the two circuit branches. Circuit branches L1 and L2 are configured with electrical components of the same electrical parameters to achieve symmetry in the differential signal output.

[0077] To improve the shaping effect of the output second analog signal and facilitate accurate signal extraction by subsequent sampling circuits, in some examples, the equalizer unit also includes a compensation circuit connected to the positive and negative output terminals respectively. This compensation circuit performs corresponding equalization compensation based on the level output from the positive input terminal or the level output from the negative output terminal. For example, when the positive output terminal outputs a high level, the compensation circuit pulls down the level of the negative output terminal; or when the negative output terminal outputs a high level, the compensation circuit pulls down the level of the positive output terminal. This increases the common-mode voltage difference. In other examples, the second equalization circuit utilizes multiple cascaded equalizer units to provide high-frequency shaping of the second analog signal. For example, the cascaded equalizer units provide slightly different equalization compensation voltages to improve the shaping of the high-frequency second analog signal.

[0078] To enable the equalizer unit to adapt to interference from the channel environment, the equalizer unit includes components adjustable by an external correction circuit; and the second equalization circuit also includes the correction circuit. The adjustable components are configured according to the circuit structure of the equalizer unit, and examples include at least one of a power amplifier, capacitor, or resistor. The adjustable components achieve the purpose of the second equalization circuit outputting a second analog signal in accordance with the correction circuit by adjusting the voltage, current, or properties (such as capacitance or resistance) of the components.

[0079] For example, the equalizer unit includes: circuit branch L1, circuit branch L2, adjustment circuit, and correction circuit. Circuit branches L1 and L2 are connected to the positive and negative output terminals of the equalizer unit, respectively. Switches M1 and M2 are respectively configured on circuit branches L1 and L2, and the control terminals of switches M1 and M2 receive differential signals. The adjustment circuit is connected to the correction circuit and is used to adjust the signal electrical parameters of the positive or negative output terminal according to the correction signal output by the correction circuit. The correction circuit is connected to both the positive and negative output terminals and is used to detect the common-mode voltage difference between the positive and negative output terminals and output a correction signal indicating whether to increase or decrease the common-mode voltage difference. In some examples, the equalizer unit also includes a compensation circuit as described in the above example.

[0080] Please see Figure 11 The diagram shows a circuit structure of an equalizer unit. Circuit branch L1 includes resistor RL1 and switch M5; circuit branch L2 includes resistor RL2 and switch M6. Resistors RL1 and RL2 have equal resistance values; switches M5 and M6 have the same electrical parameters. VDD is the reference high voltage, VSS is the reference ground voltage, and VBN is the bias voltage.

[0081] like Figure 11 As shown, the adjustment circuit 2111 is coupled between the output terminals of switches M1 and M2, and includes energy storage devices (such as capacitors) C0_1 and C0_2 connected in series. The connection point of energy storage devices C0_1 and C0_2 receives a correction signal. The compensation circuit 2112 includes, for example, switches M3 and M7 connected in series to the negative output terminal of the equalizer unit, and switches M4 and M8 connected in series to the positive output terminal of the equalizer unit; wherein the control terminal of switch M3 is connected to the positive output terminal of the equalizer unit, and the control terminal of switch M4 is connected to the negative output terminal of the equalizer unit. To further increase the common-mode voltage difference, the compensation circuit also includes energy storage devices Cc_1 and Cc_2 connected in series between the output terminals of switches M3 and M4, wherein the connection point of energy storage devices Cc_1 and Cc_2 receives a correction signal. Similar to energy storage devices C0_1 and C0_2, when the correction signal is high, the energy storage in energy storage devices Cc_1 and Cc_2 increases the level of the valid signal output at the positive output terminal, or increases the level of the valid signal output at the negative output terminal. When the correction signal is low, Cc_1 and Cc_2 in the adjustment circuit have no energy storage, that is, they do not increase the level of the valid signal output at the positive output terminal, or do not increase the level of the valid signal output at the negative output terminal.

[0082] To improve the high-frequency compensation capability of the equalizer unit, this example uses a four-stage cascaded equalizer unit based on negative capacitor technology. In the diagram, VIN and VOUT are the input and output of the equalizer unit, respectively. Since R0 is a fixed resistor in this example, only one control voltage VC is used to adjust the variable capacitors C0 and Cc of the circuit, thereby adjusting the high-frequency compensation gain of the equalizer unit. The area within the dashed line in the diagram represents the negative capacitor structure, whose equivalent impedance is:

[0083]

[0084] Among them, gmNC and CgsNC are the transconductance and gate-source capacitance of MOSFET M3 (M4), respectively.

[0085] Among them, Z NC This can be represented as negative capacitance -C C and a negative resistor -R C Serialized, where R C The value is:

[0086]

[0087] Therefore, the output impedance of the negative capacitor equalizer unit is:

[0088]

[0089] Z NC This adds a zero and a pole to the output impedance of the equalizer unit, approximately located at... On both sides, the spectrum of the equalization filter using negative capacitors is as follows: Figure 12 As shown (where the dashed line represents the frequency response of the basic equalizer unit without negative capacitance), where W n for W n The zeros and poles on both sides are Z. NC The zeros and poles. Clearly, the negative capacitor structure increases the high-frequency compensation gain and the bandwidth of the high-frequency gain of the equalizer unit.

[0090] Please see Figure 13 The diagram illustrates a circuit structure of an input unit, which includes multiple cascaded equalizer units 212 and a correction circuit 211. The number of cascaded equalizer units 212 is related to the bit depth of the correction signal provided by the correction circuit 211. The equalizer unit 212 can be exemplified by the circuit structure of the equalizer unit described in any of the above examples. The correction circuit 211 performs correction detection on the second analog signal output by the cascaded equalizer units, causing at least one equalizer unit 212 to adjust the amplitude of the output differential signal.

[0091] In some examples, while the input unit receives a first analog signal representing the sensor's measurement signal, the calibration circuit performs calibration detection and outputs a real-time calibration signal.

[0092] In other examples, before receiving the first analog signal representing the sensor's measurement signal, the calibration circuit receives a first analog signal transmitted by the aforementioned data transmission interface device for testing channel interference signals, in order to correct for interference from the channel environment on the analog signal. For this, please refer to... Figure 14 The diagram shows a schematic of a calibration circuit. The calibration circuit includes a detection sub-circuit 2121 and a calibration control sub-circuit 2124.

[0093] The detection sub-circuit is coupled to the output terminal of the input unit and is used to detect the common-mode voltage of the second analog signal (VOP and VON) output by the output terminal, so as to output a detection signal reflecting the over-compensation or under-compensation of the input unit. The detection signal can be, for example, a level signal using high and low levels to represent over-compensation or under-compensation, or a level signal representing the amount of over-compensation or under-compensation, etc.

[0094] Here, the detection sub-circuit includes: a common-mode voltage detection module, a reference signal generation module, and a detection output module. The common-mode voltage detection module detects the common-mode voltage (VCM) of the second analog signal and outputs a fluctuating electrical signal reflecting changes in the common-mode voltage. The reference signal generation module outputs a reference electrical signal. The detection output module is connected to both the common-mode voltage detection module and the reference signal generation module, and is used to output a detection signal by detecting the fluctuating electrical signal and the reference electrical signal.

[0095] To enable the reference electrical signal to adapt to the amplitude of interference signals in the channel environment, thereby improving the signal-to-noise ratio of the second analog signal, please refer to [link to relevant documentation]. Figure 15 The diagram shows a circuit structure of a detection sub-circuit. The common-mode voltage detection module includes a common-mode detection sub-module 2122 and a first amplitude detection sub-module 2123; the reference signal generation module includes a reference signal generation sub-module 2125 and a second amplitude detection sub-module 2126; the detection output module 2127 includes a comparator.

[0096] The common-mode detection submodule receives the second analog signal and outputs a common-mode voltage (VCM) to the reference signal generation submodule. The outputs of the first and second amplitude detection submodules are connected to a detection output module to output high and low level detection signals. The common-mode detection submodule detects the common-mode voltage of the input serial differential signals (i.e., the second analog signals RXP and RXN). The reference signal generation submodule converts the reference differential signals (C1 and C2) into a reference differential signal based on the detected common-mode voltage VCM, causing the swing of the reference differential signal to change in accordance with the common-mode voltage VCM. The first and second amplitude detection submodules output single-ended level signals proportional to the peak swing of the received serial differential signal and reference differential signal, respectively. A comparator compares the level signals output by the first and second amplitude detection submodules to determine whether the swing of the input serial differential signal is higher than the swing of the reference differential signal, thereby determining whether compensation is needed for each equalizer unit.

[0097] The correction control subcircuit is connected to the adjustment terminals of each equalizer unit in the detection subcircuit and the input unit. It is used to perform feedback compensation processing using the detection signal at least once, so as to transmit the corresponding control signal to each adjustment terminal. An example of an adjustment terminal is the connection terminal between the adjustment circuit and the correction circuit mentioned in the above example.

[0098] The correction control subcircuit can be composed of digital electrical devices capable of performing logic operations, such as counters, registers, comparators, and encoders, connected together to execute the correction control logic. Please refer to... Figure 16 The diagram shows a processing logic flowchart of the correction control subcircuit processing at least one detection signal. After the chip is powered on or other trigger conditions are met, the chip is set to correction mode, i.e., the initial compensation coefficient is set to 0. The digital transmission interface device starts sending test data and transmits it to each equalizer unit through the channel to start them working. At the same time, the detection subcircuit compares the amplitude of the second analog signal with the threshold value. The digital circuit inside the correction control subcircuit determines the state of the equalizer composed of cascaded equalizer units based on the comparison result. If it is determined to be in an undercompensated state, the compensation coefficient is increased; if it is determined to be in an overcompensated state, the compensation coefficient is decreased until it is determined that no compensation is needed, or other cutoff conditions are met, and the correction circuit is turned off, and the correction ends. The detection subcircuit enters the normal operation stage and uses the stored compensation coefficient as the coefficient for the normal operation of subsequent equalizer units to compensate for the gain of high-frequency signals. Examples of other trigger conditions include: handshake communication between the data transmission interface device and the data receiving interface device before transmitting the valid measurement signal from the sensor; or trigger commands generated based on measurement data such as temperature and humidity that affect the channel environment, etc.

[0099] In combination with the above Figure 16 The operation of the correction control subcircuit is illustrated below: Upon power-up, registers, counters, and other components in the correction control subcircuit are reset to their initial values ​​(e.g., 0). Each digital device in the correction control subcircuit samples the received detection signal and determines whether the sampled detection signal is over-compensated or under-compensated, adjusting the corresponding counter value based on the determination result. This process is repeated cyclically under the clock signal's step frequency until the count value or the number of determinations meets a preset cutoff condition. The encoder in the correction control subcircuit encodes the count value after the loop ends and outputs a corresponding binary correction signal according to the number of equalizer units. This binary correction signal is then used by each equalizer unit to perform equalization compensation during the period when it receives the first analog signal representing the sensor's measurement signal. Examples of cutoff conditions include no change in the count value or the number of determinations reaching its maximum value.

[0100] After the input unit performs equalization compensation on the first analog signal from the channel, it outputs the second analog signal to the sampling unit so that the digital measurement signal processed by the data transmission interface device can be recovered through the sampling unit.

[0101] The sampling unit is coupled to the input unit and is used to sample the received second analog signal according to the received clock signal, so as to output the first digital signal and the clock signal.

[0102] Here, the sampling unit responds to the rising edge of the received clock signal and outputs a first digital signal with an inverse relationship. In the example where the first analog signal is a differential signal, since the clock signal is not synchronized with the potential representing data / information in the first analog signal, the first digital signal output by the sampling unit has a large bit error rate.

[0103] Therefore, the sampling unit samples the second analog signal according to multiple clock signals with phase offsets. The first digital signal output by the sampling unit includes: high / low levels obtained by sampling according to the time corresponding to different clock signals; the output first digital signal and one of the clock signals are output to the output unit for subsequent circuitry to perform digital signal processing; the sampled first digital signal is output to the clock recovery control unit, so that the clock recovery control unit can perform phase detection on the first digital signal generated within a preset number of clock half-cycles. The phase offset (also known as phase difference) is less than 180°, for example, the phase offset includes 30°, 45°, or 90°, etc.

[0104] The clock recovery control unit is coupled to the sampling unit and outputs a clock recovery control signal that reflects the phase deviation between the second analog signal and one of the clock signals by detecting the received first digital signal.

[0105] Here, the clock recovery control unit detects the first digital signals sampled at different phases within a certain period of time to determine whether any clock signal leads or lags behind the second analog signal, and outputs a corresponding clock recovery control signal. The time period is determined based on the duration required to sample a preset number of the first digital signals. For example, the time period is an integer multiple of a clock half-cycle, or it is determined based on the sum of the phase deviations of multiple clock signals.

[0106] The clock recovery control unit utilizes digital electronic devices such as registers, flip-flops, and comparators to construct a detection logic circuit. This circuit detects whether the second analog signal leads or lags the sampled clock signal in phase, and outputs the corresponding clock recovery control signal to the clock generation unit. The clock recovery control unit can obtain the amount of phase lead or lag by detection, or obtain an identifier for phase lead or lag, and represent this information using the amplitude and encoding of the clock recovery control signal.

[0107] The clock generation unit is coupled to the clock recovery control unit and the sampling unit, and is used to adjust the generated clock signal according to the received clock recovery control signal, and output the adjusted clock signal to the sampling unit.

[0108] Here, the clock generation unit adjusts the frequency and / or initial phase of each output clock signal according to the received clock recovery control signal.

[0109] Taking the clock recovery control signal as an identifier indicating phase lead or lag, for example, the clock generation unit adjusts the frequency (and / or initial phase) of each clock signal according to a preset frequency step (and / or phase step).

[0110] Taking the clock recovery control signal representing a phase leading or lagging as an example, the clock generation unit adjusts the initial phase of each clock signal according to the phase amount. Alternatively, the clock generation unit converts the phase amount into a frequency change and adjusts the generated clock signals accordingly.

[0111] The clock generation unit typically includes an adjustment circuit, a signal generator, and a phase-locked loop (PLL) circuit. The adjustment circuit adjusts the frequency division ratio in the PLL circuit according to the clock recovery control signal. The PLL circuit performs phase-locking and phase-shifting operations on the square wave signal provided by the signal generator based on this frequency division ratio, and outputs multiple clock signals with phase offset.

[0112] Using the clock signal generated by the clock generation unit, the sampling unit adjusts the phase position of the second analog signal to accurately sample the digital signal reflecting the data transmission interface device. The sampled first digital signal is then transmitted to the output unit.

[0113] The output unit is coupled to the sampling unit and is used to convert the corresponding first digital signal into a second digital signal under the control of the received clock signal and output it.

[0114] The clock signal received by the output unit is one of the multiple clock signals, and the unit extracts 0 and 1 data from the first digital signal according to the clock signal and converts it into a second digital signal for subsequent circuit processing.

[0115] For example, if the output unit includes a differential serial output terminal, it outputs the second digital signal obtained by sampling the first digital signal according to the corresponding clock signal.

[0116] For example, if the output unit includes a parallel output terminal, then the output unit includes a serial-to-parallel conversion circuit coupled to the sampling unit. The serial-to-parallel conversion circuit is used to convert the received first digital signal, represented by a differential signal, into a second digital signal, represented by multiple parallel signals, and then output it. The serial-to-parallel conversion circuit may include, for example, a circuit with an 8-bit or 10-bit parallel output terminal.

[0117] As described in the above examples, the data receiving interface device and the data transmitting interface device test the channel environment using a test transmission signal between the transmission of valid data, thereby realizing the equalization compensation operation of the data receiving interface device in advance to suppress channel noise and improve the accuracy of the transmission signal.

[0118] In data interface devices such as those for automotive radar sensors, the radar sensor transmits a first analog signal representing the measured data in real time using data transmitting and receiving interface devices during the transmission of detected measurement data. Considering the extremely high real-time requirements of automotive measurement data, the data transmitting and receiving interface devices include a signal processing procedure for clock recovery during the transmission of differential signals, following a serial transmission protocol. Therefore, shortening this process can effectively reduce the data transmission delay.

[0119] To this end, this application also provides a data interface device (also known as a data receiving interface device) designed to shorten the time required to recover a clock signal from a received analog signal. This data interface device enables sensors used in applications such as automobiles and traffic monitoring to transmit data (or signals) within millisecond or even nanosecond time intervals, effectively reducing the transmission time.

[0120] Please see Figure 17 The diagram shows another hardware architecture of the data receiving interface device. The data receiving interface device 3 includes: an input unit 31, a sampling unit 32, a clock recovery control unit 33, a clock generation unit 34, and an output unit 35.

[0121] The input unit is used to couple with the channel to receive a first analog signal from the channel and output a corresponding second analog signal to be converted.

[0122] The sampling unit is coupled to the input unit and is used to sample the received second analog signal according to the received clock signal, so as to output the first digital signal and the clock signal.

[0123] The clock recovery control unit is coupled to the sampling unit. Within a preset number of clock half-cycles, it detects the received first digital signal and outputs a K-bit clock recovery control signal that reflects the phase deviation between the second analog signal and the clock signal. The clock recovery control signal uses a field to represent the phase value of the adjusted clock signal.

[0124] The clock generation unit is coupled to the clock recovery control unit and the sampling unit, and is used to adjust the generated clock signal according to the received clock recovery control signal, and output the adjusted clock signal to the sampling unit.

[0125] The output unit is coupled to the sampling unit and is used to convert the corresponding first digital signal into a second digital signal under the control of the received clock signal and output it.

[0126] The input unit, sampling unit, and output unit are the same as those described above. Figures 10-16 The data receiving interface devices mentioned in the examples are identical or similar to any of the examples. For example, the input unit uses a cascaded equalizer unit pre-configured via a test channel to perform swing compensation on the received first analog signal and outputs a second analog signal. The sampling unit samples the second analog signal according to the received clock signal to output paired, inverted first digital signals. The output unit converts two of the inverted first digital signals into multiple parallel second digital signals. Examples of the second digital signals are 8-channel or 10-channel parallel digital signals.

[0127] As described above, the sampling unit responds to the rising edge of the received clock signal and outputs a corresponding inverted first digital signal. When the sampling unit receives multiple clock signals with phase offset, in response to each clock signal, the first digital signal output by the sampling unit includes: a high / low level obtained by sampling according to the time corresponding to different clock signals; the output first digital signal and one of the clock signals are output to the output unit for subsequent circuitry to perform digital signal processing; the sampled first digital signal is output to the clock recovery control unit, so that the clock recovery control unit can perform phase detection on the first digital signal generated within a preset number of clock half-cycles. The phase offset (also known as phase difference) is less than 180°, for example, the phase offset is 30°, 45°, or 90°, etc.

[0128] Unlike the previous examples, the clock signal is output by the clock generation unit based on a clock recovery control signal provided by the clock recovery control unit, which includes a phase range and phase values. Specifically, the clock recovery control unit performs clock phase detection on the received first digital signal according to half a cycle of the currently received clock signal (also known as a clock half-cycle) and generates a clock recovery control signal to feed back to the clock generation unit. The clock generation unit adjusts the phase of the clock signal accordingly to synchronize it with the clock signal used by the data transmission interface device to transmit analog signals. Because the clock recovery control signal simultaneously provides the phase range and the phase values ​​within that range, the clock recovery control unit and the clock generation unit simultaneously adjust the phase range and accurate phase values ​​during the feedback-adjustment process, thereby significantly shortening the feedback-adjustment time of the clock recovery process.

[0129] In some examples, the clock recovery control unit includes an N-bit first register and an output circuit. The N-bit first register provides the phase value for a corresponding field. N is an integer greater than 1, representing the precision of the binary phase value provided by the N-bit first register. The N-bit first register can be composed of multiple cascaded registers to implement shift operations, or it can be a shift register. The N-bit first register is used to adjust the temporarily stored binary phase value using shift interpolation. The shift interpolation methods include: shift interpolation from the most significant bit to the least significant bit, and / or shift interpolation from the least significant bit to the most significant bit. The shift interpolation from the most significant bit to the least significant bit or from the least significant bit to the most significant bit is used to represent a clockwise or counterclockwise shift of the phase within the phase interval. For example, a shift interpolation of 1 from the most significant bit to the least significant bit represents a counterclockwise shift of the N-bit first register; a shift interpolation of 0 from the least significant bit to the most significant bit represents a clockwise shift of the N-bit first register.

[0130] The output circuit is connected to the N-bit first register and the clock generation unit, and is used to generate the clock recovery control signal according to the binary phase value stored in the N-bit first register, and output it to the clock generation unit. The output circuit may include, for example, a circuit containing flip-flops. For instance, each output terminal of the N-bit first register is connected to a flip-flop, and each flip-flop triggers the output of the binary phase value based on the rising edge of the clock signal.

[0131] Here, the clock recovery control unit can perform interpolation operations by detecting the clock phase of the second analog signal within a preset number of clock half-cycles, thereby controlling the N-bit first register to shift bits from high to low or from low to high. The preset number can be determined based on the system stability, robustness, and other indicators of the entire data receiving interface device. For example, the number could be 8.

[0132] In some examples, the clock generation unit generates multiple clock signals for the current moment based on the clock recovery control signal from the previous moment. These multiple clock signals have a certain phase difference, allowing the sampling unit to sample the received second analog signal multiple times within a single clock half-cycle. The sampled high and low levels are then output to the clock recovery control unit. The comparison circuit in the clock recovery control unit selects whether to interpolate from the high or low bit side of the N-bit first register by comparing the high and low levels. When a preset number of operations are performed, the output circuit outputs the binary phase value stored in the N-bit first register. Therefore, the clock generation unit maintains the output of a clock signal with a certain phase for at least the preset number of operations and a clock half-cycle.

[0133] In some other examples, unlike the previous example, the clock recovery control unit counts all high and low levels within a preset number of clock half-cycles; controls the N-bit first register to interpolate from the high-bit side or the low-bit side by comparing the count values, and outputs the result by the output circuit.

[0134] For this purpose, please refer to Figure 18 The diagram shows a circuit structure of the clock recovery control unit. The clock recovery control unit includes: a first shift decision circuit 331, a first phase adjustment circuit 332, an N-bit first register 333, and an output circuit 334.

[0135] The first shift decision circuit is coupled to the sampling unit, detects the first digital signal in each half-clock cycle of a preset number, and outputs a control signal determined according to the level logic of the preset number.

[0136] Here, the first digital signal received by the first shift decision circuit is obtained by the sampling unit sampling the second analog signal based on multiple clock signals. For example, the first shift decision circuit and the sampling unit are connected through two differential lines to receive the first digital signal; wherein, the first digital signal is obtained by the sampling unit sampling the second analog signal at different times according to the clock phase offset between multiple clock signals.

[0137] The first shift decision circuit uses counters and comparators to count the levels of the first digital signal and outputs a control signal based on the level count over at least a preset number of clock half-cycles. The control signal includes at least an identifier signal indicating whether the phase of the first digital signal leads or lags the phase of the clock signal. For example, the identifier signal may be a 2-bit signal set according to a preset truth table of phase leading, phase lagging, and phase alignment; or it may be a level signal corresponding to different levels in the truth table.

[0138] In some examples, the first shift decision circuit includes a phase shift detection circuit structure and a phase shift control circuit structure.

[0139] The phase-shift detection circuit is coupled to the sampling unit and detects the first digital signal within a preset number of clock half-cycles to obtain phase detection data.

[0140] Here, the phase-shift detection circuit structure includes: a phase detection logic circuit constructed using multiple comparators according to a preset truth table for phase detection (also known as phase discrimination). The phase-shift detection circuit structure also includes a temporary storage circuit constructed using multiple flip-flops / registers to temporarily store the phase detection results of each phase detection logic step. The phase-shift detection circuit structure also includes an output control circuit to output the data temporarily stored by each flip-flop as the phase detection data after a preset number of detections.

[0141] In some specific examples, the logic circuit in the phase-shift detection circuit structure generates an n-bit phase detection result (n≥1) based on the high / low level of the inverted first digital signal detected in each half-clock cycle; the phase detection result is output to the low-bit / high-bit flip-flop in the temporary storage circuit; wherein, the temporary storage circuit uses a shift circuit structure to temporarily store each received phase detection result; when the output control circuit detects that a preset number of phase detections have been performed, it outputs each phase detection result in the temporary storage circuit, that is, outputs the phase detection data, and resets the temporary storage circuit.

[0142] In some specific examples, the phase-shift detection circuit structure utilizes the first and / or last level detected in the first digital signal within the (n-1)th clock half-cycle to perform counting detection in the nth clock half-cycle, thereby effectively reducing the data transmission rate of the phase detection data. For example, the phase-shift detection circuit structure can reduce the data transmission rate of the phase detection data to half the frequency of the clock signal.

[0143] Based on the circuit structure examples above, in some examples, the phase shift detection circuit structure uses different received clock signals to perform phase shift detection on the level of the corresponding moment in the inverted first digital signal, and performs a preset number of counting operations, etc. In other examples, the phase shift detection circuit structure uses an internal clock signal to sample the received first digital signal, wherein the frequency of the internal clock signal is at least twice the frequency of the clock signal used by the sampling unit; and uses the sampled data to perform phase shift detection, etc.

[0144] Please see Figure 19 The diagram shows a timing sequence of a phase-shift detection circuit. Using this timing sequence, the phase-shift detection circuit, including the aforementioned circuit structure, can perform phase detection on a preset number of first digital signals. Specifically, within half a clock cycle, the first digital signal received by the phase-shift detection circuit is obtained by sampling a second analog signal D using multiple clock signals (CLK0, CLK90, CLK180, CLK270) with a 90° phase offset. The phase-shift detection circuit performs phase-shift detection by grouping three consecutive first digital signals received sequentially. Figure 19 As shown, {D0, E0, D1} are the sampling levels obtained by acquiring the second analog signal D from the three clock signal transition edges with a phase offset of 90° in the first digital signal. Based on the preset phase detection logic, a 2-bit phase detection result is output, as shown in Table 1 below:

[0145] Table 1

[0146] Phase detection logic Phase detection results explain D0≠E0=D1 10 Data lead time clock D0 = E0 ≠ D1 01 Data lag clock D0 = E0 = D1 00 / 11 Data without jumps

[0147] The phase-shift detection circuit structure is thus used to continue detecting the sampling levels of {D1,E1,D2}, ..., {Dn-1,E n-1,Dn} groups; and to buffer the phase detection results of each group; when the number of detections reaches a preset number, the output is generated by up.<n,0> and dn<n,0> The phase detection data consists of the following: each pair {up(i),dn(i)} in the phase detection data represents a phase detection data of a single detection, i∈[n,0].

[0148] The phase-shift detection circuit structure sends the generated phase detection data to the phase-shift control circuit structure. The phase-shift control circuit structure is coupled to the phase-shift detection circuit structure and the first phase adjustment circuit, counts the bit values ​​in the phase detection data, and outputs a control signal reflecting the counting result, so that the first phase adjustment circuit selects to adjust the stored binary phase value from the high-order side or the low-order side of the N-bit first register.

[0149] Here, the phase-shift control circuit structure includes a counter to count the 0s or 1s in each bit of the received phase detection data; and a comparator to compare the count result with a preset reference level, or compare the phase-shift control circuit with a preset reference level.<n,0> and dn<n,0> The two counting results obtained by counting each digit are used to output the control signal to the first phase adjustment circuit.

[0150] For example, please see Figure 20 , which is shown as a schematic diagram of a circuit structure of a phase shift control circuit structure. The phase shift control circuit structure includes two counters (Count_vote_1 and Count_vote_2) and a comparator CP_vote_1. Among them, the counter Count_vote_1 is used to count the number of 1s or 0s in the bit positions of up<n,0>; the counter Count_vote_2 is used to count the number of 1s or 0s in the bit positions of dn<n,0>; the comparator CP_vote_1 receives the level signals reflecting the count values output by the two counters and outputs a control signal including UPV and DNV. Refer to the example in Table 2. If UPV = 1 & DNV = 0, it means that N(up = 1)>N(dn = 1), that is, the data is ahead of the clock. Under the control of the control signal, the first phase adjustment circuit performs interpolation from the high-order side of the N-bit first register; if UPV = 0 & DNV = 1, it means that N(up = 1)<N(dn = 1), that is, the data lags behind the clock. Under the control of the control signal, the first phase adjustment circuit performs interpolation from the low-order side of the N-bit first register; if UPV = 0 & DNV = 0, it means that N(up = 1)=N(dn = 1), that is, the data has no change. Under the control of the control signal, the first phase adjustment circuit does not perform the interpolation operation. Among them, N(*) represents the number of 1s in the bit positions of up<n,0> or dn<n,0>.

[0151] Table 2

[0152]

[0153]

[0154] Among them, the number of bits interpolated by the first phase adjustment circuit can be 1 bit or multiple bits. For this reason, in order to quickly and accurately adjust the binary phase value, the first phase adjustment circuit further includes: a selection circuit structure, which is connected to the first shift decision circuit and is used to select, according to the control signal, to adjust the values of a bits on the high-order side or the low-order side of the first register, or to select to adjust the values of b bits on the high-order side or the low-order side of the first register; where a and b are integers less than N, and a≠b. In other words, the selection circuit structure is used to select to coarsely adjust the binary phase value in the first register or to finely adjust the binary phase value in the first register.

[0155] Among them, the specific values of a and b can be debugged according to the actual total duration limit of clock recovery.

[0156] In some specific examples, the number of bits 'a' or 'b' provided by the selection circuit structure for interpolation is a fixed value. For example, the logic circuit structure includes a parser that outputs 'a' or 'b' interpolated data based on received control signals, and inserts them accordingly from the high-order side or the low-order side of the first register. The first register adjusts the stored binary phase value according to the shifting method of the first register.

[0157] In some specific examples, the number of bits a or b provided by the selection circuit structure for interpolation can be externally set. For example, the selection circuit structure includes an encoder or decoder (e.g., a temperature encoder) coupled to the phase-shift control circuit structure, receiving external input instructions, encoding the external input instructions into a or b value, and performing the interpolation operation as exemplified above upon receiving a control signal.

[0158] The N-bit first register provides 32 bits of storage. When the received external instruction contains a 4-bit step value to set the value 'a', the thermometer encoder encodes the 4-bit step value, resulting in 'a' being 2. When the received external instruction contains a 5-bit step value to set the value 'b', the thermometer encoder encodes the 5-bit step value, resulting in 'b' being 1. The above-described values ​​and temperature encoder are examples; the encoder and step values ​​used can be selected based on the actual clock recovery control requirements, process requirements, etc.

[0159] In order to select either coarse or fine adjustment mode to control the shift number a or b in the N-bit first register, in some specific examples, the selection circuit structure determines whether to select coarse or fine adjustment by performing level logic processing on at least one received control signal.

[0160] In some other specific examples, the control signal includes a control bit for selecting coarse or fine adjustment, for the selection of circuit structure identification.

[0161] For example, the clock recovery control unit further includes: a second shift decision circuit, which is coupled to the phase shift detection circuit structure and the selection circuit structure, for counting and statistically analyzing the data lead and data lag of at least one set of received phase detection data respectively, and outputting a control signal for selecting coarse or fine adjustment, so that the selection circuit structure can perform a selection operation accordingly.

[0162] The second shift decision circuit utilizes digital and analog electronic devices such as pulse counting circuits, adders / subtractors, comparators, capacitors, charge / discharge control circuits, and isolation circuits to construct a circuit structure to execute the decision logic for selecting coarse or fine adjustment.

[0163] Examples of the judgment logic include: processing multiple sets of phase detection data (such as up)<n,0> and dn<n,0> The system performs counting; it determines whether the difference between the accumulated counts reflecting data leading and data lagging reaches a preset threshold, and outputs a control signal for selecting coarse or fine adjustment based on the determination result. The threshold is related to the number of coarse adjustment shifts and can be represented by a level signal.

[0164] Taking the second shift decision circuit as an example, which includes a decision logic circuit structure, a comparator, etc., the decision logic circuit structure is coupled to the phase shift detection circuit structure and is used to count and statistically analyze the pulses of data lead and data lag of at least one set of received phase detection data, and output a level signal to reflect the phase deviation amplitude obtained by multiple phase detections; the comparator is coupled to the decision logic circuit structure and the phase shift control circuit structure and is used to compare the level signal with a preset reference level to output a control signal that includes the selection of coarse adjustment or fine adjustment.

[0165] Therefore, the phase-shift detection circuit structure provides two channels of phase-detection data representing data leading and data lagging, respectively, such as up.<n,0> and dn<n,0> Please see. Figure 21 The diagram shows a schematic of a second shift decision circuit 335. The decision logic circuit includes two pulse counters (3351_a, 3351_b) to accumulate the number of times data is ahead or behind in each phase detection, and outputs the counted number as a level signal / digital signal. The decision logic circuit also includes a difference calculation circuit component 3352 that processes signals by controlling the level. This component subtracts the received level signal / digital signal representing the count to detect the amplitude of the phase deviation obtained from multiple phase detections; and converts the amplitude of the phase deviation into a level signal and outputs it. A comparator 3353 compares this level signal with a preset reference level to output a high or low level, where the high / low level signal is a control signal LOCK for selecting coarse or fine adjustment. This control signal, together with the control signal output by the first phase shift decision circuit, forms a control signal containing multiple control bits, which is output to the first phase adjustment circuit.

[0166] To improve the phase alignment accuracy between the clock signal phase and the level reflecting valid data in the second analog signal, the clock recovery control unit further includes an M-bit second register and a second phase adjustment circuit.

[0167] The M-bit second register stores the binary phase interval value of the clock signal. A second phase adjustment circuit, coupled to the N-bit first register, the M-bit second register, and the first shift decision circuit, selectively adjusts the binary phase interval value in the M-bit second register based on the binary phase value in the N-bit first register and the control logic composed of the control signal. Specifically, the control logic indicates that when the binary phase value in the N-bit first register reaches a boundary value, and the control signal indicates that the phase adjustment should continue beyond the current boundary value, the binary phase interval value in the M-bit second register is adjusted. Thus, by synchronously adjusting the phase interval value and the phase value, faster and more accurate phase alignment between the clock signal and the second analog signal is achieved.

[0168] Please see Figure 22 This diagram illustrates the condition-state transition of the second phase adjustment circuit when adjusting the phase interval. The N-bit first register comprises 32 bits: C0, C1, ..., C31. The control signals received by the second phase adjustment circuit include UPV and DNV. Based on four preset phase intervals (Z0, Z1, Z2, and Z3), an M-bit second register is used to store the current phase interval's numbering information. This numbering information includes, for example, the boundary information of the two phase intervals, or identification information corresponding to the phase boundaries of the phase interval.

[0169] like Figure 22 As shown, when all bits in the current N-bit first register are 1, and (UPV = 1 & DNV = 0), the phase interval is adjusted in the positive direction of the preset phase interval cycle; when all bits in the current N-bit first register are 0, and (UPV = 0 & DNV = 1), the phase interval is adjusted in the negative direction of the preset phase interval cycle; when the bits in the current first register are not all 1 or all 0, the current phase interval is maintained. This condition-state transition mode also applies to the clock recovery control unit that provides coarse and fine adjustment.

[0170] Here, the output circuit is also connected to the M-bit second register to generate the clock recovery control signal according to the phase interval and its corresponding phase value stored in the M-bit second register and the N-bit first register, and output it to the clock generation unit.

[0171] Following one of the examples above, this application provides a specific example of a clock recovery control unit. Please refer to... Figure 23 The diagram shows a circuit structure schematic of a clock recovery control unit. The clock recovery control unit includes a first shift decision circuit 331, a second shift decision circuit 335 (LD), a first phase adjustment circuit 332, an N-bit first register 333, a second phase adjustment circuit 336, an M-bit second register 337, and an output circuit 334'. The first shift decision circuit 331 includes a phase shift detection circuit structure PD and a phase shift control circuit structure Vote.

[0172] When the sampling unit outputs the first digital signal, the phase-shift detection circuit structure, according to the phase detection logic in Table 1, detects the sampling level {D0, E0, D1} of the first digital signal based on the preset number T sampled within half a clock cycle, to obtain the phase detection result representing the 2-bit value within that half clock cycle, where j∈T; all 2-bit values ​​of the preset number T are then converted to up...<n,0> and dn<n,0> The phase detection data is output to the phase shift control circuit structure.

[0173] The phase-shift control circuit structure updates each received phase detection data.<n,0> and dn<n,0> The system counts all bits that are 1; compares the leading and lagging counts in the phase detection data, and outputs a first control signal containing the binary phase value to the first phase adjustment circuit; and outputs the control signal to the second phase adjustment circuit. During this period, the second shift decision circuit performs cumulative counting of leading and lagging data on at least one set of received phase detection data according to the phase interval detection logic in Table 2, and outputs a second control signal to the first phase adjustment circuit to select coarse or fine adjustment based on the phase deviation amplitude signal obtained by cumulative counting, which reflects the phase deviation after multiple phase detections.

[0174] The first phase adjustment circuit, under the control of coarse adjustment, adjusts the phase according to the coarse adjustment bit number a and references... Figure 22 The condition-state transition diagram shows the shift adjustment of the binary phase value stored in the first register by N bits. Alternatively, under the control of fine-tuning, the first phase adjustment circuit adjusts the phase value according to the fine-tuning bit b and references... Figure 22 The condition-state transition diagram shows the shift adjustment of the binary phase value stored in the first N-bit register.

[0175] Please see Figure 24 This diagram illustrates a condition-state transition for adjusting binary phase values ​​using a first phase adjustment circuit. Taking a coarse adjustment bit a = 2 and a fine adjustment bit b = 1 as an example, the received control signal includes a first control signal and a second control signal. When UPV = 1 and DNV = 0 in the first control signal, and the second control signal indicates fine phase adjustment, the first phase adjustment circuit shifts the bit from C0 to C31 in the N-bit first register by a 1-bit increment, inserting a 0 value into C0. When UPV = 0 and DNV = 1 in the first control signal, and the second control signal indicates fine phase adjustment, the first phase adjustment circuit shifts the bit from C31 to C0 in the N-bit first register by a 1-bit increment, inserting a 1 value into C31. This continues until the N-bit first register stores a value such as... Figure 22 When all bits are 1 and UPV = 1 & DNV = 0 in the first control signal, the second phase adjustment circuit adjusts the value in the M-bit second register in the positive direction of the phase interval cycle to adjust one phase interval; when the value stored in the N-bit first register is as shown... Figure 22 As shown, when all bits are 0 and UPV = 1 & DNV = 0 in the first control signal, the second phase adjustment circuit adjusts the value in the M-bit second register in the negative cyclic direction of the phase interval to adjust one phase interval. When the first control signal indicates fine adjustment and UPV = 0 & DNV = 0 in the second control signal, the phase adjustment is complete. Each time the above-mentioned N-bit first register or M-bit second register is adjusted, the output circuit generates a clock recovery control signal and outputs it to the clock generation unit.

[0176] The clock generation unit generates multiple clock signals with phase differences within half a clock cycle based on the received phase interval and the binary phase values ​​within the corresponding phase interval, and feeds them back to the sampling unit. The sampling unit outputs one of the clock signals and a first digital signal to the output unit so as to output a second digital signal that can be recognized by subsequent circuits.

[0177] Using the signal transmission methods mentioned in the above examples, before transmitting valid data, the data transmitting interface device and the data receiving interface device transmit test data of a preset amount according to a preset transmission protocol to restore the clock signal and test the current channel environment noise, thereby recovering the accurate second digital signal from the channel.

[0178] In some electronic devices, both a data transmission interface and a data reception interface are integrated into the data interface device to achieve bidirectional communication. In other electronic devices, depending on the data transmission design between the various hardware modules, the interface device and the data reception interface device are configured in different hardware modules.

[0179] Please see Figure 25 The diagram illustrates the hardware structure of a sensor system. The sensor system 4 includes a first radar sensor 41 and a second radar sensor 42. The first radar sensor 41 or the second radar sensor 42 can be, for example, a chip-level sensor, or a printed circuit board integrating multifunctional devices such as antennas and signal transceiver chips. The two are connected via a data transmission interface device 411 and a data reception interface device 421 to expand the detection range and improve the resolution of the sensor system. The sensor system can also be, for example, a printed circuit board cascading the first and second radar sensors, or a chip-level first and second radar sensor cascading using SOC technology.

[0180] The first radar sensor and the second radar sensor further include, at least one of, an antenna device and a signal transceiver device. Driven by the signal transceiver device, the antenna device transmits a detection signal wave and receives an echo signal wave reflected from a target. The signal transceiver device outputs a baseband digital signal corresponding to the echo signal wave. For example, the signal transceiver device includes a signal transmitter and a signal receiver. The antenna device and the signal transceiver are, for example, integrated into a chip-level first or second radar sensor using a circuit structure manufactured using semiconductor technology. The signal transmitter transmits the detection signal wave via the antenna device within a preset frequency band or in a fixed-frequency manner; the signal receiver performs signal processing on the echo electrical signal corresponding to the echo signal wave, including mixing, filtering, and automatic gain adjustment, and performs analog-to-digital conversion on the analog signal to output the baseband digital signal. The echo signal wave is formed by the reflection of the detection signal wave from an object; the echo electrical signal is an electrical signal generated by the receiving antenna sensing the echo signal wave.

[0181] In some examples, at least one of the first radar sensor and the second radar sensor may further include a signal processing device to process the baseband digital signal and output measurement data. The signal processing device outputs measurement data including at least one of angle, distance, and velocity by performing signal processing on the baseband digital signal, including Fast Fourier Transform (FFT) operations.

[0182] In some other examples, at least one of the first radar sensor and the second radar sensor may further include a target detection device for performing data processing such as target detection and target tracking on the measurement data to output target detection data. The target detection device is used to perform target detection processing on the received measurement data to output corresponding target detection data.

[0183] The first radar sensor further includes a first data interface device, exemplified by a data transmission interface device as described in any of the above examples, for transmitting measurement signals detected by the first radar sensor. The measurement signals reflect at least one of the following data: a baseband digital signal detected by the first radar sensor, measurement data of at least one of the following: distance, velocity, and azimuth angle between the first radar sensor and the target, and target detection data of the target.

[0184] The second radar sensor further includes a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; wherein the second data interface device is a data receiving interface device as described in any of the above examples, used to receive the measurement signal; and the third data interface device is used to forward the measurement signal. The channel is a medium for transmitting measurement signals between the first and second radar sensors, and examples include any of the following: microstrip line, coaxial cable, or optical fiber, etc.

[0185] Here, the third data interface device may be a data transmission interface device as described in any of the above examples; or other data interface devices, such as a CAN bus interface.

[0186] As a sensor system comprising multiple radar sensors, it is typically configured with a master device and slave devices. The master device manages the operating status of the slave devices and coordinates the data / signals generated by itself and the slave devices, enabling them to be input / output through a designated data interface device. Examples of the operating status include at least one of the following: a state where the signal transceiver uses at least one transceiver channel to transmit and receive signals; a standby state; a data read / write state, etc.

[0187] Taking one of the first or second radar sensors as the master device in a cascaded sensor system, and the other as a slave device, under the control of the master device, both the first and second radar sensors transmit data with external devices using a third data interface device. For example, the measurement signals detected by each of the first and second radar sensors are transmitted through the third data interface device. To provide a more complete sensing solution, in some examples, the sensor system also includes a data processing device coupled to the third data interface device. This device performs at least one data processing operation on the measurement signals and outputs corresponding target detection results, interactive data, or control commands through the third data interface device.

[0188] The target detection result is information extracted from the measurement data to describe dynamic and / or static objects in the surrounding environment detected by the sensor system, including but not limited to: vital signs information, movement information, boundary information, and identification information for a single target (or multiple targets). The interactive data is data determined for the purpose of delivering the measurement data or target detection result to the user, including but not limited to at least one of the following data for the user to perceive: reminders, warnings, graphics, or sounds. The control command is information generated after processing the received measurement data or target detection result according to preset trigger conditions, used to change the operating state of other hardware systems; wherein the trigger conditions are related to the purpose of data processing of the measurement data or target detection result. For example, the control command includes but is not limited to at least one of the following: control commands for slowing down or turning a car, control commands for detecting life activities inside a cabin (or indoors), etc.

[0189] Therefore, the working process of the sensor system is illustrated as follows: Taking the second radar sensor as the master device and the first radar sensor as the slave device, the second radar sensor manages the first radar sensor to synchronously transmit and receive signal waves, and performs signal processing such as mixing and filtering on the electrical signals provided by their respective assigned virtual transceiver channels to output baseband digital signals. The first and second radar sensors also perform digital signal processing on the baseband digital signals to generate measurement data. Under the management and control of the second radar sensor, the first radar sensor establishes a communication mechanism to output the generated measurement data to the second radar sensor using the physical links of the first data interface device, the channel, and the second data interface device. For example, in the handshake phase of the signal transmission protocol, the first radar sensor establishes a communication link with the second radar sensor by transmitting a handshake signal through the first data interface device, in order to transmit the measurement data obtained by the first radar sensor. Furthermore, using this handshake signal, the equalization circuit in the second data interface device can preset the compensation amplitude based on the noise detected in the current channel; and the clock recovery unit and clock unit in the second data interface device recover a clock signal from the handshake signal that can be used to sample subsequent measurement signals. After the communication link is established, the first and second data interface devices accurately process the transmission and reception of measurement signals. The measurement signal is an analog signal easily transmitted, formed after the measurement data has been processed by the first data interface device. Under the management and control of the second radar sensor, the second radar sensor also sends the measurement data obtained by the first radar sensor and itself to the data processing device. This device extracts target detection data from the measurement data provided by the two radar sensors and uses the target detection data to obtain target detection results, interactive data, or control commands. This target detection result, interactive data, or control command information is output through the third data interface device for subsequent hardware circuitry to perform corresponding operations.

[0190] This application also provides a data acquisition device. The data acquisition device connects a chip-level radar sensor to peripheral circuitry to enable the radar sensor to operate, and to forward or further process any of the baseband digital signals, measurement data, or target detection results provided by the radar sensor.

[0191] Therefore, the data acquisition device includes: a data receiving interface device and a data processing device as mentioned in the above example; it may also include a data transmitting interface device Out_Port_1. For ease of description, the data receiving interface device in this example is also referred to as the fourth data interface device; the data transmitting interface device is also referred to as the fifth data interface device. The fourth data interface device is connected to the data transmitting interface device Out_Port_2 (also referred to as the sixth data interface device) in the radar sensor via a channel.

[0192] Please see Figure 26 The diagram shows a hardware structure of a data acquisition device 5, in which the third radar sensor 51, the fourth data interface device 52, the data processing device 53, and the fifth data interface device 54 are all mounted on a printed circuit board. The sixth data interface device 511 of the third radar sensor 51 is coupled to the fourth data interface device 52. Not shown, the third radar sensor and its peripheral circuitry are mounted on one printed circuit board, while the fourth data interface device 52, the data processing device 53, and the fifth data interface device 54 are mounted on another printed circuit board. The two printed circuit boards are coupled to the fourth data interface device 52 via the sixth data interface device 511 of the third radar sensor 51.

[0193] The third radar sensor is exemplified by the first radar sensor, second radar sensor, or sensor system described in the above examples; it includes a sixth data interface device, which is coupled to the fourth data interface device via a channel. The sixth data interface device is any of the data receiving interface devices provided in the above examples; the fourth data interface device is any of the data transmitting interface devices provided in the above examples. Examples of the fifth data interface device include, but are not limited to, at least one of the following: a USB interface, a CAN interface, and a SerDes interface.

[0194] The third radar sensor transmits measurement signals to the data processing device via a coupled sixth data interface device and a fourth data interface device. The data processing device is an electronic device that forwards or further processes any one of the digital signals provided by the fourth data interface device: baseband digital signals, measurement data, and target detection results. Examples of the data processing device include at least one programmable processor such as a CPU, MCU, DSP, and FPGA. Examples of forwarding operations include at least one of the following: converting the parallel data output by the fourth data interface device into data in at least one data format supported by the USB interface, or converting the parallel data into data in a data format supported by the CAN interface, etc. The further processing operation involves processing the received digital signals. For example, if the received digital signal is a baseband digital signal, the further processing operation includes at least one of the following: detecting interference signals in the baseband digital signal; processing the baseband digital signal to obtain measurement data including at least one of distance, speed, and angle, etc. For example, if the received digital signal is measurement data, the continued processing operations may include data processing for a single target (or multiple targets), such as vital sign information, movement information, boundary information, identification information, and interactive processing. As another example, if the received digital signal is a target detection result, the continued processing operations may include at least one of the following: interactive processing and control processing. The interactive data obtained through interactive processing is data determined for the purpose of delivering measurement data or target detection results to the user, including but not limited to at least one of the following data for the user to perceive: reminders, warnings, graphics, or sounds. The control commands obtained through control processing are information generated after processing the received measurement data or target detection results according to preset trigger conditions, used to change the operating state of other hardware systems; wherein the trigger conditions are related to the purpose of the data processing of the measurement data or target detection results.

[0195] In any of the above examples, the signal generated by the further processing operation is output by the fifth data interface device for subsequent circuit equipment to perform corresponding processing.

[0196] In one embodiment, this application also provides an electronic device configured with the aforementioned sensor system or data acquisition device, comprising: an antenna; a carrier; and the sensor system or data acquisition device as described in the above embodiments. The antenna is disposed on the carrier; or it may be a chip or integrated circuit integrated with the sensor and then disposed on the carrier (i.e., the antenna can be an antenna configured in an AiP or AoC structure). The chip or integrated circuit is connected to peripheral circuitry via a fifth data interface device (i.e., the chip or integrated circuit does not integrate an antenna and can be a SoC, etc.). The carrier can be a printed circuit board (PCB) (such as a development board, data acquisition board, or the motherboard of a device), and the printed circuit board provides channels such as PCB traces.

[0197] The electronic device, based on at least one pair of data transmission interface devices and data reception interface devices provided in the above examples, realizes the signal transmission of measurement signals between various electronic components. This achieves the purpose of interacting with the user regarding targets not located in the same spatial range; or the purpose of automatic control of the electronic device based on the detected target. For example, target detection information can be marked on a map and displayed to the user's terminal device. The map is a coordinate system used to abstractly describe the measurement spatial range, which can be displayed graphically on the terminal device, and the position, speed, etc., corresponding to the obtained target detection information are marked on the graphically displayed map interface. For another example, when abnormal information such as slowed breathing is obtained through analysis of the target detection information, interactive methods such as sound, light, and electricity can be used to remind the corresponding user to provide pre-rescue treatment. Yet another example is that when vital signs information such as breathing are obtained through analysis of target detection information within a room, the output energy or position of electronic devices within the room can be adjusted.

[0198] In some embodiments, the aforementioned electronic device may be a component or product applied in fields such as smart homes, transportation, smart homes, consumer electronics, monitoring, industrial automation, in-cabin inspection, and healthcare. For example, the device itself may be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home equipment (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It may also be various instruments for detecting vital signs parameters and various devices equipped with such instruments, such as in-cabin inspection in automobiles, indoor personnel monitoring, intelligent medical devices, and consumer electronic devices.

[0199] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0200] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application, and the scope of this application is determined by the scope of the appended claims.

Claims

1. A data interface device, characterized in that, include: An input unit is configured to be coupled to a channel to receive a first analog signal from the channel and to output a corresponding second analog signal to be converted. A sampling unit, coupled to the input unit, is used to sample the received second analog signal according to the received clock signal, so as to output a first digital signal and the clock signal; A clock recovery control unit, coupled to the sampling unit, detects the received first digital signal within a preset number of clock half-cycles and outputs a clock recovery control signal reflecting the phase deviation between the second analog signal and the clock signal; wherein, the clock recovery control signal uses a field to represent the phase value of the clock signal to be adjusted; A clock generation unit, coupled to the clock recovery control unit and the sampling unit, is used to adjust the generated clock signal according to the received clock recovery control signal and output the adjusted clock signal to the sampling unit. The output unit, coupled to the sampling unit, is used to convert the corresponding acquired first digital signal into a second digital signal under the control of the received clock signal and output it.

2. The data interface device according to claim 1, characterized in that, The input unit includes: Two signal leads are used to couple to the channel to receive a first analog signal represented by a differential signal from the channel; An equalization circuit, connected to the two signal leads, is used to perform equalization processing on the received first analog signal to output the second analog signal.

3. The data interface device according to claim 1, characterized in that, The clock recovery control unit includes: The first N-bit register is used to adjust the temporarily stored binary phase value using shift interpolation; where N is an integer greater than 1. The output circuit, connected to the N-bit first register and the clock generation unit, is used to generate the clock recovery control signal according to the binary phase value stored in the N-bit first register and output it to the clock generation unit.

4. The data interface device according to claim 3, characterized in that, The clock recovery control unit also includes: A first shift decision circuit, coupled to the sampling unit, detects the phase of the first digital signal within a preset number of half-clock cycles and outputs a control signal determined based on the number of phase detection results. A first phase adjustment circuit, coupled to the N-bit first register and the first shift decision circuit, is used to adjust the stored binary phase value from the high-order or low-order side of the N-bit first register according to the control signal.

5. The data interface device according to claim 4, characterized in that, The first shift decision circuit includes: The phase-shift detection circuit structure is coupled to the sampling unit to detect the first digital signal within a preset number of clock half-cycles to obtain phase detection data. The phase-shift control circuit structure is coupled to the phase-shift detection circuit structure and the first phase adjustment circuit. It counts the bit values ​​in the phase detection data and outputs a control signal reflecting the counting result, so that the first phase adjustment circuit can select to adjust the stored binary phase value from the high-bit side or the low-bit side of the N-bit first register.

6. The data interface device according to claim 5, characterized in that, The first phase adjustment circuit includes: The selection circuit structure is connected to the first shift decision circuit and is used to select, according to the control signal, the value of the high-order side or the low-order side in the first register for coarse adjustment, or to select the value of the high-order side or the low-order side in the first register for fine adjustment.

7. The data interface device according to claim 6, characterized in that, The selection circuit structure includes an encoder or decoder coupled to the phase shift detection circuit structure, for outputting information for the coarse or fine adjustment bit depth according to the received external instructions.

8. The data interface device according to claim 6, characterized in that, The clock recovery control unit further includes: The second shift decision circuit, coupled to the phase shift detection circuit structure and the selection circuit structure, is used to count and statistically analyze the data lead and data lag of at least one set of received phase detection data, and output a control signal for selecting coarse or fine adjustment, so that the selection circuit structure can perform the selection operation accordingly.

9. The data interface device according to claim 8, characterized in that, The second shift decision circuit includes: The judgment logic circuit structure is coupled to the phase shift detection circuit structure to perform pulse counting statistics on data leading and data lagging for at least one set of received phase detection data, and output a level signal reflecting the phase deviation amplitude obtained through multiple phase detections. A comparator, coupled to the judgment logic circuit structure and the phase shift control circuit structure, is used to compare the level signal with a preset reference level to output a control signal that includes the selection of coarse or fine adjustment.

10. The data interface device according to claim 4, characterized in that, The clock recovery control unit also includes: The M-bit second register, coupled to the output circuit, is used to store the binary phase interval value of the clock signal, so that the clock recovery control signal output by the output circuit includes the binary phase interval value and the binary phase value. The second phase adjustment circuit, coupled to the N-bit first register, the M-bit second register, and the first shift decision circuit, is used to selectively adjust the binary phase interval value in the M-bit second register according to the control logic composed of the binary phase value in the N-bit first register and the control signal.

11. The data interface device according to claim 1, characterized in that, The output unit includes a serial-to-parallel conversion circuit coupled to the sampling unit, used to convert the received first digital signal represented by a differential signal into a second digital signal represented by multiple parallel signals, and output it.

12. A sensor system, characterized in that, include: The first radar sensor includes a first data interface device; The first data interface device is used to transmit a measurement signal detected by the first radar sensor; wherein the measurement signal is used to reflect at least one of the following data: a baseband digital signal detected by the first radar sensor, at least one of the distance, velocity, and azimuth angle between the first radar sensor and the target, and target detection data of the target; The second radar sensor includes a second data interface device and a third data interface device; wherein the second data interface device is connected to the first data interface device via a channel; the second data interface device is a data interface device as described in any one of claims 1-11, used to receive the measurement signal; the third data interface device is used to forward the measurement signal.

13. The sensor system according to claim 12, characterized in that, Also includes: A data processing device, coupled to the third data interface device, is used to perform at least one data processing on the measurement signal and output corresponding target detection results, interactive data, or control commands.

14. The sensor system according to claim 12, characterized in that, The channel includes any of the following: microstrip line, coaxial cable, or optical fiber.

15. A data acquisition device, characterized in that, Includes the sensor system and data transmission interface device as described in any one of claims 12-14; the data transmission interface device is used to transmit the detected measurement signal.

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