A multi-pulse radar frequency-swept signal generation and echo acquisition system and method

Abstract

A multi-pulse radar sweep signal generation and echo acquisition system and method, implemented based on FPGA, includes a pulse parameter configuration module, a pulse signal generation module, an echo signal acquisition module, an angle analysis module, an echo data transmission module, and an Ethernet port control module; among them, the pulse parameter configuration module is used to read configuration parameters from the TF card and configure the pulse signal generation module and the echo signal acquisition module; the pulse signal generation module is used to generate pulse signals according to the configuration; the angle analysis module is used to analyze the real-time angle data of the radar antenna and send it to the echo signal acquisition module; the echo signal acquisition module is used to acquire echo data within a specified time period according to the configuration, and form a structured data packet with the time angle data and send it to the echo data transmission module; the echo data transmission module is used to send the structured data packet to the host computer; the Ethernet port control module is used to receive the control signal from the host computer and control the switch of the system.

Description

Technical Field

[0001] The present invention relates to the technical field of radar pulse signal generation and echo acquisition, and particularly relates to a multi-pulse radar sweep signal generation and echo acquisition system and method. Background Art

[0002] A radar is an electronic device that uses electromagnetic waves to detect targets. The radar emits electromagnetic waves to irradiate the target and receives its echo, thereby obtaining information such as the distance from the target to the electromagnetic wave emission point, the rate of change of distance (radial velocity), azimuth, altitude, etc. The functions of modern radars also include dynamic estimation, automatic collision avoidance, target recognition, target tracking, and radar imaging. With the rapid development of radar technology, radars have been widely used in military air defense, meteorology, traffic safety, robot navigation and other fields. Common radar systems mainly include a pulse parameter configuration module, a pulse signal generation module, an echo signal acquisition module, a motor control module, an angle analysis module, an echo data transmission module, an Ethernet port control module, an external control module of the radar system, etc. After years of development, the existing radar system technology has been relatively mature, but there are still some problems:

[0003] 1. The existing radar system cannot flexibly switch the transmitted pulse signal. Usually, it is necessary to rewrite the program or rewrite the ROM, which is difficult to operate in actual applications and takes a long time to configure;

[0004] 2. The existing radar system has a low integration level. Usually, signal transmission, echo acquisition, motor control, encoder control, angle analysis, and data transmission are all composed of independent circuit modules, which are large in volume, high in energy consumption, have large signal transmission losses between modules, each module requires a dedicated central control chip and supporting components, each module requires a dedicated developed program, each module requires separate power supply, the system failure risk points increase, and the development and maintenance costs are high;

[0005] 3. The existing radar system only transmits the processed echo data and does not send the original echo to the processor, which limits the scalability of the backend system;

[0006] 4. In the existing system, the frequency range supported by the pulse signal generation module is usually 0 - 200 MHz, with poor versatility and difficulty in adapting to different application scenarios. Summary of the Invention

[0007] The purpose of the present invention is to overcome the defects of the existing technology and propose a pulse radar sweep signal generation and echo acquisition system and method.

[0008] A multi-pulse radar sweep signal generation and echo acquisition system, implemented based on FPGA, the system includes a pulse parameter configuration module, a pulse signal generation module, an echo signal acquisition module, an angle analysis module, an echo data transmission module, and an Ethernet port control module; wherein,

[0009] The pulse parameter configuration module is used to read configuration parameters from the TF card and configure the pulse signal generation module and the echo signal acquisition module;

[0010] The pulse signal generation module is used to generate pulse signals according to the configuration;

[0011] The angle analysis module is used to analyze the angle of the radar antenna by combining the zero position switch signal and the encoder pulse signal, and send the obtained real-time angle data to the echo signal acquisition module;

[0012] The echo signal acquisition module is used to acquire echo data within a specified time period according to the configuration, and match the real-time angle data and the echo data to form a structured data packet and send it to the echo data transmission module;

[0013] The echo data transmission module is used to send the structured data packet to the host computer;

[0014] The network port control module is used to receive the control signal from the host computer and control the on / off state of the system.

[0015] As an improvement of the above system, the system further includes: a motor control module and an external control module of the radar system; wherein,

[0016] The motor control module is used to control the motor to switch speeds;

[0017] The external control module of the radar system is used to generate a power amplifier power modulation signal and a transceiver protection switch switching signal.

[0018] As an improvement of the above system, the configuration parameters include: the number of pulses n, the width t of each pulse i , whether each pulse is frequency-swept, the starting frequency of frequency sweep, the ending frequency of frequency sweep, the transmit repetition period T, the pulse digital signal, the protection duration τ, and the echo acquisition duration d of each pulse i , where the subscript i represents the i-th pulse, and 1 ≤ i ≤ n.

[0019] As an improvement of the above system, the processing process of the pulse parameter configuration module includes:

[0020] Read out the configuration parameters of each pulse in ASCII code form from the TF card in sequence, convert them to decimal, and write them into the DDR3 through the FIFO1 until all the configuration parameters of n pulses are written into the DDR3.

[0021] As an improvement of the above system, the processing process of the pulse signal generation module includes:

[0022] Read data from DDR3 into FIFO2 for caching, then read out the data from FIFO2, and after parallel-to-serial conversion, send it to the AD9739 chip to generate an analog signal in the frequency band of 0 - 1250MHz.

[0023] As an improvement to the above system, the angle resolution module uses STM32 to send a reporting angle instruction to the echo signal acquisition module; the reporting angle instruction is two-byte data, and the value is equal to the angle multiplied by 100 and rounded down.

[0024] As an improvement to the above system, the processing process of the echo signal acquisition module includes:

[0025] According to the echo acquisition duration d of each pulse i , perform 12-bit sampling;

[0026] Stitch the 12-bit sampling data to obtain several 32-bit data to form echo data, match the real-time angle data and the echo data to form a structured data packet and send it to the echo data transmission module; each 32-bit data is stitched as follows:

[0027] Stitch the 12 bits in the first clock cycle of sampling, the 12 bits in the second clock cycle, and the high 8 bits in the third clock cycle from high to low to form 32-bit data and generate a flag signal;

[0028] Stitch the low 4 bits in the third clock cycle, the 12 bits in the fourth clock cycle, the 12 bits in the fifth clock cycle, and the high 4 bits in the sixth clock cycle from high to low to form 32-bit data and generate a flag signal;

[0029] Stitch the low 8 bits in the sixth clock cycle, the 12 bits in the seventh clock cycle, and the 12 bits in the eighth clock cycle from high to low to form 32-bit data and generate a flag signal.

[0030] As an improvement to the above system, the structured data packet includes:

[0031] The first two bytes store the real-time angle data, the third and fourth bytes store the packet number, and the number increases cyclically from 1 to 36000; the 5th - 1440th bytes store 359 groups of echo data in groups of 32 bits.

[0032] As an improvement to the above system, the processing process of the network port control module includes:

[0033] Receive the control signal from the host computer;

[0034] When the control signal is 01, the control pulse signal generation module, the echo signal acquisition module, the motor control module, and the echo data transmission module stop working;

[0035] When the control signal is 02, start the motor control module to control the motor to run at a speed of 6 revolutions, and start the pulse signal generation module, the echo signal acquisition module, and the echo data transmission module;

[0036] When the control signal is 03, start the motor control module to control the motor to run at a speed of 6 revolutions, and start the pulse signal generation module, the echo signal acquisition module, and the echo data transmission module.

[0037] A method for generating multi-pulse radar sweep signals and collecting echoes is implemented based on the above system. The method includes the following steps:

[0038] Step 1) Power on the radar and initialize the system;

[0039] Step 2) The pulse parameter configuration module reads the configuration parameters from the TF card and configures the pulse signal generation module and the echo signal acquisition module; The configuration parameters include: the number of pulses n, the width t of each pulse i , whether each pulse is frequency-swept, the starting frequency of frequency sweep, the ending frequency of frequency sweep, the transmit repetition period T, the pulse digital signal, the protection duration τ, and the echo acquisition duration d of each pulse i , where the subscript i represents the i-th pulse, 1 ≤ i ≤ n;

[0040] Step 22) When the network port control module receives a control signal of 02 or 03 from the host computer, start the pulse signal generation module, the echo signal acquisition module, the motor control module, and the echo data transmission module;

[0041] Step 25) The pulse signal generation module generates 1 pulse signal according to the configuration;

[0042] Step 28) The angle analysis module analyzes the angle of the radar antenna according to the encoder pulse signal and sends the obtained real-time angle data to the echo signal acquisition module;

[0043] Step 31) The echo signal acquisition module acquires echo data within a specified time period according to the configuration, and matches the real-time angle data and the echo data to form a structured data packet and sends it to the echo data transmission module;

[0044] Step 34) The echo data transmission module sends the received structured data packet to the host computer;

[0045] Step 37) When the n pulses set by the pulse parameter configuration module have not been processed, go to Step 4), otherwise go to Step 9);

[0046] Step 9): When the control signal received by the network port control module from the host computer is 01, it ends; otherwise, it goes back to Step 4) with the period T set by the pulse parameter configuration module.

[0047] Compared with the prior art, the advantages of the present invention are as follows:

[0048] 1. The system of the present invention can quickly complete signal switching according to different application environments and user requirements, and has the advantages of small volume, low power consumption, small internal transmission loss, high integration, etc.;

[0049] 2. The present invention supports TF card configuration of pulse signals. It only needs to pull out the original card and insert a new card to flexibly switch signals. The existing solutions usually require re-programming or re-burning the ROM, which is difficult to operate and time-consuming in actual applications. With this solution, the signal switching can be completed within two seconds;

[0050] 3. The system of the present invention has a high degree of integration. Modules such as signal transmission, echo acquisition, motor control, encoder control, angle resolution, and data transmission are all integrated on one circuit board, with small volume, low energy consumption, small internal transmission loss, low cost, only requiring one power supply, and few system failure risk points;

[0051] 4. The present invention supports the transmission of original echo data and supports the matching of angle and echo data to form structured data for transmission, increasing the scalability of the system;

[0052] 5. The frequency range supported by the pulse signal generation module of the present invention is generally 0 - 1250 MHz, with strong versatility and the ability to adapt to various different application scenarios. Compared with the existing solutions, it can reduce one up-conversion processing step and improve the signal quality. Description of the Drawings

[0053] Figure 1 is the architecture diagram of the multi-pulse radar sweep signal generation and echo acquisition system of the present invention;

[0054] Figure 2 is the schematic diagram of the pulse width and echo acquisition duration of each pulse. Detailed Embodiments

[0055] The present invention provides a multi-pulse radar sweep signal generation and echo acquisition system, which includes:

[0056] A pulse parameter configuration module, used to configure various parameters in the radar system;

[0057] A pulse signal generation module, used to generate pulse signals according to the parameters;

[0058] The echo signal acquisition module is used to acquire echo data within a specified time period according to configuration parameters, match the angle and echo data to form structured data, and send it to the echo data transmission module.

[0059] The motor control module is used to control the motor to switch speeds.

[0060] The angle parsing module is used to parse the angle by combining the zero position switch signal and the encoder pulse signal.

[0061] The echo data transmission module is used to send the structured data to the host computer.

[0062] The network port control module is used to receive external control signals and control the switch state of the system.

[0063] The external control module of the radar system is used to generate the power amplifier power modulation signal and the transceiver protection switch switching signal.

[0064] The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

[0065] Embodiment 1

[0066] Embodiment 1 of the present invention proposes a multi-pulse radar sweep signal generation and echo acquisition device based on FPGA, and the overall module architecture is as Figure 1 shown.

[0067] A multi-pulse radar sweep signal generation and echo acquisition system, the FPGA chip based on is the XC7A100TFGG484-2 chip of the Artix-7 series of Xilinx Corporation;

[0068] The system includes a pulse parameter configuration module, a pulse signal generation module, an echo signal acquisition module, a motor control module, an angle parsing module, an echo data transmission module, a network port control module, and an external control module of the radar system.

[0069] The pulse parameter configuration module is used to configure each parameter in the radar system;

[0070] The pulse signal generation module is used to generate a pulse signal according to the parameters;

[0071] The echo signal acquisition module is used to acquire echo data within a specified time period according to configuration parameters, match the angle and echo data to form structured data, and send it to the echo data transmission module;

[0072] The motor control module is used to control the motor to switch speeds. The motor switch and speed control are implemented by STM32, and the motor control module communicates with the network port control module through the serial port method.

[0073] The angle parsing module is used to parse the angle by combining the zero - position switch signal and the encoder pulse signal;

[0074] The echo data transmission module is used to send the structured data to the host computer via UDP;

[0075] The network port control module is used to receive external control signals and control the switch state of the system;

[0076] The external control module of the radar system is used to generate the power modulation signal required by the power amplifier module and the external control signal required by the transceiver protection switch.

[0077] Further, for the pulse parameter configuration, the configuration parameters are read from the TF card, including the number of pulses n, the width t of each pulse i (1 ≤ i ≤ n), whether each pulse is frequency - swept, the starting frequency of frequency - sweep, the ending frequency of frequency - sweep, the transmit repetition period T, the pulse digital signal, the protection duration τ, and the echo acquisition duration d of each pulse i (1 ≤ i ≤ n).

[0078] Further, the pulse signal generation module is used to generate radar pulse signals according to the configuration parameters; after the system power - on initialization is completed, the FPGA first reads the data from the TF card in ASCII code form and converts the ASCII code value into a decimal raw value. After obtaining each raw value, it writes the data into FIFO1 once. FIFO1 is only used to cache data. Whenever data is written into FIFO1, the DDR3 read - write module synchronously issues a flag signal to read the data from FIFO1 and write it into DDR3. This process continues until all n - segment pulse data is written into DDR3.

[0079] When starting the transmission, the value M of the phase accumulator is incremented and used as the address value of DDR3 to read the data from DDR3 and write it into FIFO2 for caching.

[0080] Then, the data is read from FIFO2, passed through a parallel - to - serial conversion and sent to the DA chip to generate an analog signal. The specific process is as follows:

[0081] The FIFO2 data reading module controls the end point of FIFO2 data reading according to the pre - configured number of pulse segments. When the data segment reading is completed, the phase accumulator value of DDR3 is reset to zero, and the data is read from DDR3 again, written into FIFO2 and then sent to the DA chip to generate an analog signal. The DA module uses the AD9739 chip, which supports generating signals in the 0 - 1250MHz frequency band.

[0082] Further, the echo signal acquisition module is used to acquire radar echo data. After a pulse is generated by the pulse signal generation module, the echo acquisition module immediately starts AD sampling. Specifically: First, 12-bit sampling is performed using the AD module, and then the 12-bit data is converted into 32-bit data. The reason for converting to 32-bit data here is to make full use of the resources of the UDP network port. The specific method is to splice the 12 bits in the first clock cycle of the AD, the 12 bits in the second clock cycle, and the high 8 bits in the third clock cycle from high to low to form 32-bit data and generate a flag signal; then the low 4 bits in the third clock cycle, the 12 bits in the fourth clock cycle, the 12 bits in the fifth clock cycle, and the high 4 bits in the sixth clock cycle are spliced from high to low to form 32-bit data and generate a flag signal; then the low 8 bits in the sixth clock cycle, the 12 bits in the seventh clock cycle, and the 12 bits in the eighth clock cycle are spliced from high to low to form 32-bit data and generate a flag signal, and so on. Here, it can be found that a complete data conversion cycle is formed in 8 clock cycles and 3 32-bit data are generated.

[0083] After the 32-bit data conversion is completed, structured data packets are generated according to the following data format: 1-2 bytes of each data packet store the antenna angle data, which is obtained from the angle parsing module; 3-4 bytes store the packet number data, which increments cyclically from 1 to 36000; 5-1440 bytes store 359 groups of sampling data in groups of 32 bits.

[0084] Further, the motor control module uses STM32 to implement motor switching and speed control. Communication between STM32 and FPGA is carried out using a serial port, and the communication protocol is defined as follows:

[0085] 1) Motor start and speed setting instruction: FPGA sends 1 byte of data to STM32 through the serial port. x01 means starting the motor and setting the speed to 6 revolutions; x02 means starting the motor and setting the speed to 12 revolutions; x03 means starting the motor and setting the speed to 24 revolutions.

[0086] 2) Motor shutdown instruction: FPGA sends 1 byte of data to STM32 through the serial port. x00 means shutting down the motor.

[0087] Further, the angle parsing module uses STM32 to report the angle:

[0088] 1) Angle reporting instruction: STM32 sends two bytes of data to FPGA each time to report the angle, and the value is equal to the angle multiplied by 100 and rounded and rounded:

[0089]

[0090] Here, k represents the angle, rounded to three decimal places, and l represents the value. represents the floor function symbol.

[0091] 2) Angle value clearing instruction: The FPGA sends 1 byte of data to the STM32 through the serial port. x05 indicates clearing the angle value.

[0092] Furthermore, the echo data transmission module is used to send data packets. Data transmission supports two schemes, one is the gigabit Ethernet scheme and the other is the USB3.0 scheme. The PHY chip used for gigabit Ethernet is RTL8211EG, and the data exchange between this chip and the FPGA is realized through the RGMII interface. The UDP communication method is used in this scheme. The chip used for the USB3.0 interface is CYUSB3014-BZXI, and this chip communicates with the FPGA through 32 data pins. When using a 50M clock for communication, the theoretical rate can reach 1600Mbit / s.

[0093] Furthermore, the network port control module is responsible for controlling the switch state of the system. The system responds to the following hexadecimal control instructions on the UDP port 8811: 01 - Stop the system from working, including stopping the generation of analog signals, stopping data acquisition, stopping the pan-tilt motor, and stopping network port data transmission; 02 - Start the pan-tilt motor to run at a speed of 6 revolutions per minute, and transmit, acquire, and transmit data; 03 - Start the pan-tilt motor to run at a speed of 12 revolutions per minute, and transmit, acquire, and transmit data.

[0094] Furthermore, the external control module of the radar system is used to generate the power amplifier power modulation signal and the transceiver protection switch switching signal. Specifically, the external control signals include down-conversion power modulation and power amplifier power modulation. In the initial state of the system, both the down-conversion power modulation and the power amplifier power modulation are in the off state, which is represented as a low level in the control system.

[0095] Assume that the system starts working at time t0, and the pulse width and echo acquisition duration of each pulse are as Figure 2 shown, then the specific control process is as follows:

[0096] For the i-th (1 ≤ i ≤ n) pulse, the down-conversion power modulation signal is set to off in the time period [t i , t i + t i + τ], and the power amplifier power modulation signal is set to on in the time period [t i , t i + t i ; the down-conversion power modulation signal is in the time period (t i + t i + τ, t i + t i + d iis set to be turned off within the time period, and the power amplifier power modulation signal is at (t i + t i , t i + t i + d i is set to be turned off within the time period. Among them, t i = t0 + t1 + … t i-1 .

[0097] Embodiment 2

[0098] Embodiment 2 of the present invention proposes a method for generating a multi-pulse radar sweep signal and collecting echo signals, which is implemented based on the system of Embodiment 1. The method performs the following steps:

[0099] Step 1) At the beginning when the radar system is powered on, initialize the parameters of each peripheral chip;

[0100] Step 2) Read n segments of pulses from the TF card and write them into the FIFO, waiting for an external working control instruction;

[0101] Step 3) Generate 1 segment of pulse signal, and then receive the echo signal;

[0102] Step 4) The AD chip collects the echo signal to generate structured data for transmission;

[0103] Step 5) Repeat Step 2 and Step 3 until all n segments of pulses are processed;

[0104] Step 6) Repeat Steps 2 - 5 with a period of T until an external control signal to stop working is received.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the embodiments, those of ordinary skill in the art should understand that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A multi-pulse radar sweep signal generation and echo acquisition system, implemented based on FPGA, characterized in that, The system includes a pulse parameter configuration module, a pulse signal generation module, an echo signal acquisition module, an angle analysis module, an echo data transmission module, and an Ethernet port control module; among them, the pulse parameter configuration module is used to read configuration parameters from the TF card and configure the pulse signal generation module and the echo signal acquisition module; the pulse signal generation module is used to generate pulse signals according to the configuration; the angle analysis module is used to analyze the angle of the radar antenna by combining the zero position switch signal and the encoder pulse signal, and send the obtained real-time angle data to the echo signal acquisition module; the echo signal acquisition module is used to acquire echo data within a specified time period according to the configuration, and match the real-time angle data and the echo data to form a structured data packet and send it to the echo data transmission module; the echo data transmission module is used to send the structured data packet to the host computer; the Ethernet port control module is used to receive the control signal of the host computer and control the on / off state of the system; The configuration parameters include: the number of pulses n, the width t of each pulse i , whether each pulse is frequency-swept, the starting frequency of frequency sweep, the ending frequency of frequency sweep, the transmit repetition period T, the pulsed digital signal, the protection duration τ, and the echo acquisition duration d of each pulse i , where the subscript i represents the i-th pulse, 1 ≤ i ≤ n; the processing process of the pulse parameter configuration module includes: sequentially read the configuration parameters of each pulse in ASCII code form from the TF card, convert them to decimal, and write them into the DDR3 through FIFO1 until all the configuration parameters of n pulses are written into the DDR3; the processing process of the pulse signal generation module includes: read data from the DDR3 into FIFO2 for caching, then read the data from FIFO2, and send it to the AD9739 chip after serial-to-parallel conversion to generate an analog signal in the 0-1250 MHz frequency band; the processing process of the echo signal acquisition module includes: According to the echo acquisition duration d of each pulse i , 12-bit sampling is performed; concatenate 12-bit sampling data to obtain several 32-bit data to form echo data, match the real-time angle data and the echo data to form a structured data packet and send it to the echo data transmission module; where each 32-bit data is concatenated by the following steps: concatenate the 12 bits in the first clock cycle of sampling, the 12 bits in the second clock cycle, and the high 8 bits in the third clock cycle from high to low to form a 32-bit data and generate a flag signal; concatenate the low 4 bits in the third clock cycle, the 12 bits in the fourth clock cycle, the 12 bits in the fifth clock cycle, and the high 4 bits in the sixth clock cycle from high to low to form a 32-bit data and generate a flag signal; concatenate the low 8 bits in the sixth clock cycle, the 12 bits in the seventh clock cycle, and the 12 bits in the eighth clock cycle from high to low to form a 32-bit data and generate a flag signal; the structured data packet includes: The first and second bytes store the real-time angle data, the third and fourth bytes store the packet number, and the number increases cyclically from 1 to 36000; the fifth to 1440th bytes store 359 groups of echo data in groups of 32 bits.

2. The multi-pulse radar sweep signal generation and echo acquisition system according to claim 1, characterized in that The system further includes: a motor control module and an external control module for the radar system; among them, the motor control module is used to control the motor to switch speeds; the external control module for the radar system is used to generate a power amplifier power modulation signal and a transceiver protection switch switching signal.

3. The multi-pulse radar sweep signal generation and echo acquisition system according to claim 2, wherein, The angle analysis module uses STM32 to send an angle reporting instruction to the echo signal acquisition module; the angle reporting instruction is two-byte data, and the value is equal to the angle multiplied by 100 and rounded down.

4. The multi-pulse radar sweep signal generation and echo acquisition system according to claim 2, wherein, The processing process of the network port control module includes: Receiving the control signal from the host computer; When the control signal is 01, control the pulse signal generation module, the echo signal acquisition module, the motor control module, and the echo data transmission module to stop working; When the control signal is 02, start the motor control module to control the motor to run at a speed of 6 revolutions, and start the pulse signal generation module, the echo signal acquisition module, and the echo data transmission module; When the control signal is 03, start the motor control module to control the motor to run at a speed of 12 revolutions, and start the pulse signal generation module, the echo signal acquisition module, and the echo data transmission module.

5. A method for generating a multi-pulse radar sweep signal and collecting echoes, implemented based on the system described in any one of claims 2-4, the method comprising the following steps: Step 1) Power on the radar and initialize the system; Step 2) The pulse parameter configuration module reads the configuration parameters from the TF card and configures the pulse signal generation module and the echo signal acquisition module; The configuration parameters include: the number of pulses n, the width t of each pulse i , whether each pulse is frequency-swept, the starting frequency of frequency sweep, the ending frequency of frequency sweep, the transmit repetition period T, the pulsed digital signal, the protection duration τ, and the echo acquisition duration d of each pulse i , where the subscript i represents the i-th pulse, 1 ≤ i ≤ n; Step 3) When the network port control module receives the control signal from the host computer as 02 or 03, start the pulse signal generation module, the echo signal acquisition module, the motor control module, and the echo data transmission module; Step 4) The pulse signal generation module generates 1 pulse signal according to the configuration; Step 5) The angle analysis module analyzes the angle of the radar antenna according to the encoder pulse signal, and sends the obtained real-time angle data to the echo signal acquisition module; Step 6) The echo signal acquisition module collects the echo data within the specified time period according to the configuration, and matches the real-time angle data and the echo data to form a structured data packet and sends it to the echo data transmission module; Step 7) The echo data transmission module sends the received structured data packet to the host computer; Step 8) When the n pulses set by the pulse parameter configuration module have not been processed, go to Step 4), otherwise go to Step 9); Step 9) When the network port control module receives the control signal from the host computer as 01, end, otherwise go to Step 4) with the period T set by the pulse parameter configuration module.

Images