State management in storage-backed memory encapsulation

Abstract

The present application relates to state management in a storage backup memory package. Apparatus and techniques for state management in a storage backup memory are disclosed herein. An encoded message may be received at a first interface of a memory package. Here, the memory package also includes a second interface to a host. The message may be decoded to obtain a decoded message including an attribute. The attribute may be compared to an attribute set, the attribute set corresponding to an advertising state of the memory package. The comparison is capable of determining that the attribute is in the attribute set. Then, the advertising state of the memory package may be modified in response to the determination that the attribute is in the attribute set.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent case of the divisional application is the PCT international application with the application date of January 31, 2019 and the application number of PCT / US2019 / 016009, which entered China with the invention name of "State Management in Storage Backup Memory Encapsulation" No. 201980017544.X.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. Provisional Application No. 62 / 627,949, filed on February 8, 2018, and U.S. Patent Application No. 16 / 054,144, filed on August 3, 2018, the entire contents of which are incorporated herein by reference. Background Art

[0005] Memory devices are typically provided as internal semiconductor integrated circuits in a computer or other electronic device. There are many different types of memory, including volatile and non-volatile memory. Memory devices store data for other components. Byte-addressable memory devices can be used directly by a processor or other component to store current state data and data that is not directly connected to the current system state. Block-addressable devices (such as hard disk drives) are storage devices that cannot usually be used directly by system components to store state information. Typically, memory devices are used as middleware, where block-addressed data is loaded into the memory device before being used by the system.

[0006] Volatile memory requires power to maintain its data and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Volatile memory devices are widely deployed in computing systems. Typically, unlike storage devices that can be addressed in pages, blocks, etc., these devices are byte addressable and can therefore be accessed directly from the processor. Volatile memories like SRAM and DRAM are also fast enough to meet user expectations for device performance.

[0007] While the power dependency of volatile memory is not a problem in many situations, there are examples where loss of data (e.g., system state data, uncommitted transactions, etc.) can be a problem. In these situations, loss of power to the volatile memory can mean data corruption or an inability to diagnose the problem because evidence of the problem is lost when the volatile memory is powered off. To address these examples, various techniques have been attempted. For example, battery-backed RAM uses an auxiliary independent power source, a battery, to maintain volatile memory contents in case the main power source ceases to function. Battery-backed RAM has limited efficiency due to limited storage duration (e.g., when the battery is no longer providing power and the contents are lost).

[0008] A non-volatile dual in-line memory module (NVDIMM) combines a popular family of volatile memory package standards (DIMM) with non-volatile memory (e.g., NAND flash) to provide power-off retention of volatile memory contents for extended periods of time. The Joint Electronic Device Engineering Council (JEDEC) has promulgated several standards related to DIMMs, including a double data rate (DDR) memory interface and NVDIMMs using the DDR interface. NVDIMM-N is a family of JEDEC standards in which the DIMM includes flash memory and a controller in addition to DRAM or SRAM volatile memory. The JEDEC standard 245B.01 (JESD245B.05) for Byte Addressable Energy Backup Interface (BAEBI) provides many implementation and interaction details using the example of NVDIMMs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals indicate similar elements.

[0010] Figure 1 An example of an NVDIMM implementing state management according to some embodiments of the present invention is described.

[0011] Figure 2 An example of an environment including a system for state management in a storage backup memory enclosure according to some embodiments of the present invention is described.

[0012] Figure 3 Example component messaging used to implement state management in a storage-backed memory enclosure according to some embodiments of the present invention is described.

[0013] Figure 4 An example flow chart illustrating a method for state management in a storage backup memory enclosure according to some embodiments of the present invention.

[0014] Figure 5is a block diagram illustrating an example computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein, in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0015] The following discussion generally relates to storage backup memory packages that conform to the NVDIMM-N family of standards. However, other storage backup memory packages may also benefit from the devices and techniques described below. As described above, the NVDIMM-N device locates the NAND flash memory device on the module. The controller is also included on the module. The controller is typically an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other processing circuit system that is arranged or programmed to manage data transfer between the volatile portion of the DRAM or SDRAM of the module and the non-volatile portion of the flash memory (e.g., a storage device that backs up the DRAM or SDRAM memory). Typically, the controller is optimized for energy, space (e.g., grain size), or process (e.g., using a larger feature size) efficiency rather than for instruction cycles. The NVDIMM-N device includes two interfaces, a DDR version 4 (DDR4) memory interface that enables the host (e.g., a processor) to use the module for system memory and an inter-integrated circuit (I2C, I 2 C or IIC) bus.

[0016] I2C is a packet-switched bus that uses a two-wire connection (e.g., one wire for a clock signal and one wire for a data signal) and supports a 1 megahertz data rate. Thus, I2C provides a flexible and efficient addition to many discrete integrated circuits within a system. However, I2C is very slow when compared to a DDR4 memory interface, where I2C has a throughput of 100 or 400 kilobits per second (Kbit), and DDR4 has a data rate of between 1,600 megabits and 3,200 megabits per second (Mbit). Host communication with a controller via I2C typically involves reading and writing registers of the controller. For example, the host may issue a portion of a save command to the controller by setting the start and end address registers via I2C and actuating a save register.

[0017] Some NVDIMM-N I2C protocols (such as those defined in the BAEBI 2.1-1 standard) have implicit predicate (e.g., happens-before) requirements: if the requirements are not taken into account, then reliable correct communication becomes a problem. For example, the disaster save workflow is as follows:

[0018] 1. The host waits for the "Operation in Progress" bit in the NVDIMM_CMD_STATUS0 register to be cleared. This can be done via an I2C read poll by the host (eg, the host periodically checks the register value via the I2C interface).

[0019] 2. Next, the host sets bit 2 in the NVDIMM_MGT_CMD0 register (e.g., clears the CSAVE_STATUS register). This is a host I2C write command that clears the status register. Here, the host is not required to wait for any kind of response; meaning this is a blind write.

[0020] 3. Next, the host sets the START_CSAVE bit in the NVDIMM_FUNC_CMD register. This is another blind host I2C write because the host does not wait for a response. The controller needs to set the corresponding in-progress bit in NVDIMM_CMD_STATUS0.

[0021] 4. Next, the host checks the catastrophic save in progress bit in the NVDIMM_CMD_STATUS0 register. If this check is clear, the host checks the CSAVE_STATUS register. If the CSAVE_STATUS register does not indicate that the catastrophic save operation has completed, the host retries operation 3. The controller sets the catastrophic save in progress bit in operation 3, hopefully before the host checks that bit in operation 4. However, as described above, controllers are typically not optimized for speed and can be much slower than the host. This leads to a possible race condition where the controller is unable to set the appropriate status bit in operation 3 before the host performs operation 4. Because the controller has not yet modified the in progress bit, the host misinterprets the register value in operation 4 as the controller completing the catastrophic save, when in fact the controller has not even had time to modify the status to indicate that it has started the operation. This misinterpretation of the controller status by the host can lead to several operational failures, such as the host not retrying a failed operation.

[0022] Aspects of the present invention relate to state management in a storage backup memory or memory subsystem (e.g., a "memory device"). An example of a memory subsystem is a storage system, such as a solid state drive (SSD). In some embodiments, the memory subsystem is a hybrid memory / storage subsystem. In general, a host system may utilize a memory subsystem that includes one or more memory components. The host system may provide data to be stored at the memory subsystem and may request data to be retrieved from the memory subsystem.

[0023] To address the race condition issue, the controller's I2C bus interface is modified to inspect (e.g., snoop) the host's message and determine whether the packet involves an operation corresponding to an advertising status indication (e.g., a status indication that can be read outside the storage backup memory package). The modification may be in a decoder for the I2C bus interface. If the message corresponds to an operation corresponding to the advertising status indication (e.g., the catastrophic save and corresponding register bits described above), the I2C bus interface sets the advertising status indication and provides the message to the controller. The controller then operates as usual, including clearing the advertising status indication when the controller completes the operation. This arrangement prevents race conditions by setting a "busy bit" for a select operation before the host can re-read (e.g., test) the advertising status indication, regardless of the speed at which the controller engages in completing the operation. Additional details and examples are described below.

[0024] Figure 1 An example of an NVDIMM 110 implementing state management according to some embodiments of the present invention is described. In the example, the NVDIMM 110 complies with the JEDEC NVDIMM-N standard series. The NVDIMM 110 includes a controller 125, a volatile storage portion 130, a non-volatile storage portion 145, a first interface 120 (e.g., an I2C bus), and a second interface 115 (e.g., a DDR interface). The volatile portion 130 includes one or more DRAM or SRAM integrated circuits (ICs) to store data for read or write operations by the host 105 via the second interface 115. The non-volatile storage portion 145 can be implemented with any storage technology that does not require power to maintain state. Example non-volatile storage technologies can include NAND flash, NOR flash, storage class memory (e.g., phase change memory), magnetic memory, and the like.

[0025] The first interface 120 is typically used by the host 105 to communicate directly with the controller 125 to perform various operations. The controller 125 is arranged to implement these operations within the NVDIMM 110. The controller 125 is implemented as electronic hardware, such as an FPGA, ASIC, digital signal processor (DSP), or other processing circuit system, such as the example of the state control component 113 described herein. In an example, the controller executes instructions (e.g., firmware) on the electronic hardware to perform operations. This is Figure 5 Another example of a state control component 113 is illustrated in FIG. The BAEBI series of standards defines several operations performed by compliant devices.

[0026] When the first interface 120 is an I2C bus, typical communications involve the host 105 setting registers in the controller 125 via the first interface 120. For example, the host 105 may set a particular register so that a particular bit in the register changes from 0 to 1. When this bit value change corresponds to the execution of a command, the controller 125 executes the command in response to the bit modification. If the command has arguments, the host 105 may set registers corresponding to the arguments. In this case, the controller 125 is arranged to check these argument registers to retrieve data to complete the command.

[0027] As described above, because the host 105 may be implemented in a very fast processor, and the controller 125 is not optimized for speed, a race condition may occur where the host 105 (which periodically reads the advertised value (e.g., a register or portion of a register) to determine whether a command has completed, attempts to read the advertised status after the command has been called but before the controller 125 sets the advertised status in response to the command call. Here, the controller 125 is not fast enough to set the expected value of the advertised value before the host 105 performs the first check. When this occurs, the host 105 operates as if the command is complete, when in fact the controller 125 has not even started.

[0028] To address the race condition issue, the controller 125 is arranged to receive an encoded message through the first interface 120 (e.g., at a decoder 135 of the controller 125). In the case where the first interface 120 operates according to the I2C family of standards, the message encoding is an I2C marketing of the message. The decoder 135 is arranged to obtain a decoded message comprising an attribute. In an example, the attribute is the name of the command. The command name may be in the payload of the packetized message. In an example, the attribute is an address. The address may be in the header of the packetized message. In an example, the address is a page specifier. In an example, the address comprises both a page specifier and an offset.

[0029] The decoder 135 or the controller 125 is arranged to compare the attribute with the attribute set corresponding to the advertising state of the memory package to determine whether the attribute is in the attribute set. Here, the advertising state means the state of the NVDIMM 110 that can be observed outside the NVDIMM 110. For example, a status bit (e.g., a "busy bit") or a register that can be read by the host 105 is the advertising state. In an example, the advertising state indicates to the controller 125 whether there is an ongoing operation. In an example, the advertising state indicates the type of the ongoing operation.

[0030] The comparison of the attribute to the attribute set may be implemented in several ways. In an example, the attribute set is stored in a table 140 or other data structure. Here, the decoder 135 or controller 125 is arranged to match the attribute to a record in the table 140 to determine if the attribute is in the attribute set. If there is no match, then the attribute does not correspond to the advertised state of the NVDIMM 110. In an example, the attribute set is defined by the JEDEC BAEBI family of standards, such as the JESD245B.01 standard.

[0031] In an example, the attribute set has a single member corresponding to page 0. In an example, the member of the attribute set is an address with a page specifier of 0 and an offset of 1 corresponding to NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the Joint Electronic Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) JESD245B.01 standard. Therefore, these commands are identified by the decoder 135 or the controller 125 by the offset in the command address of the host because all of these commands are on page 0. Therefore, the table 140 can be a list of the offsets corresponding to these commands.

[0032] Once the decoder 135 or controller 125 determines that the command sent from the host 105 corresponds to an advertising state (e.g., an "in operation" indication), the advertising state is set. In an example, the advertising state is modified before the decoder 135 provides the decoded message to the components of the controller 125. This ensures that the advertising state is modified (e.g., correctly set) before anything else is done, thereby ensuring the fastest response from the controller 125 when setting the advertising state. In an example, the advertising state is provided to the controller 125 at the same time as the decoded message content. Here, if the decoder 135 only sets the controller register based on the message, then the advertising state register is set at the same time as the register specified in the message. In this context, at the same time means that the difference in register writes is not perceptible to an observer (e.g., the host 105 or controller 125), even if one register may actually be written before the other register.

[0033] In an example, the advertising state is modified by setting a register. In an example, setting the register includes setting exactly one bit in the register. In this example, the register may be first read by the host 105, modifying the desired bit, and writing back the complete register. In an example, exactly two bits in the register are modified to set the advertising state. In an example, setting exactly one bit indicates that an operation is in progress. In an example, setting exactly two bits indicates that an operation is in progress (one of the two bits) and an operation designation (the second of the two bits). Here, the operation designation is the type of operation, such as a command name, a command series, etc. In an example, the register has an address of one of page 0-offset 0x61 or page 0-offset 0x62.

[0034] NVDIMM 110 may optionally include a power supply 150 that is separate from the host power. Power supply 150 may be incorporated into the NVDIMM package, or connected to the NVDIMM package (as illustrated). In the event of a host power failure, power supply 150 may provide power to enable controller 125 to move data from volatile portion 130 to non-volatile portion 145.

[0035] The controller 125 or decoder 135 described above solves the race condition problem existing in the storage backup memory packaging used in today's systems, including Figure 2 By removing the controller 125 delay when executing firmware to set the advertising status, and, for example, building an attribute to advertising status check into the decoder 135, the NVDIMM 110 ensures that the advertising status is set before the host 105 can attempt to read the advertising status for the first time.

[0036] Figure 2 An example of an environment 200 including a system for state management in a storage backup memory package 210 according to some embodiments of the present invention is illustrated. The environment 200 includes a host device 205 and a storage backup memory package 210. The host device 205 or the storage backup memory package 210 may be included in various products 250, such as a data center server, a personal computer, or an Internet of Things (IoT) device (e.g., a refrigerator or other equipment, a sensor, an engine or actuator, a mobile communication device, a car, a drone, etc.) to support processing, communication, or control of the product 250. The system may be a storage backup memory package 210 or a component of the storage backup memory package 210, such as an on-package controller 225. The system may also include a memory controller 220 or a processor 215 of the host device 205.

[0037] One or more communication interfaces may be used to transfer data between storage backup memory package 210 and one or more other components of host device 205 (e.g., processor 215). In an example, DDR4 is an implementation communication interface. In an example, I2C is an implementation communication interface. Host device 205 may include a host system, an electronic device, a memory card reader, or one or more other electronic devices external to storage backup memory package 210. In some examples, host 205 may be a host computer with a reference Figure 5 The machine 500 may include some or all of the components discussed above.

[0038] The processor 215, which may be referred to as the host, generally directs or coordinates the activities of the host device 205 and the components included therein. The memory controller 220 supports the memory activities of the components of the host device 205, including the use of the storage backup memory package 210. The memory controller 220 may provide data addressing and command coordination for the storage backup memory package 210. These activities may include data transfer to (e.g., writing or erasing) or from (e.g., reading) one or more of the chips, hierarchies, or banks of the volatile portion of the storage backup memory package 210. The memory controller 215 may include, among other things, circuitry or firmware, including one or more components or integrated circuits. For example, the memory controller 215 may include one or more memory control units, circuits, or components configured to control access across the storage backup memory package 210 and provide a translation layer between the host 205 and the storage backup memory package 210. Memory controller 215 may include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from storage backup memory enclosure 210 .

[0039] Memory controller 215 may include, among other things, circuitry or firmware, such as a number of components or integrated circuits (e.g., state management component 113) associated with various memory management functions (e.g., defragging or state management techniques described herein). Memory controller 215 may parse or format host commands (e.g., commands received from a host) into device commands (e.g., commands associated with operation of a memory array, etc.), or generate device commands for storage backup memory package 210 or one or more other components of storage backup memory package 210 (e.g., to accomplish various memory management functions).

[0040] The memory controller 215 may include, among other things, circuitry or components configured to control memory operations associated with writing data to, reading data from, or erasing one or more memory cells of the storage backup memory package 210. For example, memory operations may be based on host commands (e.g., in conjunction with erasing fragments, error correction, refreshing, etc.) received from the host 205 or generated internally by the memory controller 215. The memory controller 215 may include code or logic to communicate using a standardized protocol (or features from a standardized protocol), such as GDDR6.

[0041] In addition to volatile memory (e.g., DRAM or SRAM) and a non-volatile portion (e.g., flash memory), the storage backup memory package 210 may also include an on-package controller 225. The storage backup memory package 210 may also include an on-board or external power source 230, such as an electric double layer capacitor (e.g., ELDC, supercapacitor, ultracapacitor, ultracapacitor, etc.), a battery, etc. The power source 230 may be independent of other host power sources and enable the on-package controller 225 to transfer data from the volatile portion of the storage backup memory package 210 to the non-volatile portion of the storage backup memory package 210 when the host power fails. The on-package controller 225 may also move data from the non-volatile portion to the volatile portion (e.g., when the host power is restored) or directly provide access to the non-volatile portion. This last capability may enable greater error analysis during a host crash, for example, compared to standard system memory devices.

[0042] Figure 3 Example component messaging for implementing state management in a storage backup memory package according to some embodiments of the present invention is described. The host, decoder, and controller components described are similar to those described above. In the example, the decoder is an I2C bus interface of the controller. In this example, the illustrated message flow distinguishes the decoder portion of the controller from other portions of the controller, such as portions that execute firmware to perform other actions.

[0043] Typically, the race condition solution involves the hardware setting the "operation in progress" bit immediately after receiving the I2C command. The controller will clear the bit when it has completed the operation in question.

[0044] The host writes to a specific command register to communicate to the controller (message 305). The decoder decodes the I2C packet (operation 310), matches the packet attributes to the list to determine that the command involves an "operation in progress" status register bit (operation 315) and preemptively sets the appropriate bit in the corresponding status register (operation 320). In an example, setting the appropriate bit includes setting a busy bit (e.g., bit 0) and the appropriate status bit. For example, according to the JEDEC BAEBI standard:

[0045] NVDIMM_FUNC_CMD[x43], ARM_CMD[x45], FIRMWARE_OPS_CMD[x4A], OPERATIONAL_UNIT_OPS_CMD[x4B]→NVDIMM_CMD_STATUS1[x62]; or

[0046] ES_FUNC_CMD0[0x30]→ES_CMD_STATUS0[0x50]

[0047] Once the status bit is set, a command is given by the rest of the controller (message 325). In the example, this requires setting the status bit as well as the register specified in the I2C data packet. In this example, the decoder can signal the rest of the controller with an interrupt, or the controller can just poll the register for changes.

[0048] Once control has moved from the decoder to the controller, the controller executes the command (operation 330), including setting the correct status bits during or after the command is completed.

[0049] The message transmission and control flow described here solves the timing problem between the host and the controller, which can lead to unexpected results in various operations. Some NVDIMM operations are critical, and the host and controller need them to comply with the JEDEC BAEBI standard. In these operations, the host can issue a command (e.g., through an I2C interface) and check the status register bit to determine when the command is completed. However, the BAEBI standard does not specify the timing between command reception and setting the status register (e.g., the maximum completion time). In some situations, the controller does not have time to set the bit before the host sees the bit.

[0050] This problem is solved by the described flow. The decoder sets the status register bits based on the incoming request without waiting for the controller (e.g., firmware running on the controller) to do so. In a sense, the decoder "snoops" the incoming command to determine which status register bit (if any) should be set. Once the decoder observes a particular command, the decoder sets the corresponding "I am busy bit". Because the BAEBI standard specifies a memory image of memory pages (e.g., register locations) that the controller needs to implement, the decoder can perform snooping by matching the incoming address (e.g., register and page offset within the register) with a list of addresses of commands with status bits. If the memory address matches a table entry, then it has a status bit. For example, page address 0 and page offset 43 identify NVDIMM_FUNC_CMD. In an example, the data (e.g., payload) of the I2C packet may have additional information that can be used for other status bits.

[0051] In an example, the lookup table is a register in the decoder (eg, when implemented as an ASIC, the table is within the ASIC). In an example, the lookup table is in a memory shared with the controller.

[0052] Figure 4 An example flow chart illustrating a method 400 for state management in a storage backup memory package according to some embodiments of the present invention. The operations of the method 400 are implemented in electronic hardware, such as described above with respect to Figures 1 to 2 And below about Figure 5 Electronic hardware (eg, in a circuit system) is described.

[0053] At operation 405, an encoded message is received at a first interface of a memory package. Here, the memory package also includes a second interface to a host. In an example, the first interface is a bus operating according to the I2C family of standards. In an example, the second interface is a DDR (e.g., DDR4) RAM interface. In an example, the memory package is an NVDIMM. In an example, the NVDIMM is an NVDIMM-N type according to the JEDEC family of standards.

[0054] In operation 410, the message is decoded to obtain a decoded message including an attribute. In an example, the attribute is a name of a command. In an example, the attribute is an address. In an example, the address is a page specifier. In an example, the address includes both a page specifier and an offset.

[0055] At operation 415, the attribute is compared to an attribute set corresponding to the advertising state of the memory package to determine if the attribute is in the attribute set. In an example, the advertising state indicates whether there is an ongoing operation of the memory controller. In an example, the advertising state also indicates the type of the ongoing operation.

[0056] In an example, the attribute set is stored in a table. Here, comparing an attribute to an attribute set involves matching the attribute to a record in the table to determine if the attribute is in the attribute set. In an example, the attribute set is defined by the JEDEC BAEBI family of standards. In an example, the JEDEC BAEBI family of standards includes the JESD245B.01 standard.

[0057] In an example, the attribute set has a single member corresponding to page 0. In an example, the member of the attribute set is an address with page specifier 0 and offset 1 corresponding to NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the JEDEC BAEBI JESD245B.01 standard. In an example, the attribute set has a single member corresponding to page 1 (e.g., page 1 hosts energy health checks). In an example, the member of the attribute set is an address with page specifier 1 and offset 1 corresponding to ES_FUNC_CMD0.

[0058] At operation 420, the advertising state of the memory package is modified in response to a determination that the attribute is in the attribute set. In an example, the modification of the advertising state of the memory package occurs before a decoder of a memory controller included in the non-volatile memory package provides a decoded message to a component of the memory controller.

[0059] In an example, modifying the advertising state of the memory package includes setting a register of the memory package. In an example, setting the register includes setting exactly one bit or exactly two bits in the register. In an example, one bit is set to indicate that an operation is in progress. In an example, two bits are set to indicate both that an operation is in progress and that the operation specifies. In an example, the register being set has an address of one of: page 0-offset 0x61 or page 0-offset 0x62.

[0060] Figure 5A block diagram of an example machine 500 on which any one or more of the techniques (e.g., methodology) discussed herein may be executed is described. In alternative embodiments, the machine 500 may be operated as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 500 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, the machine 500 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 500 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, an IoT device, an automotive system, or any machine capable of (sequentially or otherwise) executing instructions specifying actions to be taken by the machine. In addition, although only a single machine is described, the term "machine" should also be deemed to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0061] As described herein, an example may include logic, components, devices, packages, or mechanisms, or may be operated by logic, components, devices, packages, or mechanisms. A circuit system (e.g., a circuit set, a processing circuit system, etc.) is a circuit set (e.g., a group of circuits) implemented in a tangible entity that includes hardware (e.g., simple circuits, gates, logic, etc.). Circuit system membership may be flexible over time and underlying hardware variability. A circuit system includes members that can perform specific tasks individually or in combination when in operation. In an example, the hardware of the circuit system may be constantly designed to perform a specific operation (e.g., hard wiring). In an example, the hardware of the circuit system may include variably connected physical components (e.g., execution units, transistors, simple circuits, etc.), including a computer-readable medium that is physically modified (e.g., magnetic, electrical, removable placement, etc., of particles of constant mass, etc.) to encode instructions for the specific operation. In connecting physical components, the underlying electrical properties of the hardware composition (e.g.,) are changed from insulators to conductors or vice versa. The instructions enable participating hardware (e.g., an execution unit or a load mechanism) to generate a member of a circuit system in hardware via a variable connection to perform a portion of a specific task in operation. Thus, when the device operates, the computer-readable medium is communicatively coupled to other components of the circuit system. In an example, any of the physical components can be used in more than one member of more than one circuit system. For example, in operation, an execution unit can be used in a first circuit of a first circuit system at one point in time and reused by a second circuit in the first circuit system or by a third circuit in the second circuit system at a different time.

[0062] The machine (e.g., computer system) 500 may include a hardware processor 502 (e.g., a CPU, a GPU, a hardware processor core, or any combination thereof), a main memory 504, and a static memory 506, some or all of which may communicate with each other via an interconnect (e.g., a bus) 508. The machine 500 may further include a display unit 510, an alphanumeric input device 512 (e.g., a keyboard), and a user interface (UI) navigation device 514 (e.g., a mouse). In an example, the display unit 510, the input device 512, and the UI navigation device 514 may be a touch screen display. The machine 500 may additionally include a signal generating device 518 (e.g., a speaker), a network interface device 520, and one or more sensors 516, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 500 may include an output controller 528, such as a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection for communicating or controlling one or more peripheral devices (e.g., printer, card reader, etc.).

[0063] The machine 500 may include one or more machine-readable media 522 on which one or more sets of data structures or instructions 524 (e.g., software) are stored that implement or are utilized by any one or more of the techniques or functions described herein, such as the state control component 113. The machine-readable medium 522 may include one or more of the following: a main memory 524, a static memory 506, and a mass storage device 521. The instructions 524 may reside completely or at least partially within the main memory 504, the static memory 506, the mass storage device 521, or the hardware processor 502 during execution by the machine 500. In an example, one or any combination of the hardware processor 502, the main memory 504, the static memory 506, or the mass storage device 521 may constitute the machine-readable medium 522.

[0064] Although machine-readable medium 522 is illustrated as a single medium, the term “machine-readable medium” may include a single medium or multiple media (eg, a centralized or distributed database, or associated caches and servers) configured to store one or more instructions 524 .

[0065] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions that are executed by the machine 500 and cause the machine 500 to perform any one or more of the techniques of the present invention, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memory, optical, and magnetic media. In an example, a massed machine-readable medium includes a machine-readable medium having a plurality of particles with a constant (e.g., stationary) mass. Thus, a massed machine-readable medium is not a transient propagating signal. Specific examples of massed machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM, EEPROM) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0066] Instructions 524 (e.g., software, programs, operating system (OS), etc.) or other data are stored on mass storage device 521 and can be accessed through memory 504 for use by processor 502. Memory 504 (e.g., DRAM) is typically fast but volatile, and therefore different from the type of storage of mass storage device 521 (e.g., SSD), which is suitable for long-term storage (including when in the "off" state). Instructions 524 or data used by the user or machine 500 are typically loaded into memory 504 for use by processor 502. When memory 504 is full, virtual space from mass storage device 521 can be allocated to supplement memory 504; however, because mass storage device 521 is typically slower than memory 504, and the write speed is typically at least 1 / 2 the read speed, the use of virtual memory can greatly reduce the user experience due to storage device latency (compared to memory 504, such as DRAM). Furthermore, using the mass storage device 521 for virtual storage may significantly reduce the usable lifespan of the mass storage device 521 .

[0067] Compared to virtual memory, virtual memory compression (e.g. The kernel feature "ZRAM") uses portions of memory as compressed block storage to avoid paging to mass storage 521. Paging occurs in compressed blocks until the data must be written to mass storage 521. Virtual memory compression increases the available size of memory 504 while reducing wear on mass storage 521.

[0068] Storage devices optimized for mobile electronic devices or mobile storage devices traditionally include MMC solid-state storage devices (e.g., micro Secure Digital (microSD TM) card, etc.). MMC devices include several parallel interfaces (e.g., 8-bit parallel interfaces) to connect to a host device, and are typically components that can be removed and separated from the host device. In contrast, eMMC TM The device is attached to the circuit board and is considered a component of the host device, which has a TM (Serial AT (Advanced Technology) Attachment, or SATA) SSD devices. However, the demand for mobile device performance continues to increase, such as fully enabling virtual or augmented reality devices, taking advantage of increased network speeds, and the like. In response to this demand, storage devices have transitioned from parallel communication interfaces to serial communication interfaces. Universal Flash Storage (UFS) devices (including controllers and firmware) communicate with host devices using a low voltage differential signaling (LVDS) serial interface with dedicated read / write paths, thereby further achieving greater read / write speeds.

[0069] The instructions 524 may be further transmitted or received over a communication network 526 using a transmission medium via a network interface device 520 utilizing any of a number of transmission protocols (e.g., frame relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards (known as ), IEEE 802.16 series of standards (called ), IEEE 802.15.4 family of standards), peer-to-peer (P2P) networks, and the like. In an example, network interface device 520 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 526. In an example, network interface device 520 may include multiple antennas to wirelessly communicate using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" shall be deemed to include any intangible medium capable of storing, encoding, or carrying instructions executed by machine 500, and includes digital or analog communication signals or other intangible media that facilitate communication of such software.

[0070] Additional examples:

[0071] Example 1 is a memory package for state management in a storage backup memory package, the memory package comprising: a volatile portion; a non-volatile portion; a first interface for receiving an encoded message; a second interface for communicating with a host; and a decoder of the first interface, the decoder being used to: decode the message to obtain a decoded message containing an attribute; compare the attribute with an attribute set to determine that the attribute is in the attribute set, the attribute set corresponding to an advertising state of the memory package; and modify the advertising state of the memory package in response to a determination that the attribute is in the attribute set.

[0072] In Example 2, the subject matter of Example 1 includes, wherein the first interface is a bus operating according to the I2C family of standards.

[0073] In Example 3, the subject matter of Examples 1-2 includes, wherein the second interface is a double data rate (DDR) random access memory (RAM) interface.

[0074] In Example 4, the subject matter of Example 3 includes, wherein the memory package is a non-volatile dual in-line memory module (NVDIMM).

[0075] In Example 5, the subject matter of Example 4 includes, wherein the NVDIMM is a NVDIMM-N type according to the Joint Electron Device Engineering Council (JEDEC) standard family.

[0076] In Example 6, the subject matter of Examples 1-5 includes a memory controller wherein the decoder is used to modify an advertising state of a memory package before the decoder provides a decoded message to a component of the memory controller.

[0077] In example 7, the subject matter of examples 1-6 includes, wherein to modify the advertising state of the memory package, the decoder sets a register of the memory package.

[0078] In Example 8, the subject matter of Example 7 includes, wherein to set the register, the decoder sets exactly one bit in the register or exactly two bits in the register, wherein the one bit indicates an operation in progress and the two bits indicate both that an operation is in progress and that the operation is specified.

[0079] In Example 9, the subject matter of Examples 7-8 includes, wherein the register has an address of one of Page 0 - Offset 0x61 or Page 0 - Offset 0x62.

[0080] In Example 10, the subject matter of Examples 1-9 includes a memory controller, wherein the advertisement status indicates whether the memory controller has an ongoing operation.

[0081] In example 11, the subject matter of example 10 includes, wherein the advertisement status further indicates a type of operation in progress.

[0082] In Example 12, the subject matter of Examples 1-11 includes, wherein the attribute set is defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

[0083] In Example 13, the subject matter of Example 12 includes, wherein the JEDEC BAEBI family of standards includes the JESD245B.01 standard.

[0084] In example 14, the subject matter of examples 1 to 13 includes, wherein the attribute is the name of the command.

[0085] In example 15, the subject matter of examples 1 to 14 includes, wherein the attribute is an address.

[0086] In Example 16, the subject matter of Example 15 includes, wherein the address is a page specifier.

[0087] In Example 17, the subject matter of Example 16 includes, wherein the attribute set has a single member corresponding to page 0.

[0088] In Example 18, the subject matter of Examples 15-17 includes, wherein the address includes both a page specifier and an offset.

[0089] In Example 19, the subject matter of Example 18 includes, wherein a member of the attribute set is an address having a page specifier of 0 and an offset of 1 corresponding to an NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) JESD245B.01 standard.

[0090] In Example 20, the subject matter of Examples 1-19 includes, wherein the attribute set is stored in a table, and wherein comparing the attribute to the attribute set includes matching the attribute to a record in the table to determine that the attribute is in the attribute set.

[0091] Example 21 is a method for state management in a storage backup memory encapsulation, the method comprising: receiving an encoded message at a first interface of the memory encapsulation, the memory encapsulation comprising a second interface to a host; decoding the message to obtain a decoded message comprising an attribute; comparing the attribute with an attribute set to determine that the attribute is in the attribute set, the attribute set corresponding to an advertising state of the memory encapsulation; and modifying the advertising state of the memory encapsulation in response to a determination that the attribute is in the attribute set.

[0092] In Example 22, the subject matter of Example 21 includes, wherein the first interface is a bus operating according to the I2C family of standards.

[0093] In Example 23, the subject matter of Examples 21-22 includes, wherein the second interface is a double data rate (DDR) random access memory (RAM) interface.

[0094] In Example 24, the subject matter of Example 23 includes, wherein the memory package is a non-volatile dual in-line memory module (NVDIMM).

[0095] In Example 25, the subject matter of Example 24 includes, wherein the NVDIMM is a NVDIMM-N type according to the Joint Electron Device Engineering Council (JEDEC) standard family.

[0096] In Example 26, the subject matter of Examples 21-25 includes, wherein modifying the advertising state of the memory package occurs before a decoder of a memory controller included in the non-volatile memory package provides a decoded message to a component of the memory controller.

[0097] In example 27, the subject matter of examples 21-26 includes, wherein modifying the advertising state of the memory package includes setting a register of the memory package.

[0098] In Example 28, the subject matter of Example 27 includes, wherein setting the register includes setting exactly one bit in the register or exactly two bits in the register, wherein the one bit indicates an operation in progress and the two bits indicate both that an operation is in progress and that the operation is specified.

[0099] In Example 29, the subject matter of Examples 27-28 includes, wherein the register has an address of one of Page 0 - Offset 0x61 or Page 0 - Offset 0x62.

[0100] In example 30, the subject matter of examples 21-29 includes, wherein the advertising status indicates whether a memory controller included in the non-volatile memory package has an ongoing operation.

[0101] In example 31, the subject matter of example 30 includes, wherein the advertisement status further indicates a type of operation in progress.

[0102] In Example 32, the subject matter of Examples 21-31 includes, wherein the attribute set is defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

[0103] In Example 33, the subject matter of Example 32 includes, wherein the JEDEC BAEBI family of standards includes the JESD245B.01 standard.

[0104] In instance 34, the subject matter of instances 21 to 33 includes, wherein the attribute is the name of the command.

[0105] In example 35, the subject matter of examples 21 to 34 includes, wherein the attribute is an address.

[0106] In example 36, the subject matter of example 35 includes, wherein the address is a page specifier.

[0107] In Example 37, the subject matter of Example 36 includes, wherein the attribute set has a single member corresponding to page 0.

[0108] In Example 38, the subject matter of Examples 35-37 includes, wherein the address includes both a page specifier and an offset.

[0109] In Example 39, the subject matter of Example 38 includes, wherein a member of the attribute set is an address having a page specifier of 0 and an offset of 1 corresponding to an NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) JESD245B.01 standard.

[0110] In example 40, the subject matter of examples 21-39 includes, wherein the attribute set is stored in a table, and wherein comparing the attribute to the attribute set includes matching the attribute to a record in the table to determine that the attribute is in the attribute set.

[0111] Example 41 is at least one machine-readable medium comprising instructions for storing state management in a backup memory package, which instructions, when executed by a processing circuit system or a memory package, cause the memory package to perform operations including: receiving an encoded message at a first interface of the memory package, the memory package including a second interface to a host; decoding the message to obtain a decoded message including an attribute; comparing the attribute to an attribute set to determine that the attribute is in the attribute set, the attribute set corresponding to an advertising state of the memory package; and modifying the advertising state of the memory package in response to a determination that the attribute is in the attribute set.

[0112] In Example 42, the subject matter of Example 41 includes, wherein the first interface is a bus operating according to the I2C family of standards.

[0113] In Example 43, the subject matter of Examples 41-42 includes, wherein the second interface is a double data rate (DDR) random access memory (RAM) interface.

[0114] In Example 44, the subject matter of Example 43 includes, wherein the memory package is a non-volatile dual in-line memory module (NVDIMM).

[0115] In Example 45, the subject matter of Example 44 includes, wherein the NVDIMM is a NVDIMM-N type according to the Joint Electron Device Engineering Council (JEDEC) standard family.

[0116] In Example 46, the subject matter of Examples 41-45 includes, wherein modifying the advertising state of the memory package occurs before a decoder of a memory controller included in the non-volatile memory package provides a decoded message to a component of the memory controller.

[0117] In example 47, the subject matter of examples 41-46 includes, wherein modifying the advertising state of the memory package includes setting a register of the memory package.

[0118] In Example 48, the subject matter of Example 47 includes, wherein setting the register includes setting exactly one bit in the register or exactly two bits in the register, wherein the one bit indicates an operation in progress and the two bits indicate both that an operation is in progress and that the operation is specified.

[0119] In Example 49, the subject matter of Examples 47-48 includes, wherein the register has an address of one of Page 0 - Offset 0x61 or Page 0 - Offset 0x62.

[0120] In example 50, the subject matter of examples 41-49 includes, wherein the advertising status indicates whether there is an ongoing operation of a memory controller included in the non-volatile memory package.

[0121] In example 51, the subject matter of example 50 includes, wherein the advertisement status further indicates a type of operation in progress.

[0122] In example 52, the subject matter of examples 41-51 includes, wherein the attribute set is defined by a Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

[0123] In Example 53, the subject matter of Example 52 includes, wherein the JEDEC BAEBI family of standards includes the JESD245B.01 standard.

[0124] In instance 54, the subject matter of instances 41 to 53 includes, wherein the attribute is the name of the command.

[0125] In instance 55, the subject matter of instances 41 to 54 includes, wherein the attribute is an address.

[0126] In example 56, the subject matter of example 55 includes, wherein the address is a page specifier.

[0127] In example 57, the subject matter of example 56 includes, wherein the attribute set has a single member corresponding to page 0.

[0128] In Example 58, the subject matter of Examples 55-57 includes, wherein the address includes both a page specifier and an offset.

[0129] In Example 59, the subject matter of Example 58 includes, wherein a member of the attribute set is an address having a page specifier of 0 and an offset of 1 corresponding to an NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) JESD245B.01 standard.

[0130] In example 60, the subject matter of examples 41-59 includes, wherein the attribute set is stored in a table, and wherein comparing the attribute to the attribute set includes matching the attribute to a record in the table to determine that the attribute is in the attribute set.

[0131] Example 61 is a system for state management in a storage backup memory package, the system comprising: a component for receiving an encoded message at a first interface of the memory package, the memory package including a second interface to a host; a component for decoding the message to obtain a decoded message including an attribute; a component for comparing the attribute with an attribute set to determine that the attribute is in the attribute set, the attribute set corresponding to an advertising state of the memory package; and a component for modifying the advertising state of the memory package in response to a determination that the attribute is in the attribute set.

[0132] In Example 62, the subject matter of Example 61 includes, wherein the first interface is a bus operating according to the I2C family of standards.

[0133] In Example 63, the subject matter of Examples 61-62 includes, wherein the second interface is a double data rate (DDR) random access memory (RAM) interface.

[0134] In Example 64, the subject matter of Example 63 includes, wherein the memory package is a non-volatile dual in-line memory module (NVDIMM).

[0135] In Example 65, the subject matter of Example 64 includes, wherein the NVDIMM is a NVDIMM-N type according to the Joint Electron Device Engineering Council (JEDEC) standard family.

[0136] In Example 66, the subject matter of Examples 61-65 includes, wherein modifying the advertising state of the memory package occurs before a decoder of a memory controller included in the non-volatile memory package provides the decoded message to a component of the memory controller.

[0137] In example 67, the subject matter of examples 61-66 includes, wherein the means for modifying the advertising state of the memory package includes means for setting a register of the memory package.

[0138] In Example 68, the subject matter of Example 67 includes, wherein the means for setting the register includes means for setting exactly one bit in the register or exactly two bits in the register, wherein the one bit indicates an operation in progress and the two bits indicate both that an operation is in progress and that the operation is specified.

[0139] In Example 69, the subject matter of Examples 67-68 includes, wherein the register has an address of one of Page 0 - Offset 0x61 or Page 0 - Offset 0x62.

[0140] In example 70, the subject matter of examples 61-69 includes, wherein the advertising status indicates whether a memory controller included in the non-volatile memory package has an ongoing operation.

[0141] In example 71, the subject matter of example 70 includes, wherein the advertisement status further indicates a type of operation in progress.

[0142] In example 72, the subject matter of examples 61-71 includes, wherein the attribute set is defined by the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

[0143] In Example 73, the subject matter of Example 72 includes, wherein the JEDEC BAEBI family of standards includes the JESD245B.01 standard.

[0144] In instance 74, the subject matter of instances 61 to 73 includes, where the attribute is the name of the command.

[0145] In instance 75, the subject matter of instances 61 to 74 includes, wherein the attribute is an address.

[0146] In example 76, the subject matter of example 75 includes, wherein the address is a page specifier.

[0147] In example 77, the subject matter of example 76 includes, wherein the attribute set has a single member corresponding to page 0.

[0148] In Example 78, the subject matter of Examples 75-77 includes, wherein the address includes both a page specifier and an offset.

[0149] In example 79, the subject matter of example 78 includes, wherein a member of the attribute set is an address having a page specifier of 0 and an offset of 1 corresponding to an NVDIMM_FUNC_CMD, ARM_CMD, FIRMWARE_OPS_CMD, or OPERATIONAL_UNIT_OPS_CMD according to the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) JESD245B.01 standard.

[0150] In example 80, the subject matter of examples 61-79 includes, wherein the attribute set is stored in a table, and wherein comparing the attribute to the attribute set includes matching the attribute to a record in the table to determine that the attribute is in the attribute set.

[0151] Example 81 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-80.

[0152] Example 82 is an apparatus including means for implementing any one of Examples 1 to 80.

[0153] Example 83 is a system for implementing any one of Examples 1 to 80.

[0154] Example 84 is a method for implementing any one of Examples 1 to 80.

[0155] The above embodiments include references to the accompanying drawings that form a part of the embodiments. The drawings show specific embodiments in which the present invention can be practiced by way of illustration. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only those shown or described elements are provided. In addition, the inventors also contemplate using examples (or one or more aspects thereof) of any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0156] In the present invention, the term "a or an" is often used in patent documents to include one or more, which is independent of any other examples or uses of "at least one" or "one or more". In the present invention, the use of the term "or" refers to a non-exclusive "or", so that "A or B" includes "A but not B", "B but not A" and "A and B", unless otherwise indicated. In the accompanying claims, the terms "including" and "in which" are used as the common English equivalents of the corresponding terms "including" and "wherein". Moreover, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, object, or process that includes several elements in addition to those listed after this term in the claim is still considered to be within the scope of the claim. In addition, in the following claims, the terms "first", "second", and "third", etc. are used only as labels and do not wish to impose numerical requirements on their objects.

[0157] As used herein, operating a memory cell includes reading from the memory cell, writing to the memory cell, or erasing the memory cell. The operation of placing a memory cell in a desired state is referred to herein as "programming," and may include both writing to the memory cell or erasing from the memory cell (e.g., the memory cell may be programmed to an erased state).

[0158] It will be understood that when an element is referred to as being "on," "connected to," or "coupled with" another element, it may be directly on, connected to, or coupled with the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled with" another element, there are no intervening elements or layers. Unless otherwise indicated, if two elements are shown in a drawing as having a line connecting them, the two elements may be coupled or directly coupled.

[0159] The above description is intended to be illustrative rather than restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, other embodiments may be used by a person of ordinary skill in the art, for example. It is claimed that it is not intended to explain or limit the scope or meaning of the claims. In addition, in the above embodiments, various features may be grouped together to simplify the present invention. This should not be interpreted as expecting that the disclosed features that are not claimed are the key to any claim. The fact is that the subject matter of the present invention may be less than all the features of a specific disclosed embodiment. Therefore, the claims are incorporated into the embodiments herein, wherein each claim itself is a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. The scope of the embodiments should be determined with reference to the attached claims together with the full range of equivalents authorized by such claims.

Claims

1. A hardware memory, comprising: Memory controller; An interface used for communication between the memory controller and a host; A decoder coupled to the interface, the decoder configured to perform operations including: decoding an encoded message from the host to obtain a decoded message, the decoded message comprising attributes and a command written to a command register of the memory controller; Prior to providing the decoded message to the memory controller to execute the command written to the command register: examining the decoded message to determine whether the attribute is in a set of attributes corresponding to an advertised state accessible to the host via the interface; and modifying the advertisement state of the hardware memory in response to determining that the attribute is in the attribute set; and The decoded message is provided to the memory controller.

2. The hardware memory according to claim 1, wherein the interface is a first interface, the hardware memory comprises a second interface and a volatile part of the memory, and the second interface is a double data rate DDR random access memory RAM interface for communication between the volatile part and the host. 3 . The hardware memory according to claim 2 , wherein the hardware memory is a non-volatile dual in-line memory module (NVDIMM). 4 . The hardware memory according to claim 1 , wherein the advertisement status indicates whether the memory controller is performing an operation corresponding to the advertisement status.

5. The hardware memory of claim 1, wherein the set of attributes is defined by the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards. The hardware memory of claim 1 , wherein the attribute is an address.

7. The hardware memory of claim 6, wherein the address is a page specifier.

8. A method for state management, comprising: decoding an encoded message from a host to obtain a decoded message, the decoded message comprising attributes, and a command to be written to a command register of a memory controller of a hardware memory; Prior to providing the decoded message to the memory controller to execute the command written to the command register: examining the decoded message to determine whether the attribute is in the set of attributes corresponding to an advertised state accessible by the host via an interface of the hardware memory for the memory controller and the host to communicate; and modifying the advertisement state of the hardware memory in response to determining that the attribute is in the attribute set; and The decoded message is provided to the memory controller.

9. The method according to claim 8, wherein the interface is a first interface, the hardware memory includes a second interface and a volatile part of the memory, and the second interface is a double data rate DDR random access memory RAM interface for communication between the volatile part and the host.

10. The method of claim 9, wherein the hardware memory is a non-volatile dual in-line memory module (NVDIMM). 11 . The method of claim 8 , wherein the advertising status indicates whether the memory controller is performing an operation corresponding to the advertising status.

12. The method of claim 8, wherein the set of attributes is defined by the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

13. The method of claim 8, wherein the attribute is an address. The method of claim 13 , wherein the address is a page designator.

15. A non-transitory machine-readable medium comprising instructions that, when executed by processing circuitry of a hardware memory, cause the hardware memory to perform operations comprising: encoding an encoded message from a host to obtain a decoded message, the decoded message comprising attributes and a command to be written to a command register of a memory controller of the hardware memory; Prior to providing the decoded message to the memory controller to execute the command written to the command register: examining the decoded message to determine whether the attribute is in the set of attributes corresponding to an advertised state accessible by the host via an interface of the hardware memory for the memory controller and the host to communicate; and modifying the advertisement state of the hardware memory in response to determining that the attribute is in the attribute set; and The decoded message is provided to the memory controller.

16. The non-transitory machine-readable medium of claim 15, wherein the interface is a first interface, the hardware memory comprises a second interface and a volatile portion of the memory, and the second interface is a double data rate (DDR) random access memory (RAM) interface for communication between the volatile portion and the host.

17. The non-transitory machine-readable medium of claim 16, wherein the hardware memory is a non-volatile dual in-line memory module (NVDIMM).

18. The non-transitory machine-readable medium of claim 15, wherein the advertisement status indicates whether the memory controller is performing an operation corresponding to the advertisement status.

19. The non-transitory machine-readable medium of claim 15, wherein the set of attributes is defined by the Joint Electron Device Engineering Council (JEDEC) Byte Addressable Energy Backup Interface (BAEBI) family of standards.

20. The non-transitory machine-readable medium of claim 15, wherein the attribute is an address.

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