A vector processor processing method and system

Abstract

This invention relates to a vector processor processing method and system. The vector processor in this method includes a CPU, a vector coprocessor, and random access memory (RAM). The method utilizes the vector coprocessor to obtain address data from registers in the CPU; and uses the vector coprocessor to send the address data from the CPU registers to the RAM. This invention reduces power consumption and area without compromising programmability.

Description

Technical Field

[0001] This invention relates to the field of programming, and in particular to a vector processor processing method and system. Background Technology

[0002] Vector processors commonly employ a register file approach. Due to the large capacity of register files, they are typically implemented using SRAM. Random access to registers can lead to conflicts, resulting in significant performance degradation. Many vector processors and GPUs use Register File Cache and Operand Buffers to reduce conflicts, but this incurs some losses in power consumption and area. Since the size of individual registers in a vector register file is fixed, implementing operations of varying lengths requires substantial hardware logic, further increasing the complexity of vector processor programming. Summary of the Invention

[0003] The purpose of this invention is to provide a vector processor processing method and system that reduces power consumption and area without affecting programmability.

[0004] To achieve the above objectives, the present invention provides the following solution:

[0005] A vector processor processing method, wherein the vector processor includes: a CPU, a vector coprocessor (VectorProcessor), and random access memory (RAM); the processing method includes:

[0006] The vector coprocessor is used to obtain address data from the registers in the CPU;

[0007] The vector coprocessor is used to send the address data in the registers of the CPU to the random access memory.

[0008] Optionally, the step of using the vector coprocessor to obtain address data from the registers in the CPU and sending it to random access memory further includes:

[0009] Data instructions are sent to the instruction queue in the vector coprocessor.

[0010] Optionally, the step of using the vector coprocessor to obtain address data from registers in the CPU specifically includes:

[0011] The instruction queue decodes the data instructions based on their content;

[0012] Send the register ID from the decoded content to the CPU;

[0013] The CPU determines the value of the register based on the register ID and sends the register value to the vector processor.

[0014] Optionally, the step of using the vector coprocessor to send the address data in the registers of the CPU to the random access memory specifically includes:

[0015] The microinstruction is determined based on the value of the register and the decoded content.

[0016] The microinstructions drive the memory access unit (MAU) and the arithmetic logic unit (ALU);

[0017] The arithmetic unit selects a vector operation mode and prepares to receive address data sent by the memory access unit;

[0018] The memory access unit reads address data from the cache unit and random access memory, and sends it to the arithmetic unit; and allocates the address to be written back to the cache unit by the arithmetic unit.

[0019] The arithmetic unit performs calculations based on the received data and sends the results to the buffer unit.

[0020] After the arithmetic unit writes back to the cache unit, it sends a message to the memory access unit indicating that the instruction has been completed.

[0021] Optionally, after the arithmetic unit writes back to the cache unit, it sends an end message to the memory access unit, and then the process further includes:

[0022] The memory access unit sends instruction completion information to the CPU, and instruction execution ends;

[0023] The contents of the cache unit are automatically written back to the random access memory.

[0024] Optionally, the cache unit is allocated for writing, and the priority of read operations for the same instruction is higher than the priority of write operations. If it is not written back, it cannot be written or read.

[0025] A vector processor processing system is provided, applied to the aforementioned vector processor processing method. The vector processor includes a CPU, a vector coprocessor, and a random access memory. The processing system includes:

[0026] The data acquisition module is used to acquire address data from registers in the CPU using the vector coprocessor;

[0027] The data transmission module is used to send address data in the registers of the CPU to the random access memory using the vector coprocessor.

[0028] Optionally, it also includes:

[0029] The instruction sending module is used to send data instructions to the instruction queue in the vector coprocessor.

[0030] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0031] This invention provides a vector processor processing method and system, wherein the vector processor includes a CPU, a vector coprocessor, and random access memory (RAM). The method utilizes the vector coprocessor to obtain address data from registers in the CPU; and uses the vector coprocessor to send the address data from the CPU registers to the RAM. By removing the vector register stack, a general-purpose CPU acts as the control unit, while the vector processor reuses registers in the CPU, reducing control complexity. Compared to other vector processors, it reduces the number of instructions when performing the same function. Therefore, without affecting programmability, it reduces power consumption and area. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a vector processor processing method provided by the present invention;

[0034] Figure 2 This is a schematic diagram of a vector processor architecture;

[0035] Figure 3 This is a schematic diagram of the overall process of a vector processor processing method provided by the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] The purpose of this invention is to provide a vector processor processing method and system that reduces power consumption and area without affecting programmability.

[0038] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 2 As shown, the vector processor includes a CPU, a vector coprocessor, and a random access memory; the CPU sends vector instructions to the Vector Processor, and the vector coprocessor interacts with the RAM (which can be DRAM or SRAM) through a dedicated independent bus. Figure 1 This is a schematic diagram of a vector processor processing method provided by the present invention, as shown below. Figure 1 As shown, the vector processor processing method provided by the present invention includes:

[0040] S101, use the vector coprocessor to obtain the address data in the register of the CPU;

[0041] S101 also includes:

[0042] Data instructions are sent to the instruction queue in the vector coprocessor.

[0043] S101 specifically includes:

[0044] The instruction queue decodes the data instructions based on their content;

[0045] Send the register ID from the decoded content to the CPU;

[0046] The CPU determines the value of the register based on the register ID and sends the register's address data to the vector processor.

[0047] S102, the vector processor is used to send the address data of the registers in the CPU to the random access memory.

[0048] S102 specifically includes:

[0049] The microinstruction is determined based on the address data in the register and the decoded content.

[0050] The memory access unit and the arithmetic unit are driven by microinstructions;

[0051] The arithmetic unit selects a vector operation mode and prepares to receive address data sent by the memory access unit;

[0052] The memory access unit reads address data from the cache and random access memory and sends it to the arithmetic unit; it also allocates the address that the arithmetic unit writes back to the cache.

[0053] The arithmetic unit performs calculations based on the received data and sends the results to the buffer unit.

[0054] After the arithmetic unit writes back to the cache unit, it sends a message to the memory access unit indicating that the instruction has been completed.

[0055] After the arithmetic unit writes back to the cache unit, it sends an end message to the memory access unit, followed by:

[0056] The memory access unit sends instruction completion information to the CPU, and instruction execution ends;

[0057] The contents of the cache unit are automatically written back to the random access memory.

[0058] To address data contention issues in read-after-write (RAW), write-after-write (WAW), and write-after-read (WAR) operations, the cache unit is allocated for write operations, and read operations of the same instruction have higher priority than write operations. If a data item is not written back, it cannot be written to or read from. ALU operation results can only be written back to the cache unit, which then initiates a Clean operation to write the data back to RAM.

[0059] like Figure 3 As shown, the dashed lines represent control circuits, and the solid lines represent data paths. The CPU can be any architecture central processing unit, and the INST Queue is the instruction queue of the vector processor. The Decoder is the decoding unit of the vector processor. Reg2Addr sends the decoded register ID to the CPU, obtains the corresponding register value, and together with the decoded content, forms a microinstruction (Uop) which is sent to the microinstruction queue (Uop Queue). The Uop Queue issues instructions to the memory access unit (MAU) and the arithmetic logic unit (ALU).

[0060] Take a vector multiplication instruction as an example:

[0061] The instruction is issued to the instruction queue (INST Queue);

[0062] The instruction queue decodes the instruction content to determine that two read operands and one write operand are required. Reg2Addr sends the corresponding Reg ID to the CPU and sends the remaining information to the microinstruction queue (Uop Queue).

[0063] After the Uop Queue obtains the instruction operation content from the previous step and the specific address information of the two reads and one write returned by the CPU, it drives the MAU and ALU respectively.

[0064] The ALU selects the vector multiplication operation mode and prepares to receive the address data sent by the MAU. After receiving the data, it performs the operation and sends the result to the cache.

[0065] The MAU reads address data from the Cache or RAM based on the address information of the two read requests and sends it to the ALU; it also allocates the address for the ALU to write back to the Cache.

[0066] After the ALU writes back to the cache, it sends a completion message to the MAU. The MAU then informs the CPU that the instruction has been completed, and the instruction execution ends.

[0067] After the instruction is executed, the contents of the cache are automatically written back to RAM.

[0068] A vector processor processing system is provided, applied to the aforementioned vector processor processing method. The vector processor includes a CPU, a vector coprocessor, and a random access memory. The processing system includes:

[0069] The data acquisition module is used to acquire address data from registers in the CPU using the vector coprocessor;

[0070] The data transmission module is used to send address data in the registers of the CPU to the random access memory using the vector coprocessor.

[0071] The vector coprocessor processing system provided by this invention further includes:

[0072] The instruction sending module is used to send data instructions to the instruction queue in the vector processor.

[0073] This invention employs a reduced instruction set, supporting only arithmetic instructions, with data movement instructions being optional, and eliminating the need for jump and branch instructions. The instruction set only supports register-to-register operations.

[0074] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0075] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A vector processor processing method, characterized in that, The vector processor includes: a CPU, a vector coprocessor, and a random access memory; the processing method includes: The data instructions are sent to the instruction queue in the vector coprocessor; The vector coprocessor is used to obtain the address data in the registers of the CPU; the instruction queue decodes the data instruction according to its content; the register ID in the decoded content is sent to the CPU; the CPU determines the value of the register according to the register ID and sends the value of the register to the vector processor. The vector coprocessor sends address data from the registers in the CPU to the random access memory; microinstructions are determined based on the register values ​​and the decoded contents; the microinstructions drive the memory access unit and the arithmetic unit; the arithmetic unit selects a vector operation mode and prepares to receive address data from the memory access unit; the memory access unit reads address data from the cache unit and the random access memory and sends it to the arithmetic unit; the arithmetic unit is then allocated an address to write back to the cache unit; the arithmetic unit performs operations based on the received data and sends the result to the cache unit; after writing back to the cache unit, the arithmetic unit sends a completion message to the memory access unit.

2. The vector processor processing method according to claim 1, characterized in that, After the arithmetic unit writes back to the cache unit, it sends an end message to the memory access unit, followed by: The memory access unit sends instruction completion information to the CPU, and instruction execution ends; The contents of the cache unit are automatically written back to the random access memory.

3. A vector processor processing method according to any one of claims 2, characterized in that, The cache unit is allocated for writing, and the priority of read operations for the same instruction is higher than the priority of write operations. If it is not written back, it cannot be written or read.

4. A vector processor processing system, applied to the vector processor processing method according to any one of claims 1-3, characterized in that, The vector processor includes: a CPU, a vector coprocessor, and random access memory; the processing system includes: The data acquisition module is used to acquire address data from registers in the CPU using the vector coprocessor; The data transmission module is used to send address data in the registers of the CPU to the random access memory using the vector coprocessor.

5. The vector processor processing system according to claim 4, characterized in that, Also includes: The instruction sending module is used to send data instructions to the instruction queue in the vector coprocessor.

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