Burr suppression device and method

Abstract

Embodiments of the present disclosure relate to glitch suppression apparatus and methods. The apparatus includes a primary core processor configured to receive a first signal through a first primary buffer, a second signal through a second primary buffer, a third signal through a third primary buffer, and a fourth signal through a fourth primary buffer; a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer, and the fourth signal through a fourth shadow buffer; and a first glitch suppression buffer coupled to a common node of an input of the first primary buffer and an input of the first shadow buffer.

Description

Technical Field

[0001] This invention generally relates to a glitch suppression device and method in a dual-core lockstep system. Background Technology

[0002] As the automotive industry continues to expand and vehicles become larger, the demand for system-on-chip (SoC) semiconductor devices designed for safety-critical applications is constantly growing. Reliability is a critical issue in meeting the safety requirements of a range of automotive applications, including advanced driver assistance systems, electric power steering systems, adaptive cruise control systems, braking control systems, and more.

[0003] In safety-critical applications, system errors may occur in computer systems. If these errors are not detected and corrected in a timely manner, they may lead to system shutdown and crashes. Dual-core lockstep computer systems are used to detect system errors and prevent system crashes.

[0004] A dual-core lockstep computer system includes a master core processor and a shadow core processor configured for lockstep operation. Both the master and shadow core processors are configured to receive the same input data and execute the same instructions of the same program code at any given time. After each instruction is executed, the result from the master core processor is compared with the result from the shadow core processor. If a mismatch is found between the results from the two core processors, it indicates a fault in the computer system. Therefore, the computer system enters a defined safe mode.

[0005] In a dual-core lockstep computer system, numerous timing buffers are placed on the clock, reset, test, and data signals. These timing buffers can cause glitches in the dual-core lockstep computer system. Dual-core lockstep computer systems are designed to detect system faults. However, faults occurring on the common path of the clock, reset, and test signals (e.g., single-event toggle transition faults) are undetectable. Faults occurring on the common path can lead to reliability issues. A simple and reliable glitch suppression mechanism is desired to maintain reliable operation of the computer system. Summary of the Invention

[0006] According to one embodiment, the apparatus includes: a main core processor configured to receive a first signal via a first main buffer, a second signal via a second main buffer, a third signal via a third main buffer, and a fourth signal via a fourth main buffer; a shadow core processor configured to receive the first signal via a first shadow buffer, the second signal via a second shadow buffer, the third signal via a third shadow buffer, and the fourth signal via a fourth shadow buffer; and a first glitch suppression buffer coupled to a common node of the inputs of the first main buffer and the first shadow buffer.

[0007] According to another embodiment, the method includes: placing a first glitch suppression buffer at the end of a first common signal path to suppress glitches in a first signal before the first signal flows into two different signal paths respectively coupled to the main core processor and the shadow core processor; placing a second glitch suppression buffer at the end of a second common signal path to suppress glitches in a second signal before the second signal flows into two different signal paths respectively coupled to the main core processor and the shadow core processor; and placing a third glitch suppression buffer at the end of a third common signal path to suppress glitches in a third signal before the third signal flows into two different signal paths respectively coupled to the main core processor and the shadow core processor.

[0008] According to another embodiment, the system includes: a plurality of glitch suppression buffers configured to suppress a plurality of glitches of a plurality of signals, each of the plurality of glitch suppression buffers being placed at the end of a common path of a corresponding signal before the corresponding signal is routed to two different paths; a main core processor configured to receive a plurality of signals through a plurality of main buffers; a shadow core processor configured to receive a plurality of signals through a plurality of shadow buffers; and a fault control unit configured to compare the output signal of the main core processor with the output signal of the shadow core processor, and to detect whether the output signal of the main core processor matches the output signal of the shadow core processor.

[0009] The features and technical advantages of this disclosure have been outlined rather broadly above to provide a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below, forming the subject matter of the claims. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes for achieving the same purpose as those disclosed. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0010] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0011] Figure 1 The illustration shows a block diagram of a dual-core lockstep system according to various embodiments of the present disclosure;

[0012] Figure 2 Various embodiments according to this disclosure are illustrated. Figure 1 The diagram shown is a schematic of a dual-core lockstep system;

[0013] Figure 3 Various embodiments according to this disclosure are illustrated. Figure 2 A schematic diagram of the glitch suppression buffer shown; and

[0014] Figure 4 The illustrations depict various embodiments of suppression according to the present disclosure. Figure 1 The flowchart shows a method for handling glitch in a dual-core lockstep system.

[0015] Unless otherwise stated, corresponding reference numerals in different figures generally refer to corresponding parts. These figures are drawn to clearly illustrate relevant aspects of various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0016] The following discusses in detail the making and use of embodiments of this disclosure. However, it should be understood that the concepts disclosed herein can be embodied in various specific contexts, and the specific embodiments discussed herein are merely illustrative and not intended to limit the scope of the claims. Furthermore, it should be understood that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of this disclosure as defined by the appended claims.

[0017] This disclosure will be described in conjunction with preferred embodiments in a specific context, namely, a glitch suppression device in a dual-core lockstep system. However, this disclosure can also be applied to various safety-critical applications. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0018] Figure 1 A block diagram of a dual-core lockstepping system according to various embodiments of the present disclosure is illustrated. The dual-core lockstepping system 100 includes a first processor 102, a second processor 104, a first buffer 101, a second buffer 103, a fault control unit 106, and a glitch suppressor 110. The dual-core lockstepping system 100 is configured to receive a clock signal, a reset signal, multiple test signals, and multiple data signals. Based on the received signals, the dual-core lockstepping system 100 generates multiple functional output signals and fault output signals.

[0019] The clock signal is generated by a clock generator (not shown). The clock signal is used to regulate multiple intellectual property (IP) components (e.g., communication IP, timer IP, and memory IP). It should be noted that... Figure 1 Only one clock signal is illustrated. This is merely an example. The dual-core lockstep system 100 may include multiple clock signals. The clock signals illustrated herein are limited to clearly illustrating the inventive aspects of various embodiments.

[0020] The reset signal is used to reset different parts of the dual-core lockstep system 100 before functional operation begins. It should be noted that... Figure 1 Only one reset signal is shown in the diagram. This is just an example. Depending on the design requirements, the dual-core lockstep system 100 may include multiple reset signals.

[0021] Test signals are used when the dual-core lockstep system 100 is configured to operate in test mode. Data signals are used when the dual-core lockstep system 100 is configured to operate in function mode. Data signals are generated by various IPs and fed into the first processor 102 and the second processor 104, respectively. The first processor 102 processes the data signals and feeds the processed data signals to multiple IPs connected to the output of the first processor 102.

[0022] like Figure 1 As shown, the clock signal flows through a common signal path. At node A, the clock signal flows into two different signal paths coupled to the first processor 102 and the second processor 104, respectively. Similarly, the reset signal flows through the common signal path. At node B, the reset signal flows into two different signal paths coupled to the first processor 102 and the second processor 104, respectively. Multiple test signals flow through the common signal path. At node C, multiple test signals flow into two different signal paths coupled to the first processor 102 and the second processor 104, respectively. Multiple data signals flow through the common signal path. At node D, multiple data signals flow into two different signal paths coupled to the first processor 102 and the second processor 104, respectively.

[0023] In some embodiments, the first processor 102 and the second processor 104 are two identical processors. Both processors are reset in the same state and are fed the same input signals. If both processors operate correctly, they generate the same output. During operation, a fault may occur and reach the output of one of the two processors. This fault can be detected by comparing the outputs of the two processors. Upon detecting such a fault, the dual-core lockstep system 100 can take appropriate action to handle the fault and prevent system crash. In some embodiments, the first processor 102 is configured to perform system operations. The second processor 104 is configured to verify the correctness of the operation of the first processor 102. Throughout the description, the first processor 102 may alternatively be referred to as the main core processor 102. The second processor 104 may be referred to as the shadow core processor 104.

[0024] The first buffer 101 includes multiple buffers. Depending on design requirements, multiple buffers are added to different signal paths connected to the main core processor 102. Each of the multiple buffers can be implemented as two cascaded inverters. Throughout the description, the buffers added to the signal paths connected to the main core processor 102 can alternatively be referred to as multiple main buffers. The following will combine... Figure 2 A detailed schematic diagram describing the first buffer 101.

[0025] The second buffer 103 includes multiple buffers. Depending on design requirements, multiple buffers are added to different signal paths connected to the shadow core processor 104. Each of the multiple buffers can be implemented as two cascaded inverters. Throughout the description, the buffers added to the signal paths connected to the shadow core processor 104 can alternatively be referred to as multiple shadow buffers. The following will combine... Figure 2 Here is a detailed schematic diagram of the second buffer 103.

[0026] like Figure 1 As shown, the glitch suppressor 110 is placed on the common path of the clock signal, reset signal, and test signal. Specifically, the glitch suppressor is placed at the end of the common signal path. The glitch suppressor 110 is used to eliminate glitches that appear on the common signal path. The following will discuss... Figures 2-3 Let's discuss a detailed schematic diagram of the burr suppressor 110.

[0027] The fault control unit 106 includes a comparison unit. In some embodiments, the comparison unit is implemented as a comparator. A first input of the comparison unit is connected to the output of the main core processor 102, and a second input is connected to the output of the shadow core processor 104. The fault control unit 106 is configured to compare the output signal of the main core processor 102 with the output signal of the shadow core processor 104, and detect whether the output signal of the main core processor 102 matches the output signal of the shadow core processor 104. If a mismatch is found between the results of the two core processors, a fault exists in the dual-core lockstep system. Therefore, the dual-core lockstep system enters a defined safe mode.

[0028] Figure 2 Various embodiments according to this disclosure are illustrated. Figure 1 The diagram illustrates a dual-core lockstep system. The glitch suppressor 110 includes multiple glitch suppression buffers 115, 125, and 135 configured to suppress multiple glitches occurring on the clock, reset, and test signals. More specifically, the first glitch suppression buffer 115 is used to suppress glitches occurring on the clock signal. The second glitch suppression buffer 125 is used to suppress glitches occurring on the reset signal. The third glitch suppression buffer 135 is used to suppress glitches occurring on multiple test signals.

[0029] like Figure 2 As shown, the first glitch suppression buffer 115 is placed at the end of the common path of the clock signal, before the clock signal is fed to the two different paths. At node A, the clock signal leaves the common path and reaches the main core processor and the shadow core processor through two different paths. Figure 2As shown, the first path of coupling between node A and the main core processor 102 includes buffers 111, 112, and 113. The second path of coupling between node B and the shadow core processor 104 includes buffers 211, 212, and 213.

[0030] At node B, the reset signal leaves the common path and reaches the main core processor 102 and the shadow core processor 104 via two different paths. For example... Figure 2 As shown, the first path coupling between node B and the main core processor 102 includes buffer 121. The second path coupling between node B and the shadow core processor 104 includes buffer 221. At node C, multiple test signals leave the common path and reach the main core processor 102 and the shadow core processor 104 via two different paths. Figure 2 As shown, the first path coupling between node C and the main core processor 102 includes buffer 131. The second path coupling between node C and the shadow core processor 104 includes buffer 231.

[0031] At node D, multiple data signals leave the common path and arrive at the main core processor 102 and the shadow core processor 104 via two different paths. For example... Figure 2 As shown, the first path connecting node D to the main core processor 102 includes buffer 141. The second path connecting node D to the shadow core processor 104 includes buffer 241.

[0032] Buffers (e.g., buffers 111-113, 121, 131, 141, 211-213, 221, 231, and 241) are used to control the timing of signals fed into the main core processor 102 and the shadow core processor 104. A buffer can be implemented as two cascaded inverters.

[0033] An advantageous feature of the glitch suppression buffers 115, 125, and 135 is that the glitch suppression buffers are added only to the clock, reset, and test signal paths. These glitch suppression buffers help suppress transition faults occurring on the common signal path. Compared to the data input, the dual-core lockstep system has fewer clock, reset, and test signals in its input. Adding glitch suppression buffers only to the clock, reset, and test signal paths helps reduce the semiconductor area of ​​the dual-core lockstep system. Furthermore, compared to conventional glitch suppression devices with delay-stage flip-flops on all signal paths, Figure 2 The system shown allows for the removal of delay-level triggers, thereby simplifying the system and making it more reliable.

[0034] Figure 3 Various embodiments according to this disclosure are illustrated. Figure 2The diagram shows a glitch suppression buffer. Glue suppression buffers 115, 125, and 135 have the same structure. For simplicity, glitch suppression buffer 115 is used as an example.

[0035] like Figure 3 As shown, the glitch suppression buffer 115 includes a first NAND gate 302, a second NAND gate 304, a third NAND gate 306, a fourth NAND gate 308, and a delay buffer 310.

[0036] The first NAND gate 302 has a first input connected to the output of the glitch suppression buffer 115, a second input connected to the output of the delay buffer 310, and an output connected to the first input of the fourth NAND gate 308.

[0037] The second NAND gate 304 has a first input connected to the second input of the first NAND gate 302, a second input connected to the input of the glitch suppression buffer 115, and an output connected to the second input of the fourth NAND gate 308.

[0038] The third NAND gate 306 has a first input connected to the input of the glitch suppression buffer 115, a second input connected to the output of the glitch suppression buffer 115, and an output 308 connected to the third input of the fourth NAND gate.

[0039] The fourth NAND gate 308 has a first input connected to the output of the first NAND gate 302, a second input connected to the output of the second NAND gate 304, a third input connected to the output of the third NAND gate 306, and an output connected to the output of the glitch suppression buffer 115.

[0040] The delay buffer 310 is connected between the input of the glitch suppression buffer 115 and the first input of the second NAND gate.

[0041] In operation, when the input signal of the glitch suppression buffer 115 is in a logic low state, the output of the glitch suppression buffer 115 generates a logic low signal. Glitches (e.g., logic high glitch) may occur at the input of the glitch suppression buffer 115. The delay buffer 310 delays the incoming glitch and generates a delayed glitch at the output of the delay buffer 310.

[0042] At the first instant, a glitch reaches the second input of the second NAND gate 304 and the first input of the third NAND gate 306. Due to the delay generated by the delay buffer 310, a logic low signal is generated at the output of the delay buffer 310 at the first instant. This logic low signal is applied to the second input of the first NAND gate 302 and the first input of the second NAND gate 304. Figure 3As shown, the output of the glitch suppression buffer 115 is fed to the first input of the first NAND gate 302 and the second input of the third NAND gate 306. According to the operating principle of NAND gates, NAND gates 302, 304, and 306 all generate a logic high signal at the first moment. The fourth NAND gate 308 remains in a logic low state at the first moment.

[0043] After the glitch passes through the glitch suppression buffer 115, at the second time point, the delayed glitch reaches the second input of the first NAND gate 302 and the first input of the second NAND gate 304. A logic low signal is applied to the first input of the first NAND gate 302, the second input of the second NAND gate 304, and the input of the third NAND gate 306. According to the operating principle of NAND gates, NAND gates 302, 304, and 306 all generate a logic high signal at the first time point. The fourth NAND gate 308 remains in a logic low state at the second time point. Thus, the glitch is eliminated or absorbed by the glitch suppression buffer 115.

[0044] In operation, when the input signal is in a logic high state, the output of the glitch suppression buffer 115 generates a logic high signal. Glitches (e.g., logic low glitches) may occur at the input of the glitch suppression buffer 115. The glitch suppression buffer 115 can eliminate these logic low glitches and maintain the logic high state. The operating principle for eliminating these logic low glitches is similar to that described above and will not be repeated here.

[0045] It is important to note that Figure 3 The glitch suppression buffer shown is merely an example and should not unduly limit the scope of the claims. Many variations, alternatives, and modifications will be recognized by those skilled in the art.

[0046] Figure 4 The illustrations depict various embodiments of suppression according to the present disclosure. Figure 1 The flowchart shows a method for handling glitch in a dual-core lockstep system. Figure 4 The flowchart shown is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, alternatives, and modifications. For example, Figure 4 The steps shown can be added, removed, replaced, rearranged, and repeated.

[0047] A dual-core lockstep system includes a main core processor (e.g., Figures 1-2 The processor I in the middle) and the shadow core processor (e.g., Figures 1-2 The main core processor and the shadow core processor are both configured to receive the same input signals, including clock signals, reset signals, multiple test signals, and multiple data signals.

[0048] The clock signal flows through a common clock signal path. At the first node (e.g., Figures 1-2At node A), the clock signal is routed to two different signal paths connected to the main core processor and the shadow core processor, respectively. To control the timing of the clock signal fed into the main core processor, multiple first main buffers (e.g., Figure 2 Buffers 111, 112, and 113 are placed in the signal path between the first node and the main core processor. To control the timing of the clock signal fed into the shadow core processor, multiple first shadow buffers (e.g., ...) are used. Figure 2 The buffers 211, 212 and 213 are placed in the signal path between the first node and the shadow core processor.

[0049] The reset signal flows through the common reset signal path. At the second node (e.g., Figures 1-2 At node B), the reset signal is routed to two different signal paths connected to the main core processor and the shadow core processor, respectively. To control the timing of the reset signal fed into the main core processor, a second main buffer (e.g., ...) is used. Figure 2 The second shadow buffer (121) is placed in the signal path between the second node and the main core processor. To control the timing of the reset signal fed into the shadow core processor, the second shadow buffer (e.g., ...) is... Figure 2 The buffer 221 is placed in the signal path between the second node and the shadow core processor.

[0050] Multiple test signals flow through a common test signal path. At the third node (e.g., Figures 1-2 At node C), multiple test signals are routed to two different signal paths connected to the main core processor and the shadow core processor, respectively. To control the timing of the multiple test signals fed into the main core processor, a third main buffer (e.g., ...) is used. Figure 2 The third shadow buffer (131) is placed in the signal path between the third node and the main core processor. To control the timing of multiple test signals fed into the shadow core processor, the third shadow buffer (e.g., ...) is used... Figure 2 The buffer 231 is placed in the signal path between the third node and the shadow core processor.

[0051] Multiple data signals flow through a common data signal path. At the fourth node (e.g., Figures 1-2 At node D), multiple data signals are routed to two different signal paths connected to the main core processor and the shadow core processor, respectively. To control the timing of the multiple data signals fed into the main core processor, a fourth main buffer (e.g., ...) is used. Figure 2 The fourth shadow buffer (141) is placed in the signal path between the fourth node and the main core processor. To control the timing of multiple data signals fed into the shadow core processor, the fourth shadow buffer (e.g., ...) is used... Figure 2The buffer 241 is placed in the signal path between the fourth node and the shadow core processor.

[0052] Both the main core processor and the shadow core processor process the received signals. In the fault control unit (e.g., Figures 1-2 At the fault control unit 106 shown, the output of the main core processor is compared with the output of the shadow core processor. The fault control unit determines whether the output signals of the main core processor and the shadow core processor match. If the outputs of these core processors do not match, a fault is indicated in the dual-core lockstep system. The dual-core lockstep system enters a predetermined safe mode to prevent fault propagation.

[0053] During operation, glitches may occur in the common signal path. A standard dual-core configuration cannot detect glitches because they are fed to both the main processor and the shadow processor simultaneously. The following steps are used to suppress glitches occurring in the common signal path.

[0054] At step 402, the first glitch suppression buffer (e.g., Figure 2 The first glitch suppression buffer 115 shown is placed at the end of the first common signal path to suppress glitches in the first signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively. The first signal is a clock signal. The first common signal path is a common clock signal path. The first glitch suppression buffer is placed at the end of the common clock signal path before the clock signal is routed to the two different signal paths.

[0055] At step 404, the second glitch suppression buffer (e.g., Figure 2 The second glitch suppression buffer 125 shown is placed at the end of the second common signal path to suppress glitch in the second signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively. The second signal is a reset signal. The second common signal path is a common reset signal path. The second glitch suppression buffer is placed at the end of the common reset signal path before the reset signal is routed to the two different signal paths.

[0056] At step 406, the third glitch suppression buffer (e.g., Figure 2The third glitch suppression buffer (135) shown is placed at the end of the third common signal path to suppress glitches in the third signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively. The third signal includes multiple test signals. The third common signal path is a common test signal path. The third glitch suppression buffer is placed at the end of the common test signal path before the multiple test signals are routed to the two different signal paths.

[0057] Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, alternatives and modifications may be made herein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

[0058] Furthermore, the scope of this application is not intended to be limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of this disclosure processes, machines, manufactures, compositions of matter, means, methods, or steps that exist or will be developed thereafter and perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A device for burr suppression, comprising: The main core processor is configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer. The shadow core processor is configured to receive the first signal via a first shadow buffer, receive the second signal via a second shadow buffer, receive the third signal via a third shadow buffer, and receive the fourth signal via a fourth shadow buffer. as well as The first glitch suppression buffer is coupled to a common node of the input of the first main buffer and the input of the first shadow buffer.

2. The apparatus according to claim 1, wherein The first signal is a clock signal.

3. The apparatus according to claim 1, further comprising: The second glitch suppression buffer is coupled to the common node of the input of the second main buffer and the input of the second shadow buffer.

4. The apparatus according to claim 3, wherein: The second signal is a reset signal.

5. The apparatus according to claim 1, further comprising: The third glitch suppression buffer is coupled to the common node of the input of the third main buffer and the input of the third shadow buffer.

6. The apparatus according to claim 5, wherein: The third signal includes multiple test signals.

7. The apparatus according to claim 1, wherein: The fourth signal includes multiple data signals.

8. The apparatus of claim 1, wherein the first glitch suppression buffer comprises: A first NAND gate has a first input connected to the output of the first glitch suppression buffer; The second NAND gate has a first input connected to the second input of the first NAND gate and a second input connected to the input of the first glitch suppression buffer; The third NAND gate has a first input connected to the input of the first glitch suppression buffer and a second input connected to the output of the first glitch suppression buffer; The fourth NAND gate has a first input connected to the output of the first NAND gate, a second input connected to the output of the second NAND gate, a third input connected to the output of the third NAND gate, and an output connected to the output of the first glitch suppression buffer. as well as A delay buffer is connected between the input of the first glitch suppression buffer and the first input of the second NAND gate.

9. The apparatus according to claim 1, further comprising: A comparator has a first input coupled to the output of the main core processor and a second input coupled to the output of the shadow core processor, wherein the comparator is configured to compare the output signal of the main core processor with the output signal of the shadow core processor and detect whether the output signal of the main core processor matches the output signal of the shadow core processor.

10. The apparatus according to claim 1, wherein: The first glitch suppression buffer is placed at the end of the common path of the first signal, before the first signal is routed to two different signal paths respectively connected to the main core processor and the shadow core processor.

11. A method for burr suppression, comprising: A first glitch suppression buffer is placed at the end of the first common signal path to suppress glitch in the first signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively. A second glitch suppression buffer is placed at the end of the second common signal path to suppress glitch in the second signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively. as well as A third glitch suppression buffer is placed at the end of the third common signal path to suppress glitch in the third signal before it flows into two different signal paths coupled to the main core processor and the shadow core processor, respectively.

12. The method of claim 11, further comprising: The first signal, which is a clock signal, is delayed by adding multiple first main buffers between the output of the first glitch suppression buffer and the main core processor. The second signal, which is a reset signal, is delayed by adding at least one second main buffer between the output of the second glitch suppression buffer and the main core processor. as well as The third signal, which includes multiple test signals, is delayed by adding at least one third main buffer between the output of the third glitch suppression buffer and the main core processor.

13. The method according to claim 11, wherein: The first signal, wherein the first signal is a clock signal, is delayed by adding a plurality of first shadow buffers between the output of the first glitch suppression buffer and the shadow core processor; The second signal, which is a reset signal, is delayed by adding at least one second shadow buffer between the output of the second glitch suppression buffer and the shadow core processor. as well as The third signal, which includes multiple test signals, is delayed by adding at least one third shadow buffer between the output of the third glitch suppression buffer and the shadow core processor.

14. The method of claim 11, further comprising: Multiple data signals are delayed by adding at least one fourth master buffer between the main core processor and the end of the common data signal path, the end of the common data signal path before the multiple data signals are routed to two different signal paths coupled to the main core processor and the shadow core processor, respectively. as well as The plurality of data signals are delayed by adding at least one fourth shadow buffer between the shadow core processor and the end of the common data signal path.

15. The method of claim 11, wherein the first glitch suppression buffer comprises: A first NAND gate has a first input connected to the output of the first glitch suppression buffer; The second NAND gate has a first input connected to the second input of the first NAND gate and a second input connected to the input of the first glitch suppression buffer; The third NAND gate has a first input connected to the input of the first glitch suppression buffer and a second input connected to the output of the first glitch suppression buffer; The fourth NAND gate has a first input connected to the output of the first NAND gate, a second input connected to the output of the second NAND gate, a third input connected to the output of the third NAND gate, and an output connected to the output of the first glitch suppression buffer. as well as A delay buffer is connected between the input of the first glitch suppression buffer and the first input of the second NAND gate.

16. The method of claim 11, further comprising: Compare the output signal of the main core processor with the output signal of the shadow core processor; as well as Based on the comparison result of the step of comparing the output signal of the main core processor with the output signal of the shadow core processor, it is determined whether the output signal of the main core processor matches the output signal of the shadow core processor.

17. A system for burr suppression, comprising: Multiple glitch suppression buffers are configured to suppress multiple glitches of multiple signals, each of the multiple glitch suppression buffers being placed at the end of a common path of the corresponding signals before the corresponding signals are routed to two different paths; The main core processor is configured to receive the plurality of signals through a plurality of main buffers; The shadow core processor is configured to receive the plurality of signals through a plurality of shadow buffers; as well as The fault control unit is configured to compare the output signal of the main core processor with the output signal of the shadow core processor, and to detect whether the output signal of the main core processor matches the output signal of the shadow core processor.

18. The system according to claim 17, wherein: The main core processor is configured to receive a clock signal through a first glitch suppression buffer, a reset signal through a second glitch suppression buffer, and a test signal through a third glitch suppression buffer; and The shadow core processor is configured to receive the clock signal through the first glitch suppression buffer, the reset signal through the second glitch suppression buffer, and the test signal through the third glitch suppression buffer.

19. The system of claim 17, wherein one of the plurality of glitch suppression buffers comprises: A first NAND gate has a first input connected to the output of the glitch suppression buffer; The second NAND gate has a first input connected to the second input of the first NAND gate and a second input connected to the input of the glitch suppression buffer; The third NAND gate has a first input connected to the input of the glitch suppression buffer and a second input connected to the output of the glitch suppression buffer; The fourth NAND gate has a first input connected to the output of the first NAND gate, a second input connected to the output of the second NAND gate, a third input connected to the output of the third NAND gate, and an output connected to the output of the glitch suppression buffer. as well as A delay buffer is connected between the input of the glitch suppression buffer and the first input of the second NAND gate.

20. The system according to claim 17, wherein: The main core processor, the shadow core processor, and the fault control unit form a dual-core lockstep system.

Images