comparator

Abstract

To provide a comparator that reduces current consumption without causing a decrease in response speed.SOLUTION: In a constant current generating portion 4 that supplies a constant current to a differential input portion 2, transistors M10 and M14 are current mirror connected to load transistors M3 and M4, respectively and are connected in parallel to each other. A resistor R1 is connected between the sources of transistors M10 and M14 and a negative power supply terminal T22. A transistor M11 is connected in series to the transistors M10 and M14, and a transistor M13 is current mirror connected to the transistor M11 to supply a constant current to the differential input portion 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a comparator. [Background technology]

[0002] Global warming is thought to be caused by an increase in the concentration of greenhouse gases such as CO2, which strengthens the greenhouse effect in the atmosphere. With the rapid progress of the information and communication society, reducing the power consumption of electronic devices has become a major challenge. Many semiconductor integrated circuits are used in electronic devices, and this invention aims to reduce the current consumption of comparators, which are widely used in semiconductor integrated circuits, and contribute to mitigating global warming.

[0003] As a comparator used in semiconductor integrated circuits, the circuit shown in Figure 8 is known (see, for example, Patent Documents 1 and 2). The comparator 100 shown in Figure 8 is mainly composed of a differential input section 102, an output section 103, and a constant current generation section 104.

[0004] The differential input section 102 consists of differential transistors M1 and M2 with their sources connected in common, load transistors M3 and M4 connected to their drains respectively, and transistor M13 connected between the common source of differential transistors M1 and M2 and the positive power supply voltage VDD.

[0005] The output section 103 consists of transistors M5 and M6, which are currently mirrored to load transistors M3 and M4, respectively, and transistors M7 and M8, which are connected between their drains and the positive power supply voltage VDD, respectively. Transistors M7 and M8 are currently mirrored to take the output from the connection point between the drain of transistor M6 and the drain of transistor M8.

[0006] The constant current generation unit 104 consists of transistors M9 and M10 connected in a current mirror configuration, transistors M11 and M12 connected in a current mirror configuration, and a resistor R1. Transistors M11 and M13 are connected in a current mirror configuration to supply the generated constant current I , , , ,

[0010] ,

[0011] , , M9 , , to the differential input unit 102.

[0007] The constant current generation unit 104 constitutes a so-called bandgap reference circuit and is provided such that the area ratio of the two transistors M9 and M10 is 1:N. The same drain current flows through the two transistors M9 and M10 by means of a current mirror circuit composed of transistors M11 and M12. Therefore, a difference occurs in the gate-source voltages V GS 9 and V GS 10 of the transistors M9 and M10, and the current I M10 flowing through transistor M10 is (V GS 9 - V GS 10) / R1. As is clear from this equation, even if the positive power supply voltage VDD and the negative power supply voltage VSS vary, the constant current I M10 can be made constant.

[0008] Also, when transistors M9 and M10 operate in the subthreshold region, the drain current changes exponentially with respect to the change in the gate-source potential difference. The constant current I REF (=I M10 ) generated by the constant current generation unit 104 and the circuit current I 104 of the constant current generation unit 104 are expressed by the following equations (1) and (2).

[0009]

Equation

Equation

[0011] Here, K M9This is the aspect ratio (=W / L) of transistor M9, K M10 is the aspect ratio of transistor M10, W is the gate width, L is the gate length, V T θ is the thermal voltage (=kT / q), where k is the Boltzmann coefficient, T is the absolute temperature, q is the unit charge of an electron, and η is the subthreshold swing coefficient.

[0012] The conventional comparator 100 described above has a constant current generating unit 104 that generates the current supplied to the differential input unit 102, and the circuit current I 104 Because this flows as a steady-state current, there was a problem in that the current consumption became large. [Prior art documents] [Patent Documents]

[0013] [Patent Document 1] Patent No. 5141289 [Patent Document 2] Japanese Patent Publication No. 2009-246985 [Overview of the Initiative] [Problems that the invention aims to solve]

[0014] This invention has been made in view of the above circumstances, and its purpose is to provide a comparator that reduces current consumption without causing a decrease in response speed. [Means for solving the problem]

[0015] To achieve the aforementioned objectives, the comparator according to the present invention is characterized by the following [1] to

[15] . [1] A first differential transistor and a second differential transistor, each through which a current with a current ratio corresponding to the potential difference between the first and second input potentials flows, A third load transistor is connected between the drain or collector of the first differential transistor and the first power supply terminal to which the first power supply voltage is supplied, A fourth load transistor connected between the drain or collector of the second differential transistor and the first power supply terminal, A first differential input section having the first differential transistor and a fifth transistor connected between the source or emitter of the second differential transistor and a second power supply terminal to which a second power supply voltage is supplied, A sixth transistor is currently mirrored to the third load transistor, The fourth load transistor is connected to a seventh transistor via a current mirror, An output unit that outputs the comparison result of the currents flowing through the third load transistor and the fourth load transistor, The third load transistor and the fourth load transistor are currently mirrored to each other, and the eighth and ninth transistors are connected in parallel to each other, A first resistor connected between the source or emitter of the eighth transistor and the ninth transistor and the first power supply terminal, The current generating unit comprises a current generating unit having a tenth transistor connected between the drain or collector of the eighth transistor and the ninth transistor and the second power supply terminal, The fifth transistor is currently mirrored to the tenth transistor. It is a comparator. [2] In the comparator described in [1], The output section has an eleventh transistor connected in series with the sixth transistor and a twelfth transistor connected in current mirror with the eleventh transistor, and the seventh transistor and the twelfth transistor are connected in series, with the connection point being the output. It is a comparator. [3] In the comparator described in [1], The present invention has a thirteenth transistor connected in series with the fifth transistor, The current stabilization unit is provided that, when the potential difference between the common-mode input potential of the first differential input section and the second power supply voltage decreases and the first and second differential transistors turn off, the 13th transistor turns on and continues to supply drain current or collector current to the 5th transistor. It is a comparator. [4] In the comparator described in [3], The current stabilization unit has a second resistor connected between the 10th transistor, the 8th transistor and the 9th transistor, The connection point between the second resistor and the eighth and ninth transistors is connected to the gate or base of the thirteenth transistor. It is a comparator. [5] In the comparator described in [3], The 13th transistor is connected in parallel to the first differential transistor and in series to the third load transistor. It is a comparator. [6] In the comparator described in [3], The current stabilization unit includes a 14th transistor connected in series with the 13th transistor, and a 15th transistor connected in current mirror connection to the 14th transistor and in parallel with the 8th and 9th transistors. The 13th transistor and the 14th transistor are connected in parallel to the first differential transistor and the third load transistor, and to the second differential transistor and the fourth load transistor. It is a comparator. [7] In the comparator described in [3], A 16th differential transistor and a 17th differential transistor through which currents with a current ratio corresponding to the potential difference between the first input potential and the second input potential flow, A 18th load transistor connected between the drain or collector of the 16th differential transistor and the second power supply terminal, A 19th load transistor connected between the drain or collector of the 17th differential transistor and the second power supply terminal, The device comprises a second differential input section having the 16th differential transistor and a 20th transistor connected between the source or emitter of the 17th differential transistor and the first power supply terminal, When the 13th transistor is turned on, the 20th transistor is turned on to supply current to the second differential input. It is a comparator. [8] In the comparator described in [7], The current stabilization unit includes a 14th transistor connected in series with the 13th transistor, and a 15th transistor connected in current mirror connection to the 14th transistor and in parallel with the 8th and 9th transistors. The 20th transistor is currently mirrored to the 14th transistor. It is a comparator. [9] In the comparator described in [8], The output section includes a 21st transistor currently mirrored to the 18th load transistor, a 22nd transistor connected in series with the 21st transistor, a 23rd transistor currently mirrored to the 22nd transistor, and a 24th transistor currently mirrored to the 19th load transistor. The sixth transistor and the 19th load transistor are connected in series. The seventh transistor and the twenty-fourth transistor are connected in series, and the connection point becomes the output. The seventh transistor and the twenty-third transistor are connected in parallel. It is a comparator.

[10] In the comparator described in [1], The third load transistor and the fourth load transistor are provided with a minute current supply unit that supplies a minute current smaller than the current supplied from the current generation unit to the first differential input unit. It is a comparator.

[11] In the comparator described in

[10] , The minute current supply unit has a 25th transistor and a 26th transistor that fold back a current of 1 / N (N>1) of the current flowing through the 10th transistor, The 25th transistor and the 3rd load transistor are connected in series. The 26th transistor and the 4th load transistor are connected in series. It is a comparator.

[12] In the comparator described in

[10] , The minute current supply unit includes a 27th transistor that folds back 1 / N (N>1) of the current flowing through the 10th transistor, and a 28th transistor and a 29th transistor connected in series with the 27th transistor. The 28th transistor and the 3rd load transistor are connected in series. The 29th transistor and the 4th load transistor are connected in series. It is a comparator.

[13] In the comparator described in

[10] , The minute current supply unit includes a 28th transistor connected in series with the 5th transistor and in current mirror connection with the 2nd differential transistor, which folds back 1 / N (N>1) of the current flowing through the 2nd differential transistor, and a 29th transistor connected in series with the 5th transistor and in current mirror connection with the 1st differential transistor, which folds back 1 / N of the current flowing through the 1st differential transistor. The 28th transistor and the 3rd load transistor are connected in series. The 29th transistor and the 4th load transistor are connected in series. It is a comparator.

[14] In the comparator described in any one of items [1] to

[13] , At least one of the aforementioned transistors is composed of a field-effect transistor. It is a comparator.

[15] In the comparator described in any one of items [1] to

[13] , At least one of the aforementioned transistors is composed of a bipolar transistor. It is a comparator. [Effects of the Invention]

[0016] According to the present invention, it is possible to provide a comparator that reduces current consumption without causing a decrease in response speed.

[0017] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by referring to the attached drawings and reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments"). [Brief explanation of the drawing]

[0018] [Figure 1] Figure 1 is a circuit diagram showing the comparator of the present invention in the first embodiment. [Figure 2] Figure 2 is a circuit diagram showing the comparator of the present invention in a second embodiment. [Figure 3] Figure 3 is a circuit diagram showing the comparator of the present invention in a third embodiment. [Figure 4] Figure 4 is a circuit diagram showing the comparator of the present invention in the fourth embodiment. [Figure 5] Figure 5 is a circuit diagram showing the comparator of the present invention in the fifth embodiment. [Figure 6]Figure 6 is a circuit diagram showing the comparator of the present invention in the sixth embodiment. [Figure 7] Figure 7 is a circuit diagram showing the comparator of the present invention in the seventh embodiment. [Figure 8] Figure 8 is a circuit diagram showing an example of a conventional comparator. [Modes for carrying out the invention]

[0019] Specific embodiments of the present invention will be described below with reference to the figures.

[0020] (First Embodiment) First, the comparator 1 of the first embodiment will be described with reference to Figure 1. As shown in the figure, the comparator 1 compares the inverting input potential INM (= first input potential) input to the inverting input terminal T11 with the non-inverting input potential INP (= second input potential) input to the non-inverting input terminal T12, and outputs the comparison result from the output terminal T3. The comparator 1 includes a differential input section 2 (= first differential input section), an output section 3, and a constant current generation section 4 (= current generation section).

[0021] The differential input section 2 includes differential transistors M1 (= first differential transistor) and M2 (= second differential transistor), load transistors M3 (= third load transistor) and M4 (= fourth load transistor), and transistor M13 (= fifth transistor), all of which have a common source connection.

[0022] The differential transistors M1, M2, and transistor M13 are composed of P-channel field-effect transistors. The gate of differential transistor M1 is connected to the inverting input terminal T11, and the gate of differential transistor M2 is connected to the non-inverting input terminal T12.

[0023] Transistor M13 has its source connected to the positive power supply terminal T21 (= second power supply terminal) and its drain connected to the sources of differential transistors M1 and M2, respectively. The positive power supply voltage VDD (= second power supply voltage) is supplied to the positive power supply terminal T21. The differential input section 2 receives the current I supplied by transistor M13. M13 The current is divided between differential transistors M1 and M2. The current ratio (division ratio) of the currents flowing through differential transistors M1 and M2 is a value corresponding to the potential difference between the inverting input potential INM and the non-inverting input potential INP.

[0024] The load transistors M3 and M4 are composed of N-channel field-effect transistors. The drain and gate of load transistor M3 are connected to the drain of differential transistor M1, and the source is connected to the negative power supply terminal T22 (= first power supply terminal). The negative power supply voltage VSS (= first power supply voltage) is supplied to the negative power supply terminal T22. The drain and gate of load transistor M4 are connected to the drain of differential transistor M2, and the source is connected to the negative power supply terminal T22.

[0025] Output unit 3 is equipped with transistors M5 (=6th transistor), M6 (=7th transistor), M7 (=11th transistor), and M8 (=12th transistor), and outputs the result of comparing the currents flowing through differential transistors M1 and M2. More specifically, if the current flowing through differential transistor M2 is greater than the current flowing through differential transistor M1, output unit 3 outputs a Low state (=negative power supply voltage VSS). On the other hand, if the current flowing through differential transistor M1 is greater than the current flowing through differential transistor M2, output unit 3 outputs a High state (=positive power supply voltage VDD).

[0026] Transistors M5 and M6 are composed of N-channel field-effect transistors. Transistor M5 has its gate connected to the gate and drain of load transistor M3, and its source connected to the negative power supply terminal T22. In other words, transistor M5 is current-mirror connected to load transistor M3, copying and folding back the current flowing through load transistor M3. Transistor M6 has its gate connected to the gate and drain of load transistor M4, and its source connected to the negative power supply terminal T22. In other words, transistor M6 is current-mirror connected to load transistor M4, copying and folding back the current flowing through load transistor M4.

[0027] Transistors M7 and M8 are composed of P-channel field-effect transistors. The sources of transistors M7 and M8 are connected in common and are connected to the positive power supply terminal T21. The drain of transistor M7 is connected to the drain of transistor M5, and transistors M7 and M5 are connected in series. In addition, the gate of transistor M8 is connected to the gate and drain of transistor M7. That is, transistor M8 is current-mirror connected to transistor M7, copying and folding back the current flowing through transistor M7.

[0028] The drain of transistor M8 is connected to the drain of transistor M6, and transistors M8 and M6 are connected in series to form the output stage. The connection point between transistors M6 and M8 becomes the output of output section 3 and is connected to output terminal T3.

[0029] The constant current generating unit 4 includes transistors M10 (=8th transistor), M14 (=9th transistor), M11 (=10th transistor), and resistor R1 (=1st resistor).

[0030] Transistors M10 and M14 are composed of N-channel field-effect transistors. Transistor M10 has its source connected to the negative power supply terminal T22 via resistor R1, and its gate connected to the gate and drain of the load transistor M3. In other words, transistor M10 is current-mirror connected to the load transistor M3, and the drain current flowing through the load transistor M3 is copied and folded back to the drain current of transistor M10.

[0031] Transistor M14 has its source connected to the source of transistor M10, and its gate connected to the gate and drain of load transistor M4. In other words, transistor M14 is current-mirror connected to load transistor M4, and the drain current flowing through load transistor M4 is copied and folded back to the drain current of transistor M14. Transistors M10 and M14 are also connected in parallel.

[0032] Transistor M11 is composed of a P-channel field-effect transistor. The source of transistor M11 is connected to the positive power supply terminal T21, and the drain and gate are connected to the drains of transistors M10 and M14, respectively. In other words, transistors M10, M14 and transistor M11 are connected in series.

[0033] Furthermore, the gate of transistor M13 is connected to the gate and drain of transistor M11. In other words, transistor M13 is current-mirror connected to transistor M11, and the drain current flowing through transistor M11 is copied and folded back to the drain current of transistor M13, and current I is supplied to the differential input 2. M13 They supply it.

[0034] Next, we will describe the operation of comparator 1 in the configuration described above. First, we will describe the operation when the inverting input potential INM is higher than the non-inverting input potential INP, and the output of output terminal T3 is in a low state, that is, when the output signal is approximately the negative power supply voltage VSS.

[0035] When the inverting input potential INM is higher than the non-inverting input potential INP, more current flows from transistor M13 to differential transistor M2 than to differential transistor M1, and more current flows to load transistor M4 than to load transistor M3. Therefore, more current flows to transistors M6 and M14, which are currently mirrored to load transistor M4, than to transistors M5 and M10, which are currently mirrored to load transistor M3.

[0036] The small current flowing through transistor M5 flows to transistor M7 and is copied to the drain current of transistor M8. Transistor M8 operates to allow a small current to flow, and transistor M6 operates to allow a large current to flow, so the output signal VOUT at output terminal T3 becomes low.

[0037] Next, we will explain the operation of the constant current generator 4 when the inverting input potential INM is higher than the non-inverting input potential INP.

[0038] When power is applied, the parasitic capacitance between the drains of transistors M10, M14, and M11 and the negative power supply voltage VSS draws an excitation current from transistor M11. Since transistors M11 and M13 are current mirrored, the excitation current is copied to the drain current of transistor M13. This excitation current from transistor M13 charges the parasitic capacitance between the connection point of the drain and gate of transistor M4 and the negative power supply terminal T22. As a result of charging the parasitic capacitance, when the gate-source potential difference of transistors M4 and M14 exceeds the threshold voltage, transistors M4 and M14 change from the off state to the on state.

[0039] When sufficient current flows through transistors M11, M13 and M4, M14, the system enters a stable state and transitions to a steady state.

[0040] When transistors M4 and M14 operate in the subthreshold region, the drain current changes exponentially with respect to changes in the gate-source potential difference. The constant current I generated by the constant current generation unit 4 REF (=I M13 The circuit current I4 of the constant current generating unit 4 is expressed by the following equations 3 and 4.

[0041]

number

[0042]

number

[0043] Here, K M4 This is the aspect ratio (=W / L) of transistor M4, K M14 V is the aspect ratio (=W / L) of transistor M4, where W is the gate width, L is the gate length, and V is the gate width. T θ is the thermal voltage (=kT / q), where k is the Boltzmann coefficient, T is the absolute temperature, q is the unit charge of an electron, and η is the subthreshold swing coefficient.

[0044] As is clear from Equation 3, the constant current I REF This is the resistance value of resistor R1 and the aspect ratio K. M4 ,K M14 The value will be determined accordingly and will not be affected by fluctuations in the positive power supply voltage VDD or the negative power supply voltage VSS.

[0045] The constant current I generated by the constant current generation unit 4 REF This supplies current to the differential input section 2 via transistor M13, which is currently mirrored to transistor M11.

[0046] Next, we will explain the operation when the non-inverting input potential INP is higher than the inverting input potential INM, and the output of output terminal T3 is in a High state, i.e., the output signal VOUT is approximately equal to the positive power supply voltage VDD.

[0047] When the non-inverting input potential INP is higher than the inverting input potential INM, more current flows from transistor M13 to differential transistor M1 than to differential transistor M2, and more current flows to load transistor M3 than to load transistor M4. Therefore, more current flows to transistors M5 and M10, which are currently mirrored to load transistor M3, than to transistors M6 and M14, which are currently mirrored to load transistor M4.

[0048] The large current flowing through transistor M5 flows to transistor M7 and is copied to the drain current of transistor M8. Transistor M8 operates to allow a large current to flow, and transistor M6 operates to allow a small current to flow, so the output signal VOUT at output terminal T3 becomes high.

[0049] Next, we will explain the operation of the constant current generator 4 when the non-inverting input potential INP is higher than the inverting input potential INM.

[0050] When power is applied, the parasitic capacitance between the drains of transistors M10, M14, and M11 and the negative power supply voltage VSS draws an excitation current from transistor M11. Since transistors M11 and M13 are current mirrored, the excitation current is copied to the drain current of transistor M13. This excitation current from transistor M13 charges the parasitic capacitance between the connection point of the drain and gate of transistor M3 and the negative power supply terminal T22. As a result of charging the parasitic capacitance, when the gate-source potential difference of transistors M3 and M10 exceeds the threshold voltage, transistors M3 and M10 change from the off state to the on state.

[0051] When sufficient current flows through transistors M11, M13 and M3, M10, the system enters a stable state and transitions to a steady state.

[0052] When transistors M3 and M10 operate in the subthreshold region, the drain current changes exponentially with respect to changes in the gate-source potential difference. The constant current I generated by the constant current generation unit 4 REF The circuit current I4 of the constant current generating unit 4 is expressed by the following equations 5 and 6.

[0053]

number

[0054]

number

[0055] Here, K M3 This is the aspect ratio (=W / L) of transistor M3, K M10 V is the aspect ratio (=W / L) of transistor M10, where W is the gate width, L is the gate length, and V is the gate width. T θ is the thermal voltage (=kT / q), where k is the Boltzmann coefficient, T is the absolute temperature, q is the unit charge of an electron, and η is the subthreshold swing coefficient.

[0056] The constant current I generated by the constant current generation unit 4 REF This supplies current to the differential input section 2 via transistor M13, which is currently mirrored to transistor M11.

[0057] As described above, the differential input section 2 has a circuit configuration that also serves the functions of transistors M9 and M12 of the constant current generation section 104 in the conventional comparator 100 circuit configuration example shown in Figure 8, and the steady current I flowing through transistors M9 and M12 M9 =I REF It can be reduced.

[0058] In other words, the comparator 1 in this first embodiment can reduce the circuit current I4 of the constant current generation unit 4.

[0059] Furthermore, the constant current generation unit 4 in the first embodiment constitutes a bandgap reference circuit, similar to the conventional design. That is, transistors M3 and M4 also perform the functions of the conventional transistor M9, and are arranged so that the area ratio of transistors M3 and M4 to transistors M10 and M14 is 1:N (N>1). Also, transistor M13 performs the functions of the conventional transistor M12, and a current mirror circuit composed of transistors M11 and M13 ensures that the same drain current flows through transistors M3 and M4 and transistors M10 and M14. Therefore, when transistor M3 is ON, the gate-source voltage V of transistors M3 and M10 is GSM3 ,V GSM10 A difference occurs, and when transistor M4 is ON, the gate-source voltage V of transistors M4 and M14 GSM4 ,V GSM14 A difference arises. Current I flowing through transistor M11 M11 (=I REF ) is (V GSM3 -V GSM10 ) / R1=(V GSM4 -V GSM14 ) / R1. As before, even if the positive power supply voltage VDD and negative power supply voltage VSS fluctuate, the constant current I REF It can be kept constant.

[0060] Therefore, the effect of reducing current consumption is achieved without causing a decrease in response speed.

[0061] (Second Embodiment) Next, the comparator 1B of the second embodiment will be described with reference to Figure 2. In Figure 2, components identical to those in the circuit shown in Figure 1 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0062] As shown in the figure, the comparator 1B includes a differential input section 2, an output section 3, a constant current generation section 4, and a constant current stabilization section 5 (=current stabilization section). The differential input section 2, output section 3, and constant current generation section 4 are the same as those in the first embodiment described above, so a detailed explanation is omitted here.

[0063] The constant current stabilization unit 5 includes a transistor M15 (=13th transistor) and a resistor R2 (=2nd resistor), and when the potential difference between the common-mode input potential of the differential input unit 2 and the positive power supply voltage VDD becomes small, the drain current of transistor M13 is cut off, preventing the constant current generation unit 4 from stopping.

[0064] Transistor M15 is composed of a P-channel field-effect transistor. The source of transistor M15 is connected to the sources of differential transistors M1 and M2, respectively, and the drain is connected to the drain of transistor M1. In other words, transistor M15 and transistor M1 are connected in parallel. Resistor R2 is connected between the connection point of the drain and gate of transistor M11 and the connection point of the drains of transistors M10 and M14 and the gate of transistor M15.

[0065] Next, the operation of comparator 1B in the configuration described above will be explained. In this configuration, comparator 1B is basically the same as in the first embodiment, except for the points described later.

[0066] In the circuit configuration of the comparator 1 of the first embodiment, the common-mode input potential range V of the differential input section 2 where the drain current of transistor M13 is not interrupted. ICM This is expressed by equation 7 below.

[0067]

number

[0068] The potential difference between the common-mode input potential of the differential input section 2 and the power supply voltage VDD is equal to the threshold voltage V of transistors M1 and M2.TH The drain-source potential difference V of transistor M13 DS13 When the potential difference becomes smaller than the applied potential difference, the drain current of transistors M1 and M2 is cut off.

[0069] In the circuit configuration of comparator 1B of the second embodiment, a constant current stabilization unit 5 is provided to suppress the interruption of the drain current of transistor M13 when the potential difference between the common-mode input potential of the differential input unit 2 and the power supply voltage VDD becomes small.

[0070] The common-mode input potential of differential input section 2 rises, causing the gate potentials of transistors M1 and M2 to rise, and the gate potential of transistor M15 V G15 When the value exceeds (=Equation 8), transistors M1 and M2 turn off, but transistor M15 turns on, so the drain current of transistor M13 flows to transistor M3 through transistor M15.

[0071]

number

[0072] As a result, current flows to transistor M10, which is currently mirrored to transistor M3, the drain currents of transistors M11 and M13 are not interrupted, and the operation of the constant current generator 4 does not stop. Note that the gate potential V of transistor M15 G15 The common-mode input potential range V ICM The maximum value (= VDD - (V TH +V DS13 The resistor R2 is set so that the following occurs. As a result, the common-mode input potential is within the common-mode input potential range V ICM Before exceeding the maximum value, the gate potential V of transistor M15 G15 Beyond this point, transistor M15 turns on.

[0073] In other words, in this second embodiment, the comparator 1B is equipped with a constant current stabilization unit 5, so that even if the potential difference between the common-mode input potential of the differential input unit 2 and the power supply voltage VDD becomes small, the operation of the constant current generation unit 4 does not stop. Therefore, the current generated by the constant current generation unit 4 can be copied and folded back by current mirror connection with transistor M11, and supplied to circuit blocks other than the comparator 1B.

[0074] Therefore, the current generated by the constant current generation unit 4 can be supplied to circuit blocks other than the comparator 1B (not shown), and the effect of reducing current consumption without causing a decrease in response speed can be obtained.

[0075] Furthermore, by providing a resistor R2 and connecting the connection point between resistor R2 and transistors M10 and M14 to the gate of transistor M15, the gate voltage at which transistor M15 can be turned on can be adjusted by resistor R2.

[0076] Furthermore, by connecting transistor M15 in series with load transistor M3, current can continue to flow to load transistor M3 and transistor M10 even after transistor M15 is turned on.

[0077] Furthermore, in the second embodiment described above, the drain of transistor M15 was connected to the drain of transistor M1, but this is not the only option. The same effect can be obtained by connecting the drain of transistor M15 to the drain of transistor M2.

[0078] (Third embodiment) Next, the comparator 1C of the third embodiment will be described with reference to Figure 3. In Figure 3, components identical to those in the circuit shown in Figure 2 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0079] As shown in the figure, the comparator 1C comprises a differential input section 2, an output section 3, a constant current generation section 4, and a constant current stabilization section 5C (=current stabilization section). The differential input section 2, output section 3, and constant current generation section 4 are the same as those in the second embodiment described above, so a detailed explanation is omitted here.

[0080] The difference between the constant current stabilization unit 5 of the second embodiment and the constant current stabilization unit 5C of the third embodiment is that the drain of transistor M15C (=13th transistor), which corresponds to transistor M15, is connected to a different location, and transistors M16 (=14th transistor) and M17 (15th transistor) are provided.

[0081] The constant current stabilization unit 5C comprises transistors M15C, M16, and M17, and resistor R2. When the potential difference between the common-mode input potential of the differential input unit 2 and the power supply voltage VDD becomes small, the drain current of transistor M13 is interrupted, preventing the constant current generation unit 4 from stopping.

[0082] Transistor M15C is composed of P-channel field-effect transistors. The source of transistor M15C is connected to the respective sources of differential transistors M1 and M2, and the gate is connected to the connection point between resistor R2 and the respective drains of transistors M10 and M14.

[0083] Transistors M16 and M17 are composed of N-channel field-effect transistors. Transistor M16 has its drain and gate connected to the drain of transistor M15C, and its source connected to the negative power supply terminal T22. Transistor M17 has its drain connected to the drains of transistors M10 and M14, its gate connected to the gate of transistor M16, and its source connected to the sources of transistors M10 and M14. In other words, transistor M17 is current-mirror connected to transistor M16, copying and folding back the current flowing through transistor M16.

[0084] Next, the operation of comparator 1C in the above-described configuration will be explained. In this configuration, comparator 1C is basically the same as in the second embodiment, except for the points described later.

[0085] The common-mode input potential of differential input section 2 rises, causing the gate potentials of transistors M1 and M2 to rise, and the gate potential of transistor M15C to rise. G15C When the value exceeds (=Equation 9), transistors M1 and M2 turn off, but transistor M15C turns on, so the drain current of transistor M13 flows to transistor M16 through transistor M15C.

[0086]

number

[0087] As a result, current flows to transistor M17, which is currently mirrored to transistor M16, without interrupting the drain currents of transistors M11 and M13, and the operation of the constant current generator 4 does not stop.

[0088] In other words, in this third embodiment, the comparator 1C is provided with a constant current stabilization unit 5C, so that even if the potential difference between the common-mode input potential of the differential input unit 2 and the power supply voltage VDD becomes small, the operation of the constant current generation unit 4 does not stop. Therefore, the current generated by the constant current generation unit 4 can be copied and folded back by current mirror connection with transistor M11, and supplied to circuit blocks other than the comparator 1C.

[0089] Therefore, the current generated by the constant current generation unit 4 can be supplied to circuit blocks other than the comparator 1C, and the effect of reducing current consumption without causing a decrease in response speed can be obtained.

[0090] (Fourth Embodiment) Next, the comparator 1D of the fourth embodiment will be described with reference to Figure 4. In Figure 4, components identical to those in the circuit shown in Figure 3 are given the same reference numerals, and their detailed descriptions are omitted.

[0091] As shown in the figure, the comparator 1D includes a differential input section 2, an output section 3D, a constant current generation section 4, a constant current stabilization section 5C, and a differential input section 6 (= second differential input section). The differential input section 2, the constant current generation section 4, and the constant current stabilization section 5C are the same as those in the third embodiment described above, so a detailed explanation is omitted here.

[0092] The differential input section 6 includes differential transistors M61 (=16th differential transistor), M62 (=17th differential transistor), load transistor M63 (=18th load transistor), load transistor M64 (=19th load transistor), and transistor M65 (=20th transistor). The differential input section 2 and the differential input section 6 constitute a rail-to-rail differential input stage.

[0093] The differential transistors M61 and M62 are composed of N-channel field-effect transistors. The gate of differential transistor M61 is connected to the inverting input terminal T11. The gate of differential transistor M62 is connected to the non-inverting input terminal T12, and its drain is connected to the drain and gate of transistor M64.

[0094] The load transistors M63 and M64 are composed of P-channel field-effect transistors. The drain and gate of load transistor M63 are connected to the drain of differential transistor M61, and the source is connected to the positive power supply terminal T21. In other words, load transistor M63 and differential transistor M61 are connected in series. The drain and gate of load transistor M64 are connected to the drain of differential transistor M62, and the source is connected to the positive power supply terminal T21. In other words, load transistor M64 and differential transistor M62 are connected in series.

[0095] The differential input section 6 receives the current I supplied by transistor M65. M65 The current is divided between differential transistors M61 and M62. The current ratio (division ratio) of the currents flowing through differential transistors M61 and M62 is a value corresponding to the potential difference between the inverting input potential INM and the non-inverting input potential INP.

[0096] Transistor M65 is composed of an N-channel field-effect transistor. The source of transistor M65 is connected to the negative power supply terminal T22, the drain is connected to the sources of differential transistors M61 and M62 respectively, and the gate is connected to the gate and drain of transistor M16. In other words, transistor M65 is current-mirror connected to transistor M16, which flows when transistor M15C is turned on, and the current flowing through transistor M16 is folded back and supplied to the differential input section 6.

[0097] Output unit 3D has the same transistors M5 and M6 as output unit 3, as well as transistors M18 (=21st transistor), M19 (=22nd transistor), M20 (=23rd transistor), and M21 (=24th transistor). Transistors M18 and M21 are made up of P-channel field-effect transistors. Transistors M19 and M20 are made up of N-channel field-effect transistors.

[0098] Transistor M18 has its drain connected to the drain and gate of transistor M19, its gate connected to the gate and drain of load transistor M63, and its source connected to the positive power supply terminal T21. In other words, transistor M18 is current-mirror connected to load transistor M63, copying and folding back the current flowing through load transistor M63.

[0099] Transistor M20 has its drain connected to the drain of transistor M6, its gate connected to the gate and drain of transistor M19, and its source connected to the negative power supply terminal T22. In other words, transistor M20 is current-mirror connected to transistor M19, copying and folding back the current flowing through transistor M19.

[0100] Additionally, transistors M5 and M64 are connected in series, transistors M6 and M21 are connected in series, and transistors M20 and M6 are connected in parallel.

[0101] Next, the operation of comparator 1D in the above configuration will be described. In this configuration, comparator 1D is basically the same as in the third embodiment, except for the points described later.

[0102] Transistor M65 is current-mirror connected to transistor M16, and the drain current flowing through transistor M16 is copied and folded back to the drain current of transistor M65.

[0103] As a result, the common-mode input potentials of differential input section 2 and differential input section 6 are equal to the gate potential V of transistor M15C. G15C If the value is less than the threshold, transistor M15C turns off, and the drain current of transistor M13 is supplied as the tail current of differential input 2. On the other hand, the common-mode input potential of differential input 2 and differential input 6 is the gate potential V of transistor M15C. G15C If the value exceeds a certain limit, transistor M15C turns on and transistors M1 and M2 turn off, so the drain current of transistor M13 is supplied as the tail current of the differential input section 6 via transistors M15C, M16, and M65.

[0104] In other words, in this fourth embodiment, the comparator 1D connects transistor M65 to constant current stabilization unit 5C, so that when the potential difference between the common-mode input potential of differential input unit 2 and the power supply voltage VDD becomes small, the supply of drain current from transistor M13 is switched from differential input unit 2 to differential input unit 6, thereby enabling the configuration of a comparator having a rail-to-rail differential input stage.

[0105] Therefore, by configuring a comparator with a rail-to-rail differential input stage, the effect of reducing current consumption without causing a decrease in response speed is obtained.

[0106] Furthermore, in the fourth embodiment, the output section 3D of the comparator 1D outputs the comparison result of the currents flowing through the load transistors M3 and M4 when transistor M15C is off, and outputs the comparison result of the currents flowing through the load transistors M63 and M64 when transistor M15C is on.

[0107] (Fifth embodiment) Next, the comparator 1E of the fifth embodiment will be described with reference to Figure 5. In Figure 5, components identical to those in the circuit shown in Figure 1 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0108] As shown in the figure, the comparator 1E includes a differential input section 2, an output section 3, a constant current generation section 4, and a minute current supply section 7. The differential input section 2, output section 3, and constant current generation section 4 are the same as those in the first embodiment described above, so a detailed explanation is omitted here.

[0109] The minute current supply unit 7 is equipped with transistors M71 (the 25th transistor) and M72 (the 26th transistor), which constitute a minute constant current source.

[0110] Transistors M71 and M72 are composed of P-channel field-effect transistors. Transistor M71 has its gate connected to the gate and drain of transistor M11, and its drain connected to the drain and gate of transistor M3. Transistor M72 has its gate connected to the gate and drain of transistor M11, and its drain connected to the drain and gate of transistor M4.

[0111] Transistors M71 and M72 are current-mirror connected to transistor M11, and the drain current flowing through transistor M11 is copied and folded back to the drain currents of transistors M71 and M72. By increasing the ratio N of the accept ratio (=W / L) of transistors M71 and M72 to the accept ratio (=W / L) of transistor M11, transistors M71 and M72 fold back 1 / N (N>1) of the current flowing through transistor M11, generating a minute current.

[0112] The minute currents supplied by transistors M71 and M72 are used to supply a minute current to load transistors M3 and M4, to which differential transistors M1 and M2 are connected, respectively, which switch on and off according to the inverting input potential INM and the non-inverting input potential INP. By supplying this minute current to the load transistor that is to be turned off, the load transistor can remain in the ON state instead of being turned off, thereby improving the delay of the switching operation of the load transistor.

[0113] As a result, fluctuations in the current generated by the constant current generator 4 during the transition period when the load transistor is switched on and off are suppressed by improving the delay of the switching operation of the load transistor.

[0114] Therefore, by providing the minute current supply unit 7, the current generated by the constant current generation unit 4 is stabilized, and the effect of reducing current consumption without causing a decrease in response speed is obtained.

[0115] (Sixth Embodiment) Next, the comparator 1F of the sixth embodiment will be described with reference to Figure 6. In Figure 6, components identical to those in the circuit shown in Figure 1 are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0116] As shown in the figure, the comparator 1F comprises a differential input section 2, an output section 3, a constant current generation section 4, and a minute current supply section 7F. The differential input section 2, output section 3, and constant current generation section 4 are the same as those in the first embodiment described above, so a detailed explanation is omitted here.

[0117] The minute current supply unit 7F includes transistor M75 (the 27th transistor), which constitutes a minute constant current source, as well as differential transistors M73 (the 29th transistor) and M74 (the 28th transistor).

[0118] Transistor M75 is composed of P-channel field-effect transistors. The gate of transistor M75 is connected to the gate and drain of transistor M11, and the drain is connected to the sources of differential transistors M73 and M74, respectively.

[0119] Transistor M75 is current-mirror connected to transistor M11, and the drain current flowing through transistor M11 is copied and folded back to the drain current of transistor M75. By increasing the ratio N of the accept ratio (=W / L) of transistor M75 and the accept ratio (=W / L) of transistor M11, transistor M75 folds back 1 / N (N>1) of the current flowing through transistor M11, generating a minute current.

[0120] The differential transistors M73 and M74 are composed of P-channel field-effect transistors. The gate of differential transistor M73 is connected to the gate of transistor M1, and its drain is connected to the drain and gate of transistor M4. The gate of differential transistor M74 is connected to the gate of transistor M2, and its drain is connected to the drain and gate of transistor M3.

[0121] The minute current supplied from transistor M75 is used to supply a minute current to load transistors M3 and M4, to which differential transistors M73 and M74 are connected, respectively, which switch on and off according to the inverting input potential INM and the non-inverting input potential INP. By supplying this minute current to the load transistor that is to be turned off, the load transistor can remain in the ON state instead of being turned off, thereby improving the delay of the load transistor's switching operation.

[0122] As a result, fluctuations in the current generated by the constant current generator 4 during the transition period when the load transistor is switched on and off are suppressed by improving the delay of the switching operation of the load transistor.

[0123] Therefore, by providing the minute current supply unit 7F, the current generated by the constant current generation unit 4 is stabilized, and the effect of reducing current consumption without causing a decrease in response speed is obtained.

[0124] Furthermore, in the sixth embodiment described above, the sources of differential transistors M73 and M74 were connected to the drains of transistor M75, but this is not the only option. The sources of differential transistors M73 and M74 were connected to the drains of transistor M13. That is, transistor M13 was connected in series with transistors M73 and M74. In addition, transistor M73 was current-mirror connected to differential transistor M1, and transistor M74 was current-mirror connected to differential transistor M2.

[0125] By increasing the ratio N between the accept ratio (=W / L) of differential transistor M73 and the accept ratio (=W / L) of differential transistor M1, transistor M73 can fold back 1 / N (N>1) of the current flowing through differential transistor M1 and supply it to load transistor M4. Similarly, by increasing the ratio N between the accept ratio (=W / L) of differential transistor M74 and the accept ratio (=W / L) of differential transistor M2, transistor M74 can fold back 1 / N of the current flowing through differential transistor M2 and supply it to load transistor M3. The same effect is obtained in this case as well.

[0126] (Seventh Embodiment) Next, the comparator 1G of the seventh embodiment will be described with reference to Figure 7. In Figure 7, components identical to those in the circuit shown in Figure 1 are given the same reference numerals, and their detailed descriptions are omitted.

[0127] As shown in the figure, the comparator 1G includes a differential input section 2G, an output section 3G, and a constant current generation section 4G, similar to the first embodiment.

[0128] The difference between the first embodiment and the seventh embodiment is that the conductivity types of transistors M1G-M8G, M10G, M11G, M13G, and M14G, which correspond to transistors M1-M8, M10, M11, M13, and M14, are reversed. Another difference between the first embodiment and the seventh embodiment is that the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 is reversed.

[0129] Similarly, in the second to sixth embodiments, the conductivity type of the transistor may be reversed, and the relationship between the positive power supply terminal T21 and the negative power supply terminal T22 may be reversed.

[0130] Similar to the first embodiment, the seventh embodiment also achieves the effect of reducing current consumption without causing a decrease in response speed.

[0131] Furthermore, the present invention is not limited to the embodiments described above, and can be modified, improved, etc., as appropriate. In addition, the material, shape, dimensions, number, placement, etc. of each component in the embodiments described above are arbitrary and not limited, as long as they can achieve the present invention.

[0132] For example, in the first to seventh embodiments described above, the transistors were composed of field-effect transistors, but this is not limited to them. At least one or more transistors may be replaced with bipolar transistors. In this case, the explanation can be given by substituting the gate of the transistor with the base, the source with the emitter, and the drain with the collector.

[0133] Furthermore, in the first to seventh embodiments described above, two transistors M5(G) and M10(G) were connected to the gate of one load transistor M3(G), but this is not the only option. Two load transistors M3(G) may be provided, and transistors M5(G) and M10(G) may be connected to each of them. Similarly, two load transistors M4(G) may be provided, and transistors M6(G) and M14(G) may be connected to each of them. [Explanation of Symbols]

[0134] 1,1B~1G Comparator 2.2G Differential Input Section (First Differential Input Section) 3,3D,3G output section 4.4G Constant Current Generator (Current Generator) 5,5C constant current stabilization section (current stabilization section) 6. Differential input section (second differential input section) 7,7F Micro current supply section INM inverting input potential (first input potential) INP Non-inverting input potential (second input potential) M1, M1G Differential Transistors (First Differential Transistors) M2, M2G differential transistors (second differential transistors) M3, M3G Load transistor (third load transistor) M4, M4G Load transistor (fourth load transistor) M5, M5G transistors (the sixth transistor) M6, M6G transistors (the seventh transistor) M7, M7G transistors (the 11th transistor) M8, M8G transistors (the 12th transistor) M10, M10G transistors (the 8th transistor) M11, M11G transistors (10th transistors) M13, M13G transistors (the fifth transistor) M14, M14G transistors (the 9th transistor) M15, M15C transistors (the 13th transistor) M16 Transistor (14th Transistor) M17 Transistor (15th transistor) M18 Transistor (21st Transistor) M19 Transistor (22nd Transistor) M20 transistor (the 23rd transistor) M21 Transistor (24th Transistor) M61 Differential Transistor (16th Differential Transistor) M62 Differential Transistor (17th Differential Transistor) M63 Load Transistor (18th Load Transistor) M64 Load Transistor (19th Load Transistor) M65 transistor (20th transistor) M71 Transistor (25th Transistor) M72 transistor (26th transistor) M73 Transistor (29th Transistor) M74 Transistor (28th Transistor) M75 Transistor (27th Transistor) R1, R1G Resistors (First resistors) R2 Resistor (Second resistor) T21 Positive power terminal (second power terminal) T22 Negative power terminal (first power terminal) VDD: Positive power supply voltage (second power supply voltage) VSS Negative power supply voltage (first power supply voltage)

Claims

1. A first differential transistor and a second differential transistor, each through which a current with a current ratio corresponding to the potential difference between a first input potential and a second input potential flows, A third load transistor is connected between the drain or collector of the first differential transistor and the first power supply terminal to which the first power supply voltage is supplied, A fourth load transistor connected between the drain or collector of the second differential transistor and the first power supply terminal, A first differential input section having the first differential transistor and a fifth transistor connected between the source or emitter of the second differential transistor and a second power supply terminal to which a second power supply voltage is supplied, A sixth transistor is connected to the third load transistor via a current mirror, The fourth load transistor is connected to a seventh transistor via a current mirror, An output unit that outputs the comparison result of the currents flowing through the third load transistor and the fourth load transistor, The third load transistor and the fourth load transistor are currently mirrored to each other, and the eighth and ninth transistors are connected in parallel to each other, A first resistor connected between the source or emitter of the eighth transistor and the ninth transistor and the first power supply terminal, The current generating unit comprises a current generating unit having a tenth transistor connected between the drain or collector of the eighth transistor and the ninth transistor and the second power supply terminal, The fifth transistor is currently mirrored to the tenth transistor. comparator.

2. In the comparator according to claim 1, The output section has an eleventh transistor connected in series with the sixth transistor and a twelfth transistor connected in current mirror with the eleventh transistor, and the seventh transistor and the twelfth transistor are connected in series, with the connection point being the output. comparator.

3. In the comparator according to claim 1, The present invention has a thirteenth transistor connected in series with the fifth transistor, The current stabilization unit is provided that, when the potential difference between the common-mode input potential of the first differential input section and the second power supply voltage decreases and the first and second differential transistors turn off, the 13th transistor turns on and continues to supply drain current or collector current to the 5th transistor. comparator.

4. In the comparator according to claim 3, The current stabilization unit has a second resistor connected between the 10th transistor, the 8th transistor and the 9th transistor, The connection point between the second resistor and the eighth and ninth transistors is connected to the gate or base of the thirteenth transistor. comparator.

5. In the comparator according to claim 3, The 13th transistor is connected in parallel to the first differential transistor and in series to the third load transistor. comparator.

6. In the comparator according to claim 3, The current stabilization unit includes a 14th transistor connected in series with the 13th transistor, and a 15th transistor connected in current mirror connection to the 14th transistor and in parallel with the 8th and 9th transistors. The 13th transistor and the 14th transistor are connected in parallel to the first differential transistor and the third load transistor, and to the second differential transistor and the fourth load transistor. comparator.

7. In the comparator according to claim 3, A 16th differential transistor and a 17th differential transistor through which currents with a current ratio corresponding to the potential difference between the first input potential and the second input potential flow, A 18th load transistor connected between the drain or collector of the 16th differential transistor and the second power supply terminal, A 19th load transistor connected between the drain or collector of the 17th differential transistor and the second power supply terminal, The device comprises a second differential input section having the 16th differential transistor and a 20th transistor connected between the source or emitter of the 17th differential transistor and the first power supply terminal, When the 13th transistor is turned on, the 20th transistor is turned on to supply current to the second differential input. comparator.

8. In the comparator according to claim 7, The current stabilization unit includes a 14th transistor connected in series with the 13th transistor, and a 15th transistor connected in current mirror connection to the 14th transistor and in parallel with the 8th and 9th transistors. The 20th transistor is currently mirrored to the 14th transistor. comparator.

9. In the comparator according to claim 8, The output unit includes a 21st transistor currently mirrored to the 18th load transistor, a 22nd transistor connected in series with the 21st transistor, a 23rd transistor currently mirrored to the 22nd transistor, and a 24th transistor currently mirrored to the 19th load transistor. The sixth transistor and the 19th load transistor are connected in series. The seventh transistor and the twenty-fourth transistor are connected in series, and the connection point becomes the output. The seventh transistor and the 23rd transistor are connected in parallel. comparator.

10. In the comparator according to claim 1, The third load transistor and the fourth load transistor are provided with a minute current supply unit that supplies a minute current smaller than the current supplied from the current generation unit to the first differential input unit. comparator.

11. In the comparator according to claim 10, The minute current supply unit has a 25th transistor and a 26th transistor that fold back a current of 1 / N (N>1) of the current flowing through the 10th transistor. The 25th transistor and the 3rd load transistor are connected in series. The 26th transistor and the 4th load transistor are connected in series. comparator.

12. In the comparator according to claim 10, The minute current supply unit includes a 27th transistor that folds back 1 / N (N>1) of the current flowing through the 10th transistor, and a 28th transistor and a 29th transistor connected in series with the 27th transistor. The 28th transistor and the 3rd load transistor are connected in series. The 29th transistor and the 4th load transistor are connected in series. comparator.

13. In the comparator according to claim 10, The minute current supply unit includes a 28th transistor connected in series with the 5th transistor and in current mirror connection with the 2nd differential transistor, which folds back 1 / N (N>1) of the current flowing through the 2nd differential transistor, and a 29th transistor connected in series with the 5th transistor and in current mirror connection with the 1st differential transistor, which folds back 1 / N of the current flowing through the 1st differential transistor. The 28th transistor and the 3rd load transistor are connected in series. The 29th transistor and the 4th load transistor are connected in series. comparator.

14. In the comparator according to any one of claims 1 to 13, At least one of the aforementioned transistors is composed of a field-effect transistor. comparator.

15. In the comparator according to any one of claims 1 to 13, At least one of the aforementioned transistors is composed of a bipolar transistor. comparator.

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