Identify valid data window

Abstract

This application relates to identifying valid data windows. A tester includes an interface configured to interface with an electronic device and logic circuitry. The logic circuitry includes a pattern generator and at least one finite state machine, and is configured to: sequentially acquire read data from the electronic device at sequential test points within a test range for evaluating operating parameters of the electronic device or the tester, until a set of consecutive pass points with a first pass point and a last pass point is identified; in response to identifying the first pass point, write data identifying the first pass point into the logic circuitry of the tester; in response to identifying the last pass point, write data identifying the last pass point into the logic circuitry of the tester; and output only the data identifying the first pass point and the data identifying the last pass point to a software application.

Description

[0001] Priority Statement

[0002] This application claims the benefit of U.S. Patent Application No. 17 / 153,726, entitled “IDENTIFYING DATAVALID WINDOWS”, filed January 20, 2021. Technical Field

[0003] The embodiments of this disclosure generally relate to electronic device testers, methods for testing electronic devices, and related systems and methods. Background Technology

[0004] Electronic devices (e.g., microelectronic devices, semiconductor devices, memory devices) typically require testing to verify functionality. For example, semiconductor devices (e.g., integrated circuits) often undergo functional testing, in which input signals are fed into the electronic device and output signals from the electronic device are observed to verify the proper functioning of the electronic device.

[0005] Electronic device testers (e.g., memory device testers) typically utilize graphics generators (e.g., algorithm graphics generators) to generate test patterns for testing electronic devices, particularly memory devices. The graphics generator is used to encode instructions for testing data read / write operations.

[0006] As the capacity of electronic devices (e.g., memory devices) increases, the time required to test them also increases. For example, electronic device testers typically test (e.g., scan) the device to identify a test range (e.g., time period, voltage range, etc.) within which the device's conditions return the expected results (e.g., data read). Furthermore, during testing, each point in the test range is run, the results for each point are stored, and the stored data is subsequently analyzed (e.g., categorized) using software to determine the boundaries of the valid data window. Moreover, the stored data typically contains multiple results for each pin. Therefore, the time required to read, store, and process all results adds a significant amount of testing time to the electronic device testing (e.g., scanning). Summary of the Invention

[0007] Embodiments of this disclosure include an apparatus (e.g., a tester). The apparatus includes a graphics generator, at least one finite state machine, and logic circuitry. The logic circuitry is configured to: evaluate an electronic device at a first test point within a test range for evaluating the selected operating parameters, in response to selected operating parameters to be evaluated, comprising: acquiring read data from the electronic device at the first test point within the test range; and writing data within the logic circuitry indicating that the first test point is a first pass point, at least in part based on a first value of the read data associated with the first test point; evaluate the electronic device at a second test point within the test range, comprising: acquiring read data from the electronic device at the second test point within the test range; and writing data within the logic circuitry indicating that the second test point is a first pass point, at least in part based on a second value of the read data associated with the second test point; evaluate the electronic device at one or more additional test points within the test range until a first pass point and a last pass point are identified; and after identifying the last pass point, writing data within the logic circuitry indicating the last pass point.

[0008] One or more embodiments of this disclosure include a method. The method may include: sequentially acquiring read data from an electronic device at sequential test points within a test range for evaluating operating parameters of an electronic device or an electronic device tester, until a first pass point and a last pass point of a set (e.g., multiple) of consecutive pass points are identified; in response to identifying the first pass point, writing data identifying the first pass point into the logic chip of the electronic device tester; in response to identifying the last pass point, writing data identifying the last pass point into the logic chip of the electronic device tester; determining whether a data validity window represented by the identified first pass point and the identified last pass point is greater than or equal to a user-defined acceptable data validity window. The evaluation of the electronic device is terminated upon determining that the data valid window represented by the first and last identified pass points is greater than or equal to a user-defined acceptable data valid window; upon determining that the data valid window represented by the first and last identified pass points is not greater than or equal to a user-defined acceptable data valid window, the evaluation of the electronic device continues at other test points in the sequential test points of the test range until a new first and a new last pass point of a new set of consecutive pass points are identified; and the operating parameters of the electronic device or the electronic device tester are evaluated at least in part based on the data valid window.

[0009] Some embodiments of this disclosure include an apparatus. The apparatus includes an interface (e.g., a probe card (pin-type, vertical, and MEMS (microelectromechanical systems) type), a non-contact probe (e.g., an RF probe), any conventional interface) configured to interface with an electronic device, and logic circuitry. The logic circuitry includes a graphics generator and at least one finite state machine. The logic circuitry is configured to: sequentially acquire read data from the electronic device at sequential test points within a test range used to evaluate the operating parameters of the electronic device or tester, until a set of consecutive pass points with a first pass point and a last pass point is identified; write data identifying the first pass point into the logic circuitry of the tester in response to identifying the first pass point; write data identifying the last pass point into the logic circuitry of the tester in response to identifying the last pass point; and output only the data identifying the first pass point and the data identifying the last pass point to a software application.

[0010] Embodiments of this disclosure include a method. The method may include: sequentially acquiring read data from an electronic device at sequential test points within a test range for evaluating the operating parameters of an electronic device or a tester, until a window containing a set of consecutive pass points having a first pass point and a last pass point is identified; writing data into the logic circuitry of the tester in response to identifying the first pass point; writing data into the logic circuitry of the tester in response to identifying the last pass point; outputting only the data identifying the first pass point and the data identifying the last pass point to a software application; and evaluating the operating parameters of the electronic device or electronic device tester based at least in part on the data identifying the first pass point and the data identifying the last pass point. Attached Figure Description

[0011] Figure 1 A schematic diagram illustrating an electronic device tester according to one or more embodiments of the present disclosure;

[0012] Figure 2 A flowchart illustrating a method for testing an electronic device according to one or more embodiments of the present disclosure;

[0013] Figure 3 A flowchart illustrating a method for testing an electronic device according to one or more embodiments of the present disclosure; and

[0014] Figure 4 A flowchart illustrating the state machine logic of an electronic device according to one or more embodiments of the present disclosure is provided. Detailed Implementation

[0015] The illustrations presented herein are not actual views of any particular electronic device (e.g., a semiconductor device) or electronic device tester, but are merely idealized representations used to describe exemplary embodiments of this disclosure. The following description provides specific details of embodiments of this disclosure in order to provide a thorough description thereof. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without such specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional techniques used in the industry. Furthermore, the description provided below does not include all elements forming a complete structure or assembly. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional conventional actions and structures may be used. It should also be noted that any accompanying drawings are for illustrative purposes only and are therefore not drawn to scale. Additionally, elements shared between the drawings may have corresponding numerical designations.

[0016] As used herein, the terms “comprising,” “including,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional unlisted elements or method steps, and also include the more restrictive terms “consisting of” and “substantially consisting of” and their grammatical equivalents.

[0017] As used herein, the term “may” refers to materials, structures, features, or methodological actions and indicates that such persons are intended for use in implementing embodiments of this disclosure, and such terms are preferred to be used in the more restrictive sense of the term “yes” in order to avoid any implication that they correspond to or must exclude other compatible materials, structures, features, and methods that may be used in combination with them.

[0018] As used herein, the term “configuration” refers to the size, shape, material composition, material distribution, orientation, and arrangement of one or more of at least one structure and at least one device in order to facilitate the operation of one or more of the structure and device in a predetermined manner.

[0019] As used herein, unless the context clearly indicates otherwise, the singular forms “a / an” and “the” are intended to include the plural forms as well.

[0020] As used herein, the term “and / or” includes any and all combinations of one or more of the associated enumerations.

[0021] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes, to a degree, that a given parameter, property, or condition will be understood by one of ordinary skill in the art to be satisfied with a certain degree of deviation, such as within acceptable manufacturing tolerances. For example, depending on the particular parameter, property, or condition that is substantially satisfied, said parameter, property, or condition may be satisfied with at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0022] As used herein, the term "match" in relation to read data (e.g., output data) and expected data means and includes the degree to which read data and expected data match (e.g., within acceptable test variation, tolerance, and error levels) as would be understood by a person skilled in the art. For example, depending on the specific read data and expected data, if the amount by which the read data is less than the expected data is within 10%, 5%, or 1% of the expected data, then the read data is considered to match the expected data.

[0023] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functions. In other words, by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory of microelectronic devices, and graphics processing units (GPUs) incorporating memory.

[0024] Embodiments of this disclosure include an electronic device tester (e.g., an electronic device testing apparatus) and a method for testing electronic devices (e.g., microelectronic devices, semiconductor devices, memory devices). The electronic device tester can generate test signals and test patterns for testing (e.g., inputting to) the electronic device and for acquiring (e.g., receiving) return outputs (e.g., signals and / or reading data) from the electronic device during a test procedure. Furthermore, the electronic device tester can be used to determine and identify valid data windows (e.g., windows through which given conditions are passed) for various operating parameters of the electronic device by testing and evaluating the electronic device.

[0025] An electronic device tester may include a graphics generator (e.g., an algorithm graphics generator) that can be used to decode instructions to implement data read / write test operations. Additionally, the graphics generator may include one or more consistent finite state machines. Each of the finite state machines may contain a mathematical computational model. Furthermore, each of the finite state machines may be in one of a finite number of states at any given time. Each of the finite state machines can change from one state to another in response to a specific input. The graphics generator and the finite state machines may form at least a portion of the logic circuitry (e.g., hardware) of the electronic device tester. Furthermore, during a test procedure for identifying a data valid window, the electronic device tester may only store (e.g., write) data about the boundaries of the identified data valid window (e.g., the first and last pass points) (e.g., setting values ​​in the result register of the logic circuitry). Therefore, the hardware of the electronic device tester only reports the first and last pass points of the data valid window, along with other diagnostic information, to assist in debugging situations where a data valid window is not identified.

[0026] The electronic device tester and method described herein at least substantially replace conventional software methods for calculating the data validity window. Furthermore, the electronic device tester and method described herein are superior to conventional testers and methods for testing electronic devices. For example, by storing (e.g., writing) only data about the boundaries of the identified data validity window (e.g., the first and last pass points) (e.g., setting values ​​in the result register of the logic circuit), rather than storing valid / invalid data for each test point, the electronic device tester and method according to embodiments of this disclosure reduces the required testing time and lowers the software complexity required to process the stored data. For example, because the electronic device tester only stores the results and / or other minimal diagnostic information for the first and last pass points of the scan test, only those results are provided (e.g., output) to the test software (e.g., an external software application and / or program), and the test software only needs to process the first and last pass points and other minimal diagnostic information. Furthermore, the electronic device tester according to embodiments of this disclosure only needs to spend time storing the results for the first and last pass points. Therefore, the time generally required to read, store, and process the results for each test point is significantly reduced. For example, pass / fail information for each test point in a scan test does not need to be read out (e.g., read out to processing software). For example, the finite state machine and logic circuit of an electronic device tester only output (e.g., report) the first and last pass points of the recognized acceptable data valid window.

[0027] Furthermore, some semiconductor devices (e.g., memory devices and / or graphics devices) require data validity window (i.e., data eye) training whenever a semiconductor device is initialized, which occurs in every test. Therefore, in some cases, while the reduction in test time provided by the electronic device testers and methods described herein depends on the resolution of the scan test (e.g., the number and density of test points), the configuration readout time, and other factors, the electronic device testers and methods described herein can reduce conventional training time by more than 50% while achieving higher resolution and simplifying the process.

[0028] Furthermore, by reducing the amount of time required to test electronic devices, the electronic device tester and method of this disclosure can reduce production time and increase overall yield. Increased overall yield can lead to increased sales and revenue. In addition, by reducing the amount of time required to test electronic devices, the electronic device tester and method of this disclosure enable higher resolution testing to be performed within normal time requirements.

[0029] Figure 1 A schematic diagram of an electronic device tester 100 for testing electronic devices (e.g., semiconductor devices) according to one or more embodiments of the present disclosure is shown. As used herein, the term "semiconductor device" may include memory devices (e.g., NAND flash memory devices), graphics devices (e.g., Graphics Double Data Rate Synchronous Dynamic Random Access Memory), microelectronic devices, and / or microelectronic device structures. As described in further detail below, the electronic device tester 100 may generate test signals and test patterns for testing the electronic device and for acquiring (e.g., receiving) return outputs (e.g., signals and / or reading data) from the electronic device during a test procedure. Additionally, real-time testing can be performed using the electronic device tester 100.

[0030] As described in more detail below, the electronic device tester 100 can be used to determine and identify data validity windows (e.g., windows through which the electronic device 112 passes under given conditions (e.g., returning expected read data) by testing and evaluating the electronic device 112. In some embodiments, the electronic device tester 100 can be used to classify the electronic device 112 at least in part based on the determined data validity windows.

[0031] In some embodiments, the electronic device tester 100 may include a power supply 102, a driver 104, a comparator 106, a graphics generator 108, a timing generator 109, and a central processing unit 110. In some embodiments, one or more of the driver 104, the comparator 106, the graphics generator 108, and the central processing unit (“CPU”) 110 may form part of the logic circuitry of the electronic device tester 100.

[0032] Electronic device tester 100 can apply voltage to electronic device 112 under test using power supply 102. Electronic device tester 100 can input one or more signals to electronic device 112 using driver 104. Electronic device tester 100 can compare the signal output from electronic device 112 with one and / or more expected values ​​within electronic device tester 100 using comparator 130. Electronic device tester 100 can generate an array of signals (i.e., a test pattern) input to electronic device 112 via driver 104 using pattern generator 108. Electronic device tester 100 can generate (e.g., determine) the timing of the signals (e.g., the signal array) input to electronic device 112 using timing generator 109. CPU 110 can act as a controller for power supply 102, driver 104, comparator 106, pattern generator 108, and timing generator 109. Additionally, during operation, the CPU 110 can read data from an external storage device and interpret the read data through an operating system (OS), thereby generating and determining signals for testing the electronic device 112 (e.g., testing a pattern) and performing predetermined tests. In some embodiments, the electronic device tester 100 may further include an AC / DC test circuit 114 for performing AC and DC tests on the electronic device 112 (e.g., detecting the output voltage level or output current level from the electronic device 112 during testing).

[0033] Still referencing Figure 1 In some embodiments, the graphics generator 108 may include an algorithmic graphics generator, which can be used to decode instructions to implement data read / write test operations. Additionally, the graphics generator 108 may include several (e.g., multiple) finite state machines. Each of the finite state machines may contain a mathematical computational model. Furthermore, each of the finite state machines may be in one of a finite number of states at any given time. Each of the finite state machines can change from one state to another in response to a specific input. As is known in the art, a change from one state to another is generally referred to as a transition. Typically, a finite state machine is defined by its states, its initial state, and the inputs that trigger each transition. In some embodiments, the graphics generator 108 may include a finite state machine for each of the pins of the electronic device tester 100. Additionally, each of the finite state machines for a given pin of the bus of the electronic device tester 100 may be used to track results (e.g., read data) within a given pin. The electronic device tester 100 may include data and command pins (e.g., input and output pins), and may have assigned values ​​during the test procedure for transmitting and receiving read and write commands (i.e., signals) to and from the electronic device 112. The following section discusses... Figure 1 The state machine logic of the finite state machine is further described.

[0034] In some embodiments, one or more of the CPU 110, driver 104, comparator 106, graphics generator 108, timing generator 109, and AC / DC test circuit 170 may form the logic circuit of electronic device tester 100.

[0035] In some embodiments, the electronic device tester 100 may also be operatively coupled to an external controller having memory and software, and the software may interface with the electronic device tester 100 (e.g., the hardware of the electronic device tester 100).

[0036] As described in more detail below, during operation, the electronic device tester 100 can be used to evaluate the operating parameters of the electronic device 112 and / or the electronic device tester 100 based on the conditions of the electronic device 112 throughout the test range. For example, the electronic device tester 100 can subject the electronic device 112 to a given input (e.g., an applied test pattern) and determine the range (e.g., time period, voltage range, etc.) during which the electronic device 112 returns (e.g., outputs) the expected result (i.e., read data) while subjecting the given input (e.g., the range through which the conditions of the electronic device 112 (e.g., the output) pass). In other words, when the electronic device 112 is subjected to a given input, the electronic device tester 100 can be used to determine the range during which the read data (e.g., the output) from the electronic device 112 matches the expected result. The range can represent a valid data window for the operating parameters of the electronic device 112 and / or the electronic device tester 100. As used herein, the term "data valid window" refers to the range (e.g., duration) during which valid data (e.g., expected data) can be read from the electronic device 112 based on a given input experienced by the electronic device 112. In other words, the data valid window of the electronic device 112 can be identified by the electronic device tester 100 for one or more operating parameters of the electronic device 112 and / or the electronic device tester 100.

[0037] In some embodiments, the electronic device tester 100 may be used to determine a data validity window for evaluating one or more of the DC voltage parameters or AC voltage parameters of the electronic device 112. For example, the electronic device tester 100 may be used to determine a data validity window for evaluating one or more of the device's (e.g., electronic device 112) supply voltage, device reference voltage (e.g., Vref), and device output voltage (e.g., VOH, VOL). Additionally, the electronic device tester 100 may be used to determine a data validity window for evaluating driver voltages (e.g., high and / or low signal voltage levels from the electronic device tester 100 to the electronic device 112). As described in more detail below, the DC voltage parameters or AC voltage parameters for the electronic device 112 can be evaluated by subjecting the electronic device 112 to a series of voltages.

[0038] In one or more embodiments, the electronic device tester 100 may be used to determine a data validity window for evaluating one or more AC timing parameters of the electronic device 112. For example, the electronic device tester 100 may be used to determine a data validity window for evaluating one or more of the following: clock frequency, pin-to-pin timing (e.g., setup timing, hold timing, alignment timing, and training timing), command-to-command timing, read data strobe placement, write data edge placement, or edge-to-edge timing (e.g., duty cycle). As described in more detail below, the AC timing parameters of the electronic device 112 may be evaluated by subjecting the electronic device 112 to an AC timing signal.

[0039] Furthermore, other parameters can be evaluated and adjusted, at least in part, based on the identified data validity window of electronic device 112. For example, configuration register settings (e.g., type register settings) and / or test type settings can be evaluated and adjusted, at least in part, based on the identified data validity window of electronic device 112. In view of the foregoing, operating parameters of electronic device 112 and / or electronic device tester 100 can be evaluated, at least in part, based on the identified data validity window.

[0040] Figure 2 A schematic flowchart depicting a method 200 for determining a valid data window (associated with the selection of operating parameters) for electronic devices and / or electronic device testers. Figure 2 The description includes information about Figure 1 Reference for electronic device tester 100 and electronic device 112.

[0041] In some embodiments, method 200 may include receiving the selection of operating parameters for evaluation of electronic device 112 and / or electronic device tester 100, such as... Figure 2As illustrated in action 202. In one or more embodiments, receiving selections of operating parameters for evaluation of electronic device 112 and / or electronic device tester 100 may include receiving selections from an external controller and / or software application (e.g., a test application or program). For example, electronic device tester 100 may receive selections of operating parameters from an external controller and / or software application (e.g., a test application). The selected operating parameter may have an associated test type (e.g., the type of input signal used to evaluate the operating parameter) and an associated test range within which read data from electronic device 112 is expected to match expected data for at least a portion of the test range (e.g., conditions of electronic device 112 are expected to pass), and within the test range, a data validity window is expected (e.g., a portion of the test range in which a given condition passes).

[0042] As discussed above, in some embodiments, the test range may include any other conventional test range relating to a time period, voltage range, or operating parameters of an electronic device (e.g., a semiconductor device) for a specific event (e.g., a clock edge, a start point, voltage input, etc.). Furthermore, the test range may include several (e.g., multiple) sequential test points associated with the test range. For example, when the test range is a time period, each test point in the sequence may represent a point in time within a time period from which data is acquired from the electronic device 112. In some embodiments, the sequential test points may be equidistant from each other. For example, the first test point may be one millisecond after a specific event, and the second test point may be two milliseconds after a specific event. As another non-limiting example, when the test range is a voltage range, the first test point may represent a first input voltage (e.g., one millivolt) and measure the output voltage (e.g., response) from the electronic device 112, and the second test point may represent a second input voltage (e.g., two millivolts) and measure the output voltage (e.g., response) from the electronic device 112. As discussed below, at each of the test points in the sequential test points, the reading data from the electronic device 112 is evaluated relative to the expected value to determine whether the corresponding test point passes or fails.

[0043] In some embodiments, receiving the selection of operating parameters for evaluation may further include receiving the selection of an acceptable data validity window size for the operating parameters, such as... Figure 2As illustrated in action 204. For example, receiving the selection of operating parameters for evaluation may include receiving the selection of an acceptable data valid window size for reporting from / via an external controller and / or software application (e.g., a test application). In some embodiments, the acceptable valid window size may be user-defined. For example, the electronic device tester 100 may receive the selection of the acceptable data valid window size from an external controller and / or software application (e.g., a test application or program). In some embodiments, the selection of the acceptable data valid window size may define a minimum data valid window size to ensure the end of the scan test and reporting of the data valid window (e.g., providing output data about the data valid window). In some embodiments, the acceptable data valid window size may be defined as at least a portion of the test range. For example, selecting an acceptable data valid window may indicate a specific number of consecutive test points that must be passed in order to qualify it as an acceptable data valid window. In other embodiments, selecting an acceptable data valid window may represent a time period, voltage range, or range of any other conventional input signal that the conditions of the electronic device 112 must pass through.

[0044] Based on the selected operating parameters to be evaluated, method 200 may include performing a scan test on electronic device 112, at least partially via the hardware (e.g., logic circuitry) of electronic device tester 100, as shown in action 206. For example, electronic device tester 100 (e.g., a finite state machine within an algorithmic graphics generator of electronic device tester 100) may perform a scan test on electronic device 112. As described below, performing a scan test on electronic device 112 may include evaluating read data from electronic device 112 at at least some of the test points in a sequence of test points within a test range associated with the selected operating parameters. Furthermore, the method for performing the test points may be defined by the test pattern associated with the selected operating parameters. The following section discusses... Figure 2 A more detailed description of the instance logic flowchart for the scan test.

[0045] Performing a scan test may involve evaluating the electronic device 112 via the logic circuitry of the electronic device tester 100 at the first test point of a sequential test range associated with selected operating parameters, such as... Figure 2 Action 208 is illustrated. For example, the electronic device tester 100 may evaluate the electronic device 112 at a first test point in a sequence of test points. In some embodiments, evaluating the electronic device 112 at the first test point may optionally include an input associated with a first input of the first test point in the sequence of test points, such as... Figure 2Action 209 illustrates this. For example, at the first test point, the evaluation electronics 112 may include an input first voltage value, a first timing signal (e.g., an AC timing signal), or any other conventional signal. In one or more embodiments, at the first test point, the evaluation electronics 112 may include acquiring read data (e.g., output) from the electronics 112, such as... Figure 2 As illustrated in action 210. Referring, along with actions 209 and 210, as a non-limiting example, evaluating the electronics 112 at the first test point may include inputting a first voltage level into the electronics 112 and reading an output voltage (e.g., a response voltage) from the electronics 112. As another non-limiting example, evaluating the electronics 112 at the first test point may include acquiring read data (e.g., output data) from the electronics 112 without inputting any input.

[0046] In some embodiments, a scan test may be performed after the electronic device 112 has been subjected to an initial signal (e.g., voltage, timing signal, etc.) and before the electronic device 112 is evaluated at the first test point of the sequential test points.

[0047] In view of the foregoing, evaluating the electronic device 112 at the first test point of the sequential test points may include subjecting the electronic device 112 to the test pattern described above (e.g., input) and any conventional test pattern and / or any conventional test type used to test any of the operating parameters described above.

[0048] Evaluating the electronic device 112 at the first test point may further include determining whether the electronic device 112 returns the expected read data (e.g., via) at the first test point of the sequential test points, such as Figure 2 Action 211 illustrates this. In other words, evaluating electronic device 112 at the first test point may include determining whether the conditions of electronic device 112 are met at the first test point. For example, electronic device tester 100 may use comparator 106 to compare the read data from electronic device 112 at the first test point with the expected read data at the first test point.

[0049] In some embodiments, evaluating the electronic device 112 at the first test point may include repeatedly evaluating the electronic device 112 (e.g., writing and reading data or reading data) ten, twenty, fifty, one hundred, or more iterations at the first test point. Additionally, the electronic device tester 100 may utilize a comparator 106 to compare the read data from the electronic device 112 in each iteration evaluating the first test point with the expected read data for the first test point. In some cases, if a specific percentage (e.g., a threshold) of the expected read data is returned in the iterations evaluating the first test point, then the electronic device tester 100 may determine that the electronic device 112 has passed the condition at the first test point. For example, if at least about 60%, about 70%, about 80%, about 90%, about 95%, or about 99% of the expected read data is returned in the iterations evaluating the first test point, then the electronic device tester 100 may determine that the electronic device 112 has passed the condition at the first test point.

[0050] Still referencing Figure 2 If it is determined that electronic device 112 returns the expected read data at the first test point of the sequential test points (i.e., the condition of electronic device 112, as proven by the read data, passes at the first test point), then method 200 may include storing data indicating that the first test point is a first pass point within the logic circuitry of the electronic device tester 100, such as... Figure 2 Action 212 illustrates this. For example, method 200 may include setting the value of a first pass point in the result register representing the logic circuitry of the electronic device tester 100 to a value representing a first test point. Specifically, after each test point in the test sequence, the finite state machine of the graphics generator 108 of the electronic device tester 100 may be timed by the graphics generator 108. For example, after timing, each of the finite state machines selectively sets the result register (e.g., stores the result) using a combination of its current state and the pass or fail state of its associated pin. Furthermore, if the first test point is determined to be a pass point, then method 200 may further include storing data indicating that the first test point is within the data valid window and may not be a boundary of the data valid window (i.e., updating the result register), such as... Figure 2 Action 214 illustrates this. For example, method 200 may include data indicating that a first test point is a pass point. As mentioned above, the data may be stored in the hardware of the electronic device tester 100.

[0051] Referring to actions 212 and 214, after storing data indicating that the first test point is a pass point, method 200 may include evaluating the electronic device 112 at a second or subsequent test point (referred to herein as the "second test point") in the sequence of test points, such as... Figure 2Action 216 is illustrated. For example, the electronic device tester 100 may evaluate the electronic device 112 at a second or subsequent test point in the sequence of test points (referred to herein as a “second test point”). The evaluation of the electronic device 112 at the second test point in the sequence of test points is described in more detail below (e.g., action 216).

[0052] Return to Figure 2 Action 211, if it is determined that electronic device 112 did not return the expected read data at the first test point of the sequential test points (i.e., the condition of electronic device 112, as demonstrated by the read data, failed at the first test point), then as shown in box 213, method 200 can also move to evaluate electronic device 112 at the second test point of the sequential test points, such as... Figure 2 Action 216 illustrates this. For example, the electronic device tester 100 can evaluate the electronic device 112 at a second or subsequent test point in a sequence of test points (referred to herein as a "second test point"). Evaluating the electronic device 112 at the second test point in a sequence of test points may include, via the above description of... Figure 2 The electronic device 112 is evaluated in any manner as described in actions 208 to 212.

[0053] If it is determined that electronic device 112 returns the expected read data at the second test point of the sequential test points (i.e., the conditions of electronic device 112, as proven by the read data, pass at the second test point), and electronic device 112 does not return the expected read data at the first test point (i.e., the first test point fails), then method 200 may include storing data indicating that the second test point is a pass point and is also a first pass point, such as... Figure 2 Action 218 illustrates this. Specifically, method 200 may include setting the value of a first pass point in a result register representing the logic circuitry of the electronic device tester 100 to a value representing a second test point. For example, this can be achieved via the above description... Figure 2 The data can be stored in any manner as described in action 212. Furthermore, method 200 may continue to evaluate a sequential test point (e.g., a third test point), such as... Figure 2 Action 220 is illustrated below. The evaluation of electronic device 112 (e.g., action 220) at the sequential test points is described in more detail below.

[0054] Additionally, still refer to Figure 2Actions 211 and 216, if it is determined that electronic device 112 returns the expected read data at the second test point of the sequential test points (i.e., the conditions of electronic device 112, as demonstrated by the read data, pass at the second test point), and electronic device 112 also returns the expected read data at the first test point (i.e., the first test point passes), as shown in box 221, then method 200 may also include evaluating a sequential test point (e.g., a third test point, a subsequent test point) associated with a test range of selected operating parameters, such as... Figure 2 Action 220 is shown. For example, the electronic device tester 100 can evaluate the electronic device 112 at the sequential test point (e.g., the third test point).

[0055] Additionally, still refer to Figure 2 Actions 211 and 216, if it is determined that electronic device 112 did not return the expected read data at the second test point of the sequential test points (i.e., the condition of electronic device 112, as proven by the read data, failed at the second test point), but electronic device 112 returned the expected read data at the first test point (i.e., the first test point passed), then method 200 may include designating the most recently passed point of the sequential test points as the last passed point, such as... Figure 2 Action 222 of method 200 is illustrated. For example, action 222 of method 200 may include storing data indicating that the most recently passed test point is the last passed point, such as... Figure 2 Action 224 illustrates this. Specifically, method 200 may include setting the value of the last passed point in the result register representing the logic circuitry of the electronic device tester 100 to a value representing the most recently passed test point. Action 224 may include, via the above description... Figure 2 Action 212 describes any method of storing data.

[0056] Additionally, still refer to Figure 2 Action 222: If it is determined that electronic device 112 did not return the expected read data at the second test point of the sequential test points, but electronic device 112 returned the expected read data at the first test point (i.e., the first test point passed), then method 200 may also include determining whether the number of sequentially passed points of the sequential test points is greater than or equal to the required number of sequentially passed points of the user-defined acceptable data valid window (i.e., the minimum acceptable data valid window size), such as... Figure 2 Action 226 illustrates this. For example, the electronic device tester 100 can determine whether the number of sequential pass points is greater than or equal to the required number of sequential pass points for the user-defined acceptable data validity window.

[0057] If it is determined that the number of sequentially passed test points is not greater than or equal to the required number of sequentially passed test points in the user-defined acceptable data validity window, as indicated by arrow 227, then method 200 may include returning the test point for evaluating the sequential test point and evaluating subsequent points of the test point (e.g., the third test point), as described above regarding... Figure 2 Action 220 is illustrated and discussed. For example, the electronic device tester 100 can return to the point where the sequential test point is evaluated and evaluate the subsequent point of the sequential test point (e.g., the third test point).

[0058] Alternatively, if the number of sequential pass points determined to be for sequential test points is greater than or equal to the required number of sequential pass points for the user-defined acceptable data validity window, as indicated by arrow 231, then method 200 may include terminating the scan test, such as... Figure 2 Action 228 illustrates this. For example, the electronic device tester 100 can terminate the scan test. Alternatively, if the scan test is not yet fully completed (e.g., each point of the sequential test points has not been tested), then method 200 may include storing data indicating that the scan test is not complete (e.g., updating the results register) before identifying an acceptable data validity window for selected operating parameters, as shown. Figure 2 Action 229 is shown.

[0059] If method 200 continues Figure 2 Action 220, then at subsequent points of the sequential test point, the evaluation of electronic device 112 may include via the above regarding... Figure 2 The electronic device 112 may be evaluated in any manner as described in actions 208 to 212. Additionally, the above regarding... Figure 2 The evaluation process for the evaluation points described in actions 216 to 226 can be repeated any number of times for subsequent points of the sequential test points until the first and last pass points are identified, as follows: Figure 2 Action 230 is shown. Furthermore, points can be identified as the first and last passing points in any of the ways described above regarding the first and last passing points. For example, in some cases, the above regarding... Figure 2 The evaluation process described in actions 216 to 226 may be repeated until the first pass point and the last pass point are identified, wherein the sequential pass points of the sequential test points represented by the first pass point and the last pass point (e.g., between and including the first pass point and the last pass point) are greater than or equal to the required number of sequential pass points in the user-defined acceptable data validity window. In other cases, the above regarding... Figure 2 The evaluation process described in actions 216 to 226 may be repeated until the condition of electronic device 112 has been evaluated at each test point in the sequence of test points.

[0060] In some embodiments, if the final point of the sequential test points of the selected operating parameters is determined to be a pass point, then method 200 may include storing data indicating that the final test point of the sequential test points is a pass point (e.g., updating a result register), such as... Figure 2 Action 232 illustrates this. For example, if the final test point of the sequential test points is determined to be a pass point, and is a portion of the number of sequential pass points greater than or equal to the required number of sequential pass points within the user-defined acceptable data validity window (e.g., the final point is a portion of the data validity window), then method 200 may include marking the final point. For example, the electronic device tester 100 may mark the data indicating the last pass point as the final test point within the hardware of the electronic device tester 100.

[0061] Additionally, as mentioned above, if the acceptable data validity window is identified as each of the sequential test points before completing a full scan test (e.g., evaluating electronic device 112), then method 200 may include storing data indicating that the scan test is not completed (e.g., updating the results register) before identifying the data validity window, as in Figure 2 As shown in action 229. For example, the electronic device tester 100 may mark data identifying the first pass point and / or the last pass point within the hardware (e.g., logic circuitry) of the electronic device tester 100.

[0062] Still referencing Figure 2 When a pass point is identified after the first pass point and before the last pass point, method 200 may include not storing any data (e.g., not updating the result register). For example, when a pass point is identified after the first pass point and before the last pass point, the electronic device tester 100 may not store any data (e.g., may not update the result register). Similarly, when a failure point is identified, method 200 may include not storing any data (e.g., not updating the result register). For example, when a failure point is identified, the electronic device tester 100 may not store any data (e.g., may not update the result register).

[0063] Figure 3 A schematic flowchart depicting a method 300 for evaluating operating parameters of an electronic device and / or an electronic device tester according to one or more embodiments. In some embodiments, Figure 3 Method 300 can be used Figure 2 The continuation of method 200. Figure 3 The description includes information about Figure 1 Reference for electronic device tester 100 and electronic device 112.

[0064] Method 300 may include retrieving scan test results from the hardware (e.g., hardware state machine, logic circuit, etc.) of the electronic device tester 100, such as... Figure 3 Action 302 illustrates this. For example, retrieving the results of a scan test from the hardware of the electronic device tester 100 may include retrieving the results via an external controller and / or a software application interfaced with the electronic device tester 100. Furthermore, as briefly described above, retrieving the results of a scan test may include retrieving only data about the first and last pass points of the identified acceptable data valid window, as well as other diagnostic information from the electronic device tester 100 (e.g., data indicating that the first test point was a pass point, the scan test was not completed, etc.).

[0065] Method 300 may also include evaluating (e.g., grading, characterization, limitation, etc.) the operating parameters of electronic device 112 and / or electronic device tester 100 based at least in part on the identified acceptable data validity windows represented by the first and last retrieved points. Figure 3 Action 304 illustrates this. For example, evaluating the operating parameters of electronic device 112 and / or electronic device tester 100 may include determining the functional level of electronic device 112 or electronic device tester 100 with respect to the operating parameters, or classifying electronic device 112 or electronic device tester 100 with respect to the operating parameters.

[0066] In some embodiments, evaluating the operating parameters of electronic device 112 and / or electronic device tester 100 may include determining optimal settings for the operating parameters. In one or more embodiments, determining optimal settings for the operating parameters may include training the electronic device tester 100. In some embodiments, multiple operating parameters, which may or may not depend on each other, may be evaluated sequentially until an optimal setting is determined for each operating parameter.

[0067] In some embodiments, based at least in part on an identified acceptable data validity window, method 300 may include evaluating one or more of the following: DC voltage parameters and / or AC voltage parameters (device supply voltage, device reference voltage (e.g., Vref)) and device output voltage (e.g., VOH, VOL) ​​or driver voltage (e.g., high and / or low signal voltage levels from device tester 100 to device 112).

[0068] In one or more embodiments, at least in part based on an identified acceptable data validity window, method 300 may include evaluating one or more AC timing parameters of the electronics 112. For example, at least in part based on the identified acceptable data validity window, method 300 may include evaluating one or more of the following: clock frequency, pin-to-pin timing (e.g., setup timing, hold timing, alignment timing, and training timing), command-to-command timing, read data strobe placement, write data edge placement, or edge-to-edge timing (e.g., duty cycle).

[0069] Common Reference Figures 1 to 3 The electronic device tester 100 and method described herein are superior to conventional testers and methods. The electronic device tester 100 and method described herein at least substantially replace conventional software methods for calculating the data validity window. Furthermore, the electronic device tester 100 and method described herein reduce the required testing time and lower the complexity of the software required for further processing. For example, because the electronic device tester 100 only stores the results of the first and last pass points of the scan test and other minimal diagnostic information, only these results are provided (e.g., output) to the test software, and the test software only needs to process the first and last pass points and other minimal diagnostic information. Therefore, the time generally required to read, store, and process the results of each test point is significantly reduced. For example, the pass / fail information for each test point in the test range of the scan test does not need to be read out (e.g., read out to the processing software). For example, the finite state machine and logic circuit of the electronic device tester 100 only output (e.g., report) the first and last pass points of the identified acceptable data validity window.

[0070] Furthermore, some semiconductor devices (e.g., memory devices and / or graphics devices) require data validity window training whenever a semiconductor device is initialized, which occurs in every test. Therefore, in some cases, while the reduction in test time provided by the electronic device tester 100 and method described herein depends on the resolution of the scan test (e.g., the number and density of test points), the configuration readout time, and other factors, the electronic device tester 100 and method described herein can reduce conventional training time by more than 50% while achieving higher resolution and simplifying the process.

[0071] Furthermore, by reducing the amount of time required to test electronic devices, the electronic device tester 100 and method of this disclosure can reduce production time and increase overall yield. Increased overall yield can lead to increased sales and revenue. In addition, by reducing the amount of time required to test electronic devices, the electronic device tester 100 and method of this disclosure enable higher resolution testing to be performed within normal time requirements.

[0072] Figure 4 A schematic flowchart 400 illustrates an instance state machine logic of an electronic device tester (e.g., electronic device tester 100) according to one or more embodiments. The state machine logic may initialize a reset action that resets the stored values ​​(e.g., a result register) of each of the following in the hardware of the electronic device tester 100: the value of a first pass point, an estimated value, a first pass value, a last pass value, and an eye size value, to zero (“0”), as shown in action 402.

[0073] After resetting the result register, the state machine logic can initiate an evaluation of the first test point of a sequential test range associated with selected operating parameters of the electronic device 112 and / or the electronic device tester 100 used for evaluation, such as... Figure 4 Action 404 illustrates this. The first test point in the evaluation sequence may include the information mentioned above. Figure 2 Any of the actions described in actions 208 to 211.

[0074] Furthermore, the state machine logic can initiate a process to determine whether the condition of electronic device 112 passes or fails at the first test point of the sequential test points, such as by... Figure 4 Arrows 406 and 408 indicate this. The state machine logic can be determined via the above-mentioned... Figure 2 In any of the ways described in actions 211, 216, and 220, the condition of electronic device 112 passes or fails at the first test point of the sequential test points.

[0075] If the condition of electronic device 112 fails at the first test point of the sequential test points, then the state machine logic can initiate the evaluation of one of the sequential test points, such as... Figure 4 Action 410 is shown. The sequential test points for evaluating sequential test points may include those mentioned above. Figure 2 Any of the actions described in actions 208, 216 and 220.

[0076] Additionally, the state machine logic can initiate a determination of whether the condition of electronic device 112 passes or fails at the sequential test point, as determined by... Figure 4 Arrows 412 and 414 indicate this. The state machine logic can be determined via the above-mentioned... Figure 2 In any manner as described in actions 211, 216, and 220, the condition of electronic device 112 passes or fails at the sequential test point.

[0077] If the condition of electronic device 112 fails at the sequential test point, then the state machine logic can initiate an evaluation of another sequential test point, such as... Figure 4Action 416 illustrates this. The sequential test point (e.g., another sequential test point) used to evaluate sequential test points may include the information above regarding... Figure 2 Any of the actions described in actions 208, 216, and 220. Additionally, the state machine logic repeats action 410 and evaluates sequential test points until the condition of the electronic device 112 passes at the first test point of the sequential test points, as indicated by arrow 412.

[0078] Return to Figure 4 Actions 404 and arrow 406 indicate that if the condition of electronic device 112 passes at the first test point of the sequential test points, or if the state machine logic recognizes that the condition of electronic device 112 has passed the sequential test points, then the state machine logic can initiate the evaluation of the condition of electronic device 112 at other test points of the sequential test points until the last passing point of the sequential test points is recognized. Figure 4 Action 418 demonstrates this. For example, Figure 4 Action 418 may be repeated (arrow 419) until the condition of electronic device 112 fails at a test point of the sequential test point (e.g., another sequential test point), as by Figure 4 Arrow 420 indicates the sequence of test points. The sequence of test points for evaluation may include those mentioned above. Figure 2 Any of the actions described in actions 208, 216, and 220. Additionally, the state machine logic can determine the actions described above. Figure 2 In any manner as described in actions 211, 216, and 220, the condition of electronic device 112 passes or fails at the sequential test point.

[0079] Referring to actions 404 and 418, after identifying the first pass point, the state machine logic can set the first pass value of the result register to the value representing the first test point to be passed (e.g., curr_idx).

[0080] Additionally, after the condition of the electronic device 112 at the sequential test point where it failed is identified, the state machine logic can set the last pass value of the result register to the value (e.g., curr_idx) representing the last test point to be passed (e.g., the previous pass point), where the identified failed test point immediately follows the previous pass point.

[0081] Additionally, after identifying the last pass point, the state machine logic can initiate a determination regarding whether the number of sequential pass points (e.g., eye size) represented by the first and last pass points is greater than or equal to the minimum required number of sequential pass points (e.g., minimum eye size), such as... Figure 4 Action 422 illustrates this. The state machine logic can be derived from the above discussion. Figure 2Action 226 describes any method for determining whether the number of sequential pass points (e.g., eye value) is greater than or equal to the minimum required number of sequential pass points.

[0082] If the state machine logic determines that the number of sequential passpoints represented by the first passpoint and the last passpoint (e.g., eye size) is not greater than or equal to the minimum required number of sequential passpoints (e.g., minimum eye size), then the state machine logic can return to action 410, as indicated by arrow 424, and can re-initiate the evaluation of sequential test points until a new first passpoint is identified. Furthermore, actions 416, 418, 422, and 424 can be repeated until a number of sequential passpoints represented by the first passpoint and the last passpoint (e.g., eye size) greater than or equal to the minimum required number of sequential passpoints is identified, or until the scan test is completed.

[0083] In response to identifying a number of sequential pass points greater than or equal to the minimum required number of sequential pass points (e.g., minimum eye size), the state machine logic may terminate the scan test as shown in action 426.

[0084] refer to Figures 2 to 4 Methods 200 and 300 and logic flow 400 may further include classifying and sorting electronic devices based at least in part on an evaluation of the operating parameters of the electronic devices.

[0085] Common Reference Figures 1 to 4 While the embodiments described herein utilize logic circuitry to perform the methods described herein, this disclosure is not limited thereto. Specifically, the actions and methods described herein are also applicable to electronic device testers having memory controllers. Furthermore, the actions and methods described herein apply to the memory controller itself.

[0086] Embodiments of this disclosure include an apparatus (e.g., a tester). The apparatus includes a graphics generator, at least one finite state machine, and logic circuitry. The logic circuitry is configured to: evaluate an electronic device at a first test point within a test range for evaluating the selected operating parameters, in response to selected operating parameters to be evaluated, comprising: acquiring read data from the electronic device at the first test point within the test range; and writing data within the logic circuitry indicating that the first test point is a first pass point, at least in part based on a first value of the read data associated with the first test point; evaluate the electronic device at a second test point within the test range, comprising: acquiring read data from the electronic device at the second test point within the test range; and writing data within the logic circuitry indicating that the second test point is a first pass point, at least in part based on a second value of the read data associated with the second test point; evaluate the electronic device at one or more additional test points within the test range until a first pass point and a last pass point are identified; and after identifying the last pass point, writing data within the logic circuitry indicating the last pass point.

[0087] One or more embodiments of this disclosure include a method. The method may include: sequentially acquiring read data from an electronic device at sequential test points within a test range for evaluating operating parameters of an electronic device or an electronic device tester, until a first pass point and a last pass point of a set (e.g., multiple) of consecutive pass points are identified; in response to identifying the first pass point, writing data identifying the first pass point into the logic chip of the electronic device tester; in response to identifying the last pass point, writing data identifying the last pass point into the logic chip of the electronic device tester; determining whether a data validity window represented by the identified first pass point and the identified last pass point is greater than or equal to a user-defined acceptable data validity window. The evaluation of the electronic device is terminated upon determining that the data valid window represented by the first and last identified pass points is greater than or equal to a user-defined acceptable data valid window; upon determining that the data valid window represented by the first and last identified pass points is not greater than or equal to a user-defined acceptable data valid window, the evaluation of the electronic device continues at other test points in the sequential test points of the test range until a new first and a new last pass point of a new set of consecutive pass points are identified; and the operating parameters of the electronic device or the electronic device tester are evaluated at least in part based on the data valid window.

[0088] Some embodiments of this disclosure include an apparatus. The apparatus includes an interface (e.g., a probe card (pin-type, vertical, and MEMS (microelectromechanical systems) type), a non-contact probe (e.g., an RF probe), any conventional interface) configured to interface with an electronic device, and logic circuitry. The logic circuitry includes a graphics generator and at least one finite state machine. The logic circuitry is configured to: sequentially acquire read data from the electronic device at sequential test points within a test range used to evaluate the operating parameters of the electronic device or tester, until a set of consecutive pass points with a first pass point and a last pass point is identified; write data identifying the first pass point into the logic circuitry of the tester in response to identifying the first pass point; write data identifying the last pass point into the logic circuitry of the tester in response to identifying the last pass point; and output only the data identifying the first pass point and the data identifying the last pass point to a software application.

[0089] Embodiments of this disclosure include a method. The method may include: sequentially acquiring read data from an electronic device at sequential test points within a test range for evaluating the operating parameters of an electronic device or a tester, until a window containing a set of consecutive pass points having a first pass point and a last pass point is identified; writing data into the logic circuitry of the tester in response to identifying the first pass point; writing data into the logic circuitry of the tester in response to identifying the last pass point; outputting only the data identifying the first pass point and the data identifying the last pass point to a software application; and evaluating the operating parameters of the electronic device or electronic device tester based at least in part on the data identifying the first pass point and the data identifying the last pass point.

[0090] Embodiments of this disclosure further include:

[0091] Example 1. An apparatus comprising: a graphics generator; and at least one finite state machine; and logic circuitry configured to: evaluate electronic devices at a first test point of a test range for evaluating the selected operating parameters in response to selected operating parameters to be evaluated, comprising: acquiring read data from the electronic devices at the first test point of the test range; and writing data indicating the first test point as a first pass point within the logic circuitry based at least in part on a first value of the read data associated with the first test point; evaluating electronic devices at a second test point of the test range, comprising: acquiring read data from the electronic devices at the second test point of the test range; and writing data indicating the second test point as a first pass point within the logic circuitry based at least in part on a second value of the read data associated with the second test point; evaluating electronic devices at one or more additional test points of the test range until a first pass point and a last pass point are identified; and after identifying the last pass point, writing data indicating the last pass point within the logic circuitry.

[0092] Example 2. The device according to Example 1, wherein the logic circuitry is further configured to determine whether the data valid window represented by the first identified pass point and the last identified pass point is greater than or equal to a user-defined acceptable data valid window.

[0093] Example 3. The device according to Example 2, wherein the logic circuitry is further configured to terminate the evaluation of the electronic device in response to determining that the data valid window represented by the first identified pass point and the last identified pass point is greater than or equal to a user-defined acceptable data valid window.

[0094] Example 4. The device according to Example 2, wherein the logic circuit is further configured to sequentially evaluate the electronic device at other test points in the test range in response to determining that the data valid window represented by the identified first pass point and the identified last pass point is not greater than or equal to a user-defined acceptable data valid window, until a new first pass point and a new last pass point are identified.

[0095] Example 5. The device according to any one of Examples 1 to 4, wherein the test range represents a time period, and each test point within the test range represents a time point within the time period.

[0096] Example 6. The device according to any one of Examples 1 to 5, wherein the test range represents the range of input voltage, and each test point within the test range represents a unique input voltage value within the range of input voltage.

[0097] Example 7. The device according to any one of Examples 1 to 6, wherein the test range represents the range of the input timing signal, and each test point within the test range represents a unique input timing signal within the range of the input timing signal.

[0098] Example 8. The device according to any one of Examples 1 to 7, wherein the logic circuitry is further configured to receive selection of selected operating parameters from an external system.

[0099] Example 9. The device according to any one of Examples 1 to 8, wherein the selected operating parameters include the operating parameters of the electronic device.

[0100] Example 10. The device according to any one of Examples 1 to 9, wherein the selected operating parameters include the operating parameters of the tester.

[0101] Example 11. The device according to any one of Examples 1 to 10, wherein evaluating the electronic device at a first test point in the test range further includes subjecting the electronic device to an input signal before acquiring read data from the electronic device at the first test point in the test range.

[0102] Example 12. The device according to any one of Examples 1 to 11, wherein the selected operating parameters include the DC voltage parameters or AC voltage parameters of the electronic device.

[0103] Example 13. The device according to any one of Examples 1 to 12, wherein the selected operating parameters include the AC timing parameters of the electronic device or the AC timing parameters of the tester.

[0104] Example 14. The device according to any one of Examples 1 to 13, wherein evaluating the electronic device at a first test point in the test range includes: repeatedly evaluating the electronic device at the first test point for at least about ten, about twenty, about fifty, or about one hundred iterations; determining whether read data from the electronic device in each of the iterations at the first test point matches the expected read data at the first test point; and determining whether a threshold percentage of the iterations at the first test point produces read data from the electronic device that matches the expected read data at the first test point.

[0105] Example 15. A method comprising: sequentially acquiring read data from an electronic device at sequential test points within a test range for evaluating operating parameters of an electronic device or an electronic device tester, until a first pass point and a last pass point of consecutive pass points are identified; in response to identifying the first pass point, writing data identifying the first pass point into a logic chip of the electronic device tester; in response to identifying the last pass point, writing data identifying the last pass point into a logic chip of the electronic device tester; determining whether a data validity window represented by the identified first pass point and the identified last pass point is greater than or equal to a user-defined acceptable data validity window. The evaluation of the electronic device is terminated upon determining that the data valid window represented by the first and last identified pass points is greater than or equal to a user-defined acceptable data valid window; upon determining that the data valid window represented by the first and last identified pass points is not greater than or equal to a user-defined acceptable data valid window, the evaluation of the electronic device continues at other test points in the sequential test points of the test range until a new first and a new last pass point of a new set of consecutive pass points are identified; and the operating parameters of the electronic device or the electronic device tester are evaluated at least in part based on the data valid window.

[0106] Example 16. The method according to Example 15 further includes: in response to a mismatch between the read data of a given test point of the sequential test points of the test range and the read data of the given test point, not writing any data into the logic circuit; and in response to identifying a pass point after the first pass point but before the last pass point, not writing any data into the logic circuit.

[0107] Example 17. The method according to any of Examples 15 and 16, wherein identifying the first pass point includes: acquiring read data from an electronic device at a given test point of sequential test points in a test range; and determining that the read data from the electronic device at the given test point matches the expected read data associated with the given test point.

[0108] Example 18. The method according to any one of Examples 15 to 17, wherein sequentially acquiring read data from the electronic device at sequential test points in the test range includes: inputting a series of voltage values ​​into the electronic device; and acquiring read data from the electronic device in response to each voltage value input in the series of voltage values.

[0109] Example 19. The method according to any one of Examples 15 to 18, wherein sequentially acquiring read data from the electronic device at sequential test points within the test range includes acquiring read data at time points within a certain time period.

[0110] Example 20. The method according to any one of Examples 15 to 19, wherein evaluating the operating parameters of the electronic device or electronic device tester includes at least one of the following: determining the functional level of the electronic device or electronic device tester with respect to the operating parameters, or classifying the electronic device or electronic device tester with respect to the operating parameters.

[0111] Example 21. The method according to any one of Examples 15 to 20, wherein the operating parameters of the evaluated electronic device or electronic device tester include the DC voltage parameters or AC voltage parameters of the evaluated electronic device.

[0112] Example 22. The method according to any one of Examples 15 to 21, wherein the operating parameters of the evaluation electronic device or the electronic device tester include the AC timing parameters of the evaluation electronic device or the AC timing parameters of the electronic device tester.

[0113] Example 23. The method according to any one of Examples 15 to 22 further includes receiving the selection of operating parameters from an external application.

[0114] Example 24. An apparatus comprising: an interface configured to interface with an electronic device; a graphics generator; at least one finite state machine; and logic circuitry configured to: sequentially acquire read data from the electronic device at sequential test points in a test range for evaluating operating parameters of the electronic device or a tester, until consecutive pass points with a first pass point and a last pass point are identified; in response to identifying the first pass point, write data indicating the first pass point into the logic circuitry of the tester; in response to identifying the last pass point, write data indicating the last pass point into the logic circuitry of the tester; and output only the data indicating the first pass point and the data indicating the last pass point to a software application.

[0115] Example 25. A method comprising: sequentially acquiring read data from an electronic device at sequential test points in a test range for evaluating operating parameters of an electronic device or a tester via a tester, until a window containing consecutive pass points having a first pass point and a last pass point is identified; writing data into logic circuitry of the tester in response to identifying the first pass point; writing data into logic circuitry of the tester in response to identifying the last pass point; outputting only the data identifying the first pass point and the data identifying the last pass point to a software application; and evaluating operating parameters of the electronic device or an electronic device tester based at least in part on the data identifying the first pass point and the data identifying the last pass point.

[0116] While this disclosure has been described with respect to certain illustrative embodiments, those skilled in the art will recognize and understand that this disclosure is not limited thereto. In fact, many additions, deletions, and modifications can be made to the illustrated embodiments without departing from the scope of the invention as claimed, including its legal equivalents. Furthermore, features from one embodiment can be combined with features from another embodiment while still being covered within the scope of this disclosure as contemplated by the inventors. Moreover, embodiments of this disclosure are applicable to a wide variety of tool types and configurations.

Claims

1. An apparatus for testing electronic devices, comprising: Graphics generator; At least one finite state machine; as well as The logic circuit is configured as follows: In response to selected operating parameters to be evaluated, the electronic device is evaluated at a first test point within a test range used to evaluate the selected operating parameters, comprising: Data is acquired from the electronic device at the first test point within the test range; and At least in part, data indicating that the first test point is a first pass point is written into the first register of the logic circuit based on the first value of the read data associated with the first test point; Evaluating the electronic device at a second test point within the test range includes: Data is acquired from the electronic device at the second test point within the test range; and At least in part, based on the second value of the read data associated with the second test point, data indicating that the second test point is a pass point is written into the second register of the logic circuit; and The evaluation of the electronic device is repeated at each of the additional test points in the test range, including obtaining read data from the electronic device and writing data for each of the additional pass points into the second register of the logic circuit, until the additional test point fails, such that the remaining data in the second register of the logic circuit indicating the previous pass point indicates the last pass point.

2. The device of claim 1, wherein the logic circuitry is further configured to determine whether the data valid window represented by the first pass point and the last pass point is greater than or equal to a user-defined acceptable data valid window.

3. The device of claim 2, wherein the logic circuitry is further configured to terminate the evaluation of the electronic device in response to determining that the data valid window represented by the first pass point and the last pass point is greater than or equal to the user-defined acceptable data valid window.

4. The device of claim 2, wherein the logic circuitry is further configured to sequentially evaluate the electronic device at other test points in the test range in response to determining that the data valid window represented by the first pass point and the last pass point is not greater than or equal to the user-defined acceptable data valid window, until a new first pass point and a new last pass point are identified.

5. The device according to claim 1, wherein the test range represents a time period, and each test point within the test range represents a time point within the time period.

6. The device according to claim 1, wherein the test range represents a range of input voltages, and each test point within the test range represents a unique input voltage value within the range of input voltages.

7. The device according to claim 1, wherein the test range represents the range of the input timing signal, and each test point within the test range represents a unique input timing signal within the range of the input timing signal.

8. The device of claim 1, wherein the logic circuitry is further configured to receive selection of the selected operating parameters from an external system.

9. The device according to claim 1, wherein the selected operating parameters include the operating parameters of the electronic device.

10. The device according to claim 1, wherein the selected operating parameters include the operating parameters of the device, and the device is an electronic device tester.

11. The device of claim 1, wherein evaluating the electronic device at the first test point of the test range further comprises subjecting the electronic device to an input signal before acquiring read data from the electronic device at the first test point of the test range.

12. The device according to claim 1, wherein the selected operating parameters include the DC voltage parameters or AC voltage parameters of the electronic device.

13. The device according to claim 1, wherein the selected operating parameters include the AC timing parameters of the electronic device or the AC timing parameters of the device, and the device is an electronic device tester.

14. The device of claim 1, wherein evaluating the electronic device at the first test point within the test range comprises: The electronic device was repeatedly evaluated at the first test point for multiple iterations; Determine whether the read data from the electronic device in each of the iterations at the first test point matches the expected read data at the first test point; as well as Determine whether the threshold percentage of the iteration at the first test point produces read data from the electronic device that matches the expected read data at the first test point.

15. A method for testing an electronic device, comprising: Data is sequentially acquired from the electronic device at sequential test points within a test range used to evaluate the operating parameters of the electronic device or electronic device tester, until the first and last consecutive pass points are identified. In response to identifying the first pass point, data identifying the first pass point is written into the first register of the logic chip of the electronic device tester; In response to identifying a pass point after the first pass point, data identifying the pass point is written into the second register of the logic chip of the electronic device tester; The data of each of the other pass points is repeatedly written into the second register of the logic chip until the sequential test point fails, so that the remaining data in the second register of the logic chip that identified the previous pass point identifies the last pass point. Determine whether the valid data window represented by the first and last identified pass points is greater than or equal to the user-defined acceptable valid data window; In response to determining that the data valid window represented by the first identified pass point and the last identified pass point is greater than or equal to the user-defined acceptable data valid window, the evaluation of the electronic device is terminated. In response to determining that the data valid window represented by the first pass point and the last pass point is not greater than or equal to the user-defined acceptable data valid window, the electronic device is evaluated at other test points of the sequential test points in the test range until a new first pass point and a new last pass point of a new set of consecutive pass points are identified. as well as The operating parameters of the electronic device or electronic device tester are evaluated, at least in part, based on the data validity window.

16. The method of claim 15, further comprising: If the read data of a given test point in the sequential test points of the test range does not match the expected read data of the given test point, no data is written into the logic chip.

17. The method of claim 15, wherein identifying the first transit point comprises: Data is acquired from the electronic device at a given test point of the sequential test points within the test range; as well as It is determined that the read data from the electronic device at the given test point matches the expected read data associated with the given test point.

18. The method of claim 15, wherein sequentially acquiring read data from the electronic device at the sequential test points within the test range comprises: A series of voltage values ​​are input into the electronic device; as well as In response to each voltage value of the input series of voltage values, read data is obtained from the electronic device.

19. The method of claim 15, wherein sequentially acquiring read data from the electronic device at the sequential test points within the test range includes acquiring read data at time points within a certain time period.

20. The method of claim 15, wherein evaluating the operating parameters of the electronic device or the electronic device tester includes at least one of: determining the functional level of the electronic device or the electronic device tester with respect to the operating parameters, or classifying the electronic device or the electronic device tester with respect to the operating parameters.

21. The method of claim 15, wherein evaluating the operating parameters of the electronic device or the electronic device tester includes evaluating the DC voltage parameters or AC voltage parameters of the electronic device.

22. The method of claim 15, wherein evaluating the operating parameters of the electronic device or the electronic device tester includes evaluating the AC timing parameters of the electronic device or the AC timing parameters of the electronic device tester.

23. The method of claim 15, further comprising receiving selection of the operating parameters from an external application.

24. An apparatus for testing electronic devices, comprising: An interface configured to interface with an electronic device; Graphics generator; At least one finite state machine; as well as The logic circuit is configured as follows: Data is sequentially acquired from the electronic device at sequential test points within the test range used to evaluate operating parameters until consecutive pass points with a first pass point and a last pass point are identified. In response to identifying the first pass point, data indicating the first pass point is written into the first register of the logic circuit; In response to identifying a pass point after the first pass point, data indicating the pass point is written into the second register of the logic circuit; The data for each of the additional pass points is repeatedly written into the second register of the logic circuit until the sequential test point fails, such that the remaining data in the second register of the logic circuit indicating the previous pass point indicates the last pass point; and The data identifying the first pass point and the data identifying the last pass point are output to the software application.

25. A method for testing an electronic device, comprising: Data is sequentially acquired from the electronic device at sequential test points within a test range used to evaluate the operating parameters of the electronic device or the tester, until a window containing consecutive pass points with a first pass point and a last pass point is identified. In response to identifying the first pass point, data indicating the first pass point is written into the first register of the logic circuit of the tester; In response to identifying a pass point after the first pass point, data indicating the pass point is written into the second register of the logic circuit; The data for each of the additional pass points is repeatedly written into the second register of the logic circuit until the sequential test point fails, such that the remaining data in the second register of the logic circuit that indicates the previous pass point indicates the last pass point. The data identifying the first pass point and the data identifying the last pass point are output to the software application; as well as The operating parameters of the electronic device or electronic device tester are evaluated based at least in part on the data identifying the first pass point and the data identifying the last pass point.

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