Pixel driving circuit, driving method thereof, display panel, and display device

Abstract

The present disclosure relates to the field of display technologies, and provides a pixel driving circuit, a driving method thereof, a display panel, and a display device. The pixel driving circuit includes: a driving circuit, a reset circuit, a data writing circuit, a first storage circuit, and a second storage circuit. The driving circuit is configured to input a driving current from a second node to a third node according to a voltage difference between a first node and the third node; the reset circuit is configured to transmit a signal of an initial signal terminal to the third node in response to a signal of a reset signal terminal, and to connect the third node and a fourth node in response to a signal of a first gate driving signal terminal; the data writing circuit is configured to transmit a signal of a data signal terminal to the fourth node in response to a signal of a second gate driving signal terminal; the first storage circuit is connected between the first node and the fourth node; and the second storage circuit is connected between the third node and the fourth node. The display panel can improve the technical problem of uneven display.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to a pixel driving circuit, a driving method thereof, a display panel, and a display device. Background Art

[0002] The pixel driving circuit in a display panel generally includes a driving transistor, and the threshold voltage of the driving transistor affects the magnitude of its output current. Due to process problems, it is difficult to make the threshold voltages of the driving transistors in the display panel exactly the same. Therefore, the display panel will have the problem of uneven display brightness at the same gray level.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] According to one aspect of the present disclosure, a pixel driving circuit is provided. The pixel driving circuit includes: a driving circuit, a reset circuit, a data writing circuit, a first storage circuit, and a second storage circuit. The driving circuit is connected to a first node, a second node, and a third node, and is configured to input a driving current to the third node using the second node according to the voltage difference between the first node and the third node; the reset circuit is connected to the third node, an initial signal terminal, a reset signal terminal, a fourth node, and a first gate driving signal terminal, and is configured to transmit the signal of the initial signal terminal to the third node in response to the signal of the reset signal terminal, and is configured to connect the third node and the fourth node in response to the signal of the first gate driving signal terminal; the data writing circuit is connected to the fourth node, a data signal terminal, and a second gate driving signal terminal, and is configured to transmit the signal of the data signal terminal to the fourth node in response to the signal of the second gate driving signal terminal; the first storage circuit is connected between the first node and the fourth node; the second storage circuit is connected between the third node and the fourth node.

[0005] In an exemplary embodiment of the present disclosure, the pixel driving circuit further includes: a compensation circuit and a light emitting control circuit. The compensation circuit is connected to the first node, the second node, and a third gate driving signal terminal, and is configured to connect the first node and the second node in response to the signal of the third gate driving signal terminal; the light emitting control circuit is connected to a first power supply terminal, the second node, and an enable signal terminal, and is configured to transmit the signal of the first power supply terminal to the second node in response to the signal of the enable signal terminal.

[0006] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, a first pole of the driving transistor is connected to the second node, a second pole is connected to the third node, and a gate is connected to the first node, wherein the driving transistor is an N-type transistor.

[0007] In an exemplary embodiment of the present disclosure, the compensation circuit includes: a second transistor, a first pole of the second transistor is connected to the first node, a second pole is connected to the second node, and a gate is connected to the third gate driving signal terminal.

[0008] In an exemplary embodiment of the present disclosure, the reset circuit includes: a third transistor and a fourth transistor, a first pole of the third transistor is connected to the initial signal terminal, a second pole is connected to the third node, and a gate is connected to the reset signal terminal; a first pole of the fourth transistor is connected to the third node, a second pole is connected to the fourth node, and a gate is connected to the first gate driving signal terminal.

[0009] In an exemplary embodiment of the present disclosure, the data writing circuit includes: a fifth transistor, a first pole of the fifth transistor is connected to the data signal terminal, a second pole is connected to the fourth node, and a gate is connected to the second gate driving signal terminal.

[0010] In an exemplary embodiment of the present disclosure, the first storage circuit includes: a first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode is connected to the fourth node; the second storage circuit includes: a second capacitor, a first electrode of the second capacitor is connected to the third node, and a second electrode is connected to the fourth node.

[0011] In an exemplary embodiment of the present disclosure, the light emitting control circuit includes: a sixth transistor, a first pole of the sixth transistor is connected to the first power supply terminal, a second pole is connected to the second node, and a gate is connected to the enable signal terminal.

[0012] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, a first pole of the driving transistor is connected to the second node, a second pole is connected to the third node, and a gate is connected to the first node. The compensation circuit includes: a second transistor, a first pole of the second transistor is connected to the first node, a second pole is connected to the second node, and a gate is connected to the third gate driving signal terminal. The reset circuit includes: a third transistor and a fourth transistor, a first pole of the third transistor is connected to the initial signal terminal, a second pole is connected to the third node, and a gate is connected to the reset signal terminal; a first pole of the fourth transistor is connected to the third node, a second pole is connected to the fourth node, and a gate is connected to the first gate driving signal terminal. The data writing circuit includes: a fifth transistor, a first pole of the fifth transistor is connected to the data signal terminal, a second pole is connected to the fourth node, and a gate is connected to the second gate driving signal terminal. The first storage circuit includes: a first capacitor, a first electrode of the first capacitor is connected to the first node, and a second electrode is connected to the fourth node. The second storage circuit includes: a second capacitor, a first electrode of the second capacitor is connected to the third node, and a second electrode is connected to the fourth node. The light emitting control circuit includes: a sixth transistor, a first pole of the sixth transistor is connected to the first power supply terminal, a second pole is connected to the second node, and a gate is connected to the enable signal terminal. The driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors.

[0013] According to one aspect of the present disclosure, a method for driving a pixel driving circuit is provided. The method for driving a pixel driving circuit is used to drive the above-mentioned pixel driving circuit, and the method for driving a pixel driving circuit includes:

[0014] In the reset stage, an effective level is input to the reset signal terminal and the first gate driving signal terminal, and an invalid level is input to the second gate driving signal terminal;

[0015] In the data writing stage, an effective level is input to the second gate driving signal terminal and the reset signal terminal, and an invalid level is input to the first gate driving signal terminal;

[0016] In the light emitting stage, an invalid level is input to the first gate driving signal terminal, the second gate driving signal terminal, and the reset signal terminal.

[0017] According to one aspect of the present disclosure, a display panel is provided. The display panel includes the above-mentioned pixel driving circuit.

[0018] According to one aspect of the present disclosure, a display device is provided. The display device includes the above-mentioned display panel.

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. Brief Description of the Drawings

[0020] The accompanying drawings herein are incorporated into and constitute a part of this specification, showing embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0021] Figure 1 Schematic structural diagram of an exemplary embodiment of a pixel driving circuit according to the present disclosure;

[0022] Figure 2 Schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;

[0023] Figure 3 For Figure 2 Timing diagram of each control signal in a driving method of the pixel driving circuit shown;

[0024] Figure 4 For Figure 2 State diagram of the pixel driving circuit shown in the reset stage;

[0025] Figure 5 For Figure 2 State diagram of the pixel driving circuit shown in the threshold compensation stage;

[0026] Figure 6 For Figure 2 State diagram of the pixel driving circuit shown in the data writing stage;

[0027] Figure 7 For Figure 2 State diagram of the pixel driving circuit shown in the light emitting stage. Detailed Embodiments

[0028] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and thorough, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote the same or similar structures, and thus their detailed descriptions will be omitted.

[0029] The terms "a", "an", and "the" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used in an open-ended inclusive sense and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0030] This exemplary embodiment first provides a pixel driving circuit, as Figure 1 shown, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include: a driving circuit 1, a reset circuit 2, a data writing circuit 3, a first storage circuit 41, and a second storage circuit 42. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3, and is configured to input a driving current to the third node N3 using the second node N2 according to the voltage difference between the first node N1 and the third node N3; the reset circuit 2 is connected to the third node N3, an initial signal terminal Vinit, a reset signal terminal Re, a fourth node N4, and a first gate driving signal terminal G1, and is configured to transmit the signal of the initial signal terminal Vinit to the third node N3 in response to the signal of the reset signal terminal Re, and is configured to connect the third node N3 and the fourth node N4 in response to the signal of the first gate driving signal terminal G1; the data writing circuit 3 is connected to the fourth node N4, a data signal terminal Da, and a second gate driving signal terminal G2, and is configured to transmit the signal of the data signal terminal Da to the fourth node N4 in response to the signal of the second gate driving signal terminal G2; the first storage circuit 41 is connected between the first node N1 and the fourth node N4; the second storage circuit 42 is connected between the third node N3 and the fourth node N4. Among them, as Figure 1 shown, the third node N3 may be used to connect to a first electrode of a light-emitting unit OLED, a second electrode of the light-emitting unit OLED may be connected to a second power supply terminal VSS, and the pixel driving circuit may be used to drive the light-emitting unit OLED to emit light.

[0031] In this exemplary embodiment, the driving circuit 1 may include a driving transistor T1. The driving method of this pixel driving circuit may include: a reset stage, a threshold compensation stage, a data writing stage, and a light emitting stage. In the reset stage, an effective level may be input to the reset signal terminal Re and the first gate driving signal terminal G1, and an ineffective level may be input to the second gate driving signal terminal G2. The reset circuit 2 transmits the signal of the initial signal terminal Vinit to the third node N3 and the fourth node N4. The voltages of the third node N3 and the fourth node N4 are Vini, where Vini is the voltage of the initial signal terminal Vinit. In the threshold compensation stage, a threshold compensation voltage Vth + Vx may be input to the first node N1, where Vth is the threshold voltage of the driving transistor T1 and Vx is a reference voltage, and the value of Vx may be adjusted according to actual conditions. In the data writing stage, an effective level may be input to the second gate driving signal terminal G2 and the reset signal terminal Re, and an ineffective level may be input to the first gate driving signal terminal G1. The data writing circuit 3 transmits the data signal of the data signal terminal Da to the fourth node N4. The voltage of the fourth node N4 changes from Vini to Vdata, where Vdata is the voltage of the data signal. Under the coupling action of the first storage circuit 41, the voltage of the first node N1 becomes Vth + Vx + Vdata - Vini. At the same time, the reset circuit 2 transmits the signal of the initial signal terminal Vinit to the third node N3, and the voltage of the third node N3 is Vini. In the light emitting stage, ineffective levels may be input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, and the reset signal terminal Re. The driving transistor T1 is turned on under the action of the voltage of the first node N1 to input a driving current to the third node N3, and the voltage of the third node N3 becomes V3. Under the coupling action of the first storage circuit 41 and the second storage circuit 42, the voltage of the first node N1 becomes Vth + Vx + Vdata - Vini + V3 - Vini. According to the output current formula of the driving transistor I = (μWCox / 2L)(Vgs - Vth) 2 , where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. In this exemplary embodiment, the output current I of the driving transistor T1 to the third node N3 = (μWCox / 2L)(Vth + Vx + Vdata - Vini + V3 - Vini - V3 - Vth) 2 = (μWCox / 2L)(Vx + Vdata - 2Vini) 2According to the output current formula of the driving transistor T1, it can be seen that in this exemplary embodiment, the output current of the pixel driving circuit is independent of the threshold voltage of the driving transistor, and this pixel driving circuit can improve the problem of uneven display of the display panel caused by inconsistent threshold voltages of the driving transistors.

[0032] It should be noted that in this exemplary embodiment, the effective level refers to the level that can drive the target circuit to work, and the invalid level refers to the level that cannot drive the target circuit to work. For example, when the target circuit is an N-type transistor, the effective level is the high level and the invalid level is the low level.

[0033] In this exemplary embodiment, as Figure 2 shown, it is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. This pixel driving circuit may further include: a compensation circuit 5 and a light emission control circuit 6. The compensation circuit 5 is connected to the first node N1, the second node N2, and the third gate driving signal terminal G3, and is configured to connect the first node N1 and the second node N2 in response to the signal of the third gate driving signal terminal G3; the light emission control circuit 6 is connected to the first power supply terminal VDD, the second node N2, and the enable signal terminal EM, and is configured to transmit the signal of the first power supply terminal VDD to the second node N2 in response to the signal of the enable signal terminal EM.

[0034] In this exemplary embodiment, in the reset stage, an effective level can be input to the enable signal terminal EM and the third gate driving signal terminal G3. The compensation circuit 5 can conduct the first node N1 and the second node N2, and at the same time, the light emission control circuit 6 can transmit the signal of the first power supply terminal VDD to the first node N1 to reset the first node N1. In the threshold compensation stage, an invalid level can be input to the enable signal terminal EM and the second gate driving signal terminal G2, and an effective level can be input to the reset signal terminal Re, the first gate driving signal terminal G1, and the third gate driving signal terminal G3. The reset circuit 2 can transmit the signal of the initial signal terminal to the third node N3, and the third node N3 can input a threshold compensation voltage Vini + Vth to the first node N1, where Vini is the voltage of the initial signal terminal Vinit and Vth is the threshold voltage of the driving transistor T1. In this exemplary embodiment, the pixel driving circuit uses the compensation circuit 5 to input a threshold compensation voltage including the threshold voltage of the driving transistor to the first node N1 in the threshold compensation stage. It should be understood that in other exemplary embodiments, this pixel driving circuit may also use an external circuit to input a threshold compensation voltage to the first node N1 in the threshold compensation stage.

[0035] In this exemplary embodiment, as Figure 2As shown, the driving circuit 1 may include: a driving transistor T1, a first pole of the driving transistor T1 is connected to the second node N2, a second pole is connected to the third node N3, and a gate is connected to the first node N1, wherein the driving transistor T1 may be an N-type transistor.

[0036] In this exemplary embodiment, as Figure 2 shown, the compensation circuit 5 may include: a second transistor T2, a first pole of the second transistor T2 is connected to the first node N1, a second pole is connected to the second node N2, and a gate is connected to the third gate driving signal terminal G3.

[0037] In this exemplary embodiment, as Figure 2 shown, the reset circuit 2 may include: a third transistor T3 and a fourth transistor T4, a first pole of the third transistor T3 is connected to the initial signal terminal Vinit, a second pole is connected to the third node N3, and a gate is connected to the reset signal terminal Re; a first pole of the fourth transistor T4 is connected to the third node N3, a second pole is connected to the fourth node N4, and a gate is connected to the first gate driving signal terminal G1.

[0038] In this exemplary embodiment, as Figure 2 shown, the data writing circuit 3 may include: a fifth transistor T5, a first pole of the fifth transistor T5 is connected to the data signal terminal Da, a second pole is connected to the fourth node N4, and a gate is connected to the second gate driving signal terminal G2.

[0039] In this exemplary embodiment, as Figure 2 shown, the first storage circuit 41 may include: a first capacitor C1, a first electrode of the first capacitor C1 is connected to the first node N1, and a second electrode is connected to the fourth node N4; the second storage circuit 42 may include: a second capacitor C2, a first electrode of the second capacitor C2 is connected to the third node N3, and a second electrode is connected to the fourth node N4.

[0040] In this exemplary embodiment, as Figure 2 shown, the light emitting control circuit 6 may include: a sixth transistor T6, a first pole of the sixth transistor T6 is connected to the first power supply terminal VDD, a second pole is connected to the second node N2, and a gate is connected to the enable signal terminal EM.

[0041] In this exemplary embodiment, as Figure 2As shown, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are N-type transistors. The N-type transistor has a small off-state leakage current, so that the pixel driving circuit can reduce the leakage current of each node through the transistor, thereby improving the display effect. In addition, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor T1 are all N-type transistors. The channel regions of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the driving transistor T1 can be fabricated on the same active layer, so that this arrangement can simplify the manufacturing process and structure of the display panel. It should be understood that in other exemplary embodiments, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can also be P-type transistors.

[0042] As Figure 3 shown, for Figure 2 shown is a timing diagram of each control signal in a driving method of the pixel driving circuit shown. Among them, G1 represents the timing diagram of the signal on the first gate driving signal terminal, G2 represents the timing diagram of the signal on the second gate driving signal terminal, G3 represents the timing diagram of the signal on the third gate driving signal terminal, EM represents the timing diagram of the signal on the enable signal terminal, Re represents the timing diagram of the signal on the reset signal terminal, and Da represents the timing diagram of the signal on the data signal terminal. In this exemplary embodiment, the first power supply terminal VDD can be a high-level signal terminal, and the second power supply terminal VSS can be a low-level signal terminal.

[0043] As Figure 3 shown, the driving method of the pixel driving circuit can include four stages: a reset stage t1, a threshold compensation stage t2, a data writing stage t3, and a light emitting stage t4.

[0044] In the reset stage t1, a high level can be input to the first gate driving signal terminal G1, the reset signal terminal Re, the third gate driving signal terminal G3, and the enable signal terminal EM, and a low level can be input to the second gate driving signal terminal G2. As Figure 4 shown, for Figure 2 shown is a state diagram of the pixel driving circuit in the reset stage. Among them, the transistor with a cross is in the off state, and the transistor without a cross is in the on state. In the reset stage t1, the initial signal terminal Vinit inputs an initial voltage Vini to the third node N3 and the fourth node N4 to reset the third node N3 and the fourth node N4. At the same time, the first power supply terminal VDD inputs the power supply voltage Vdd of the first power supply terminal VDD to the second node N2 and the first node N1 to reset the second node N2 and the first node N1.

[0045] In the threshold compensation stage t2, a high level can be input to the first gate driving signal terminal G1, the reset signal terminal Re, and the third gate driving signal terminal G3, and a low level can be input to the second gate driving signal terminal G2 and the enable signal terminal EM. As Figure 5 shown, it is Figure 2 the state diagram of the pixel driving circuit in the threshold compensation stage. Among them, the transistors with a cross are in the off state, and the transistors without a cross are in the on state. In the threshold compensation stage t2, the initial signal terminal Vinit inputs an initial voltage Vini to the third node N3 and the fourth node N4, driving the driving transistor T1 to form a diode-connected structure, driving the driving transistor T1 to conduct, and the voltage of the first node N1 gradually decreases until it decreases to Vini + Vth, where Vth is the threshold voltage of the driving transistor T1.

[0046] In the data writing stage t3, a high level can be input to the reset signal terminal Re and the second gate driving signal terminal G2, a low level can be input to the first gate driving signal terminal G1, the third gate driving signal terminal G3, and the enable signal terminal EM, and at the same time, a data signal can be input to the data signal terminal Da. As Figure 6 shown, it is Figure 2 the state diagram of the pixel driving circuit in the data writing stage. Among them, the transistors with a cross are in the off state, and the transistors without a cross are in the on state. In the data writing stage t3, the data signal terminal Da writes a data signal to the fourth node N4, and the voltage of the fourth node N4 changes from Vini to Vdata, where Vdata is the voltage of the data signal. Under the coupling action of the first capacitor C1, the voltage of the first node N1 becomes Vini + Vth + Vdata - Vini. At the same time, the initial signal terminal Vinit inputs an initial voltage Vini to the third node N3.

[0047] In the light emitting stage t4, a high level can be input to the enable signal terminal EM, and a low level can be input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, the third gate driving signal terminal G3, and the reset signal terminal Re. As Figure 7 shown, it is Figure 2 the state diagram of the pixel driving circuit in the light emitting stage. Among them, the transistors with a cross are in the off state, and the transistors without a cross are in the on state. In the light emitting stage t4, the driving transistor T1 conducts, the voltage of the third node changes from Vini to V3, and under the coupling action of the first capacitor C1 and the second capacitor C2, the voltage of the first node N1 becomes Vini + Vth + Vdata - Vini + V3 - Vini. In this exemplary embodiment, the output current I of the driving transistor T1 to the third node N3 is I = (μWCox / 2L)(Vini + Vth + Vdata - Vini + V3 - Vini - V3 - Vth) 2= (μWCox / 2L)(Vdata - Vini) 2 As can be seen from the output current formula of the driving transistor T1, in this exemplary embodiment, the output current of the pixel driving circuit is independent of the threshold voltage of the driving transistor, and this pixel driving circuit can improve the problem of uneven display of the display panel caused by inconsistent threshold voltages of the driving transistors.

[0048] This exemplary embodiment further provides a method for driving a pixel driving circuit. The method for driving the pixel driving circuit is used to drive the above-mentioned pixel driving circuit, and the method for driving the pixel driving circuit includes:

[0049] In the reset stage, an effective level is input to the reset signal terminal Re and the first gate driving signal terminal G1, and an ineffective level is input to the second gate driving signal terminal G2;

[0050] In the data writing stage, an effective level is input to the second gate driving signal terminal G2 and the reset signal terminal Re, and an ineffective level is input to the first gate driving signal terminal G1;

[0051] In the light emitting stage, an ineffective level is input to the first gate driving signal terminal G1, the second gate driving signal terminal G2, and the reset signal terminal Re.

[0052] The method for driving the pixel driving circuit has been described in detail above and will not be elaborated here.

[0053] This exemplary embodiment further provides a display panel, which may include the above-mentioned pixel driving circuit.

[0054] This exemplary embodiment further provides a display device, which may include the above-mentioned display panel. The display device may be a display device such as a mobile phone, a tablet computer, or a television.

[0055] After considering the specification and practicing the content disclosed herein, those skilled in the art will readily think of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common general knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0056] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A pixel driving circuit, characterized in that, The pixel driving circuit includes: A driving circuit, connected to the first node, the second node, and the third node, for inputting a driving current to the third node from the second node according to the voltage difference between the first node and the third node; A reset circuit, connected to the third node, the initial signal terminal, the reset signal terminal, the fourth node, and the first gate driving signal terminal, for transmitting the signal of the initial signal terminal to the third node in response to the signal of the reset signal terminal, and for connecting the third node and the fourth node in response to the signal of the first gate driving signal terminal; A data writing circuit, connected to the fourth node, the data signal terminal, and the second gate driving signal terminal, for transmitting the signal of the data signal terminal to the fourth node in response to the signal of the second gate driving signal terminal; A first storage circuit, connected between the first node and the fourth node; A second storage circuit, connected between the third node and the fourth node; The pixel driving circuit further includes: A compensation circuit, connected to the first node, the second node, and the third gate driving signal terminal, for connecting the first node and the second node in response to the signal of the third gate driving signal terminal; A light emission control circuit, connected to the first power supply terminal, the second node, and the enable signal terminal, for transmitting the signal of the first power supply terminal to the second node in response to the signal of the enable signal terminal.

2. The pixel driving circuit according to claim 1, wherein The driving circuit includes: A driving transistor, with the first pole connected to the second node, the second pole connected to the third node, and the gate connected to the first node, wherein the driving transistor is an N-type transistor.

3. The pixel driving circuit according to claim 1, wherein The compensation circuit includes: A second transistor, with the first pole connected to the first node, the second pole connected to the second node, and the gate connected to the third gate driving signal terminal.

4. The pixel driving circuit according to claim 1, wherein The reset circuit includes: A third transistor, with the first pole connected to the initial signal terminal, the second pole connected to the third node, and the gate connected to the reset signal terminal; A fourth transistor, with the first pole connected to the third node, the second pole connected to the fourth node, and the gate connected to the first gate driving signal terminal.

5. The pixel driving circuit according to claim 1, wherein The data writing circuit includes: A fifth transistor, with the first pole connected to the data signal terminal, the second pole connected to the fourth node, and the gate connected to the second gate driving signal terminal.

6. The pixel driving circuit according to claim 1, wherein The first storage circuit includes: A first capacitor, with the first electrode of the first capacitor connected to the first node and the second electrode connected to the fourth node; The second storage circuit includes: A second capacitor, with the first electrode of the second capacitor connected to the third node and the second electrode connected to the fourth node.

7. The pixel driving circuit according to claim 1, wherein The light emission control circuit includes: A sixth transistor, with the first pole connected to the first power supply terminal, the second pole connected to the second node, and the gate connected to the enable signal terminal.

8. The pixel driving circuit according to claim 1, wherein The driving circuit includes: A driving transistor, with the first pole connected to the second node, the second pole connected to the third node, and the gate connected to the first node; The compensation circuit includes: A second transistor, with the first pole connected to the first node, the second pole connected to the second node, and the gate connected to the third gate driving signal terminal; The reset circuit includes: A third transistor, having a first pole connected to the initial signal terminal, a second pole connected to the third node, and a gate connected to the reset signal terminal; A fourth transistor, having a first pole connected to the third node, a second pole connected to the fourth node, and a gate connected to the first gate driving signal terminal; The data writing circuit includes: A fifth transistor, having a first pole connected to the data signal terminal, a second pole connected to the fourth node, and a gate connected to the second gate driving signal terminal; The first storage circuit includes: A first capacitor, having a first electrode of the first capacitor connected to the first node and a second electrode connected to the fourth node; The second storage circuit includes: A second capacitor, having a first electrode of the second capacitor connected to the third node and a second electrode connected to the fourth node; The light emitting control circuit includes: A sixth transistor, having a first pole connected to the first power supply terminal, a second pole connected to the second node, and a gate connected to the enable signal terminal; The driving transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are N-type transistors.

9. A method for driving a pixel driving circuit, characterized in that, The pixel driving circuit driving method is used to drive the pixel driving circuit according to any one of claims 1-8, and the pixel driving circuit driving method includes: In the reset stage, an effective level is input to the reset signal terminal and the first gate driving signal terminal, and an ineffective level is input to the second gate driving signal terminal; In the data writing stage, an effective level is input to the second gate driving signal terminal and the reset signal terminal, and an ineffective level is input to the first gate driving signal terminal; In the light emitting stage, an ineffective level is input to the first gate driving signal terminal, the second gate driving signal terminal, and the reset signal terminal.

10. A display panel, characterized in that, Including the pixel driving circuit according to any one of claims 1-8.

11. A display device, characterized in that, Including the display panel according to claim 10.

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