Sensitive amplifier, memory, and how the memory works

Abstract

A sensitive amplifier includes: a first transistor, the gate of which is connected to a first bit line of a memory cell; a second transistor, the gate of which is connected to a second bit line of the memory cell, and the source of which is connected to the source of the first transistor; a third transistor, the gate of which is connected to the second bit line of the memory cell, and the source of which is connected to the source of the second transistor; the first, second, and third transistors have different threshold voltages; a mirror cell, including a mirrored terminal, a first mirrored terminal, and a second mirrored terminal, the mirrored terminal being connected to the drain of the first transistor, the first mirrored terminal being connected to the drain of the second transistor, and the second mirrored terminal being connected to the drain of the third transistor; and a detection unit connected to the first mirrored terminal and the second mirrored terminal of the mirror cell. The sensitive amplifier circuit improves the overall read / write speed of the memory.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and more specifically to a sensitive amplifier, a memory, and a method for operating the memory. Background Technology

[0002] With the widespread use of electronic devices such as mobile phones, tablets, and personal computers, semiconductor memory technology has also developed rapidly. For example, Dynamic Random Access Memory (DRAM) and Static Random-Access Memory (SRAM) are widely used in various electronic devices due to their advantages such as high density, low power consumption, and low cost.

[0003] A sense amplifier (SA) is an important component of a semiconductor memory. Its main function is to amplify small signals on the bit lines to perform read or write operations.

[0004] As technology continues to advance, the size of semiconductor memories is constantly decreasing. In this case, transistor mismatch in the sensitive amplifier will have a certain impact on the output of the sensitive amplifier, thereby affecting the performance of the memory. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a sensitive amplifier, a memory, and a method for operating the memory to improve the performance of the memory.

[0006] To solve the above technical problems, the present invention provides a sensitive amplifier, comprising: a first transistor, the gate of which is connected to the first bit line of a memory cell; a second transistor, the gate of which is connected to the second bit line of the memory cell, and the source of which is connected to the source of the first transistor; a third transistor, the gate of which is connected to the second bit line of the memory cell, and the source of which is connected to the source of the second transistor, wherein the sources of the first transistor, the second transistor, and the third transistor are coupled to a ground voltage node, and the threshold voltages of the first transistor, the second transistor, and the third transistor are different; a mirror unit, comprising a mirrored terminal, a first mirrored terminal, and a second mirrored terminal, wherein the mirrored terminal is connected to the drain of the first transistor, the first mirrored terminal is connected to the drain of the second transistor, and the second mirrored terminal is connected to the drain of the third transistor; and a detection unit, wherein the first mirrored terminal of the mirror unit is connected to the detection unit, and the second mirrored terminal of the mirror unit is connected to the detection unit.

[0007] Optionally, the mirrored end of the mirror unit includes: a fourth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a first transistor, and the gate of which is connected to the drain of the first transistor.

[0008] Optionally, the first mirror terminal of the mirror unit includes: a fifth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a second transistor, and the gate of which is connected to the gate of a fourth transistor; the detection unit is connected to the drain of the fifth transistor.

[0009] Optionally, the second mirror terminal of the mirror unit includes: a sixth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a third transistor, and the gate of which is connected to the gate of a fourth transistor and the gate of a fifth transistor; the detection unit is connected to the drain of the sixth transistor.

[0010] Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

[0011] Optionally, the mirror unit further includes a voltage input node, which is connected to the power supply voltage node.

[0012] Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

[0013] Optionally, it also includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

[0014] Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

[0015] Optionally, it also includes: a seventh transistor, the drain of which is connected to the second bit line of the memory cell and the gate of the third transistor, the source of which is connected to a ground voltage node, and the gate of which is connected to the gate of the third transistor.

[0016] Optionally, the seventh transistor is an N-type transistor.

[0017] Optionally, it also includes: an eighth transistor, the drain of which is connected to the second bit line of the memory cell and the gate of the second transistor, the source of which is connected to a ground voltage node, and the gate of which is connected to the gate of the second transistor.

[0018] Optionally, the eighth transistor is an N-type transistor.

[0019] Optionally, it also includes: a ninth transistor, the drain of which is connected to the first bit line of the memory cell and the gate of the first transistor, the source of which is connected to a ground voltage node, and the gate of which is connected to the gate of the first transistor.

[0020] Optionally, the ninth transistor is an N-type transistor.

[0021] Optionally, it also includes: a tenth transistor, the drain of which is connected to the source of the first transistor, the source of the second transistor and the source of the third transistor, and the source of which is connected to a ground voltage node.

[0022] Optionally, the tenth transistor is an N-type transistor.

[0023] Accordingly, the present invention also provides a memory, comprising: a plurality of memory cells, each memory cell including a first bit line and a second bit line; a sensitive amplifier connected to the memory cells, the sensitive amplifier including: a first transistor, the gate of the first transistor being connected to the first bit line of the memory cell; a second transistor, the gate of the second transistor being connected to the second bit line of the memory cell, and the source of the second transistor being connected to the source of the first transistor; a third transistor, the gate of the third transistor being connected to the second bit line of the memory cell, and the source of the third transistor being connected to the source of the second transistor, the sources of the first transistor, the second transistor, and the third transistor being coupled to a ground voltage node, the first transistor, the second transistor, and the third transistor having different threshold voltages; a mirror unit, the mirror unit including a mirrored end, a first mirrored end, and a second mirrored end, the mirrored end being connected to the drain of the first transistor, the first mirrored end being connected to the drain of the second transistor, and the second mirrored end being connected to the drain of the third transistor; a detection unit, the first mirrored end of the mirror unit being connected to the detection unit, and the second mirrored end of the mirror unit being connected to the detection unit; and a read unit connected to the sensitive amplifier.

[0024] Optionally, the mirrored end of the mirror unit includes: a fourth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a first transistor, and the gate of which is connected to the drain of the first transistor.

[0025] Optionally, the first mirror terminal of the mirror unit includes: a fifth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a second transistor, and the gate of which is connected to the gate of a fourth transistor; the detection unit is connected to the drain of the fifth transistor.

[0026] Optionally, the second mirror terminal of the mirror unit includes: a sixth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a third transistor, and the gate of which is connected to the gate of a fourth transistor and the gate of a fifth transistor; the detection unit is connected to the drain of the sixth transistor.

[0027] Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

[0028] Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

[0029] Optionally, the sensitive amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

[0030] Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

[0031] Accordingly, the present invention also provides a method for operating a memory, comprising: providing a memory, the memory comprising: a plurality of memory cells, each memory cell including a first bit line and a second bit line; a sensitive amplifier connected to the memory cells, the sensitive amplifier comprising: a first transistor, the gate of the first transistor being connected to the first bit line of the memory cell; a second transistor, the gate of the second transistor being connected to the second bit line of the memory cell, the source of the second transistor being connected to the source of the first transistor; a third transistor, the gate of the third transistor being connected to the second bit line of the memory cell, the source of the third transistor being connected to the source of the second transistor, the sources of the first transistor, the second transistor, and the third transistor being coupled to a ground voltage node, wherein the first transistor, the second transistor, and the... The threshold voltage of the third transistor is different; a mirror unit, the mirror unit includes a mirrored terminal, a first mirrored terminal and a second mirrored terminal, the mirrored terminal is connected to the drain of the first transistor, the first mirrored terminal is connected to the drain of the second transistor, and the second mirrored terminal is connected to the drain of the third transistor; a detection unit, the first mirrored terminal of the mirror unit is connected to the detection unit, and the second mirrored terminal of the mirror unit is connected to the detection unit; a read unit connected to a sensitive amplifier; comparing the current magnitudes of the mirrored terminal and the first mirrored terminal and outputting a first signal; comparing the current magnitudes of the mirrored terminal and the second mirrored terminal and outputting a second signal; the detection unit compares the first signal and the second signal to obtain a comparison result; the read unit obtains the read cycle corresponding to the comparison result to read the memory.

[0032] Optionally, the method by which the reading unit obtains the corresponding read cycle to read the memory includes: if the first signal and the second signal are the same, the memory is read using the first read cycle; if the first signal and the second signal are different, the memory is read using the second read cycle.

[0033] Optionally, the first read cycle is shorter than the second read cycle.

[0034] Optionally, the mirrored end of the mirror unit includes: a fourth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a first transistor, and the gate of which is connected to the drain of the first transistor.

[0035] Optionally, the first mirror terminal of the mirror unit includes: a fifth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a second transistor, and the gate of which is connected to the gate of a fourth transistor; the detection unit is connected to the drain of the fifth transistor.

[0036] Optionally, the second mirror terminal of the mirror unit includes: a sixth transistor, the source of which is connected to a power supply voltage node, the drain of which is connected to the drain of a third transistor, and the gate of which is connected to the gate of a fourth transistor and the gate of a fifth transistor; the detection unit is connected to the drain of the sixth transistor.

[0037] Optionally, the fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

[0038] Optionally, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

[0039] Optionally, the sensitive amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

[0040] Optionally, the method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the current at the mirror terminal is greater than the current at the first mirror terminal, the first signal is "0"; if the current at the mirror terminal is less than the current at the first mirror terminal, the first signal is "1".

[0041] Optionally, the method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current at the mirror terminal is greater than the current at the second mirror terminal, the second signal is "0"; if the current at the mirror terminal is less than the current at the second mirror terminal, the second signal is "1".

[0042] Optionally, the first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] The sensitive amplifier in this invention features a first transistor, a second transistor, and a third transistor with different threshold voltages. These transistors are connected to the mirrored terminal, the first mirrored terminal, and the second mirrored terminal of a mirror unit, respectively. The different threshold voltages of the first, second, and third transistors result in different current magnitudes. This allows the detection unit to detect and compare the signals output from the first and second mirrored terminals of the mirror unit. Based on the accuracy of the comparison, the strength of the memory cell connected to the sensitive amplifier is determined. This allows for subsequent reading of memory cells with different strengths using different read cycles, thereby improving the overall read / write speed of the memory and enhancing its performance.

[0045] Furthermore, the threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor. The current flowing through the first transistor is the same as the current at the mirror terminal of the mirror unit. After the current at the mirror terminal of the mirror unit is mirrored to the first and second mirror terminals of the mirror unit, the current at the first mirror terminal of the mirror unit is leveled with the current flowing through the second transistor, and the current at the second mirror terminal of the mirror unit is leveled with the current flowing through the third transistor. Thus, the detection unit can determine the strength state of the memory cell connected to the sensitive amplifier by judging whether the signal changes at the first and second mirror terminals of the mirror unit are consistent. If the signal at the first and second mirror terminals of the mirror unit are the same, the memory cell connected to the sensitive amplifier is a strongly driven cell; if the signal at the first and second mirror terminals of the mirror unit are different, the memory cell connected to the sensitive amplifier is a weakly driven cell. Attached Figure Description

[0046] Figure 1 This is a circuit diagram of a voltage-type sensitive amplifier in one embodiment;

[0047] Figure 2 This is a circuit diagram of the sensitive amplifier in an embodiment of the present invention;

[0048] Figure 3 This is a circuit diagram of a sensitive amplifier in another embodiment of the present invention;

[0049] Figure 4 This is a flowchart of the working method of the memory in an embodiment of the present invention. Detailed Implementation

[0050] As described in the background section, the performance of existing memory still needs to be improved.

[0051] Specifically, taking SRAM (Dynamic Random Access Memory) as an example, SRAM performance depends on read operations. The drive capabilities of memory cells in the memory array are inconsistent. To ensure the correctness of SRAM read operations, when the word lines are turned off (the sensitive amplifier is turned on), the bit line swing of all memory cells in the memory array must exceed the offset voltage of the sensitive amplifier. Therefore, the read latency of the memory array depends on the weakest driven memory cell in the array. A weaker driven memory cell results in a relatively larger read latency.

[0052] Throughout the read operation path, the word line driving circuit and the output driving module correspond to ordinary logic circuits. The delay can be reduced by using low-threshold devices and increasing transistor size. However, the delay of the memory array is determined by the driving capability of the memory cell. Compared with logic circuits, the driving capability of SRAM memory cells is relatively weak, so its discharge delay is relatively large.

[0053] When the power supply voltage drops to near the threshold region, local process fluctuations cause a significant tailing phenomenon in the statistical distribution of the discharge delay of the memory cell bit lines. The discharge delay of the vast majority of memory cells is within 15ns, and only a few weakly driven memory cells have a discharge delay between 15ns and 30ns. The weakly driven memory cells cause the design margin to increase further as the power supply voltage decreases. The overly pessimistic design margin causes the performance of the memory array to drop sharply, thus the overall performance of SRAM drops sharply.

[0054] Figure 1 This is a circuit of a voltage-type sensitive amplifier. An example of a sensitive amplifier is provided to analyze and explain the impact of transistor mismatch caused by local process fluctuations on the output of the sensitive amplifier.

[0055] Please refer to Figure 1The sensitive amplifier includes: a first transistor M1; a second transistor M2, the drain of the second transistor M2 being connected to the gate of the first transistor M1, and the drain of the first transistor M1 being connected to the gate of the second transistor M2; a third transistor M3 and a fourth transistor M4, the source of the third transistor M3 being connected to the source of the fourth transistor M4, the drain of the third transistor M3 being connected to the drain of the fourth transistor M4, the sources of the third transistor M3 and the fourth transistor M4 being connected to the power supply voltage node VDD, the drains of the third transistor M3 and the fourth transistor M4 being connected to the drain of the first transistor M1, and the gate of the fourth transistor M4 being connected to the gate of the first transistor M1; a fifth transistor M5 and a sixth transistor M6, the source of the fifth transistor M5 being connected to the source of the sixth transistor M6, the drain of the fifth transistor M5 being connected to the drain of the sixth transistor M6, and the sources of the fifth transistor M5 and the sixth transistor M6 being connected to the power supply voltage node VDD. The following transistors are connected: a voltage-limited junction (VDD), a fifth transistor M5, a sixth transistor M6, and a second transistor M2; a gate of the sixth transistor M6 and a second transistor M2; a seventh transistor M7, whose drain is connected to the source of the first transistor M1 and whose gate is connected to the first bit line IN of the memory cell; an eighth transistor M8, whose drain is connected to the source of the second transistor M2 and whose gate is connected to the second bit line INB of the memory cell; a source of the eighth transistor M8 and a seventh transistor M7; a ninth transistor M9, whose drain is connected to the sources of the eighth transistor M8 and the seventh transistor M7, whose source is connected to the ground voltage node; a third transistor M3 and a ninth transistor M9; and a sixth transistor M6 and a ninth transistor M9.

[0056] In the sensitive amplifier, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are P-type transistors; the first transistor M1, the second transistor M2, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9 are N-type transistors.

[0057] In the sensitive amplifier, when local process fluctuations result in a weak driving force for the memory cell, the voltage difference Vinput between the seventh transistor M7 connected to the first bit line IN and the eighth transistor M8 connected to the second bit line INB is small. Vinput may be less than the bias voltage Voffset of the sensitive amplifier, which may cause the output of the sensitive amplifier to be erroneous and affect the performance of the memory.

[0058] To address the aforementioned problems, the present invention provides a sensitive amplifier, a memory, and a method for operating the memory. By setting different threshold voltages for the first, second, and third transistors in the sensitive amplifier, and connecting these transistors to the mirrored terminal, first mirrored terminal, and second mirrored terminal of a mirror unit, respectively, the different threshold voltages of the transistors result in different current magnitudes. This allows the detection unit to detect and compare the signals output from the first and second mirrored terminals of the mirror unit. Based on the accuracy of the comparison, the strength of the memory cell connected to the sensitive amplifier is determined. This allows for subsequent reading of memory cells with different strengths using different read cycles, thereby improving the overall read / write speed of the memory and enhancing its performance.

[0059] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0060] Figure 2 This is a circuit diagram of the sensitive amplifier in an embodiment of the present invention.

[0061] Please refer to Figure 2 The sensitive amplifier includes: a first transistor M1, the gate of which is connected to the first bit line BL of the memory cell;

[0062] The second transistor M2 has its gate connected to the second bit line BLB of the memory cell, and its source connected to the source of the first transistor M1.

[0063] The third transistor M3 has its gate connected to the second bit line BLB of the memory cell, and its source connected to the source of the second transistor M2. The sources of the first transistor M1, the second transistor M2, and the third transistor M3 are coupled to a ground voltage node. The threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different.

[0064] A mirror unit, comprising a mirrored end, a first mirrored end, and a second mirrored end, wherein the mirrored end is connected to the drain of a first transistor M1, the first mirrored end is connected to the drain of a second transistor M2, and the second mirrored end is connected to the drain of a third transistor M3.

[0065] The detection unit T is connected to the first mirror end of the mirror unit and the second mirror end of the mirror unit.

[0066] In this embodiment, the mirrored end of the mirror unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, the drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and the gate of the fourth transistor M4 is connected to the drain of the first transistor M1.

[0067] In this embodiment, the first mirror terminal of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, the drain of the fifth transistor M5 is connected to the drain of the second transistor M2, and the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.

[0068] In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, the drain of the sixth transistor M6 is connected to the drain of the third transistor M3, and the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.

[0069] In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.

[0070] The threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different, resulting in different current magnitudes in the first transistor M1, the second transistor M2, and the third transistor M3. This allows the detection unit T to detect and compare the signals output from the first and second mirror terminals of the mirror unit. Based on the correctness of the comparison result, the strength state of the memory cell connected to the sensitive amplifier is determined. This allows for subsequent reading of memory cells with different strength states using different read cycles, thereby improving the overall read / write speed of the memory and enhancing its performance.

[0071] In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.

[0072] Therefore, the current flowing through the first transistor M1 is the same as the current at the mirror terminal of the mirror unit. After the current at the mirror terminal of the mirror unit is mirrored to the first and second mirror terminals of the mirror unit, the current at the first mirror terminal of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirror terminal of the mirror unit is leveled with the current flowing through the third transistor M3. Thus, the detection unit can determine the strength of the memory cell connected to the sensitive amplifier by judging whether the signal changes at the first and second mirror terminals of the mirror unit are consistent. If the signal at the first and second mirror terminals of the mirror unit are the same, the memory cell connected to the sensitive amplifier is a strongly driven cell; if the signal at the first and second mirror terminals of the mirror unit are different, the memory cell connected to the sensitive amplifier is a weakly driven cell.

[0073] In this embodiment, the mirror unit further includes a voltage input node (not shown), which is connected to the power supply voltage node VDD.

[0074] In this embodiment, it further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror unit and the detection unit T.

[0075] The first inverter B1 is used to shape the current signal output from the first mirror terminal so that the signal arriving at the detection unit T is a standard logic signal, which the detection unit T can then identify and judge. The standard logic signal is a first signal. The first signal is the result of comparing the current magnitudes at the mirror terminal and the first mirror terminal.

[0076] The second inverter B2 is used to shape the current signal output from the second mirror terminal so that the signal arriving at the detection unit T is a standard logic signal, which the detection unit T can then identify and judge. This standard logic signal is the second signal. The second signal is the result of comparing the current magnitudes at the first mirror terminal and the second mirror terminal.

[0077] The first signal is 0 or 1; the second signal is 0 or 1.

[0078] In other embodiments, the circuit may also exclude the first inverter and the second inverter.

[0079] In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.

[0080] In this embodiment, it further includes: a seventh transistor M7, the drain of the seventh transistor M7 is connected to the second bit line BLB of the memory cell and the gate of the third transistor M3, the source of the seventh transistor M7 is connected to the ground voltage node, and the gate of the seventh transistor M7 is connected to the gate of the third transistor M3.

[0081] The seventh transistor M7 acts as a current mirror, and the current flowing through the seventh transistor M7 is mirrored to the third transistor M3.

[0082] In other embodiments, the circuit may also exclude the seventh transistor M7.

[0083] In this embodiment, the seventh transistor M7 is an N-type transistor.

[0084] In this embodiment, it further includes: an eighth transistor M8, the drain of the eighth transistor M8 is connected to the second bit line BLB of the memory cell and the gate of the second transistor M2, the source of the eighth transistor M8 is connected to the ground voltage node, and the gate of the eighth transistor M8 is connected to the gate of the second transistor M2.

[0085] The eighth transistor M8 acts as a current mirror, reflecting the current flowing through the eighth transistor M8 to the second transistor M2.

[0086] In other embodiments, the circuit may also exclude the eighth transistor M8.

[0087] In this embodiment, the eighth transistor M8 is an N-type transistor.

[0088] In this embodiment, it further includes: a ninth transistor M9, the drain of the ninth transistor M9 being connected to the first bit line BL of the memory cell and the gate of the first transistor M1, the source of the ninth transistor M9 being connected to the ground voltage node, and the gate of the ninth transistor M9 being connected to the gate of the first transistor M1.

[0089] The ninth transistor M9 acts as a current mirror, reflecting the current flowing through the ninth transistor M9 to the first transistor M1.

[0090] In other embodiments, the circuit may also exclude the ninth transistor M9.

[0091] In this embodiment, the ninth transistor M9 is an N-type transistor.

[0092] In this embodiment, it further includes: a tenth transistor M10, the drain of the tenth transistor M10 being connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, and the source of the tenth transistor M10 being connected to a ground voltage node.

[0093] In this embodiment, the tenth transistor M10 is an N-type transistor.

[0094] The tenth transistor M10 is used as a switch to turn on the sensitive amplifier circuit.

[0095] Figure 3 This is a circuit diagram of a sensitive amplifier in another embodiment of the present invention.

[0096] Please refer to Figure 3 The sensitive amplifier includes: a first transistor M1, the gate of which is connected to the first bit line BL of the memory cell;

[0097] The second transistor M2 has its gate connected to the second bit line BLB of the memory cell, and its source connected to the source of the first transistor M1.

[0098] The third transistor M3 has its gate connected to the second bit line BLB of the memory cell, and its source connected to the source of the second transistor M2. The sources of the first transistor M1, the second transistor M2, and the third transistor M3 are coupled to a ground voltage node. The threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different.

[0099] A mirror unit, comprising a mirrored end, a first mirrored end, and a second mirrored end, wherein the mirrored end is connected to the drain of a first transistor M1, the first mirrored end is connected to the drain of a second transistor M2, and the second mirrored end is connected to the drain of a third transistor M3.

[0100] The detection unit T is connected to the first mirror end of the mirror unit and the second mirror end of the mirror unit.

[0101] In this embodiment, the mirrored end of the mirror unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, the drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and the gate of the fourth transistor M4 is connected to the drain of the first transistor M1.

[0102] In this embodiment, the first mirror terminal of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, the drain of the fifth transistor M5 is connected to the drain of the second transistor M2, and the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.

[0103] In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, the drain of the sixth transistor M6 is connected to the drain of the third transistor M3, and the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.

[0104] In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.

[0105] The threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different, resulting in different current magnitudes in the first transistor M1, the second transistor M2, and the third transistor M3. This allows the detection unit T to detect and compare the signals output from the first and second mirror terminals of the mirror unit. Based on the correctness of the comparison result, the strength state of the memory cell connected to the sensitive amplifier is determined. This allows for subsequent reading of memory cells with different strength states using different read cycles, thereby improving the overall read / write speed of the memory and enhancing its performance.

[0106] In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.

[0107] Therefore, the current flowing through the first transistor M1 is the same as the current at the mirror terminal of the mirror unit. After the current at the mirror terminal of the mirror unit is mirrored to the first and second mirror terminals of the mirror unit, the current at the first mirror terminal of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirror terminal of the mirror unit is leveled with the current flowing through the third transistor M3. Thus, the detection unit can determine the strength of the memory cell connected to the sensitive amplifier by judging whether the signal changes at the first and second mirror terminals of the mirror unit are consistent. If the signal at the first and second mirror terminals of the mirror unit are the same, the memory cell connected to the sensitive amplifier is a strongly driven cell; if the signal at the first and second mirror terminals of the mirror unit are different, the memory cell connected to the sensitive amplifier is a weakly driven cell.

[0108] In this embodiment, the mirror unit further includes a voltage input node (not shown), which is connected to the power supply voltage node VDD.

[0109] In this embodiment, it further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror unit and the detection unit T.

[0110] The first inverter B1 is used to shape the current signal output from the first mirror terminal so that the signal arriving at the detection unit T is a standard logic signal, which the detection unit T can then identify and judge. The standard logic signal is a first signal. The first signal is the result of comparing the current magnitudes at the mirror terminal and the first mirror terminal.

[0111] The second inverter B2 is used to shape the current signal output from the second mirror terminal so that the signal arriving at the detection unit T is a standard logic signal, which the detection unit T can then identify and judge. This standard logic signal is the second signal. The second signal is the result of comparing the current magnitudes at the first mirror terminal and the second mirror terminal.

[0112] The first signal is 0 or 1; the second signal is 0 or 1.

[0113] In other embodiments, the circuit may also exclude the first inverter and the second inverter.

[0114] In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.

[0115] In this embodiment, it further includes: a tenth transistor M10, the drain of the tenth transistor M10 being connected to the source of the first transistor M1, the source of the second transistor M2 and the source of the third transistor M3, and the source of the tenth transistor M10 being connected to a ground voltage node.

[0116] In this embodiment, the tenth transistor M10 is an N-type transistor.

[0117] The tenth transistor M10 is used as a switch to turn on the sensitive amplifier circuit.

[0118] Figure 4 This is a flowchart of the working method of the memory in an embodiment of the present invention.

[0119] Please refer to Figure 4 The operating method of the memory includes:

[0120] S100: Provides memory.

[0121] The memory includes: a plurality of storage cells, each storage cell including a first bit line and a second bit line; a sensitive amplifier connected to the storage cells; and a read unit connected to the sensitive amplifier.

[0122] S101: Compare the current magnitudes of the mirror terminal and the first mirror terminal and output a first signal; compare the current magnitudes of the mirror terminal and the second mirror terminal and output a second signal.

[0123] S102: Compare and judge the first signal of the first mirror end and the second signal of the second mirror end, and obtain the comparison result.

[0124] S103: The reading unit obtains the read cycle corresponding to the comparison result and reads the memory.

[0125] Please refer to the circuit diagram of the aforementioned sensitive amplifier. Figure 2The system includes: a first transistor M1, the gate of which is connected to the first bit line BL of the memory cell; a second transistor M2, the gate of which is connected to the second bit line BLB of the memory cell, and the source of which is connected to the source of the first transistor M1; a third transistor M3, the gate of which is connected to the second bit line BLB of the memory cell, and the source of which is connected to the source of the second transistor M2; the sources of the first transistor M1, the second transistor M2, and the third transistor M3 are coupled to a ground voltage node; and the threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different; a mirror unit, which includes a mirrored terminal, a first mirrored terminal, and a second mirrored terminal, the mirrored terminal being connected to the drain of the first transistor M1, the first mirrored terminal being connected to the drain of the second transistor M2, and the second mirrored terminal being connected to the drain of the third transistor M3; and a detection unit T, the first mirrored terminal of which is connected to the detection unit T, and the second mirrored terminal of which is connected to the detection unit T.

[0126] In this embodiment, the method for the reading unit to obtain the corresponding read cycle to read the memory includes: if the first signal and the second signal are the same, the memory is read using the first read cycle; if the first signal and the second signal are different, the memory is read using the second read cycle.

[0127] In this embodiment, the first read cycle is shorter than the second read cycle.

[0128] If the first signal and the second signal are the same, the memory cell connected to the sensitive amplifier is the cell with stronger drive, and a shorter first read cycle is used to read the memory cell with stronger drive. If the first signal and the second signal are different, the memory cell connected to the sensitive amplifier is the cell with weaker drive, and a longer second read cycle is used to read the memory cell with weaker drive. By using different read cycles to read memory cells with different drive states in the memory array, the overall read and write speed of the memory is improved, thus enhancing the memory performance.

[0129] In this embodiment, there can be multiple second read cycles.

[0130] In this embodiment, the mirrored end of the mirror unit includes: a fourth transistor M4, the source of the fourth transistor M4 is connected to the power supply voltage node VDD, the drain of the fourth transistor M4 is connected to the drain of the first transistor M1, and the gate of the fourth transistor M4 is connected to the drain of the first transistor M1.

[0131] In this embodiment, the first mirror terminal of the mirror unit includes: a fifth transistor M5, the source of the fifth transistor M5 is connected to the power supply voltage node VDD, the drain of the fifth transistor M5 is connected to the drain of the second transistor M2, and the gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4; the detection unit T is connected to the drain of the fifth transistor M5.

[0132] In this embodiment, the second mirror terminal of the mirror unit includes: a sixth transistor M6, the source of the sixth transistor M6 is connected to the power supply voltage node VDD, the drain of the sixth transistor M6 is connected to the drain of the third transistor M3, and the gate of the sixth transistor M6 is connected to the gate of the fourth transistor M4 and the gate of the fifth transistor M5; the detection unit T is connected to the drain of the sixth transistor M6.

[0133] In this embodiment, the fourth transistor M4 is a P-type transistor; the fifth transistor M5 is a P-type transistor; and the sixth transistor M6 is a P-type transistor.

[0134] The threshold voltages of the first transistor M1, the second transistor M2, and the third transistor M3 are different, resulting in different current magnitudes in the first transistor M1, the second transistor M2, and the third transistor M3. This allows the detection unit T to detect and compare the signals output from the first and second mirror terminals of the mirror unit. Based on the correctness of the comparison result, the strength state of the memory cell connected to the sensitive amplifier is determined. This allows for subsequent reading of memory cells with different strength states using different read cycles, thereby improving the overall read / write speed of the memory and enhancing its performance.

[0135] In this embodiment, the threshold voltage of the first transistor M1 is greater than the threshold voltage of the second transistor M2; the threshold voltage of the third transistor M3 is greater than the threshold voltage of the first transistor M1.

[0136] Therefore, the current flowing through the first transistor M1 is the same as the current at the mirror terminal of the mirror unit. After the current at the mirror terminal of the mirror unit is mirrored to the first and second mirror terminals of the mirror unit, the current at the first mirror terminal of the mirror unit is leveled with the current flowing through the second transistor M2, and the current at the second mirror terminal of the mirror unit is leveled with the current flowing through the third transistor M3. Thus, the detection unit can determine the strength of the memory cell connected to the sensitive amplifier by judging whether the signal changes at the first and second mirror terminals of the mirror unit are consistent. If the signal at the first and second mirror terminals of the mirror unit are the same, the memory cell connected to the sensitive amplifier is a strongly driven cell; if the signal at the first and second mirror terminals of the mirror unit are different, the memory cell connected to the sensitive amplifier is a weakly driven cell.

[0137] In this embodiment, the sensitive amplifier further includes: a first inverter B1 and a second inverter B2; the first inverter B1 is connected to the first mirror terminal of the mirror unit and the detection unit T; the second inverter B2 is connected to the second mirror terminal of the mirror unit and the detection unit T.

[0138] The first inverter B1 shapes the current signal output from the first mirror terminal, making the signal arriving at the detection unit T a standard logic signal for identification and judgment by the detection unit T. The standard logic signal is a first signal. The first signal is the result of comparing the current magnitudes at the mirror terminal and the first mirror terminal. The second inverter B2 shapes the current signal output from the second mirror terminal, making the signal arriving at the detection unit T a standard logic signal for identification and judgment by the detection unit T. The standard logic signal is a second signal. The second signal is the result of comparing the current magnitudes at the mirror terminal and the second mirror terminal.

[0139] The first signal is 0 or 1; the second signal is 0 or 1.

[0140] The method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the current at the mirror terminal is greater than the current at the first mirror terminal, the first signal is "0"; if the current at the mirror terminal is less than the current at the first mirror terminal, the first signal is "1".

[0141] The method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current at the mirror terminal is greater than the current at the second mirror terminal, the second signal is "0"; if the current at the mirror terminal is less than the current at the second mirror terminal, the second signal is "1".

[0142] In this embodiment, the first transistor M1 is an N-type transistor; the second transistor M2 is an N-type transistor; and the third transistor M3 is an N-type transistor.

[0143] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A sensitive amplifier, characterized in that, include: The first transistor has its gate connected to the first bit line of the memory cell; The second transistor has its gate connected to the second bit line of the memory cell, and its source connected to the source of the first transistor. The third transistor has its gate connected to the second bit line of the memory cell, and its source connected to the source of the second transistor. The sources of the first transistor, the second transistor, and the third transistor are coupled to a ground voltage node. The threshold voltages of the first transistor, the second transistor, and the third transistor are different. A mirror unit includes a mirrored end, a first mirrored end, and a second mirrored end. The mirrored end of the mirror unit includes a fourth transistor, the drain of which is connected to the drain of the first transistor. The first mirrored end of the mirror unit includes a fifth transistor, the drain of which is connected to the drain of the second transistor. The second mirrored end of the mirror unit includes a sixth transistor, the drain of which is connected to the drain of the third transistor. The detection unit is connected to the drain of the fifth transistor and the drain of the sixth transistor.

2. The sensitive amplifier as described in claim 1, characterized in that, Also includes: The source of the fourth transistor is connected to the power supply voltage node, and the gate of the fourth transistor is connected to the drain of the first transistor.

3. The sensitive amplifier as described in claim 2, characterized in that, Also includes: The fifth transistor has its source connected to the power supply voltage node and its gate connected to the gate of the fourth transistor.

4. The sensitive amplifier as described in claim 3, characterized in that, Also includes: The source of the sixth transistor is connected to the power supply voltage node, and the gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor.

5. The sensitive amplifier as described in claim 4, characterized in that, The fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

6. The sensitive amplifier as described in claim 1, characterized in that, The mirror unit also includes a voltage input node, which is connected to the power supply voltage node.

7. The sensitive amplifier as described in claim 1, characterized in that, The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

8. The sensitive amplifier as described in claim 1, characterized in that, It also includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

9. The sensitive amplifier as described in claim 1, characterized in that, The first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

10. The sensitive amplifier as claimed in claim 1, characterized in that, Also includes: The seventh transistor has its drain connected to the second bit line of the memory cell and the gate of the third transistor, its source connected to the ground voltage node, and its gate connected to the gate of the third transistor.

11. The sensitive amplifier as claimed in claim 10, characterized in that, The seventh transistor is an N-type transistor.

12. The sensitive amplifier as described in claim 1, characterized in that, Also includes: The eighth transistor has its drain connected to the second bit line of the memory cell and the gate of the second transistor, its source connected to the ground voltage node, and its gate connected to the gate of the second transistor.

13. The sensitive amplifier as described in claim 12, characterized in that, The eighth transistor is an N-type transistor.

14. The sensitive amplifier as claimed in claim 1, characterized in that, Also includes: The ninth transistor has its drain connected to the first bit line of the memory cell and the gate of the first transistor, its source connected to the ground voltage node, and its gate connected to the gate of the first transistor.

15. The sensitive amplifier as described in claim 14, characterized in that, The ninth transistor is an N-type transistor.

16. The sensitive amplifier as claimed in claim 1, characterized in that, Also includes: The tenth transistor has its drain connected to the source of the first transistor, the source of the second transistor, and the source of the third transistor, and its source connected to a ground voltage node.

17. The sensitive amplifier as claimed in claim 16, characterized in that, The tenth transistor is an N-type transistor.

18. A memory, characterized in that, include: A plurality of storage cells, wherein the storage cells include a first bit line and a second bit line; A sensitive amplifier connected to a storage unit, the sensitive amplifier comprising: A first transistor, the gate of which is connected to the first bit line of the memory cell; a second transistor, the gate of which is connected to the second bit line of the memory cell, and the source of which is connected to the source of the first transistor; a third transistor, the gate of which is connected to the second bit line of the memory cell, and the source of which is connected to the source of the second transistor; the sources of the first transistor, the second transistor, and the third transistor are coupled to a ground voltage node; the threshold voltages of the first transistor, the second transistor, and the third transistor are different; a mirror unit, the mirror unit including a mirrored terminal, a first mirrored terminal, and a second mirrored terminal; the mirrored terminal of the mirror unit includes: a fourth transistor, the drain of which is connected to the drain of the first transistor; the first mirrored terminal of the mirror unit includes: a fifth transistor, the drain of which is connected to the drain of the second transistor; the second mirrored terminal of the mirror unit includes: a sixth transistor, the drain of which is connected to the drain of the third transistor; a detection unit, the drain of the fifth transistor is connected to the detection unit, and the drain of the sixth transistor is connected to the detection unit; A readout unit connected to a sensitive amplifier.

19. The memory as claimed in claim 18, characterized in that, The source of the fourth transistor is connected to the power supply voltage node, and the gate of the fourth transistor is connected to the drain of the first transistor.

20. The memory as claimed in claim 19, characterized in that, The source of the fifth transistor is connected to the power supply voltage node, and the gate of the fifth transistor is connected to the gate of the fourth transistor.

21. The memory as claimed in claim 20, characterized in that, The source of the sixth transistor is connected to the power supply voltage node, and the gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor.

22. The memory as claimed in claim 21, characterized in that, The fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

23. The memory as claimed in claim 18, characterized in that, The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

24. The memory as claimed in claim 18, characterized in that, The sensitive amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

25. The memory as claimed in claim 18, characterized in that, The first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

26. A method for operating a memory, characterized in that, include: Provide a memory, the memory comprising: A plurality of storage cells, wherein the storage cells include a first bit line and a second bit line; A sensitive amplifier connected to a memory cell, the sensitive amplifier comprising: a first transistor, the gate of the first transistor being connected to a first bit line of the memory cell; a second transistor, the gate of the second transistor being connected to a second bit line of the memory cell, and the source of the second transistor being connected to the source of the first transistor; a third transistor, the gate of the third transistor being connected to the second bit line of the memory cell, and the source of the third transistor being connected to the source of the second transistor, the sources of the first transistor, the second transistor, and the third transistor being coupled to a ground voltage node, and the first transistor, the second transistor, and the third transistor having different threshold voltages; a mirror unit, the mirror unit comprising a mirrored terminal, a first mirrored terminal, and a second mirrored terminal, the mirrored terminal of the mirror unit comprising: a fourth transistor, the drain of the fourth transistor being connected to the drain of the first transistor; the first mirrored terminal of the mirror unit comprising: a fifth transistor, the drain of the fifth transistor being connected to the drain of the second transistor; the second mirrored terminal of the mirror unit comprising: a sixth transistor, the drain of the sixth transistor being connected to the drain of the third transistor; and a detection unit, the drain of the fifth transistor being connected to the detection unit, and the drain of the sixth transistor being connected to the detection unit. A readout unit connected to a sensitive amplifier; The current magnitudes at the mirror terminal and the first mirror terminal are compared and a first signal is output; the current magnitudes at the mirror terminal and the second mirror terminal are compared and a second signal is output. The detection unit compares and judges the first signal and the second signal to obtain a comparison result; The reading unit acquires the read cycle corresponding to the comparison result and reads the memory.

27. The method of operating the memory as described in claim 26, characterized in that, The method for the reading unit to obtain the corresponding read cycle to read the memory includes: if the first signal and the second signal are the same, the memory is read using the first read cycle; if the first signal and the second signal are different, the memory is read using the second read cycle.

28. The method of operating the memory as described in claim 27, characterized in that, The first read cycle is shorter than the second read cycle.

29. The method of operating the memory as described in claim 26, characterized in that, The source of the fourth transistor is connected to the power supply voltage node, and the gate of the fourth transistor is connected to the drain of the first transistor.

30. The method of operating the memory as described in claim 29, characterized in that, The source of the fifth transistor is connected to the power supply voltage node, and the gate of the fifth transistor is connected to the gate of the fourth transistor.

31. The method of operating the memory as described in claim 30, characterized in that, The source of the sixth transistor is connected to the power supply voltage node, and the gate of the sixth transistor is connected to the gate of the fourth transistor and the gate of the fifth transistor.

32. The method of operating the memory as described in claim 31, characterized in that, The fourth transistor is a P-type transistor; the fifth transistor is a P-type transistor; and the sixth transistor is a P-type transistor.

33. The method of operating the memory as described in claim 26, characterized in that, The threshold voltage of the first transistor is greater than the threshold voltage of the second transistor; the threshold voltage of the third transistor is greater than the threshold voltage of the first transistor.

34. The method of operating the memory as described in claim 26, characterized in that, The sensitive amplifier further includes: a first inverter and a second inverter; the first inverter is connected to the first mirror terminal of the mirror unit and the detection unit; the second inverter is connected to the second mirror terminal of the mirror unit and the detection unit.

35. The method of operating the memory as described in claim 26, characterized in that, The method for comparing the current magnitudes of the mirror terminal and the first mirror terminal includes: if the current at the mirror terminal is greater than the current at the first mirror terminal, the first signal is "0"; if the current at the mirror terminal is less than the current at the first mirror terminal, the first signal is "1".

36. The method of operating the memory as described in claim 26, characterized in that, The method for comparing the current magnitudes of the mirror terminal and the second mirror terminal includes: if the current at the mirror terminal is greater than the current at the second mirror terminal, the second signal is "0"; if the current at the mirror terminal is less than the current at the second mirror terminal, the second signal is "1".

37. The method of operating the memory as described in claim 26, characterized in that, The first transistor is an N-type transistor; the second transistor is an N-type transistor; and the third transistor is an N-type transistor.

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