A memory device, memory system, and method of operation

Abstract

A memory device, a memory system and an operating method are disclosed. The memory device includes a memory array including a plurality of memory blocks; and a control circuit coupled to the memory array and configured to control the memory array; the control circuit is configured to: determine a first average of threshold voltages of bottom dummy cells in a non-used memory block; determine a difference between the first average and a first reference value; determine whether to program the bottom dummy cells in the memory block based on the difference to make the first average reach a first threshold value; the first threshold value is used to reduce a potential difference between an edge word line and an adjacent non-edge word line when programming memory cells coupled to a selected non-edge word line; the edge word line is at least one word line adjacent to a source line among the plurality of word lines; the non-edge word line is a word line other than the edge word line among the plurality of word lines; and the selected non-edge word line is not adjacent to the edge word line.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory technology, and in particular to a memory device, a memory system and an operating method. BACKGROUND

[0002] Non-volatile memory has been widely used in electronic devices in various fields. Flash memory is one of the most widely used non-volatile memories that can be electrically erased and reprogrammed, and can include NOR and NAND architecture memories, wherein the threshold voltage of each memory cell in the flash memory is changed to the required level to implement various operations such as reading, programming and erasing. When operating the flash memory, the erasing operation can be performed at the block level, the programming operation can be performed at the page level, and the reading operation can be performed at the memory cell level. Currently, planar structure NAND flash memory has been widely used, and in order to further improve the storage capacity of the flash memory and reduce the storage cost per bit, a three-dimensional (3D) NAND memory structure is proposed, which includes a substrate, a stack structure disposed on the substrate, a plurality of channel holes penetrating the stack structure, and a storage structure disposed in the channel hole, the storage structure includes a charge storage layer disposed on the side wall surface of the channel hole and a channel layer disposed on the side wall surface of the charge storage layer. The position where the storage structure in each channel hole intersects with each control gate corresponds to a memory cell. In the 3D NAND structure, when programming a memory cell at a certain layer of a certain channel hole, other memory cells at other layers of other channel holes can be subjected to hot carrier injection (HCI) type programming interference. SUMMARY

[0003] Therefore, the main purpose of the present application is to provide a memory device, a memory system and an operating method to reduce the HCI type programming interference when the 3D NAND performs programming.

[0004] To achieve the above purpose, the technical solution of the present application is as follows:

[0005] In a first aspect, the present application provides a memory device, comprising a memory array, the memory array including a plurality of memory blocks; each memory block including a plurality of memory cell strings; each memory cell string including a top dummy cell, a plurality of memory cells and a bottom dummy cell connected in series; wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are respectively coupled to a plurality of word lines; and the top dummy cell is coupled to a top dummy word line.

[0006] and control circuitry coupled to the memory array and configured to control the memory array;

[0007] wherein the control circuitry is configured to:

[0008] determine a first average of threshold voltages of bottom dummy cells in a non-used memory block;

[0009] determine a difference between the first average and a first reference value;

[0010] determine whether to program the bottom dummy cells in the memory block to cause the first average to reach a first threshold value based on the difference; the first threshold value is used to cause a potential difference between an edge word line and an adjacent non-edge word line to be reduced when programming memory cells coupled to a selected non-edge word line in a selected memory cell string; the edge word line is at least one word line of the plurality of word lines adjacent to the source line; the non-edge word line is a word line of the plurality of word lines other than the edge word line; the selected non-edge word line is not adjacent to the edge word line.

[0011] In a second aspect, the present application provides a method for programming a memory device, the memory device comprising a memory array, the memory array comprising a plurality of memory blocks; each memory block comprising a plurality of memory cell strings; each memory cell string comprising a top dummy cell, a memory cell, and a bottom dummy cell connected in series, wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are coupled to a plurality of word lines, respectively; the top dummy cell is coupled to a top dummy word line; the method comprising:

[0012] determining a first average of threshold voltages of bottom dummy cells in a non-used memory block;

[0013] determining a difference between the first average and a first reference value;

[0014] determining whether to program the bottom dummy cells in the memory block to cause the first average to reach a first threshold value based on the difference; the first threshold value is used to cause a potential difference between an edge word line and an adjacent non-edge word line to be reduced when programming memory cells coupled to a selected non-edge word line in a selected memory cell string; the edge word line is at least one word line of the plurality of word lines adjacent to the source line; the non-edge word line is a word line of the plurality of word lines other than the edge word line; the selected non-edge word line is not adjacent to the edge word line.

[0015] In a third aspect, the embodiments of the present application also provide a memory system, comprising a memory device, the memory device comprising a memory array, the memory array comprising a plurality of memory blocks; each memory block comprising a plurality of strings of memory cells; each string of memory cells comprising a top dummy cell, a plurality of memory cells, and a bottom dummy cell connected in series; wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are respectively coupled to a plurality of word lines; the top dummy cell is coupled to a top dummy word line; and a control circuit coupled to the memory array and configured to control the memory array; wherein the control circuit is configured to: determine a first average of threshold voltages of the bottom dummy cells in a memory block that has not been used; determine a difference between the first average and a first reference value; determine whether to program the bottom dummy cells in the memory block based on the difference to cause the first average to reach a first threshold value; the first threshold value is used to cause a potential difference between an edge word line and an adjacent non-edge word line to decrease when programming memory cells coupled to the selected non-edge word line; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is a word line other than the edge word line among the plurality of word lines; the selected non-edge word line is not adjacent to the edge word line;

[0016] and,

[0017] a memory controller coupled to the memory device, the memory controller configured to control the memory device.

[0018] Embodiments of the present disclosure provide a memory device, a memory system and an operating method. The memory device includes a memory array including a plurality of memory blocks, each memory block including a plurality of memory cell strings, each memory cell string including a top dummy cell, a plurality of memory cells and a bottom dummy cell connected in series, the top dummy cell connected to a bit line, the bottom dummy cell connected to a source line, the bottom dummy cell coupled to a bottom dummy word line, the plurality of memory cells coupled to a plurality of word lines, the top dummy cell coupled to a top dummy word line, and a control circuit coupled to the memory array and configured to control the memory array, the control circuit configured to determine a first average of threshold voltages of the bottom dummy cells in an unused memory block, determine a difference between the first average and a first reference value, determine whether to program the bottom dummy cells in the memory block based on the difference to reach a first threshold value, the first threshold value configured to reduce a potential difference between an edge word line and an adjacent non-edge word line when programming memory cells coupled to a selected non-edge word line, the edge word line being at least one word line adjacent to the source line among the plurality of word lines, the non-edge word line being a word line other than the edge word line among the plurality of word lines, the selected non-edge word line being non-adjacent to the edge word line. The memory device, the memory system and the operating method provided by embodiments of the present disclosure compare the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line in the memory device with a reference value to determine whether to program the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line in the memory device to a target value (i.e., the first threshold value), at which the potential difference between the adjacent edge word line (e.g., word line WL1) and the non-edge word line (e.g., word line WL2) is reduced, so as to reduce the HCI type interference on the edge word line (e.g., word line WL1) during programming of the non-edge word line (e.g., word line WL3), and further reduce the impact on the read window margin. BRIEF DESCRIPTION OF DRAWINGS

[0019] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings generally

[0020] Figure 1 A structure diagram of a NAND string provided by embodiments of the present disclosure;

[0021] Figure 2 An equivalent circuit diagram of a NAND string provided by embodiments of the present disclosure;

[0022] Figure 3 An array structure diagram of a memory cell provided by an embodiment of the present application;

[0023] Figure 4 A structure diagram of a monolithic three-dimensional memory array provided by an embodiment of the present application;

[0024] Figures 5A to 5E A related structure diagram of a three-dimensional NAND provided by an embodiment of the present application;

[0025] Figure 6 A structure diagram of a memory device provided by an embodiment of the present application with read / write circuitry for parallel reading and programming of a memory cell array;

[0026] Figure 7 A structure diagram between a peripheral circuit and a memory array provided by an embodiment of the present application;

[0027] Figure 8 A curve diagram of threshold voltage and number of memory cells provided by an embodiment of the present application;

[0028] Figure 9 A flowchart of programming provided by an embodiment of the present application;

[0029] Figure 10 A structure diagram of a programming pulse of ISPP provided by an embodiment of the present application;

[0030] Figure 11 A structure diagram of a memory device provided by an embodiment of the present application;

[0031] Figure 12 A diagram of a first average value of threshold voltage of a bottom dummy cell provided by an embodiment of the present application;

[0032] Figure 13 A diagram of an optional embodiment of applying a programming voltage and a pass voltage when programming a memory device provided by an embodiment of the present application;

[0033] Figure 14 A flowchart of a method of programming a memory device provided by an embodiment of the present application;

[0034] Figure 15 A structure diagram of a memory system provided by an embodiment of the present application;

[0035] FIG. 16(A) is a diagram of an exemplary memory card with a memory system according to some aspects of the present application;

[0036] FIG. 16(B) is a schematic diagram of an exemplary solid state drive (SSD) having a memory system, in accordance with aspects of the present application. DETAILED DESCRIPTION

[0037] Various embodiments of the application are described in greater detail below. Embodiments of the application can be configured or arranged differently, or otherwise modified, to form other embodiments of the application that can be considered as variants of any disclosed embodiment. Accordingly, the application is not limited to the embodiments described herein. Rather, the described embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. It should be noted that references to "an embodiment," "another embodiment," etc. do not necessarily refer to the same embodiment, and that a plurality of embodiments can be presented that differ from one another

[0038] The drawings are not necessarily to scale and, in some instances, proportions can have been exaggerated in order to clearly convey the concepts of the embodiments. When an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements or layers present. Like reference numerals denote like elements throughout the specification. In addition, the term "comprising" is used herein to mean including at least the recited elements, that it is open-ended and that one or more additional elements can be included.

[0039] The terminology used in the context of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this application, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this application, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Unless otherwise defined, all terms used in connection with the present application, including technical and scientific terms, have the same meaning as those which are commonly understood by one of ordinary skill in the art to which this application belongs and shall not be interpreted differently herein. It should be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and should not be interpreted in an overly formal or overly literal sense.

[0040] In the following description, numerous specific details are set forth to provide a thorough understanding of the application. The application can be practiced without some or all of these specific details. In other instances, well known process structures and / or processes have not been described in detail, in order not to unnecessarily obscure the application. It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements or

[0041] The application will be further described with reference to the drawings and specific examples.

[0042] Figure 1 A structure diagram of a NAND string provided for an embodiment of the application; Figure 2 A structure diagram of a NAND string provided for an embodiment of the application; Figure 1 An equivalent circuit diagram of the NAND string shown. In a NAND structure flash memory system, a plurality of transistors are arranged in series and are sandwiched between two select gates (source gate and drain gate), the series-connected transistors and the two select gates are called a NAND string. As shown in Figure 1 An equivalent circuit diagram of the NAND string shown. In a NAND structure flash memory system, a plurality of transistors are arranged in series and are sandwiched between two select gates (source gate and drain gate), the series-connected transistors and the two select gates are called a NAND string. As shown in Figure 2The illustrated NAND string includes a top select gate SGD (on the drain side), a bottom select gate SGS (on the source side), and a top dummy transistor SGDT, four transistors 101-104, and a bottom dummy transistor SGST sandwiched therebetween. The top select gate SGD connects the NAND string to a bit line through a bit line contact; the top select gate SGD is controlled by applying an appropriate voltage to a top select gate line SGDL. The bottom select gate SGS connects the NAND string to a source line; the bottom select gate SGS is controlled by applying an appropriate voltage to a bottom select gate line SGSL. Each of the top dummy transistor SGDT, the four transistors 101-104, and the bottom dummy transistor SGST includes a control gate and a floating gate. For example, the top dummy transistor SGDT includes a control gate CGDT and a floating gate FGDT; the transistor 101 includes a control gate 101CG1 and a floating gate 101FG1; the transistor 102 includes a control gate 102CG1 and a floating gate 102FG1; the transistor 103 includes a control gate 103CG1 and a floating gate 103FG1; the transistor 104 includes a control gate 105BG1 and a floating gate 105EG1; and the bottom dummy transistor SGST includes a control gate CGST and a floating gate FGST. The control gate CGST is connected to a bottom dummy word line BDWL; the control gates 101CG1-105BG1 are connected to word lines WL0-WL3, respectively; and the control gate CGDT is connected to a top dummy word line TSWL.

[0043] It should be noted that, Figure 1 and Figure 2 The four memory cells (transistors 101-104) used for read / write operations and the two dummy memory cells (top dummy transistor SGDT and bottom dummy transistor SGST) used for read / write testing are shown by way of example only. In actual applications, a NAND string can include 8, 16, 32, 64, 128 memory cells, etc., i.e., the number of memory cells or dummy memory cells in a NAND string does not limit the scope of the present application. Furthermore, a typical structure of a flash memory system using a NAND structure includes a plurality of NAND strings. Each NAND string is connected to a source line through a bottom select gate SGS controlled by a bottom select gate line SGSL and to a corresponding bit line through a top select gate SGD controlled by a top select gate line SGDL. Each bit line and the corresponding NAND string (single or multiple) connected to the bit line through a bit line contact form a column in an array of memory cells. Bit lines are shared by multiple NAND strings. Typically, bit lines extend on top of the NAND strings in a direction perpendicular to the word lines and are connected to one or more sense amplifiers. It should be understood that the present application is not limited to the use of a single bit line per NAND string.Figure 1 and Figure 2 The example illustrates the NAND string structure. In practical applications, the charge trapping layer is not necessarily a floating gate; it could also be a charge trapping nitride layer, a non-conductive dielectric material, etc.

[0044] In practical applications, the memory array in a memory device is transmitted via... Figure 1 and Figure 2 The NAND strings shown are arranged in a reasonable manner to form a memory array containing multiple storage blocks. An example structure is as follows: Figure 3 As shown. The memory array 300 is divided into BLOCK1-BLOCK. T A memory array with multiple storage blocks, where T is a positive integer and is generally a large number. Each storage block contains a set of NAND strings, which are transmitted via bit lines BL0-BL10. M-1 and a set of common word lines WL0-WL N-1 Access, where M and N are both integers greater than 1. One terminal of the NAND string is connected to the corresponding bit line via the top select gate SGD (controlled by the top select gate line SGDL), and the other terminal is connected to the source line via the bottom select gate SGS (controlled by the bottom select gate line SGSL). Each memory block is divided into multiple pages. In some embodiments, the memory block is a conventional erase unit, and the page is a conventional programming unit. In other embodiments, other units of erase and programming may also be used. In an example, Figure 3 The physical structure of the memory cells in the illustrated memory array does not limit the scope of the invention.

[0045] In this invention, Figure 3 The memory array shown can be arranged in a 3D QLC structure. It should be noted that other structural arrangements do not limit the scope of the present invention.

[0046] For the structure of a certain storage block, such as Figure 4 The diagram illustrates a structural schematic of a three-dimensional memory array with a single memory block provided in an embodiment of the present invention. (See reference...) Figure 4 The storage block 400 comprises multiple layers stacked on a substrate (not shown) and parallel to the surface of the substrate. Figure 4Four word lines (WL) are shown on four tiers, which can be denoted as WL0 to WL3. The memory block 400 is also arranged with a plurality of vias that are perpendicular to the word lines. An intersection of one word line and one via forms one memory cell, and thus one via can also be referred to as a memory cell string. Those skilled in the art should understand that the number of word lines and the number of memory cell strings of the memory block 400 are not limited to specific values. For example, the memory block 400 can include 64 word lines that intersect with one memory cell string to form 64 memory cells along the memory cell string. For another example, the memory block 400 includes a number of memory cell strings that can be counted in the order of hundreds of thousands, millions, or even larger, and one word line includes a number of memory cells that are formed by intersecting with, for example, millions of memory cell strings. The memory cells in the memory block 400 can be single-level memory cells or multi-level memory cells, where a single-level memory cell can be a single-level cell (SLC) capable of storing 1 bit, a multi-level memory cell can be a multi-level cell (MLC) capable of storing 2 bits, a triple-level cell (TLC) capable of storing 3 bits, a quad-level cell (QLC) capable of storing 4 bits, or a penta-level cell (PLC) capable of storing 5 bits. As shown in Figure 4 The memory block 400 also includes bit lines (BL), bit line selectors (BLS, which can also be referred to as top select gate lines SGDL), source lines (SL), and source selectors (SLS, which can also be referred to as bottom select gate lines SGSL), which together with the word lines (WL) can enable addressing of any memory cell in the memory block 400.

[0047] Figures 5A to 5E A top view, a cross-sectional view, and the like of a portion of a three-dimensional (3D) NAND structure corresponding to Figure 4 is depicted. Figure 5A A top view of a portion of a three-dimensional (3D) NAND structure in Figure 4 is provided. It is noted that Figure 5A The plurality of circles in Figure 5A depicts vertical columns 501, 502, 503, and 504, where the vertical column 501 implements a NAND string 501A. The vertical column 502 implements a NAND string 502A. The vertical column 503 implements a NAND string 503A. The vertical column 503 implements a NAND string 503A. It is understood that Figure 5A Only a portion of the top view of the memory block 400 is shown, and thus the memory block 400 should have more vertical columns than Figure 5A are shown.Figure 5A A set of bit lines 505 is also depicted. Figure 5A Only twenty-four bit lines are shown because only a portion of the memory block 400 is shown. It should be understood that there should be more than twenty-four vertical columns of bit lines connected to the memory block 400. Each circle representing a vertical column has an "x" to indicate that it is connected to a bit line; for example, bit line 5051 is connected to vertical columns 501, 502, 503, and 504. Figure 5A The memory block depicted also includes a set of local interconnects 506, 507, 508, 509, and 510 that connect the various layers to source lines below the vertical columns. Local interconnects 506, 507, 508, 509, and 510 also serve to divide each layer of memory block 400 into four regions, for example, Figure 5A The top layer depicted is divided into regions 511, 512, 513, and 514, which are referred to as fingers. In the layer of the memory block implementing the memory cells, these four regions are referred to as word line fingers, and they are separated by local interconnects. In one embodiment, word line fingers on the common level of the memory block are connected together to form a single word line. In another embodiment, word line fingers on the same level are not connected together. In an exemplary embodiment, the bit line is connected to only one vertical column in each of regions 511, 512, 513, and 514. In this embodiment, each memory block has sixteen active columns, and each bit line is connected to four rows in each memory block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line fingers connected together on the same level); therefore, the memory system uses source select lines and drain select lines to select one (or a subset of another) of the four rows for memory operations (programming, verifying, reading, and / or erasing).

[0048] It should be noted that, although Figure 5A The diagram illustrates a storage block with four vertical columns per region, resulting in sixteen vertical columns for four regions; however, these exact numbers are exemplary implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block. Furthermore, Figure 5A It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the vertical columns are not staggered.

[0049] Figure 5B It shows along Figure 5A The sectional view of line AA. This sectional view cuts through vertical column 502 and vertical column 515 adjacent to vertical column 502, as well as region 512 (see details). Figure 5A). Figure 5B The memory block 400 is shown to include four drain side select layers SGD0, SGD1, SGD2, and SGD3; four source side select layers SGS0, SGS1, SGS2, and SGS3; six dummy word line layers TSWL0, TSWL1, BDLWL0, BDLWL1, WLDL, WLDU; and 128 data word line layers WLL0 through WLL127, which are used to connect to data storage cells. Other embodiments can implement more or less than four drain side select layers, more or less than four source side select layers, more or less than six dummy word line layers, and more or less than 128 word line layers. The vertical columns 502 and 515 are depicted as protruding through the drain side select layers, the source side select layers, the dummy word line layers, and the word line layers. In one embodiment, each vertical column includes a vertical NAND string. For example, the vertical column 502 includes a NAND string 502A. Under the vertical column and the layers listed below are a substrate, an insulating film disposed on the substrate, and a source line SL. The NAND string of the vertical column 502 has a source end at the bottom of the stack and a drain end at the top of the stack. Figure 5B The vertical column 502 is shown connected to a bit line 5051 via a connector 516. Local interconnects 507 and 508 are also depicted.

[0050] For ease of reference, the drain side select layers SGD0, SGD1, SGD2, and SGD3; the source side select layers SGS0, SGS1, SGS2, and SGS3; the dummy word line layers TSWL0, TSWL1, BDLWL0, BDLWL1, WLDL, WLDU; and the word line layers WLL0 through WLL127 are collectively referred to as conductive layers. In one embodiment, the conductive layers can be made of a combination of TiN and tungsten. In other embodiments, other materials can also be used to form the conductive layers, such as doped polysilicon, metals such as tungsten or metal silicides. In some embodiments, different conductive layers can be formed of different materials. Between the conductive layers are dielectric layers DL0 through DL145. For example, the dielectric layer DL104 is above the word line layer WL94 and below the word line layer WL95. In one embodiment, the dielectric layers can be made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0051] In one embodiment, the memory cells are arranged in NAND strings. Word line layers WLO to WL127 are connected to the memory cells (may also be referred to as word line layers WLO to WL127 are coupled to the memory cells, which can also be referred to as data memory cells). Dummy word line layers TSWLO, TSWL1, BDLWO, BDLWL, WLDL, WLDU are connected to dummy memory cells. The dummy memory cells do not store host data and are not eligible to store host data (data provided from a host, such as data from a host user), while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells can have the same structure. The dummy word lines are connected to the dummy memory cells. Drain side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND strings with bit lines. Source side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND strings with source lines SL.

[0052] Figure 5B A junction region is also shown. In one embodiment, etching 128 word line layers mixed with dielectric layers is expensive and / or challenging. To mitigate this burden, one embodiment includes laying down a first stack of 64 word line layers alternating with dielectric layers, laying down a junction region, and laying down a second stack of 64 word line layers alternating with dielectric layers. The junction region is positioned between the first stack and the second stack. The junction region is used to connect the first stack to the second stack. In Figure 5B In one embodiment, the first stack can be labeled as a lower set of word lines; the second stack can be labeled as an upper set of word lines. In one embodiment, the junction region can be made of the same material as the word line layers. In one example implementation set, the plurality of word lines (control lines) can include a first stack of alternating word line layers and dielectric layers, a second stack of alternating word line layers and dielectric layers, and a junction region between the first stack and the second stack, as shown in Figure 5B

[0053] Figure 5C A logical representation of the conductive layers of a portion of a memory block is depicted in Figure 5B , such as having a logical representation of SGD0, SGD1, SGD2, SGD3, SGS0, SGS1, SGS2, SGS3, TSWLO, TSWL1, BDLWO, BDLWL, and WL0 to WL127 word lines. In accordance with the above regarding Figure 5A ​In one embodiment, local interconnects 506, 507, 508, 509, and 510 divide the conductive layer into four regions / fingers (or storage sub-blocks), e.g., word line layer WL126 is divided into regions 517, 518, 519, and 520. For a word line layer with WL0 to WL95, the regions are referred to as word line fingers, thus, word line layer WL94 is divided by local interconnects 506, 507, 508, 509, and 510 into word line fingers 517, 518, 519, and 520. In actual use, region 517 is one word line finger on one word line layer. In one embodiment, the four word line fingers on the same level are connected together. In another embodiment, each word line finger operates as a separate word line.

[0054] Figure 5D A cross-sectional view of region 521 is depicted. Figure 5B In one embodiment, the vertical column is circular; however, in other embodiments, other shapes can be used. In one embodiment, vertical column 502 can include an inner core layer 522 made of a dielectric such as SiO2. Other materials can also be used. Surrounding inner core layer 522 is a polysilicon channel 523. Materials other than polysilicon can also be used. It should be noted that channel 523 is connected to a bit line and a source line. Surrounding channel 523 is a tunneling dielectric 524. In one embodiment, tunneling dielectric 524 has an ONO structure. Surrounding tunneling dielectric 524 is a charge trapping layer 525, such as silicon nitride. Other memory materials and structures can also be used. The techniques described herein are not limited to any particular material or structure.

[0055] Figure 5DDielectric layers DL139, DL138, DL137, DL136, and DL135 are depicted, as well as word lines WL127, WL126, WL125, WL124, and WL123. Each word line layer includes a word line region 527 surrounded by an aluminum oxide layer 526, which is surrounded by a barrier oxide layer 528. The physical interaction between the word line layers and the vertical column forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 523, a tunneling dielectric 524, a charge trapping layer 525, a barrier oxide layer 528, an aluminum oxide layer 526, and a word line region 527. For example, word line layer WL127 and a portion of vertical column 502 constitute memory cell MC1. Word line layer WL126 and a portion of vertical column 502 constitute memory cell MC2. Word line layer WL125 and a portion of vertical column 502 constitute memory cell MC3. Word line layer WL124 and a portion of vertical column 502 constitute storage cell MC4. Word line layer WL123 and a portion of vertical column 502 constitute storage cell MC5. In other architectures, storage cells may have different structures; however, the storage cell will still be a data storage unit.

[0056] When a memory cell is programmed, electrons are stored in a portion of a charge trapping layer 525 associated with the memory cell. In response to an appropriate voltage on the word line region 527, these electrons are attracted from the channel 523 into the charge trapping layer 525 through the tunneling dielectric 524. The threshold voltage (V) of the memory cell... th The amount of charge increases proportionally to the amount stored. In one embodiment, programming is achieved by electrons tunneling into the charge trapping layer via Fowler-Nordheim tunneling. During the erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate-induced drain leakage (GIDL).

[0057] Figure 5E yes Figures 4 to 5D A schematic diagram depicting a portion of the memory. Figure 5E The physical word lines WL0 to WL127, which extend across the entire block, are shown. Figure 5E The structure corresponds to Figures 5A to 5DA portion of the memory block 400 includes bit lines 505. Within this memory block, each bit line is connected to four NAND strings. Drain-side select lines SGD0, SGD1, SGD2, and SGD3 are used to determine which of the four NAND strings is connected to one or more associated bit lines. Source-side select lines SGS0, SGS1, SGS2, and SGS3 are used to determine which of the four NAND strings is connected to a common source line. Alternatively, the block can be divided into four memory sub-blocks B0, B1, B2, and B3. Memory sub-block B0 corresponds to the vertical NAND strings controlled by SGD0 and SGS0, memory sub-block B1 corresponds to the vertical NAND strings controlled by SGD1 and SGS1, memory sub-block B2 corresponds to the vertical NAND strings controlled by SGD2 and SGS2, and memory sub-block B3 corresponds to the vertical NAND strings controlled by SGD3 and SGS3.

[0058] It should be noted that, Figures 4 to 5E An exemplary memory system is a three-dimensional memory structure comprising vertical NAND strings with charge trapping material, but other (2D and 3D) memory structures may also be used with the techniques described herein.

[0059] Return based on Figure 3 The memory array shown, Figure 6 This illustrates the embodiment of the invention based on... Figure 3 The diagram shows a memory system 60 with read / write circuitry for parallel reading and / or programming of pages (or other units) of the memory array.

[0060] like Figure 6As shown, memory system 60 includes memory device 601 and memory controller 602, where memory device 601 includes memory array 300 (two-dimensional or three-dimensional) and peripheral circuits including control circuit 6011, read / write circuits 6012A and 6012B, row decoders 6013A and 6013B, and column decoders 6014A and 6014B. In some embodiments, the various peripheral circuits access memory array 300 in a symmetrical fashion on opposite sides of memory array 300 to reduce the density of the circuitry on each side by half. Read / write circuits 6012A and 6012B include a plurality of sense blocks SB for reading or programming a page of memory array 300 in parallel. Memory array 300 is addressable by word lines via row decoders 6013A and 6013B and by bit lines via column decoders 6014A and 6014B. In some embodiments, memory array 300, control circuit 6011, read / write circuits 6012A and 6012B, row decoders 6013A and 6013B, and column decoders 6014A and 6014B can be fabricated on a chip. Figure 6 The dashed boxes in the middle can also represent chips. External signals and data are transferred between the host and memory controller 602 via signal lines 603, and between memory controller 602 and the chips via signal lines 604.

[0061] Control circuit 6011 is configured to cooperate with read / write circuits 6012A and 6012B to perform memory operations on memory array 300. Control circuit 6011 includes a state machine, an on-chip address decoder, and a power control module, where the state machine is configured to provide chip-level control of memory operations, the on-chip address decoder is configured to provide an address interface between the addresses used by the host or the controller of the memory system and the hardware addresses used by row decoders 6013A and 6013B and column decoders 6014A and 6014B, and the power control module is configured to provide power and voltages to the word lines and bit lines during memory operations controlled by the memory controller.

[0062] The memory arrays in the memory systems discussed above can be erased, programmed, and read. At the end of a successful programming process (with verification), the threshold voltages of the programmed memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within the distribution of threshold voltages for erased memory cells, as appropriate.

[0063] Although the relationship between the peripheral circuits and memory array 300 is discussed in detail above, in other embodiments, the peripheral circuits and memory array can also be shown in the following Figure 7 structure.Figure 7 A block diagram illustrating an exemplary memory device including a memory array and peripheral circuitry according to some aspects of the present disclosure is shown.

[0064] Figure 7 Some exemplary peripheral circuitry is shown, including a page buffer 704, a column decoder 706, a row decoder 708, a voltage generator 710, a control logic unit 712, registers 714, input / output (I / O) circuitry 716. It should be appreciated that additional peripheral circuitry not shown in FIG. 7 can also be included in some examples.

[0065] The page buffer 704 can be connected to the memory cell array 300 via bit lines and configured to read data from and program (write) data to the memory array 300 according to control signals from the control logic unit 712. In one example, the page buffer 704 can store a page of program data (write data) to be programmed into one page of the memory array 300. In another example, the page buffer 704 can sense signals from the bit lines to verify that data has been correctly programmed into the target memory cells coupled to the selected word line 718. In yet another example, the page buffer 704 can also sense low power signals from the bit lines representing data bits stored in the memory cells and amplify small voltage swings to an identifiable logic level during a read operation. The column decoder 706 can be configured to be controlled by the control logic unit 712 and select one or more NAND memory strings by applying bit line voltages generated from the voltage generator 710.

[0066] The row decoder 708 can be connected to the memory array 300 via word lines and can select a word line based on a row address. The row decoder 708 can be configured to be controlled by the control logic unit 712 according to control signals and select / deselect memory blocks of the memory array 300 and select / deselect selected rows of the memory blocks. The row decoder 708 can also be configured to provide word line voltages generated from the voltage generator 710 to the word lines. In some implementations, the row decoder 708 can also provide SSG voltages and DSG voltages generated from the voltage generator 710 to the SSG lines 315 and the DSG lines 313.

[0067] The voltage generator 710 can be configured to be controlled by the control logic unit 712 and generate various voltages provided to the memory array 300, such as word line voltages (e.g., read voltages, program voltages, pass voltages, verify voltages, etc.), SSG voltages (select / deselect voltages), DSG voltages (select / deselect voltages), bit line voltages, and source line voltages, etc.

[0068] The control logic 712 can be coupled to each of the peripheral circuits described above and configured to control the operation of the individual peripheral circuits. The registers 714 can be coupled to the control logic 712 and include status registers, command registers, and address registers for storing status information, command opcodes, and command addresses used to control the operation of each of the peripheral circuits. The control logic 712 can be implemented by a microprocessor, a microcontroller (a.k.a., a microcontroller unit (MCU)), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic device (PLD), a state machine, gated logic, discrete hardware circuits, or a combination of other suitable hardware, firmware, and / or software that is configured to perform the various functions described below detailed description.

[0069] The input / output circuit 716 can be coupled to the control logic 712 and act as a control buffer to buffer control commands received from the memory controller 602 and relay them to the control logic 712, and to buffer status information received from the control logic 712 and relay them to the memory controller. The input / output circuit 716 can also be coupled to the column decoder 706 and act as a data input / output interface and data buffer to buffer data and relay them to or from the memory array 300.

[0070] It is noted that, Figure 6 and Figure 7 The peripheral circuits and the memory array are described from different perspectives, in which, Figure 6 the control circuit in Figure 7 the control logic in

[0071] Figure 8 is a plot of threshold voltage versus number of storage cells, and illustrates an exemplary threshold voltage distribution of a memory array when each storage cell stores four bits of data. However, other embodiments can use other data capacities per storage cell, such as the aforementioned SLC storing 1 bit of data, MLC storing 2 bits of data, TLC storing 3 bits of data, PLC storing 5 bits of data, etc. Storage cells that store more than one bit of data are referred to as multi-level cells MLC. Figure 8The 16 threshold voltage distributions are shown, which correspond to 16 threshold voltage distributions: E (may also be referred to as L0), LI, L2, L3, L4, L5, L6, L7, L8, L9, L10, LI 1, L12, L13, L14, L15, with the threshold voltage increasing in order. Likewise, the threshold voltage distribution E corresponds to an erased data state; the threshold voltage distributions LI, L2, L3, L4, L5, L6, L7, L8, L9, L10, LI 1, L12, L13, L14, L15 correspond to programmed data states, for data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. In some embodiments, the QLC type of memory cell stores four bits of data, specifically, an erased memory cell can store data 1111, memory cells programmed to data states LI, L2, L3, L4, L5, L6, L7, L8, L9, L10, LI 1, L12, L13, L14, L15 can store data 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000, in order. For data state N, the data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. The first threshold voltage distribution corresponding to data state L0 indicates an erased memory cell. The other 15 threshold voltage distributions corresponding to data states LI to L15 indicate programmed memory cells, and are therefore also referred to as programmed data states. In some implementations, data states LI - L15 can overlap, with the memory controller 602 relying on error correction to identify the correct data being stored. Figure 8 Also shown are 15 read reference voltages Vrl, Vr2, Vr3, Vr4, Vr5, Vr6, Vr7, Vr8, Vr9, VrlO, Vrl 1, Vrl2, Vrl3, Vrl4, Vrl5, for reading data from a memory cell, specifically a test, such as performing a sense operation, given the threshold voltage of a memory cell is higher or lower than the 15 read reference voltages, the memory system can determine the data state the memory cell is in.

[0072] Figure 8Fifteen verification reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, Vv7, Vv8, Vv9, Vv10, Vv11, Vv12, Vv13, Vv14, and Vv15, are also shown; these verification reference voltages can also be referred to as verification target voltages. When a memory cell is programmed to data state L1, the memory system tests whether these memory cells have a threshold voltage greater than or equal to Vv1. When a memory cell is programmed to data state L2, the memory system tests whether the memory cell has a threshold voltage greater than or equal to Vv2. When a memory cell is programmed to data state L3, the memory system determines whether the memory cell has a threshold voltage greater than or equal to Vv3. When a memory cell is programmed to data state L4, the system tests whether these memory cells have a threshold voltage greater than or equal to Vv4. When a memory cell is programmed to data state L5, the memory system tests whether these memory cells have a threshold voltage greater than or equal to Vv5. When a memory cell is programmed to data state L6, the memory system tests whether these memory cells have a threshold voltage greater than or equal to Vv6. When a memory cell is programmed to data state L7, the memory system tests whether these memory cells have a threshold voltage greater than or equal to Vv7. The remaining data states are then sequentially verified to have a threshold voltage greater than or equal to Vv8, Vv9, Vv10, Vv11, Vv12, Vv13, Vv14, and Vv15 to determine whether they are programmed to L8, L9, L10, L11, L12, L13, L14, and L15. In one implementation known as full-sequence programming, memory cells can be programmed directly from erased data state L0 to any of the programmed data states L1-S15. For example, a group of memory cells to be programmed can be erased first, leaving all memory cells in the erased data state L0. Then, a programming process is used to directly program the memory cells into one of the data states L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15. For example, while some memory cells are being programmed from data state L0 to data state L1, other memory cells are being programmed from data state L0 to data state L2 and / or from data state L0 to data state L3, and so on. Figure 8 The arrow indicates full-sequence programming. In addition to full-sequence programming, the techniques described herein can also be used with other types of programming, including but not limited to multi-level / multi-phase programming.

[0073] Figure 8Each threshold voltage distribution (data state) of the memory cells corresponds to a predetermined value of a set of data bits stored in the memory cells. The specific relationship between data programmed into a memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme employed by the memory cells. In one embodiment, a Gray code assignment is used to assign data values to threshold voltage ranges such that if the threshold voltage of a memory cell is erroneously shifted to its adjacent physical state, only one bit will be affected.

[0074] In general, during verify operations and read operations, the selected word line is connected to a voltage that is a reference signal, the level of which is specified for each read operation (see, e.g., the read reference voltage of Figure 8 ) or verify operation (see, e.g., the verify reference voltage of Figure 8 ) in order to determine whether the threshold voltage of the relevant memory cell has reached this level. After applying the voltage to the word line, the conduction current of the memory cell is measured to determine whether the memory cell turns on (whether there is a conduction current, and the size of the conduction current is measured) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, it is assumed that the memory cell turns on and the voltage applied to the word line is greater than the threshold voltage of the memory cell. If the conduction current is not measured to be greater than a certain value, it is assumed that the memory cell does not turn on and the voltage applied to the word line is not greater than the threshold voltage of the memory cell. During the read or verify process, the unselected memory cells are provided with one or more pass voltages, also referred to as bypass voltages, at their control gates, so that these memory cells will conduct current as pass gates, regardless of whether these memory cells are programmed or erased.

[0075] There are many ways to measure the conduction current of a memory cell during a read or verify operation. In one example, the conduction current of a memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of the selected memory cell allows (or does not allow) the NAND string including the memory cell to discharge a corresponding bit line, and the voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used with different methods for verify / read known in the art. Other read and verify techniques known in the art can also be used.

[0076] Figure 9 is a flowchart that describes one embodiment of a process performed by the memory device 601 for programming. In one example embodiment, Figure 9 The process of Figure 9 is performed on the memory device 601 under the direction of a state machine using the control circuitry discussed above. The process of Figure 8Full-sequence programming or other programming schemes that include multi-level programming. When implementing multi-level programming, Figure 8 The process is used to implement any / every stage of a multi-level programming process.

[0077] Typically, during programming operations, the programming signal Vpgm (also known as the programming voltage or programming pulse) is applied as a series of programming voltage pulses to the control gate (applied via a selected word line), such as... Figure 10 As shown. Between the programming pulses is a set of verification pulses to perform verification. In some embodiments, the amplitude of Vpgm increases with each successive pulse by a predetermined step size, for example, the predetermined step size may be selected from 0.2V to 0.5V. Figure 9 In step 901, the programming voltage (Vpgm) is initialized to an initial amplitude, such as any level between approximately 12V and 16V, or another suitable level, and the programming counter PC maintained by the state machine is initialized to 1. In step 902, a programming pulse of Vpgm is applied to a selected word line (the selected word line is the word line chosen for programming). In one embodiment, a group of memory cells to be programmed simultaneously are all connected to the same word line (the selected word line). Unselected word lines receive one or more boost voltages (or pass voltages), such as approximately 7V to 11V, to perform boost schemes known in the art. In one embodiment, if a memory cell is to be programmed, the corresponding bit line is grounded. On the other hand, if a memory cell is to be held at its current threshold voltage, the corresponding bit line is connected to Vdd, for example, 1V to 3.5V, to suppress programming. In step 902, programming voltage pulses are simultaneously applied to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously. In other words, they are programmed simultaneously or during overlapping periods (both are considered simultaneous). In this way, unless they have been locked to prevent programming, all memory cells connected to the selected word line will simultaneously have their threshold voltage change.

[0078] In step 903, a suitable set of verification reference voltages is used to perform one or more verification operations to verify the appropriate memory cell. In one embodiment, the verification process is performed by testing whether the threshold voltage of the selected memory cell for programming has reached the appropriate verification reference voltage.

[0079] In step 904, a determination is made as to whether all memory cells have reached their first threshold (pass). If so, the programming process is complete and is successful because all selected memory cells are programmed and verified to their target state. In step 905, a "pass" (or success) status is reported. If in step 904 it is determined that not all memory cells have reached their first threshold (fail), then the programming process continues to step 906.

[0080] In step 906, the system counts the number of memory cells that have not reached their respective first threshold distribution. That is, the system counts the number of memory cells for which the verification process has failed so far. This counting can be done by the state machine, the memory controller 602, or other logic. In one specific implementation, each sense block stores the status (pass / fail) of its respective memory cells. In one embodiment, there is a total count that reflects the total number of currently programmed memory cells for which the last verification step has failed. In another embodiment, a separate count is kept for each data state.

[0081] In step 907, a determination is made as to whether the count from step 906 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction code (ECC) during the read process of a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, then the programming process can stop and a "pass" status is reported in step 905. In this case, enough memory cells are correctly programmed so that the remaining few memory cells that are not fully programmed can be corrected using ECC during the read process. In some embodiments, step 906 counts the number of failed cells for each sector, each target data state, or other unit, and these counts are individually or collectively compared to one or more thresholds in step 907.

[0082] In one embodiment, the predetermined limit can be less than the total number of bits that can be corrected by ECC during the read process to account for future errors. When programming less than all memory cells of a page, or comparing counts for only one data state (or less than all states), the predetermined limit can be a fraction (proportional or not) of the number of bits that can be corrected by ECC during the read process of a page of memory cells. In some embodiments, the limit is not predetermined. Rather, it varies based on the number of errors already counted for a page, the number of program-erase cycles performed, or other criteria.

[0083] If the number of failed memory cells is not less than the predetermined limit, the programming process continues at step 908 and checks the program counter PC against a program limit value (PL). The program limit value, such as includes 6, 20, and 30, etc.; however, other values can be used. If the program counter PC is not less than the program limit value PL, the programming process is deemed to have failed and a "fail" status is reported in step 910. If the program counter PC is less than the program limit value PL, the process continues at step 909, during which the program counter PC is incremented by one and the program voltage Vpgm is stepped to the next value. For example, the next pulse will have a magnitude that is one step size larger than the previous pulse, e.g., a step size of 0.1 volts to 0.4 volts. After step 909, the process loops back to step 902 and another program pulse is applied to the selected word line, such that another iteration of the program process (steps 902-909) is performed. Figure 9

[0084] Because errors can occur when programming or reading, and errors can occur when storing data (e.g., due to electron drift, data retention issues, or other phenomena), error correction is used in conjunction with data programming. Memory systems often use error-correcting codes (ECC) to protect data from corruption. Numerous ECC encoding schemes are well known in the art. These conventional error-correcting codes are particularly useful in mass storage memory including flash (and other non-volatile) memory, as such encoding schemes can provide a substantial impact on manufacturing yield and device reliability, making devices with a few unprogrammable or defective cells usable. Of course, there is a tradeoff between yield savings and the cost of providing additional storage cells to store code bits (i.e., the encoding "rate"). Thus, some ECC codes are more suitable for flash memory devices than others. Generally, ECC codes for flash memory devices tend to have a higher encoding rate (i.e., a lower code bit / data bit ratio) than codes used in data communication applications, which can have an encoding rate as low as 1 / 2. Examples of well-known ECC codes that are often used in conjunction with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, etc. Sometimes, error-correcting codes used in conjunction with flash memory storage are "systematic" in that the data portion of the final code word is not changed from the actual data being encoded, with code or parity bits being appended to the data bits to form the complete code word.

[0085] ​The particular parameters of a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the total length of the code word after encoding. For example, a typical BCH code applied to a 512-byte (4096-bit) data sector can correct up to four error bits if at least 60 ECC or parity check bits are used. Reed-Solomon codes are a subset of BCH codes and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512-byte data sector using about 72 ECC bits. In the case of flash memory, error correction coding provides a significant improvement in manufacturing yield as well as the reliability of flash memory over time.

[0086] In some embodiments, the memory controller 602 receives host data (also referred to as user data or data from an entity outside the memory system), also referred to as information bits, to be stored in the non-volatile memory. The information bits are represented by the matrix i = [1 0] (note that two bits are used for example purposes only, and many embodiments have code words longer than two bits). An error correction coding process, such as any of the processes mentioned above or below, is implemented by the ECC engine of the memory controller 602, where parity bits are added to the information bits to provide data represented by the matrix or code word v = [1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in a more complex manner. For example, low density parity check (LDPC) codes, also known as Gallager codes, can be used. In implementation, such LDPC codes are typically applied (e.g., by the ECC engine) to multiple pages of data encoded across multiple storage elements, but they need not be applied across multiple pages. The data bits can be mapped to a logical page and stored in the memory array by programming one or more storage units to one or more programming states corresponding to v.

[0087] In one embodiment, programming is used to raise the threshold voltage of the storage unit to one of the programmed data states LI to Ll 5. Erasing is used to lower the threshold voltage of the storage unit to the erased data state L0.

[0088] One technique to erase a storage unit in some memory devices is to bias the p-well (or other type of) substrate to a high voltage to charge the NAND channel. An erase enable voltage is applied to the control gate of the storage unit while the NAND channel is at a high voltage to erase the non-volatile storage element (storage unit). Another method to erase a storage unit is to generate a gate-induced drain leakage (GIDL) current to charge the NAND string channel. An erase enable voltage is applied to the control gate of the storage unit while the string channel potential is held to erase the storage unit.

[0089] In one embodiment, a band to band tunneling (BTBT) effect is induced by a voltage difference between the drain and the gate at the selected transistor to generate electron-hole pairs to create a gate induced drain leakage (GIDL) current. In one embodiment, the GIDL current can cause one type of carriers (e.g., holes) to move predominantly into the NAND channel, thereby raising the potential of the channel. The other type of carriers, e.g., electrons, are extracted from the channel by the electric field in the direction of the bit line or in the direction of the source line. During erase, the holes can tunnel from the channel to the charge storage region of the memory cell and recombine with the electrons therein to lower the threshold voltage of the memory cell.

[0090] wherein the GIDL current can be generated at either end of the NAND string, such as a voltage difference between two terminals of a select transistor (e.g., a drain side select transistor) connected to a bit line can generate a first GIDL current; or such as a voltage difference between two terminals of a select transistor (e.g., a source side select transistor) connected to a source line can generate a second GIDL current. Erasing based on the GIDL current at only one end of the NAND string is referred to as one-sided GIDL erase. Erasing based on the GIDL current at both ends of the NAND string is referred to as two-sided GIDL erase. Note that when programming a selected word line, the voltage applied to the selected word line (applied program voltage Vpgm) is different from the voltage applied to unselected word lines, top dummy word line, bottom dummy word line (applied pass voltage Vpass). Generally, Vpgm is not less than Vpass.

[0091] It is found that in a 3D memory device, due to different voltages or different programming states applied to adjacent word lines, the potential difference between the adjacent word lines can cause hot carrier injection from a low potential word line to a high potential word line, which can cause the threshold voltage of a memory cell coupled to the high potential word line to increase. This phenomenon is referred to as hot carrier injection effect.

[0092] The aforementioned hot carrier injection phenomenon, such as in a 3D NAND with 128 word line layers (word line numbers from bottom to top are word line WL0, WL1, WL2, …, WL127, respectively), can be illustrated as follows: N-1, N is an integer not less than 1), the hot carrier injection effect is particularly obvious between the word line WL2 and the word line WL1 during programming of the storage units coupled to the word lines WL3 to WL127. Under the influence of the hot carrier injection effect, the threshold voltage corresponding to the erased state of the storage unit coupled to the word line WL1 will drift toward the positive direction (generally the threshold voltage corresponding to the erased state is negative), so that the first readable distribution corresponding to the storage unit coupled to the word line WL1 will be affected.

[0093] It should be noted that the first readable distribution can refer to a voltage interval between the threshold voltage distribution corresponding to the erased state of the storage unit coupled to the word line WL1 and the threshold voltage distribution corresponding to the first programmed data state, which can be used to read the data on the storage unit in the erased state, and this voltage interval can also be referred to as E0, as shown in Figure 8 In the QLC type storage unit, the voltage interval between the lower wing of the threshold voltage distribution corresponding to the data state L0 and the voltage Vr1 is the first readable distribution E0, as shown in the QLC type storage unit. It should be understood by those skilled in the art that for the QLC type storage unit, there are two readable distributions between every two adjacent data states, the former readable distribution is used to read the data on the storage unit in the former data state, and the latter readable distribution is used to read the data on the storage unit in the latter data state, for example, the readable distribution between the data state L0 and the data state L1 includes E0 and E1, wherein E0 is the aforementioned first readable distribution; E1 is the voltage interval between the voltage Vr1 and the upper wing of the threshold voltage distribution corresponding to the data state L1. In some embodiments, for the QLC type storage unit, the total of the readable distributions can include: E0, E1, …, E29, a total of 30 readable distributions, which can be denoted as: Esum=E0+E1+…+E29.

[0094] In the above case, especially when the storage unit coupled to the word line WL1 and the storage unit above the word line WL1 adopts QLC, during programming of the storage unit coupled to the word lines WL3 to WL127, the hot carriers are injected from the word line WL2 to the word line WL1 due to the potential difference between the storage unit coupled to the word line WL1 and in the lowest data state (L0) and the storage unit coupled to the word line WL2 and in the highest data state (L15). Under the influence of the hot carrier injection effect, the threshold voltage of the storage unit coupled to the word line WL1 and in the lowest data state (L0) drifts toward the positive direction, so that the first readable distribution E0 corresponding to the storage unit coupled to the word line WL1 and in the non-selected string is lost more seriously.

[0095] In order to solve the above technical problems, as Figure 11As shown, an embodiment of the present invention provides a memory device 601, including a memory array 300. The memory array includes multiple memory blocks; each memory block includes multiple memory cell strings; each memory cell string includes a top dummy cell, multiple memory cells, and a bottom dummy cell connected in series; wherein, the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the multiple memory cells are respectively coupled to multiple word lines; the top dummy cell is coupled to a top dummy word line.

[0096] And a control circuit 6011 coupled to the memory array and used to control the memory array;

[0097] The control circuit 6011 is configured to: determine a first average value of the threshold voltage of the bottom dummy cell in the unused memory block;

[0098] Determine the difference between the first average value and the first reference value;

[0099] Based on the difference, it is determined whether to program the bottom dummy cell in the memory block so that the first average value reaches a first threshold; the first threshold is used to reduce the potential difference between the edge word line and the adjacent non-edge word line when programming the selected non-edge word line coupled memory cell; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is the word line other than the edge word line among the plurality of word lines; the selected non-edge word line is not adjacent to the edge word line.

[0100] It should be noted that the aforementioned appendix Figures 1 to 7 The described memory device is merely illustrative of the partial connection relationships and some working principles among the memory cell strings, memory blocks, memory sub-blocks, word lines, bit lines, etc., contained in the memory device, and is not intended to limit the present invention. That is to say, the memory device 601 described in the embodiments of the present invention may be an appendix. Figures 1 to 7 The described structure can also be other implementations with similar functionality. In some embodiments, the plurality of word lines may all be contained in a first stack; the first stack further includes dielectric layers alternately laid with the word lines, that is, the first stack may be a mixture of word lines and dielectric layers. In some embodiments, the material used for the plurality of word lines may be any of the word line materials described above; the material used for the dielectric layers may be any of the dielectric layer materials described above.

[0101] In some embodiments, based on the foregoing description, since etching multiple word line layers mixed with dielectric layers is expensive and / or challenging, in order to alleviate such burden, the memory device provided by embodiments of the present application can also include the multiple word lines in the first stack and the second stack, and connect the first stack and the second stack by using a bonding region, wherein the material of the bonding region can be the same as the material of the word lines. In some embodiments, the number of word lines in the first stack is less than the number of word lines in the second stack. In some embodiments, the number of word lines in the first stack is greater than the number of word lines in the second stack.

[0102] In some embodiments, the selected non-edge word lines in the memory device provided by embodiments of the present application can be in the first stack or in the second stack.

[0103] In some embodiments, the memory array in the memory device provided by embodiments of the present application can be a three-dimensional NAND memory array, or other 3D memory array.

[0104] In the above-described technical solutions, the division of edge word lines and non-edge word lines is not fixed, and the two are a relative concept. In other words, for different memory devices 601, the defined edge word lines and non-edge word lines are not the same. Specifically, how to define edge word lines and non-edge word lines depends on the severity of the influence of hot carrier injection between word lines in the memory device (determined according to the loss of E0). An optional determination method can be that the word lines and the following word lines that are more severely affected by hot carrier injection are defined as edge word lines; and the word lines and the above word lines that are less severely affected by hot carrier injection are defined as non-edge word lines. For example, in some memory devices 601, the edge word lines are defined to include WL0 and WL1 (for the memory array shown in FIG. 5(B)), and then the non-edge word lines include WL2 and the above word lines. For another example, in some memory devices 601, the edge word lines are defined to include WL0, WL1, and WL2, and then the non-edge word lines include WL3 and the above word lines.

[0105] Here, the unused storage block can refer to a new storage block that has never been used, because the threshold voltage of the bottom dummy cell has been set before the new storage block is programmed for the first time, and the threshold voltage of the bottom dummy cell is generally unchanged when the storage block is subsequently programmed. Therefore, the storage device provided by the embodiments of the present application can modify the threshold voltage of the bottom dummy cell for a new storage block that has never been used. The first average value of the threshold voltage of the bottom dummy cell can refer to the average value of the threshold voltage of all bottom dummy cells on the bottom dummy word line. Those skilled in the art should understand that, in actual application, several, tens, or even thousands of bottom dummy cells are coupled to the bottom dummy word line, and each bottom dummy cell has its own threshold voltage. Then, the threshold voltages of the bottom dummy cells are added together, and then divided by the total number of bottom dummy cells to obtain the first average value of the threshold voltage of the bottom dummy cell. For details, refer to Figure 12 In FIG. 12, the abscissa is the threshold voltage, and the ordinate is the number of bottom dummy cells. It should be noted that the storage cell is essentially the transistor described above for storing user data, the bottom dummy cell is essentially the bottom dummy transistor described above, and the top dummy cell is essentially the top dummy transistor described above.

[0106] Therefore, the above technical solution can be understood as detecting the first average value of the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line in the new storage block that has never been used, and then comparing the first average value with the first reference value. Then, whether to program the bottom dummy cell to the first threshold (i.e., the first threshold value) is determined according to the difference, so that the potential difference between the edge word line and the adjacent non-edge word line is reduced when the storage cell coupled to the selected non-edge word line of the plurality of word lines is programmed, and the HCI type of programming interference can be avoided.

[0107] For example, taking the memory array with the structure shown in FIG. 5(B) as an example, the edge word line includes word lines WL0 and WL1, the non-edge word line includes word lines WL2 and above, and the storage cell coupled to the word line WL1 and above is a QLC type storage cell. When the storage cell coupled to any word line (selected non-edge word line) of the non-edge word line WL3 and above is programmed, the storage device provided by the embodiments of the present application can reduce the potential difference between WL2 (the non-edge word line adjacent to the edge word line) and the word line WL1 (the edge word line adjacent to the non-edge word line) after Vpass is applied, thereby reducing the influence on the first read distribution E0 of the storage cell coupled to the unselected string of the word line WL1.

[0108] Here, the first reference value can be selected as a threshold voltage of the memory device that is not affected by an operation, where the operation can be any operation on the memory device such as programming, reading, erasing, etc.

[0109] As an optional implementation, the first reference value is a second average of threshold voltages of top dummy cells in the memory block.

[0110] It is noted that the second average of threshold voltages of the top dummy cells is calculated in a similar manner as the first average of the first threshold voltages, which will not be repeated here.

[0111] Based on this, in some embodiments, the determining whether to program the bottom dummy cells in the memory block based on the difference to make the first average reach the first threshold can include:

[0112] when the difference is less than a second reference value, determining that the bottom dummy cells in the memory block need to be programmed to make the first average reach the first threshold, where a difference between the first threshold and the first reference value is not less than the second reference value;

[0113] when the difference is not less than the second reference value, determining that the bottom dummy cells in the memory block do not need to be programmed.

[0114] Here, it is described that when the first reference value is an average of threshold voltages of the top dummy cells coupled to the top dummy word lines, referred to as a second average, when the difference is less than a second reference value, the bottom dummy cells need to be programmed to make the first average of threshold voltages of the bottom dummy cells reach the first threshold, where a difference between the first threshold and the first reference value is not less than the second reference value, that is, the threshold voltage of the bottom dummy cells is raised and the difference between the threshold voltage of the bottom dummy cells and the first reference value is not less than another second reference value. When the difference is not less than the second reference value, the bottom dummy cells do not need to be programmed to make the first average of threshold voltages of the bottom dummy cells reach the first threshold. In some embodiments, the second reference value can be determined according to the type of actual memory array and the model of chip used, for example, the second reference value can be 1 volt (V), 0.5V, etc.

[0115] In actual application, the second average is 0 volts, that is, the first reference value can be 0 volts (V). In this case, for the determining whether to program the bottom dummy cells in the memory block based on the difference to make the first average reach the first threshold, can include:

[0116] determining that the bottom dummy cells in the memory block need to be programmed to cause the first average to reach a first threshold value, the first threshold value being greater than the first reference value, when the difference is not greater than the first reference value;

[0117] determining that the bottom dummy cells in the memory block do not need to be programmed, when the difference is greater than the first reference value.

[0118] It should be noted that the first threshold value can be determined according to the type of actual memory array and the model of chip used, for example, the first threshold value can be 0.5 volts (V), 1V, etc., wherein the higher the first threshold value, the lower the probability of preventing the occurrence of HCI type programming interference. It should be understood that the first threshold value is also the average of the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line.

[0119] According to the above description, the setting of the bottom dummy cell can be performed before the storage cells coupled to the word lines WL0 to WLN-1 are programmed in a new memory block that has never been used. Based on this, in some embodiments, the control circuit is further configured to: when programming the storage cells coupled to the selected non-edge word lines in the selected storage cell string, apply a first pass voltage to the edge word lines in the plurality of word lines; apply a second pass voltage to the non-edge word lines adjacent to the edge word lines; the first pass voltage is less than the second pass voltage.

[0120] It should be noted that the technical solution described herein is: after the first average of the threshold voltage of the bottom dummy cell reaches the first threshold value, a first pass voltage is applied to the edge word lines in the plurality of word lines; a second pass voltage is applied to the non-edge word lines adjacent to the edge word lines, and the first pass voltage is not greater than the second pass voltage. In this way, the potential difference between the edge word lines and the non-edge word lines adjacent thereto is further reduced, thereby reducing the influence on the E0 of the storage cells coupled to the edge word lines adjacent to the non-edge word lines (for example, word line WL1).

[0121] For example, in the memory array with the structure shown in FIG. 5(B), the edge word lines include word lines WL0 and WL1, the non-edge word lines include word lines WL2 and above, and when the storage units coupled to the word lines WL1 and above are QLC type storage units, the memory device provided by the embodiments of the present application can apply a first pass voltage on the word lines WL0 and WL1 when programming the threshold voltage of the bottom dummy unit, and can apply a second pass voltage on the word lines WL2 after the first average value of the threshold voltage of the bottom dummy unit reaches the first threshold value, so as to reduce the potential difference between the word line WL2 and the word line WL1, thereby reducing the influence on the first read distribution of the storage units coupled to the unselected string of the word line WL1. For details, refer to FIG. 5(C). Figure 13

[0122] In some embodiments, the first pass voltage applied on each of the edge word lines can be different.

[0123] For example, the aforementioned edge word lines WL0 and WL1, the first pass voltage applied on the word line WL0 is different from the first pass voltage applied on the word line WL1, but both are less than the second pass voltage. That is, the first pass voltage can be a group of voltage values less than the second pass voltage. In some embodiments, in order to reduce the potential difference between the edge word lines, the first pass voltage applied on the edge word line closer to the substrate can be smaller, for example, the aforementioned edge word lines WL0 and WL1, the first pass voltage applied on the word line WL0 is smaller than the first pass voltage applied on the word line WL1.

[0124] In some embodiments, when the plurality of word lines are numbered in sequence from the source line as word lines WL0, WL1, …, WLm, …, WLn, …, the control circuit is further configured to: when the edge word lines include the word line WL0 and the word line WL1, and the selected non-edge word line is the word line WLn, the second pass voltage applied on the unselected non-edge word lines WL2 to the word line WLm; and the third pass voltage applied on the unselected non-edge word lines WLn-4 to the word line WLm, where n is not less than 17, and m is not greater than 15.

[0125] It should be noted that the above is to reduce the programming interference between other non-edge word lines caused by the applied pass voltage when programming the storage units coupled to the non-edge word lines WL17 and above.

[0126] In some embodiments, the third pass voltage includes a group of voltage values different from the first pass voltage and the second pass voltage.​

[0127] It is to be noted that the third pass voltage can be a set of voltage values different from the first pass voltage and the second pass voltage, that is, different pass voltages are applied to the unselected non-edge word lines WLn-4 to WLm according to specific memory devices.

[0128] In some embodiments, in order to ensure the read / write speed of a part of the memory device, the storage unit coupled to the word line WL0 is one of a single-level cell (SLC) storage unit, a multi-level cell (MLC) storage unit, and a triple-level cell (TLC) storage unit; and the storage unit coupled to the remaining word lines is a quad-level cell (QLC) storage unit. In other embodiments, in order to ensure the storage capacity, each of the storage units coupled to the plurality of word lines is set to one of an MLC storage unit, a TLC storage unit, a QLC storage unit, and a penta-level cell (PLC) storage unit. This is only a part of the example setting mode, and the specific setting can be determined according to customer requirements.

[0129] The memory device provided by the embodiment of the present application compares the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line in the memory device with a reference value to determine whether the threshold voltage of the bottom dummy cell coupled to the bottom dummy word line in the memory device needs to be programmed to a target value (i.e., a first threshold value), at which the potential difference between the adjacent edge word line (e.g., the word line WL1) and the non-edge word line (e.g., the word line WL2) is reduced, so as to reduce the HCI type interference on the edge word line (e.g., the word line WL1) during the programming of the non-edge word line (e.g., the word line WL3), and further reduce the influence on the read window margin.

[0130] The same inventive concept as described above, as shown in Figure 14 The present application also provides an operation method of a memory device, the memory device comprising a memory array, the memory array comprising a plurality of memory blocks; each memory block comprising a plurality of memory cell strings; each memory cell string comprising a top dummy cell, a plurality of memory cells, and a bottom dummy cell connected in series, wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are coupled to a plurality of word lines; the top dummy cell is coupled to a top dummy word line; the operation method comprises:

[0131] S1401: determining a first average value of the threshold voltage of the bottom dummy cell in the unused memory block;

[0132] S1402: determining a difference between the first average value and a first reference value;

[0133] S1403: determining whether to program bottom dummy cells in the memory block to make the first average value reach a first threshold value based on the difference;

[0134] wherein the first threshold value is used to reduce a potential difference between an edge word line and an adjacent non-edge word line when programming a selected non-edge word line coupled to a selected memory cell in a selected memory cell string; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is a word line other than the edge word line among the plurality of word lines; and the selected non-edge word line is not adjacent to the edge word line.

[0135] In some embodiments, the first reference value is a second average value of threshold voltages of top dummy cells in the memory block.

[0136] In some embodiments, wherein the determining whether to program bottom dummy cells in the memory block to make the first average value reach a first threshold value based on the difference comprises:

[0137] when the difference is less than a second reference value, determining that it is needed to program bottom dummy cells in the memory block to make the first average value reach the first threshold value; and a difference between the first threshold value and the first reference value is not less than the second reference value;

[0138] when the difference is not less than the second reference value, determining that it is not needed to program bottom dummy cells in the memory block.

[0139] In some embodiments, the second average value is 0 volt.

[0140] In some embodiments, wherein the determining whether to program bottom dummy cells in the memory block to make the first average value reach a first threshold value based on the difference comprises:

[0141] when the difference is not greater than the first reference value, determining that it is needed to program bottom dummy cells in the memory block to make the first average value reach the first threshold value; and the first threshold value is greater than the first reference value;

[0142] when the difference is greater than the first reference value, determining that it is not needed to program bottom dummy cells in the memory block.

[0143] In some embodiments, the operation method further comprises:

[0144] When programming the selected memory cells coupled to the selected non-edge word lines in the selected memory cell string, a first pass voltage is applied to edge word lines in the plurality of word lines; a second pass voltage is applied to non-edge word lines adjacent to the edge word lines; the first pass voltage is less than the second pass voltage.

[0145] In some embodiments, when the plurality of word lines are numbered sequentially from the source line as word line WL0, WL1, …, WLm, …, WLn, …, the method further comprises: when the edge word lines include word line WL0 and word line WL1 and the selected non-edge word line is word line WLn, the second pass voltage applied to unselected non-edge word lines WL2 to word line WLm; a third pass voltage applied to unselected non-edge word lines WLn-4 to word line WLm, where n is not less than 17; m is not greater than 15.

[0146] In some embodiments, the third pass voltage includes a set of voltage values different from the first pass voltage and the second pass voltage.

[0147] In some embodiments, the memory cells coupled to the word line WL0 are one of single level cell (SLC), multi-level cell (MLC), and triple level cell (TLC) memory cells; the memory cells coupled to the remaining word lines are quad-level cell (QLC) memory cells.

[0148] In some embodiments, each of the memory cells coupled to the non-edge word lines in the plurality of word lines is one of multi-level cell (MCL) memory cell, TLC memory cell, QLC memory cell, and penta-level cell (PLC) memory cell.

[0149] It should be noted that the method belongs to the same inventive concept as the aforementioned memory device, and the terms appearing in the method are explained in detail in the aforementioned memory device, which also applies here, and will not be repeated.

[0150] Based on the same inventive concept as the aforementioned, such as Figure 15As shown, the embodiments of the present application also provide a memory system including a memory device, the memory device including a memory array, the memory array including a plurality of memory blocks; each memory block including a plurality of strings of memory cells; each string of memory cells including a top dummy cell, a plurality of memory cells, and a bottom dummy cell in series; wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are respectively coupled to a plurality of word lines; the top dummy cell is coupled to a top dummy word line; and a control circuit coupled to the memory array and configured to control the memory array; wherein the control circuit is configured to: determine a first average of threshold voltages of the bottom dummy cells in an unused memory block; determine a difference between the first average and a first reference value; determine whether to program the bottom dummy cells in the memory block to cause the first average to reach a first threshold value based on the difference; the first threshold value is used to cause a potential difference between an edge word line and an adjacent non-edge word line to decrease when programming a selected non-edge word line coupled memory cell; the edge word line is at least one word line of the plurality of word lines adjacent to the source line; the non-edge word line is a word line of the plurality of word lines other than the edge word line; the selected non-edge word line is not adjacent to the edge word line.

[0151] and,

[0152] a memory controller 602 coupled to the memory device, the memory controller configured to control the memory device.

[0153] It is noted that the memory system 60 can communicate with a host (Host) in the aforementioned Figure 6 The host and / or the memory system 60 can be included in various products, such as Internet of Things (IoT) devices, e.g., a refrigerator or other appliance, a sensor, a motor, a mobile communication device, an automobile, a self-driving vehicle, etc., to support processing, communication, or control of the product. In one embodiment, the memory system 60 can be a discrete memory or memory component of the host device. In other embodiments, the memory system 60 can also be part of an integrated circuit, such as part of a System on Chip (SOC). In this case, the memory system 60 is stacked or otherwise assembled with one or more components of the host. In other embodiments, the aforementioned memory system can be implemented and packaged in a memory card, drive, or other product, such as shown in FIG. 16(A) and FIG. 16(B), where FIG. 16(A) shows a schematic diagram of an exemplary memory card having a memory system according to some aspects provided by the present application;

[0154] FIG. 16(B) illustrates a schematic diagram of an exemplary solid state drive (SSD) with a memory system, in accordance with some aspects of the present disclosure. In one example as shown in FIG. 16(A), the memory controller 602 and the single memory device 601 of the memory system can be integrated into a memory card 160. The memory card 160 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 160 can also include a memory card connector 1601 that couples the memory card 160 with a host (e.g., a host in Figure 6 FIG. 16(B)). In another example as shown in FIG. 16(B), the memory controller 602 and the plurality of memory devices 601 of the memory system can be integrated into an SSD 161. The SSD 161 can also include an SSD connector 1611 that couples the SSD 161 with a host (e.g., a host in Figure 6 FIG. 16(B)). In some implementations, the storage capacity and / or operating speed of the SSD 161 is greater than the storage capacity and / or operating speed of the memory card 160.

[0155] In some embodiments, the host can include a processor and a host RAM, where the host RAM can include DRAM, SDRAM, or any other suitable volatile or non-volatile memory device. One or more communication interfaces can be provided on the memory system 60 to communicate with one or more components in the host. The one or more components in the host can be a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, a universal serial bus (USB) interface, a universal flash storage (UFS) interface, an eMMC™ interface, etc. The host can also include an electronic element, a memory card reader, or one or more other electronic elements external to the memory system 60.

[0156] In some embodiments, the memory controller 602 can receive instructions from a host, communicate with the memory devices 601, such as transferring data into one or more memory cells, planes, sub-blocks, blocks, or pages in the memory devices 601 by executing write or erase instructions, or transferring data to the host by executing read instructions. In hardware, the memory controller 602 can include one or more controller units, circuits, or components configured to control access across the memory devices 601 and provide a translation layer between the host and the memory system 600. The memory controller 602 can also include one or more input / output (I / O) circuits, lines, or interfaces to transfer data to or from the memory devices 601. The memory controller 602 can also include a memory management unit and an array control unit.

[0157] The memory management unit can include circuit hardware or firmware, such as a plurality of components or integrated circuits associated with various memory management functions. For example, the memory system operates or manages functions for NAND memory. Those skilled in the art will appreciate that other forms of non-volatile memory can have similar memory operating or management functions. Among other things, the management functions for NAND memory can include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit can process instructions from a host into commands recognizable by the memory system 600, such as parsing or formatting instructions received from a host into commands related to operations of the memory devices 601, etc. Or the memory management unit can also generate device commands for the array control unit or one or more other components of the memory system 600, such as commands to implement various memory management functions.

[0158] The memory management unit can be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 60, such as various information related to a memory array coupled to the memory controller 602, or one or more memory units. For example, the management tables can include information such as block age, block erase count, error history, or one or more error counts for one or more blocks of a memory unit coupled to the memory controller 602. The error counts can include operational error counts, read bit error counts, and the like. In some embodiments, a bit error is an uncorrectable bit error if the detected error count is above a certain threshold. In some embodiments, the management tables can maintain counts of correctable or uncorrectable bit errors, and the like. The management tables can also include one or more L2P tables that include one or more L2P pointers that associate a logical address with a physical address at the memory device 601. In some embodiments, the management tables can include unencrypted L2P tables and / or encrypted L2P tables. The unencrypted L2P tables can include L2P pointers that indicate unencrypted logical addresses and unencrypted physical addresses; the encrypted L2P tables can include encrypted L2P pointers that include encrypted physical addresses and unencrypted logical addresses. In practice, the management tables can be shown at the memory management unit, i.e., the management tables can be stored in the RAM of the memory controller 602. In other embodiments, the management tables can also be stored at the memory device 601. In use, the memory management unit can read some or all of the management tables from the RAM of the memory controller 602; the memory management unit can also read the management tables from the memory device 601.

[0159] The array control unit can include circuitry or components configured to control the performance of related memory operations, such as writing data to, reading data from, or erasing one or more memory units in the memory system 60 coupled to the memory controller 602. The array control unit can receive commands sent by the host or internally generated by the memory management unit, such as commands associated with wear leveling, error detection or correction, and the like.

[0160] The array control unit can also include an error correction code (ECC) component that can include an ECC engine or other circuitry for detecting or correcting errors associated with writing data to or reading data from one or more memory cells coupled in a memory system 60 of the memory controller 602. The memory controller 602 is configured to effectively detect error events associated with various operations or data storage, such as bit errors, operational errors, and the like, and recover from the error events while maintaining the integrity of data transferred between a host and the memory system 60, or maintaining the integrity of stored data, such as can be using redundant RAID storage, and the like, can remove, such as retire, failed memory resources, such as memory cells, memory arrays, pages, blocks, and the like, for preventing future errors.

[0161] In some embodiments, the first reference value is a second average of threshold voltages of top dummy cells in the memory block.

[0162] In some embodiments, the control circuit is further configured to apply a first pass voltage to edge word lines in the plurality of word lines when programming selected memory cells coupled to selected non-edge word lines in the selected string of memory cells; and apply a second pass voltage to non-edge word lines adjacent to the edge word lines; the first pass voltage is less than the second pass voltage.

[0163] In some embodiments, the plurality of word lines are included in a first stack; the first stack further includes dielectric layers interleaved with the word lines.

[0164] In some embodiments, the plurality of word lines are included in a first stack and a second stack, wherein a number of word lines in the first stack is less than a number of word lines in the second stack.

[0165] In some embodiments, the selected non-edge word lines are in the first stack or in the second stack.

[0166] In some embodiments, the memory array is a three-dimensional NAND memory array.

[0167] It is to be noted that the memory system includes the aforementioned memory device, and thus, both have the same technical features. The terms appearing in the memory system are explained in detail in the aforementioned memory device, and the same applies here, and thus, will not be described one by one.

[0168] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be utilized, such as would be apparent to one of ordinary skill in the art upon reading the above description. It should be appreciated that it will not be construed as meaning to explain or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features can be grouped together in one or more aspects of the application. This should not be interpreted as a requirement that these features be in any single aspect. Rather, the disclosed subject matter can encompass any number of separate aspects, each of which can include one or more of the disclosed features. The application should therefore not be construed as limited to only those embodiments described in the detailed description above. Rather, the scope of the application should be determined by the appended claims and their equivalents.

Claims

1. A memory device, characterized in that, The system includes a memory array comprising multiple memory blocks; each memory block comprises multiple memory cell strings; each memory cell string comprises a top dummy cell, multiple memory cells, and a bottom dummy cell connected in series; wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the multiple memory cells are respectively coupled to multiple word lines; and the top dummy cell is coupled to a top dummy word line. And a control circuit coupled to the memory array and used to control the memory array; The control circuit is configured as follows: Determine the first average value of the threshold voltage of the bottom dummy cell in the unused memory block; Determine the difference between the first average value and the first reference value; Based on the difference, it is determined whether to program the bottom dummy cell in the memory block so that the first average value reaches a first threshold; the first threshold is used to reduce the potential difference between the edge word line and the adjacent non-edge word line when programming the selected non-edge word line coupled memory cell; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is the word line other than the edge word line among the plurality of word lines; the selected non-edge word line is not adjacent to the edge word line.

2. The memory device according to claim 1, characterized in that, The first reference value is the second average value of the threshold voltage of the top dummy cell in the memory block.

3. The memory device according to claim 2, characterized in that, The step of determining whether to program the bottom dummy cells in the storage block based on the difference to make the first average value reach a first threshold includes: When the difference is less than the second reference value, it is determined that the bottom dummy cell in the storage block needs to be programmed so that the first average value reaches the first threshold; the difference between the first threshold and the first reference value is not less than the second reference value; When the difference is not less than the second reference value, it is determined that no programming is required for the bottom dummy unit in the storage block.

4. The memory device according to claim 2, characterized in that, The second average value is 0 volts.

5. The memory device according to claim 4, characterized in that, The step of determining whether to program the bottom dummy cells in the storage block based on the difference to make the first average value reach a first threshold includes: When the difference is not greater than the first reference value, it is determined that the bottom dummy cell in the storage block needs to be programmed so that the first average value reaches the first threshold; the first threshold is greater than the first reference value. When the difference is greater than the first reference value, it is determined that programming is not required for the bottom dummy unit in the storage block.

6. The memory device according to claim 1, characterized in that, The control circuit is further configured to: when programming a selected non-edge word line coupled memory cell in the selected memory cell string, apply a first pass voltage to the edge word line among the plurality of word lines; apply a second pass voltage to the non-edge word line adjacent to the edge word line; wherein the first pass voltage is less than the second pass voltage.

7. The memory device according to claim 6, characterized in that, When the plurality of word lines are numbered sequentially from the source line as word lines WL0, WL1, ..., WLm, ..., WLn, ..., the control circuit is further configured to: apply a second pass voltage to unselected non-edge word lines WL2 to WLm when the edge word lines include word lines WL0 and WL1 and the selected non-edge word line is word line WLn; and apply a third pass voltage to unselected non-edge word lines WLn-4 to WLm, wherein n is not less than 17 and m is not greater than 15.

8. The memory device according to claim 7, characterized in that, The third through voltage includes a set of voltage values ​​that are different from the first through voltage and the second through voltage.

9. The memory device according to claim 7, characterized in that, The storage cell coupled to the word line WL0 is one of the single-level cell (SLC), multi-level cell (MLC), and three-level cell (TLC) storage cells; the storage cells coupled to the other word lines are four-level cell (QLC) storage cells.

10. A method of operating a memory device, characterized in that, The memory device includes a memory array, the memory array including multiple memory blocks; each memory block includes multiple memory cell strings; each memory cell string includes a top dummy cell, a pair of memory cells, and a bottom dummy cell connected in series, wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the multiple memory cells are respectively coupled to multiple word lines; the top dummy cell is coupled to a top dummy word line; the operation method includes: Determine the first average value of the threshold voltage of the bottom dummy cell in the unused memory block; Determine the difference between the first average value and the first reference value; Based on the difference, it is determined whether to program the bottom dummy cell in the memory block so that the first average value reaches a first threshold; the first threshold is used to reduce the potential difference between the edge word line and the adjacent non-edge word line when programming the selected non-edge word line coupled memory cell in the selected memory cell string; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is the word line other than the edge word line among the plurality of word lines; the selected non-edge word line is not adjacent to the edge word line.

11. The operating method according to claim 10, characterized in that, The first reference value is the second average value of the threshold voltage of the top dummy cell in the memory block.

12. The operating method according to claim 11, characterized in that, The step of determining whether to program the bottom dummy cells in the storage block based on the difference to make the first average value reach a first threshold includes: When the difference is less than the second reference value, it is determined that the bottom dummy cell in the storage block needs to be programmed so that the first average value reaches the first threshold; the difference between the first threshold and the first reference value is not less than the second reference value; When the difference is not less than the second reference value, it is determined that no programming is required for the bottom dummy unit in the storage block.

13. The operating method according to claim 11, characterized in that, The second average value is 0 volts.

14. The operating method according to claim 13, characterized in that, The step of determining whether to program the bottom dummy cells in the storage block based on the difference to make the first average value reach a first threshold includes: When the difference is not greater than the first reference value, it is determined that the bottom dummy cell in the storage block needs to be programmed so that the first average value reaches the first threshold; the first threshold is greater than the first reference value. When the difference is greater than the first reference value, it is determined that programming is not required for the bottom dummy unit in the storage block.

15. The operating method according to claim 10, characterized in that, The operation method further includes: When programming a selected non-edge word line coupled memory cell in the selected memory cell string, a first pass voltage is applied to the edge word line among the plurality of word lines; a second pass voltage is applied to the non-edge word line adjacent to the edge word line; the first pass voltage is less than the second pass voltage.

16. The operating method according to claim 15, characterized in that, When the plurality of word lines are numbered sequentially from the source line as word lines WL0, WL1, ..., WLm, ..., WLn, ..., the operation method further includes: when the edge word lines include word lines WL0 and WL1 and the selected non-edge word line is word line WLn, applying a second pass voltage to the unselected non-edge word lines WL2 to WLm; and applying a third pass voltage to the unselected non-edge word lines WLn-4 to WLm, wherein n is not less than 17 and m is not greater than 15.

17. The operating method according to claim 16, characterized in that, The third through voltage includes a set of voltage values ​​that are different from the first through voltage and the second through voltage.

18. A memory system, characterized in that, The memory device includes a memory array comprising a plurality of memory blocks; each memory block comprising a plurality of memory cell strings; each memory cell string comprising a top dummy cell, a plurality of memory cells, and a bottom dummy cell connected in series; wherein the top dummy cell is connected to a bit line; the bottom dummy cell is connected to a source line; the bottom dummy cell is coupled to a bottom dummy word line; the plurality of memory cells are respectively coupled to a plurality of word lines; the top dummy cell is coupled to a top dummy word line; and a control circuit coupled to the memory array for controlling the memory array; wherein the control circuit is configured to: determine that... The first average value of the threshold voltage of the bottom dummy cells in the used memory block; the difference between the first average value and the first reference value; based on the difference, whether to program the bottom dummy cells in the memory block so that the first average value reaches a first threshold; the first threshold is used to reduce the potential difference between the edge word line and the adjacent non-edge word line when programming the selected non-edge word line coupled memory cell; the edge word line is at least one word line adjacent to the source line among the plurality of word lines; the non-edge word line is the word line other than the edge word line among the plurality of word lines; the selected non-edge word line is not adjacent to the edge word line; as well as, A memory controller is coupled to the memory device and is configured to control the memory device.

19. The memory system according to claim 18, characterized in that, The first reference value is the second average value of the threshold voltage of the top dummy cell in the memory block.

20. The memory system according to claim 18, characterized in that, The control circuit is further configured to: when programming a selected non-edge word line coupled memory cell in the selected memory cell string, apply a first pass voltage to the edge word line among the plurality of word lines; apply a second pass voltage to the non-edge word line adjacent to the edge word line; wherein the first pass voltage is less than the second pass voltage.

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