Memory device having a page buffer

Abstract

Provided herein can be a memory device having a page buffer. The memory device can include memory cells configured to store data, and can include a page buffer coupled to the memory cells via bit lines and configured to: store data to be used in a programming operation; and during a program verification operation performed in the programming operation, depending on the data, precharge the bit lines to a first precharge voltage or a second precharge voltage, the second precharge voltage being lower than the first precharge voltage.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0008773, filed with the Korean Intellectual Property Office on January 21, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a memory device having a page buffer, and more particularly, to a memory device having a page buffer capable of precharging bit lines. Background Art

[0004] A memory system may include a memory device and a controller. The memory device may store data, and the controller may control the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices. Since volatile memory devices have different characteristics, they are appropriately used in accordance with corresponding functions in electronic devices. For example, such volatile memory devices are characterized in that the speeds of programming operations and reading operations are higher than those of non-volatile memory devices, but when the supply of power is interrupted, the stored data is lost. Non-volatile memory devices are characterized in that the speeds of programming operations and reading operations are lower than those of volatile memory devices, but the stored data is maintained even when the supply of power is interrupted. In addition, since non-volatile memory devices may have a higher degree of integration than volatile memory devices, non-volatile memory devices may store a large amount of data.

[0005] A memory device may include: a memory cell array for storing data; a peripheral circuit for performing a programming operation, a reading operation, or an erasing operation on the memory cells included in the memory cell array; and a control logic circuit for controlling the peripheral circuit.

[0006] The memory cell array may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The peripheral circuit may include a row decoder coupled to the plurality of memory cells through word lines, and may include a page buffer group coupled to the plurality of memory cells through bit lines. A programming voltage, a reading voltage, a verification voltage, or a pass voltage may be applied through the word lines, and data in the memory cells may be sensed through the bit lines. Summary of the Invention

[0007] Various embodiments of the present disclosure relate to a memory device having a page buffer, which may reduce current consumption and may reduce variations in current or voltage of bit lines when the bit lines are precharged.

[0008] One embodiment of the present disclosure provides a memory device, which includes: memory cells configured to store data; and a page buffer coupled to the memory cells via bit lines and configured to: store data to be used in a programming operation; and, during a program verification operation performed during the programming operation, precharge the bit lines to a first precharge voltage or a second precharge voltage depending on the data, the second precharge voltage being lower than the first precharge voltage.

[0009] Another embodiment of the present disclosure provides a memory device, which includes: memory cells configured to store data; and a page buffer coupled to the memory cells via bit lines and configured to: apply a first precharge voltage to the bit lines in response to program data and apply a second precharge voltage to the bit lines in response to erase data, the second precharge voltage being lower than the first precharge voltage, wherein the page buffer may include: a first precharge circuit configured to: output the first precharge voltage to a current sensing node in response to program data; a second precharge circuit configured to: output the second precharge voltage to the current sensing node in response to erase data; and a bit line coupling circuit configured to: transmit the first or second precharge voltage applied to the current sensing node to the bit lines.

[0010] Another embodiment of the present disclosure provides a memory device, which includes: memory cells configured to store data; a page buffer coupled to the memory cells via bit lines and configured to: precharge the bit lines in response to program data or erase data, wherein the page buffer may be configured to: generate a first precharge voltage through a first path for precharging the bit lines in response to program data; and generate a second precharge voltage through a second path for precharging the bit lines in response to erase data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 is a diagram illustrating Figure 1 the memory cell array illustrated in

[0013] Figure 3 is a diagram illustrating Figure 2 the memory block illustrated in

[0014] Figure 4 is a diagram illustrating a page buffer bank.

[0015] Figure 5 is a diagram illustrating a page buffer according to an embodiment.

[0016] Figure 6is a circuit diagram illustrating a page buffer according to a first embodiment.

[0017] Figure 7A and Figure 7B is a diagram illustrating a precharge operation using the page buffer according to the first embodiment.

[0018] Figure 8 is a circuit diagram illustrating a page buffer according to a second embodiment.

[0019] Figure 9A and Figure 9B is a diagram illustrating a precharge operation using the page buffer according to the second embodiment.

[0020] Figure 10 is a circuit diagram illustrating a page buffer according to a third embodiment.

[0021] Figure 11A and Figure 11B is a diagram illustrating a precharge operation using the page buffer according to the third embodiment.

[0022] Figure 12 is a circuit diagram illustrating a page buffer according to a fourth embodiment.

[0023] Figure 13A and Figure 13B is a diagram illustrating a precharge operation using the page buffer according to the fourth embodiment.

[0024] Figure 14 is a diagram illustrating a memory system to which a memory device according to an embodiment is applied.

[0025] Figure 15 is a diagram illustrating a memory card system to which a memory device according to an embodiment is applied.

[0026] Figure 16 is a diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment is applied. DETAILED DESCRIPTION

[0027] The specific structures or functional descriptions in the embodiments of the present disclosure introduced in this specification or application are illustrated to describe embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be practiced in various forms, and the embodiments should not be construed as limited to the embodiments described in the specification or application.

[0028] Figure 1 is a diagram illustrating a memory device according to an embodiment.

[0029] Reference Figure 1, the memory device 1100 may include: a memory cell array 110 for storing data; a peripheral circuit 200 that can perform programming, reading, and erasing operations; and a control logic circuit 170 that can control the peripheral circuit 200.

[0030] The memory cell array 110 may include a plurality of memory blocks in which data is stored. Each memory block in the memory blocks may include a plurality of memory cells, and the plurality of memory cells may be implemented in a two-dimensional (2D) structure (where the memory cells are horizontally arranged on a substrate) or a three-dimensional (3D) structure (where the memory cells are vertically stacked on a substrate).

[0031] The peripheral circuit 200 may include a row decoder 120, a voltage generator 130, a page buffer bank 140, a column decoder 150, and an input / output circuit 160.

[0032] The row decoder 120 may select one memory block from the memory blocks included in the memory cell array 110 in response to a row address RADD, and the row decoder 120 may transmit an operation voltage Vop to the selected memory block.

[0033] The voltage generator 130 may generate and output an operation voltage Vop for various operations in response to an operation code OPCD. For example, the voltage generator 130 may generate a programming voltage, a reading voltage, an erasing voltage, a pass voltage, and a verification voltage in response to the operation code OPCD, and the voltage generator 130 may also generate a negative voltage. The voltage generator 130 may selectively output the generated voltages.

[0034] The page buffer bank 140 may be coupled to the memory cell array 110 through bit lines. In one embodiment, the page buffer bank 140 may include page buffers coupled to corresponding bit lines. The page buffers may be simultaneously operated in response to page buffer control signals PBSIGS, and the page buffers may temporarily store data during a programming or reading operation. During a sensing operation, the page buffers may sense a current or voltage on the bit lines that varies with the threshold voltage of the memory cells, and store the sensed data. A sensing operation may be performed during a programming verification operation performed during a programming operation, an erase verification operation performed during an erase operation, and / or a reading operation. In one embodiment, during a sensing operation, the page buffer bank 140 may pre-charge the bit lines to a positive voltage, and then the page buffer bank 140 may sense a current or voltage on the bit lines that varies with the threshold voltage of the memory cells.

[0035] The column decoder 150 may transfer data DATA between the input / output circuit 160 and the page buffer bank 140 in response to a column address CADD.

[0036] The input / output circuit 160 may be coupled to an external device through input / output lines IO, and may receive / transmit a command CMD, an address ADD, and data DATA from / to the external device through the input / output lines IO. The external device may be a controller capable of controlling the memory device 1100. In one embodiment, the input / output circuit 160 may transmit the command CMD and the address ADD received from the controller through the input / output lines IO to the control logic circuit 170, and may transmit the data DATA received from the controller through the input / output lines IO to the column decoder 150. The input / output circuit 160 may output the data DATA received from the column decoder 150 to the controller through the input / output lines IO.

[0037] The control logic circuit 170 may output an opcode OPCD, a row address RADD, page buffer control signals PBSIGS, and a column address CADD in response to the command CMD and the address ADD. For example, the control logic circuit 170 may include software that executes an algorithm in response to the command CMD, and may include hardware that outputs various signals depending on the address ADD and the algorithm.

[0038] Figure 2 is a diagram Figure 1 of the memory cell array illustrated in

[0039] Refer to Figure 2 , the memory cell array 110 may be implemented as a single-plane structure or a multi-plane structure. The single-plane structure represents a configuration in which only one plane is included in the memory cell array 110, and the multi-plane structure represents a configuration in which multiple planes are included in the memory cell array 110. In Figure 2 , a memory cell array 110 having a multi-plane structure is illustrated. A plane may be defined as a memory region in which different row decoders are coupled to different page buffer groups. In one embodiment, when the first plane PL1 to the jth plane PLj (where j is a positive integer) are included in the memory cell array 110, each of the first plane PL1 to the jth plane PLj may include the first memory block BLK1 to the ith memory block BLKi (where i is a positive integer). The first memory block BLK1 to the ith memory block BLKi included in different planes may be coupled to different row decoders and different page buffer groups, and the first to the ith memory blocks included in the same plane may be coupled to the same row decoder and the same page buffer group. The first memory block BLK1 to the ith memory block BLKi may be configured with the same structure.

[0040] Figure 3 is a diagram Figure 2 of the memory block illustrated in

[0041] Reference Figure 3 , by way of example, Figure 2 any one of the plurality of memory blocks BLK1 to BLKi illustrated in

[0042] The memory block BLKi may include a plurality of strings ST coupled between the first bit line BL1 to the m-th bit line BLm (where m is a positive integer) and the source line SL. Each of the strings ST may include a source select transistor SST, a first memory cell C1 to an n-th memory cell Cn, and a drain select transistor DST coupled in series between the source line SL and a corresponding one of the first bit line BL1 to the m-th bit line BLm:

[0043] Since Figure 3 the memory block BLKi illustrated in Figure 3 is intended to illustrate the configuration of the memory block, the number of the source select transistor SST, the first memory cell C1 to the n-th memory cell Cn, and the drain select transistor DST is not limited to

[0044] those illustrated in

[0045] The respective gates of the source select transistors SST coupled to different strings ST may be coupled to the source select line SSL, the respective gates of the first memory cell C1 to the n-th memory cell Cn may be coupled to the first word line WL1 to the n-th word line WLn, and the respective gates of the drain select transistors DST may be coupled to the drain select line DSL.

[0046] The group of memory cells coupled to the same word line and included in different strings ST may form a page (PG). The programming operation and the read operation may be performed on the basis of the page (PG).

[0047] Figure 4 is a diagram illustrating a page buffer group.

[0048] Reference Figure 4, the page buffer group 140 may include a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm may be coupled between a first bit line BL1 to an m-th bit line BLm and a first data line DL1 to an m-th data line DLm. During a programming operation, the first page buffer PB1 to the m-th page buffer PBm may temporarily store data input through the first data line DL1 to the m-th data line DLm, and depending on the data, the first page buffer PB1 to the m-th page buffer PBm may apply a programming enable voltage or a programming inhibit voltage to the first bit line BL1 to the m-th bit line BLm. During a read operation, the first page buffer PB1 to the m-th page buffer PBm may sense the current or voltage of the bit lines BL1 to BLm, and may output the sensed data through the first data line DL1 to the m-th data line DLm.

[0049] The programming operation may include: a step of inputting data received from a controller that controls the memory device into the first page buffer PB1 to the m-th page buffer PBm; a step of setting the voltage of the first bit line BL1 to the m-th bit line BLm depending on the data input into the first page buffer PB1 to the m-th page buffer PBm; a step of applying a programming voltage to a selected word line; and a step of verifying the threshold voltage of a selected memory cell coupled to the selected word line.

[0050] The programming verification operation of verifying the threshold voltage of the memory cell is performed in a manner similar to that of the read operation, but does not output the sensed data through the first data line DL1 to the m-th data line DLm. In one embodiment, during the programming verification operation, the first page buffer PB1 to the m-th page buffer PBm may reduce the current consumption through the first bit line BL1 to the m-th bit line BLm, and may reduce the change in the current or voltage of the first bit line BL1 to the m-th bit line BLm.

[0051] The programming verification operation may include: a pre-charging step of pre-charging the first bit line BL1 to the m-th bit line BLm to a positive voltage; a step of evaluating the current or voltage of the first bit line BL1 to the m-th bit line BLm by applying a verification voltage to the selected word line, where the current or voltage has changed together with the threshold voltage of the memory cell; and a step of sensing the current or voltage of the first bit line BL1 to the m-th bit line BLm. At the above steps, in one embodiment, when a positive pre-charging voltage of the same level is applied to the first bit line BL1 to the m-th bit line BLm (i.e., all bit lines), the current consumption may increase rapidly. In one embodiment, the pre-charging voltage may be changed depending on the data input to the first page buffer PB1 to the m-th page buffer PBm or the data changed due to the verification operation. In one embodiment, in response to the page buffer control signal PBSIGS, the first page buffer PB1 to the m-th page buffer PBm may apply a first pre-charging voltage Vp1 to the selected bit line and a second pre-charging voltage Vp2 lower than the first pre-charging voltage Vp1 to the unselected bit line. The second pre-charging voltage Vp2 may be set to a positive voltage lower than the first pre-charging voltage Vp1 but higher than 0V.

[0052] The step of pre-charging the first bit line BLl to the m-th bit line BLm will be described in detail below.

[0053] When the programming operation starts, data can be input through the first data lines DL1 to the m-th data lines DLm coupled to the first page buffer PB1 to the m-th page buffer PBm. The data input to the first page buffer PB1 to the m-th page buffer PBm may be data output from the controller that controls the memory device. The data may consist of programming data DT_P and erase data DT_E. In one embodiment, the programming data DT_P may be set to '0', and the erase data DT_E may be set to '1', but depending on the memory device or memory system, at least one of the programming data DT_P or the erase data DT_E may be set differently.

[0054] Since the programming operation is performed to increase the threshold voltage of the memory cell in the erased state, the page buffer to which the programming data DT_P is input may be the selected page buffer, the bit line coupled to the selected page buffer may be the selected bit line, and the memory cell coupled to the selected bit line and the selected word line may be the selected memory cell. The page buffer to which the erase data DT_E is input may be the unselected page buffer, the bit line coupled to the unselected page buffer may be the unselected bit line, and the memory cell coupled to the unselected bit line and the selected word line may be the unselected memory cell.

[0055] After a program voltage has been applied to a selected word line for a predetermined period of time since the start of a self-programming operation, a program verification operation can be performed. When the program verification operation starts, the page buffer among the first page buffer PB1 to the m-th page buffer PBm, to which program data DT_P is input, applies a first precharge voltage Vp1 to the bit line, and the page buffer to which erase data DT_E is input can apply a second precharge voltage Vp2 to the bit line.

[0056] Suppose that the step (or stage) of applying a program voltage and the program verification step (stage) form a program loop, and multiple program loops can be executed until the threshold voltage of the selected memory cell increases upward to a target voltage. Whenever each program loop is executed, the program voltage can be increased by a step voltage. This scheme of increasing the step voltage is referred to as an incremental step pulse programming (ISPP) scheme in this article. Since, in the case where the ISPP scheme is executed, the threshold voltage of the selected memory cell is increased by the program voltage increase, the program data DT_P stored in the page buffer corresponding to the memory cell that has passed the program verification operation can be changed to erase data DT_E in order to prevent over-programming.

[0057] In one embodiment, as the number of program loops increases during a programming operation, the number of page buffers having erase data DT_E increases, and thus, during the program verification operation, the number of bit lines to which the second precharge voltage Vp2 is applied also increases.

[0058] Each page buffer will be described in detail below, which is configured to apply a first precharge voltage Vp1 or a second precharge voltage Vp2 to the bit line depending on the data.

[0059] Figure 5 is a diagram illustrating a page buffer according to an embodiment.

[0060] Reference Figure 5 , the first to the m-th page buffers are configured in the same manner (e.g., Figure 4 PB1 to PBm of Figure 5 ), and thus, as an example,

[0061] In one embodiment, the page buffer PB may include at least one latch LAT configured to store data, and may selectively activate a first precharge circuit 1PRE (which may output a first precharge voltage Vp1) or a second precharge circuit 2PRE (which may output a second precharge voltage Vp2) depending on the data stored in the latch LAT. The first precharge voltage Vp1 and the second precharge voltage Vp2 may be set to positive voltages higher than 0V, and the second precharge voltage Vp2 may be set to a value lower than the first precharge voltage Vp1. The first through mth page buffers (e.g., Figure 4 PB1 to PBm) of Figure 4 may be operated simultaneously in response to page buffer control signals PBSIGS, but the first through mth page buffers may selectively activate the first precharge circuit 1PRE or the second precharge circuit 2PRE depending on the stored data. In one embodiment, when programming data is stored in the latch LAT, the page buffer PB may activate the first precharge circuit 1PRE and then apply the first precharge voltage Vp1 to the bit line BL. In one embodiment, when the first precharge circuit 1PRE is activated, the second precharge circuit 2PRE may be deactivated. In one embodiment, when erase data is stored in the latch LAT, the page buffer PB may activate the second precharge circuit 2PRE and then apply the second precharge voltage Vp2 to the bit line BL.

[0062] The first precharge circuit 1PRE and the second precharge circuit 2PRE may be commonly supplied with a supply voltage VCC, but may generate the first precharge voltage Vp1 and the second precharge voltage Vp2 having different voltage levels through different paths depending on the data stored in the latch LAT.

[0063] The page buffer PB including the first precharge circuit 1PRE and the second precharge circuit 2PRE may be configured in various forms. The page buffer PB, which may output the first precharge voltage Vp1 and the second precharge voltage Vp2 having different voltage levels through different paths, will be described in detail below.

[0064] Figure 6 is a circuit diagram illustrating a page buffer according to a first embodiment.

[0065] Refer to Figure 6, the page buffer PB may include a bit line coupling circuit 61, a first precharge circuit 1PRE, and a second precharge circuit 2PRE. The bit line coupling circuit 61, the first precharge circuit 1PRE, and the second precharge circuit 2PRE may be commonly coupled to a current sensing node CSO. For example, the bit line coupling circuit 61 may be coupled between the current sensing node CSO and the bit line BL. A supply voltage VCC may be supplied to the first precharge circuit 1PRE. Both the supply voltage VCC and a ground voltage VSS may be supplied to the second precharge circuit 2PRE.

[0066] The bit line coupling circuit 61 may include a first switch S1, and the first switch S1 may be turned on in response to a page buffer sense signal PBSENSE. The first switch S1 may be implemented as an NMOS transistor. In one embodiment, when the bit line is precharged, a page buffer sense signal PBSENSE having a high level may be applied to the first switch S1.

[0067] The first precharge circuit 1PRE may include an unselected precharge circuit 62 and a sensing circuit 63.

[0068] The unselected precharge circuit 62 may apply a constant positive voltage to the bit line BL regardless of the data. The unselected precharge circuit 62 may include a third switch S3 coupled between a first node N1 and the current sensing node CSO. The third switch S3 may be implemented as an NMOS transistor, which is turned on or off in response to a current sense signal SA_CSOC. During a precharge operation, the third switch S3 may be turned on in response to a current sense signal SA_CSOC having a high level.

[0069] The sense circuit 63 can be coupled to the unselected precharge circuit 62 through the first node N1, and the sense circuit 63 can be electrically coupled to or decoupled from the unselected precharge circuit 62 depending on the data input to the data node QS. The sense circuit 63 can include a fourth switch S4 to a sixth switch S6, which are serially coupled between a terminal supplied with a supply voltage VCC and a current sense node CSO. The fourth switch S4 can be implemented as a PMOS transistor, which is turned on or off depending on the data input to the data node QS. The fifth switch S5 can be implemented as a PMOS transistor, which is turned on or off in response to an inverted precharge signal SA_PRE_N. The first node N1 can be coupled between the fourth switch S4 and the fifth switch S5. The sixth switch S6 can be coupled between the fifth switch S5 and the current sense node CSO, and the sixth switch S6 can be implemented as an NMOS transistor, which is turned on or off in response to a transmission signal TRANSO. The sense node SO can be coupled between the fifth switch S5 and the sixth switch S6. In one embodiment, a plurality of latches can be coupled to the sense node SO.

[0070] The second precharge circuit 2PRE can include a selected precharge circuit 64, a discharge circuit 65, a first latch LATl, and a first initialization circuit 66.

[0071] The selected precharge circuit 64 can include a seventh switch S7 and an eighth switch S8, which are coupled between a terminal supplied with a supply voltage VCC and a current sense node CSO. The seventh switch S7 can be coupled between the current sense node CSO and a second node N2, and the seventh switch S7 can be implemented as an NMOS transistor, which is turned on or off in response to a precharge signal SA_PRE. The eighth switch S8 can be coupled between the terminal supplied with the supply voltage VCC and the second node N2, and the eighth switch S8 can be implemented as a PMOS transistor, which is turned on or off in response to the data input to the inverted data node QS_N.

[0072] The discharge circuit 65 can include a ninth switch S9 and a tenth switch S10, which are serially coupled between a terminal supplied with a ground voltage VSS and a current sense node CSO. The ninth switch S9 can be coupled between the current sense node CSO and a third node N3, and the ninth switch S9 can be implemented as an NMOS transistor, which is turned on or off in response to a discharge signal SA_DIS. The tenth switch S10 can be coupled between the terminal supplied with the ground voltage VSS and the third node N3, and the tenth switch S10 can be implemented as an NMOS transistor, which is turned on or off in response to the data input to the data node QS.

[0073] The first latch LATl can be a latch used in a programming verification operation, and the first latch LATl can correspond to Figure 5 the latch LAT illustrated in. For example, the first latch LAT1 can include a first inverter I1 and a second inverter I2, and the first inverter I1 and the second inverter I2 are coupled in parallel between the data node QS and the inverted data node QS_N. For example, the sensed data can be input to the data node QS, and the data node QS can be coupled to the input terminal of the first inverter I1. The output terminal of the first inverter I1 can be coupled to the inverted data node QS_N. The inverted data node QS_N can be coupled to the input terminal of the second inverter I2, and the data node QS can be coupled to the output terminal of the second inverter I2. Thus, data segments that are inverted from each other can be input to the data node QS and the inverted data node QS_N.

[0074] The first initialization circuit 66 can be coupled between the terminal supplied with the ground voltage VSS and the first latch LATl. In one embodiment, the first initialization circuit 66 can include: an eleventh switch S11 coupled between the inverted data node QS_N and the fourth node N4; a twelfth switch S12 coupled between the data node QS and the fourth node N4; and a thirteenth switch S13 coupled between the terminal supplied with the ground voltage VSS and the fourth node N4. The eleventh switch S11 can be implemented as an NMOS transistor that conducts or turns off in response to the first set signal 1SET. The twelfth switch S12 can be implemented as an NMOS transistor that conducts or turns off in response to the first reset signal 1RST. The thirteenth switch S13 can be implemented as an NMOS transistor that conducts or turns off in response to the first initialization signal 1INT.

[0075] The precharge operation using the above page buffer PB according to the first embodiment will be described below.

[0076] Figure 7A and Figure 7B are diagrams illustrating the precharge operation of the page buffer according to the first embodiment. Figure 7A is a diagram illustrating the precharge operation of the page buffer PB coupled to the selected bit line Sel_BL, and Figure 7B is a diagram illustrating the precharge operation of the page buffer PB coupled to the unselected bit line Unsel_BL.

[0077] Refer to Figure 7AThe selected bit line Sel_BL represents the bit line coupled to the selected memory cell, and the selected memory cell represents the memory cell whose threshold voltage is to be increased during the programming operation. The selected memory cell and the unselected memory cell can be distinguished from each other based on the data of the data node QS input to the first latch LAT1. In one embodiment, it is assumed that the programming data corresponding to the selected memory cell is '0', and the erased data corresponding to the unselected memory cell is '1'. The data '0' can be identified as having a low-level voltage, and the data '1' can be identified as having a high-level voltage.

[0078] During the precharge operation, the page buffer sense signal PBSENSE, the precharge signal SA_PRE, the current sense signal SA_CSOC, and the transfer signal TRANSO having high levels can be applied to the page buffer PB. In one embodiment, the voltages of some signals can be set to different values. In one embodiment, the voltage level of the current sense signal SA_CSOC can be set to a value lower than the voltage level of the transfer signal TRANSO, the voltage level of the page buffer sense signal PBSENSE can be set to a value lower than the voltage level of the current sense signal SA_CSOC, and the voltage level of the precharge signal SA_PRE can be set to a value lower than or equal to the voltage level of the page buffer sense signal PBSENSE.

[0079] When the data input to the data node QS is '0', the data '1' is input to the inverted data node QS_N, and thus the eighth switch S8 is turned off. Therefore, even if the precharge signal SA_PRE having a high level is applied and the seventh switch S7 is turned on, the second node N2 is not coupled to the current sense node CSO.

[0080] Since the data input to the data node QS is '0', and both the current sense signal SA_CSOC and the page buffer sense signal PBSENSE have high levels, the fourth switch S4, the third switch S3, and the first switch S1 are turned on, and thus the first path 1PTH can be formed. The first precharge voltage Vp1 is generated from the supply voltage VCC supplied to the fourth switch S4 when passing through the first path 1PTH, and the selected bit line Sel_BL can be precharged to the first precharge voltage Vp1. That is, the page buffer in which the data '0' is input to the data node QS of the first latch LAT1 can precharge the bit line to the first precharge voltage Vp1.

[0081] Reference Figure 7B, the unselected bit line Unsel_BL represents the bit line coupled to the unselected memory cell, and the unselected memory cell represents the memory cell whose threshold voltage should not be increased during the programming operation. The selected memory cell and the unselected memory cell can be distinguished from each other based on the data of the data node QS input to the first latch LAT1. In one embodiment, it is assumed that the data corresponding to the selected memory cell is '0', and the data corresponding to the unselected memory cell is '1'. The data '0' can be identified as having a low-level voltage, and the data '1' can be identified as having a high-level voltage.

[0082] When the data input to the data node QS is '1', the data '0' is input to the inverted data node QS_N, and thus the eighth switch S8 can be turned on. Since the page buffer sense signal PBSENSE and the precharge signal SA_PRE have a high level, the seventh switch S7 and the first switch S1 can be turned on to form the second path 2PTH. Therefore, the second precharge voltage Vp2 can be generated from the supply voltage VCC supplied to the eighth switch S8 through the second path 2PTH, and the second precharge voltage Vp2 can be applied to the unselected bit line Unsel_BL. That is, the page buffer where the data '1' is input to the data node QS of the first latch LAT1 can apply the second precharge voltage Vp2 to the bit line.

[0083] In one embodiment, since the voltage level of the precharge signal SA_PRE used to turn on the seventh switch S7 included in the second path 2PTH is set to a value lower than the voltage level of the signal used to turn on the switch included in the first path (e.g., Figure 7A of 1PTH), the conduction level of the seventh switch S7 is at a voltage level lower than the conduction level of the switch included in the first path 1PTH. Therefore, the second precharge voltage Vp2 lower than the first precharge voltage Vp1 can be applied to the current sense node CSO, and the first switch S1 can be turned on, and thus the unselected bit line Unsel_BL can be precharged to the second precharge voltage Vp2. That is, the page buffer where the data '1' is input to the data node QS of the first latch LAT1 can precharge the bit line to the second precharge voltage Vp2 lower than the first precharge voltage (e.g., Figure 7A of Vp1). Since the second precharge voltage Vp2 output through the second path 2PTH is lower than the first precharge voltage Vp1, the current consumption can be lower than the current consumption when all bit lines are precharged to the first precharge voltage Vp1.

[0084] Figure 8 is a circuit diagram illustrating a page buffer according to the second embodiment.

[0085] Reference Figure 8 , some components of the page buffer PB according to the second embodiment are similar to those of the page buffer PB according to the first embodiment, and thus the repeated description of the components overlapping with the first embodiment will be omitted.

[0086] In the page buffer PB according to the second embodiment, the selection precharge circuit (e.g., Figure 6 64) according to the first embodiment is omitted, and a power selection circuit 81 for selectively supplying the power supply voltage VCC or the ground voltage VSS may be included in the discharge circuit 65.

[0087] The power selection circuit 81 may be coupled to the tenth switch S10 of the discharge circuit 65. The power selection circuit 81 may include a fourteenth switch S14 and a fifteenth switch S15, and the fourteenth switch S14 and the fifteenth switch S15 are serially coupled between a terminal supplied with the power supply voltage VCC and a terminal supplied with the ground voltage VSS. The fourteenth switch S14 may be coupled between the terminal supplied with the power supply voltage VCC and the fifth node N5, and the fourteenth switch S14 may be implemented as an NMOS transistor that is turned on or off in response to a first power selection signal 1VS. The fifteenth switch S15 may be coupled between the terminal supplied with the ground voltage VSS and the fifth node N5, and the fifteenth switch S15 may be implemented as an NMOS transistor that is turned on or off in response to a second power selection signal 2VS. In one embodiment, in the case of performing a precharge operation, the second power selection signal 2VS may have a low level, and the first power selection signal 1VS may have a high level. In one embodiment, when the precharge operation is not performed, the first power selection signal 1VS may have a low level, and the second power selection signal 2VS may have a high level.

[0088] Figure 9A and Figure 9B is a diagram illustrating a precharge operation of a page buffer using the second embodiment, Figure 9A is a diagram illustrating a precharge operation of the page buffer PB coupled to the selected bit line Sel_BL, and Figure 9B is a diagram illustrating a precharge operation of the page buffer PB coupled to the unselected bit line Unsel_BL.

[0089] Reference Figure 9A, during the precharge operation, a page buffer sense signal PBSENSE, a precharge signal SA_PRE, a current sense signal SA_CSOC, a transfer signal TRANSO, and a discharge signal SA_DIS having high levels can be applied to the page buffer PB. In one embodiment, the voltages of some signals can be set to different values. In one embodiment, the voltage level of the current sense signal SA_CSOC can be set to a value lower than the voltage level of the transfer signal TRANSO, the voltage level of the page buffer sense signal PBSENSE can be set to a value lower than the voltage level of the current sense signal SA_CSOC, and the voltage level of the discharge signal SA_DIS can be set to a value lower than or equal to the voltage level of the page buffer sense signal PBSENSE.

[0090] When the data input to the data node QS is '0', the page buffer PB can output a first precharge voltage Vpl through the first path 1PTH. Since the first path 1PTH through which the first precharge voltage Vp1 is output is the same as the first path 1PTH of the first embodiment, a repeated description thereof will be omitted.

[0091] Reference Figure 9B , since the data input to the data node QS is '1', and both the discharge signal SA_DIS and the first power selection signal 1VS have high levels, the fourteenth switch S14, the tenth switch S10, the ninth switch S9, and the first switch S1 can be turned on, and thus a second path 2PTH can be formed. Therefore, a second precharge voltage Vp2 can be generated from the supply voltage VCC supplied to the fourteenth switch S14 in the case of passing through the second path 2PTH, and the second precharge voltage Vp2 can be applied to the unselected bit line Unsel_BL. That is, the page buffer in which the data '1' is input to the data node QS of the first latch LAT1 can apply the second precharge voltage Vp2 to the bit line.

[0092] In one embodiment, since the voltage level of the discharge signal SA_DIS for turning on the ninth switch S9 included in the second path 2PTH is set to be lower than that for the first path (e.g., Figure 9AThe voltage level value of the signal for turning on the switch included in the first path 1PTH, so the conduction level of the ninth switch S9 is at a voltage level lower than the conduction level of the switch included in the first path 1PTH. Therefore, the second precharge voltage Vp2 lower than the first precharge voltage Vp1 can be applied to the current sensing node CSO, and the first switch S1 can be turned on, and thus the unselected bit line Unsel_BL can be precharged to the second precharge voltage Vp2. That is, the page buffer where data '1' is input to the data node QS of the first latch LAT1 can precharge the bit line to a second precharge voltage Vp2 lower than the first precharge voltage (e.g., Figure 9A Vp1). Since the second precharge voltage Vp2 output through the second path 2PTH is lower than the first precharge voltage Vp1, the current consumption can be lower than the current consumption when all bit lines are precharged to the first precharge voltage Vp1.

[0093] Figure 10 FIG. is a circuit diagram showing a page buffer according to the third embodiment.

[0094] Refer to Figure 10 , some components of the page buffer PB according to the third embodiment are similar to those of the page buffer PB according to the second embodiment, and thus the repeated description of the components overlapping with the second embodiment will be omitted.

[0095] In the page buffer PB according to the third embodiment, the power selection circuit 81 according to the second embodiment is omitted, and may include a second sub-precharge circuit 121, a second latch LAT2, and a second initialization circuit 122.

[0096] The second sub-precharge circuit 121 may be coupled between the terminal supplied with the supply voltage VCC and the current sensing node CSO, the second latch LAT2 may be coupled between the second sub-precharge circuit 121 and the second initialization circuit 122, and the second initialization circuit 122 may be coupled between the terminal supplied with the ground voltage VSS and the second latch LAT2.

[0097] The second sub-precharge circuit 121 may include a seventeenth switch S17 and an eighteenth switch S18. The seventeenth switch S17 and the eighteenth switch S18 are serially coupled between a terminal supplied with a supply voltage VCC and a current sensing node CSO. The seventeenth switch S17 may be coupled between the current sensing node CSO and a seventh node N7, and the seventeenth switch S17 may be implemented as an NMOS transistor that is turned on or off in response to a precharge signal SA_PRE. The eighteenth switch S18 may be coupled between the terminal supplied with the supply voltage VCC and the seventh node N7, and the eighteenth switch S18 may be implemented as a PMOS transistor that is turned on or off in response to data input to an inverted data replication node QP_N of the second latch LAT2.

[0098] The second latch LAT2 may be configured to store the same data as the first latch LAT1. In one embodiment, the second latch LAT2 may store data replicated from the data stored in the first latch LAT1. The second latch LAT2 may include a third inverter I3 and a fourth inverter I4. The third inverter I3 and the fourth inverter I4 are parallely coupled between a data replication node QP and an inverted data replication node QP_N. An output terminal of the third inverter I3 may be coupled to the inverted data replication node QP_N, and the inverted data replication node QP_N may be coupled to a gate of the eighteenth switch S18. An input terminal of the fourth inverter I4 may be coupled to the output terminal of the third inverter I3, and an output terminal of the fourth inverter I4 may be coupled to an input terminal of the third inverter I3.

[0099] The second initialization circuit 122 may be coupled between a terminal supplied with a ground voltage VSS and the second latch LAT2. In one embodiment, the second initialization circuit 122 may include: a nineteenth switch S19 coupled between the inverted data replication node QP_N and an eighth node N8; a twentieth switch S20 coupled between the data replication node QP and the eighth node N8; and a twenty-first switch S21 coupled between the terminal supplied with the ground voltage VSS and the eighth node N8. The nineteenth switch S19 may be implemented as an NMOS transistor that is turned on or off in response to a second set signal 2SET. The twentieth switch S20 may be implemented as an NMOS transistor that is turned on or off in response to a second reset signal 2RST. The twenty-first switch S21 may be implemented as an NMOS transistor that is turned on or off in response to a second initialization signal 2INT.

[0100] A precharge operation using the above page buffer PB according to the third embodiment will be described below.

[0101] Figure 11A and Figure 11BFIG. is a diagram illustrating a precharge operation of a page buffer according to a third embodiment. Figure 11A FIG. is a diagram illustrating a precharge operation of a page buffer PB coupled to a selected bit line Sel_BL, and Figure 11B FIG. is a diagram illustrating a precharge operation of a page buffer PB coupled to an unselected bit line Unsel_BL.

[0102] Reference Figure 11A , during a precharge operation, a page buffer sense signal PBSENSE and a precharge signal SA_PRE having a high level can be applied to the page buffer PB. In one embodiment, the voltages of some signals can be set to different values. In one embodiment, the voltage level of a current sense signal SA_CSOC can be set to a value lower than the voltage level of a transmission signal TRANSO, the voltage level of the page buffer sense signal PBSENSE can be set to a value lower than the voltage level of the current sense signal SA_CSOC, and the voltage level of the precharge signal SA_PRE can be set to a value lower than or equal to the voltage level of the page buffer sense signal PBSENSE.

[0103] When the data input to a data node QS is '0', the page buffer PB can output a first precharge voltage Vpl through a first path 1PTH. Since the first path 1PTH through which the first precharge voltage Vp1 is output is the same as the first path 1PTH of the first embodiment, a repetitive description thereof will be omitted.

[0104] Reference Figure 11B , when the data input to the data node QS is 1, the data '1' can be input to a data replication node QP, and the data '0' can be input to an inverted data replication node QP_N. Since the data input to the inverted data replication node QP_N is '0', and the precharge signal SA_PRE has a high level, the eighteenth switch S18, the seventeenth switch S17, and the first switch S1 can be turned on to form a second path 2PTH. Therefore, a second precharge voltage Vp2 can be generated from a supply voltage VCC supplied to the eighteenth switch S18 while passing through the second path 2PTH, and the second precharge voltage Vp2 can be applied to the unselected bit line Unsel_BL. That is, the page buffer in which the data '0' is input to the inverted data replication node QP_N of the second latch LAT2 can apply the second precharge voltage Vp2 to the bit line.

[0105] In one embodiment, since the voltage level of the precharge signal SA_PRE for turning on the seventeenth switch S17 included in the second path 2PTH is set to be lower than that for the first path (e.g., Figure 11Athe voltage level value of the signal for turning on the switch included in the 1PTH), so the conduction level of the seventeenth switch S17 is lower than the conduction level of the switch included in the first path 1PTH. Therefore, the second precharge voltage Vp2 lower than the first precharge voltage Vp1 can be applied to the current sense node CSO, and the first switch S1 can be turned on, and thus the unselected bit line Unsel_BL can be precharged to the second precharge voltage Vp2. That is, the page buffer where the data '1' is input to the data replication node QP of the second latch LAT2 can precharge the bit line to a second precharge voltage Vp2 lower than the first precharge voltage (e.g., Figure 11A Vp1). Since the second precharge voltage Vp2 output through the second path 2PTH is lower than the first precharge voltage Vp1, the power consumption can be lower than the power consumption when all bit lines are precharged to the first precharge voltage Vp1.

[0106] Figure 12 is a circuit diagram showing a page buffer according to the fourth embodiment.

[0107] Refer to Figure 12 , some components of the page buffer PB according to the fourth embodiment are similar to those of the page buffer PB according to the third embodiment, and thus the repeated description of the components overlapping with the third embodiment will be omitted.

[0108] In the page buffer PB according to the fourth embodiment, the second sub-precharge circuit 121 can be coupled to the sense node SO instead of the current sense node CSO, and the coupling configuration of the remaining circuits can be the same as the coupling configuration of the third embodiment.

[0109] The precharge operation using the above page buffer PB according to the fourth embodiment will be described below.

[0110] Figure 13A and Figure 13B are diagrams showing the precharge operation using the page buffer according to the fourth embodiment. Figure 13A is a diagram showing the precharge operation of the page buffer PB coupled to the selected bit line Sel_BL, and Figure 13B is a diagram showing the precharge operation of the page buffer PB coupled to the unselected bit line Unsel_BL.

[0111] Refer to Figure 13A, during the precharge operation, a page buffer sense signal PBSENSE and a precharge signal SA_PRE having a high level can be applied to the page buffer PB. In one embodiment, the voltages of some signals can be set to different values. In one embodiment, the voltage level of a current sense signal SA_CSOC can be set to a value lower than the voltage level of a transmission signal TRANSO, the voltage level of the page buffer sense signal PBSENSE can be set to a value lower than the voltage level of the current sense signal SA_CSOC, and the voltage level of the precharge signal SA_PRE can be set to a value lower than or equal to the voltage level of the page buffer sense signal PBSENSE.

[0112] When the data input to the data node QS is '0', the page buffer PB can output a first precharge voltage Vpl through a first path 1PTH. Since the first path 1PTH through which the first precharge voltage Vp1 is output is the same as the first path 1PTH of the first embodiment, a repeated description thereof will be omitted.

[0113] Reference Figure 13B , when the data input to the data node QS is 1, the data '1' can be input to a data replication node QP, and the data '0' can be input to an inverted data replication node QP_N. Since the data input to the inverted data replication node QP_N is '0' and the precharge signal SA_PRE has a high level, the eighteenth switch S18, the seventeenth switch S17, the sixth switch S6, and the first switch S1 can be turned on to form a second path 2PTH. Accordingly, a second precharge voltage Vp2 can be generated from a supply voltage VCC supplied to the eighteenth switch S18 in passing through the second path 2PTH, and the second precharge voltage Vp2 can be applied to an unselected bit line Unsel_BL. That is, the page buffer in which the data '0' is input to the inverted data replication node QP_N of the second latch LAT2 can apply the second precharge voltage Vp2 to the bit line.

[0114] In one embodiment, since the voltage level of the precharge signal SA_PRE for turning on the seventeenth switch S17 included in the second path 2PTH is set to be lower than that for the first path (e.g., Figure 13Athe voltage level value of the signal for turning on the switch included in the 1PTH), the conduction level of the seventeenth switch S17 is lower than the conduction level of the switch included in the first path 1PTH. Accordingly, a second precharge voltage Vp2 lower than the first precharge voltage Vp1 can be applied to the current sensing node CSO, and the first switch S1 can be turned on, and thus the unselected bit line Unsel_BL can be precharged to the second precharge voltage Vp2. That is, the page buffer in which data '1' is input to the data replication node QP of the second latch LAT2 can precharge the bit line to a second precharge voltage Vp2 lower than the first precharge voltage (e.g., Figure 13A Vp1). Since the second precharge voltage Vp2 output through the second path 2PTH is lower than the first precharge voltage Vp1, the power consumption can be lower than the power consumption when all bit lines are precharged to the first precharge voltage Vp1.

[0115] Figure 14 FIG. is a diagram of a memory system to which a memory device according to an embodiment is applied.

[0116] Reference Figure 14 , the memory system 1000 may store, erase, or output data in response to a request from the host 2000. For example, the memory system 1000 may include a memory device 1100 and a controller 1200. The memory device 1100 may store data, and the controller 1200 may perform communication between the host 2000 and the memory device 1100. Although the memory system 1000 including one memory device 1100 is illustrated in Figure 14 , the memory system 1000 may include two or more memory devices. Figure 14 The memory device 1100 illustrated in Figure 1 may be the same as the memory device 1100 illustrated in

[0117] When receiving a request output from the host 2000, the controller 1200 may generate a command for controlling the memory device 1100 in response to the request. The controller 1200 may manage the logical address used by the host 2000 and the physical address used by the memory device 1100. When a programming operation is described as an example, the host 2000 may output a programming request and data to the memory system 1000. The controller 1200 included in the memory system 1000 may generate a programming command in response to the programming request received from the host 2000, and may output the programming command, the physical address, and the data to the memory device 1100.

[0118] Figure 15FIG. is a diagram of a memory card system to which a memory device according to one embodiment is applied.

[0119] Referring Figure 15 , the memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0120] The controller 3100 is coupled to the memory device 3200. The controller 3100 can access the memory device 3200. In one embodiment, the controller 3100 may control programming, reading, or erasing operations on the memory device 3200, or may control background operations on the memory device 3200. The controller 3100 can provide an interface between the memory device 3200 and a host (such as, for example, Figure 14 the host 2000 shown in Figure 16 or the host 4100 shown in

[0121] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In one embodiment, the controller 3100 can communicate with an external device through at least one of various interface protocols, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA) protocol, Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WIFI, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In one embodiment, the connector 3300 can be defined by at least one of the above various communication protocols.

[0122] The memory device 3200 can be configured in the same manner as the memory device 1100 illustrated in Figure 1

[0123] The controller 3100 and the memory device 3200 may be integrated into a single semiconductor device to form a memory card. In one embodiment, the controller 3100 and the memory device 3200 may be integrated into a single semiconductor device, and then the controller 3100 and the memory device 3200 may form a memory card, such as a Personal Computer Memory Card International Association (PCMCIA), CompactFlash (CF), SmartMedia (SM or SMC), Memory Stick, Multimedia Card (MMC, RS-MMC, microMMC or eMMC), SD card (SD, miniSD, microSD or SDHC), or Universal Flash Storage (UFS).

[0124] Figure 16 FIG. is a diagram of a solid state drive (SSD) system to which a memory device according to one embodiment is applied.

[0125] Reference Figure 16 , the SSD system 4000 may include a host 4100 and an SSD 4200. The SSD 4200 may exchange signals SIG with the host 4100 through a signal connector 4001, and the SSD 4200 may receive power PWR through a power connector 4002. The SSD 4200 may include a controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0126] The controller 4210 may control the plurality of flash memories 4221 to 422n in response to signals received from the host 4100. In one embodiment, the signal may be a signal based on the interface between the host 4100 and the SSD 4200. In one embodiment, such a signal may be a signal defined by at least one of various interfaces, such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), WiFi, Bluetooth, and Non-Volatile Memory Express (NVMe) interfaces.

[0127] Each of the flash memories 4221 to 422n may be configured in the same manner as the memory device 1100 illustrated in Figure 1 .

[0128] The auxiliary power supply 4230 can be coupled to the host 4100 through the power connector 4002. The auxiliary power supply 4230 can be supplied with the power supply voltage from the host 4100, and the auxiliary power supply 4230 can use the power supply voltage to charge. When the power supply from the host 4100 is not successfully executed, the auxiliary power supply 4230 can provide the power supply voltage of the SSD 4200. In one embodiment, the auxiliary power supply 4230 can be located inside the SSD 4200 or outside the SSD 4200. In one embodiment, the auxiliary power supply 4230 can be located in the motherboard, and the auxiliary power supply 4230 can also provide auxiliary power to the SSD 4200.

[0129] The buffer memory 4240 can be used as the buffer memory of the SSD 4200. In one embodiment, the buffer memory 4240 can temporarily store the data received from the host 4100 or the data received from the plurality of flash memories 4221 to 422n, or can temporarily store the metadata (e.g., mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 can include volatile memory (such as DRAM, SDRAM, DDR SDRAM, and LPDDR SDRAM) or non-volatile memory (such as FRAM, ReRAM, STT-MRAM, and PRAM).

[0130] The memory system and operations described herein can reduce the current consumption when the bit lines are precharged, and the memory system can reduce the change in the current or voltage of the bit lines, thereby improving the reliability of the verification operations performed on the memory cells.

Claims

1. A memory device, comprising: Memory cells configured to store data; And A page buffer configured to: Store data to be stored in the memory cells through a programming operation, and During a programming verification operation, in response to the data stored in the page buffer being programming data, precharge a bit line to a first precharge voltage, or in response to the data stored in the page buffer being erased data, precharge the bit line to a second precharge voltage, the second precharge voltage being lower than the first precharge voltage.

2. The memory device according to claim 1, wherein the page buffer comprises: A first precharge circuit configured to generate the first precharge voltage; A second precharge circuit configured to generate the second precharge voltage and comprising a first latch configured to store the data; And A bit line coupling circuit configured to transmit the first precharge voltage or the second precharge voltage to the bit line.

3. The memory device according to claim 2, wherein: The first precharge circuit, the second precharge circuit and the bit line coupling circuit are commonly coupled to a current sensing node, and The bit line coupling circuit is configured to: transmit the first precharge voltage or the second precharge voltage applied to the current sensing node to the bit line.

4. The memory device according to claim 3, wherein the first precharge circuit is supplied with a supply voltage and is configured to: generate the first precharge voltage from the supply voltage through a first path.

5. The memory device according to claim 4, wherein the second precharge circuit is supplied with the supply voltage and is configured to: generate the second precharge voltage from the supply voltage through a second path different from the first path.

6. The memory device according to claim 5, wherein: When the data is programming data, the first precharge circuit is activated, and When the data is erased data, the second precharge circuit is activated.

7. The memory device according to claim 5, wherein: The first precharge circuit includes a first switch included in the first path, and The second precharge circuit includes a second switch included in the second path.

8. The memory device according to claim 7, wherein the voltage applied to the gate of at least one of the second switches has a level lower than the level of the voltage applied to the gate of the first switch.

9. The memory device according to claim 7, wherein the conduction level of at least one of the second switches has a level lower than the conduction level of the first switch.

10. A memory device, comprising: Memory cells configured to store data; And A page buffer, coupled to the memory cell via a bit line, and configured to: apply a first precharge voltage to the bit line in response to programming data, and apply a second precharge voltage to the bit line in response to erase data, the second precharge voltage being lower than the first precharge voltage, wherein the page buffer includes: A first precharge circuit, configured to: in response to the programming data, output the first precharge voltage to a current sensing node; A second precharge circuit, configured to: in response to the erase data, output the second precharge voltage to the current sensing node; and A bit line coupling circuit, configured to: transmit the first precharge voltage or the second precharge voltage applied to the current sensing node to the bit line.

11. The memory device according to claim 10, wherein: The first precharge circuit is configured to: be deactivated when the erase data is input to the page buffer, and The second precharge circuit is configured to: be deactivated when the programming data is input to the page buffer.

12. The memory device according to claim 10, wherein the first precharge circuit includes: A first switch, supplied with a supply voltage, and configured to: in response to the programming data, transmit the supply voltage to a first node; And A second switch, configured to: transmit the voltage applied to the first node to the current sensing node.

13. The memory device according to claim 12, wherein the first switch is configured to be turned off in response to the erase data.

14. The memory device according to claim 10, wherein the second precharge circuit includes: A latch, configured to: store the programming data or the erase data; And A third switch, supplied with a supply voltage, and configured to: in response to inverted erase data, which is the inverted data of the erase data, reduce the level of the supply voltage to generate the second precharge voltage; And then output the second precharge voltage to the current sensing node.

15. The memory device according to claim 14, wherein the voltage level of the signal applied to the gate of the third switch is set to a level lower than the voltage level of the signal applied to the gate of the switch included in the first precharge circuit.

16. The memory device according to claim 14, wherein: When the memory cell is a programming target cell, the programming data is stored in the latch, and When the memory cell is not a programming target cell, the erase data is stored in the latch.

17. The memory device according to claim 14, wherein after the programming data has been stored in the latch, when the threshold voltage of the memory cell increases upward to a target voltage, the programming data stored in the latch is changed to the erase data.

18. A memory device, including: Memory cells, configured to store data; A page buffer, coupled to the memory cell via a bit line, and configured to: pre-charge the bit line in response to programming data or erasing data, wherein the page buffer is configured to: in response to the programming data, generate a first pre-charge voltage through a first path for pre-charging the bit line, and in response to the erasing data, generate a second pre-charge voltage through a second path for pre-charging the bit line.

19. The memory device according to claim 18, wherein the first path is activated in response to the programming data and deactivated in response to the erasing data.

20. The memory device according to claim 18, wherein the second path is activated in response to the erasing data and deactivated in response to the programming data.

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