Mitigating read disturb effects in memory devices

Abstract

This application relates to mitigating read disturb effects in a memory device. A total read counter, a plurality of die read counters, and a plurality of block read counters are maintained. Each die read counter is associated with a respective die of the memory device. A value of a block read counter and a value of a die read counter are determined for a specified block. An estimated number of read events associated with the specified block of the memory device is determined based on the value of the block read counter, the value of the die read counter, and a value of the total read counter. In response to determining that the estimated number of read events satisfies a predefined criterion, a media management operation of one or more pages associated with the specified block is performed.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically, to mitigating read interference effects in memory devices. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a method comprising: maintaining a plurality of die read counters via a processing means, wherein each of the plurality of die read counters is associated with a corresponding die of a memory device; maintaining a plurality of block read counters; maintaining a total read counter associated with the memory device; determining values ​​of the block read counters and the die read counters for a specified block of the memory device; determining an estimated number of read events associated with the specified block of the memory device based on the values ​​of the block read counters, the values ​​of the die read counters, and the value of the total read counter; and performing media management operations on one or more pages associated with the specified block of the memory device in response to determining that the estimated number of read events satisfies a predefined criterion.

[0004] Another aspect of this disclosure provides a system comprising: a plurality of memory devices; a processing means operatively coupled to the plurality of memory devices; and a direct memory access (DMA) controller operatively coupled to the plurality of memory devices to perform operations including: receiving one or more block read counter values, one or more die read counter values, and a total read counter value from memory devices among the plurality of memory devices; determining a plurality of estimated numbers of read events, wherein each estimated number of read events is associated with a block of the memory device and is based on one of the block read counter values, one of the die read counter values, and the total read counter value; identifying one or more blocks whose associated estimated number of read events satisfies a predefined criterion; and performing media management operations on one or more pages associated with each identified block whose associated estimated number of read events satisfies the predefined criterion.

[0005] Another aspect of this disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations including: maintaining a plurality of die read counters, each of the plurality of die read counters being associated with a corresponding die of a memory device; maintaining a plurality of block read counters; maintaining a total read counter associated with the memory device; determining values ​​for the block read counters and the die read counters for a specified block of the memory device; determining an estimated number of read events associated with the specified block of the memory device based on the values ​​of the block read counters, the values ​​of the die read counters, and the value of the total read counter; and performing media management operations for one or more pages associated with the specified block of the memory device in response to determining that the estimated number of read events satisfies a predefined criterion. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the particular embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This document describes an example workflow of matrix read interference with enhanced direct memory access capability according to some embodiments of the present disclosure.

[0009] Figure 3 This is a flowchart illustrating an example method for reading an interference matrix according to some embodiments of the present disclosure.

[0010] Figure 4 This is a flowchart illustrating an example method for reading an interference matrix using a controller with DMA capability, according to some embodiments of this disclosure.

[0011] Figure 5 This describes an example arrangement of memory devices and corresponding read counters within a memory subsystem according to some embodiments of the present disclosure.

[0012] Figure 6A This describes the first step of determining the matrix read value according to some embodiments of this disclosure.

[0013] Figure 6B This describes an example of reading an interference matrix based on some embodiments of this disclosure.

[0014] Figure 7This is a block diagram of an example computer system in which embodiments of the present disclosure can be operated. Detailed Implementation

[0015] Various aspects of this disclosure relate to mitigating read interference effects in memory devices. The memory subsystem may be a memory device, a memory module, or a combination of a memory device and a memory module. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem, which includes one or more components, such as memory devices for storing data. The host system can provide data to be stored in the memory subsystem and can request to retrieve data from the memory subsystem.

[0016] The memory subsystem may contain high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logical states associated with the number of bits stored. Logical states may be represented by binary values ​​(such as “0” and “1”) or combinations of such values.

[0017] Memory devices can be composed of bits arranged in a two-dimensional grid. Memory cells are etched onto a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in the memory device, which are used in conjunction with one or more bit lines to generate an address for each of the memory cells. The intersection of bit lines and word lines constitutes the address of the memory cell. Hereinafter, a block refers to a cell of the memory device used to store data and can include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form planes of the memory device to allow concurrent operation on each plane. The memory device can include circuitry for performing concurrent memory page accesses on two or more memory planes. For example, the memory device can include corresponding access line driver circuitry and power circuitry for each plane of the memory device to facilitate concurrent access to pages in two or more memory planes containing different page types.

[0018] When data is read from a memory cell, nearby or adjacent memory cells may experience events known as read interference. Read interference is the result of continuously reading from one memory cell without any interrupted erase operation, causing other nearby memory cells to change over time. If too many read operations are performed on a memory cell, the data stored in adjacent memory cells of the memory device can be corrupted, leading to a higher error rate of the data stored in the memory cell. Read interference can increase the use of error detection and correction operations (e.g., error control operations) for subsequent operations performed on the memory cell (e.g., reads and / or writes). The increased use of error control operations can lead to a degradation of the performance of the memory subsystem. Furthermore, as the error rate of a memory cell or block continues to increase, it may eventually exceed the error correction capabilities of the memory subsystem, resulting in irreparable loss of data. In addition, because more resources of the memory subsystem are used to perform error control operations, fewer resources are available for performing other read or write operations.

[0019] The error rate associated with the data stored at the block can increase due to read interference. Therefore, after performing a threshold number of read operations on the block, the memory subsystem can perform various media management operations, such as data integrity checks (also referred to herein as "scans"), to verify that the data stored at the block does not contain errors. During the data integrity check, one or more reliability statistics are determined for the data stored at the block. One example of a reliability statistic is the raw bit error rate (RBER). RBER corresponds to the number of bit errors encountered per unit time by the data stored at the block.

[0020] Sometimes, the memory subsystem may monitor the number of read operations performed on a specific block and perform a scan operation when the read count (i.e., the number of read operations) meets and / or exceeds a certain read threshold. Therefore, the number of read counters required to determine when to perform data integrity checks at the block level can consume a significant amount of available memory space (e.g., RAM). For example, for a memory subsystem with a maximum capacity of 16 terabytes, maintaining the read count at the block level would require 545,248 32-bit counters and would consume over 2.26 megabytes.

[0021] To consume less memory space, the memory subsystem can maintain read counts at the die level rather than the block level. Each die counter contains scan-triggered events based on a window count limit. Randomly scanning blocks and sets of risky pages within the window count limit presents a behavioral problem (e.g., scanning RBER). The scan result can lead to a decision to flush the block or allow it to remain in the read pool. While this approach to address read interference requires fewer counters (e.g., a 16-bit counter per die in the memory subsystem) to be effective, the window count limit should be relatively low. This low window count limit can lead to more scans, thus adversely affecting the quality of service (QoS) of the memory subsystem.

[0022] The aspects of this disclosure address the aforementioned and other drawbacks by implementing a memory subsystem that mitigates read interference effects by maintaining a smaller number of read counters. Therefore, the memory subsystem controller can maintain a die read counter for each die of the memory device, a block read counter for the number of blocks per die, and a total read counter to count the total number of read operations performed on the memory device. For example, for a memory device with 256 dies and 1,352 blocks per die, the memory subsystem controller can maintain 256 die read counters (one die read counter per die), 1,352 block read counters (one block read counter per block number per die), and a total read counter. Upon detecting a page read event, the total read counter, the die read counter associated with the die being read, and the block read counter associated with the block number being read are each incremented by a specified value (e.g., 1). Using these three types of counters, the memory subsystem controller fills a read count value matrix for each block. Each block is represented by a block-die combination in the matrix.

[0023] To populate the matrix, the memory subsystem controller may first calculate the share of readings associated with each block (i.e., the block read counter value divided by the total read counter value) and the share of readings associated with each die (i.e., the die read counter value divided by the total read counter value). The memory subsystem controller may then multiply the share of readings associated with blocks in the block-die combination by the share of readings associated with dies in the block-die combination. To determine the final read count value in the matrix, the resulting value is multiplied by the total read count and rounded to the nearest integer. In some embodiments, the memory subsystem controller calculates the read count value for each block-die combination by multiplying the block read counter value in the block-die combination by the die read counter value in the block-die combination and dividing by the total read counter value, rounding to the nearest integer.

[0024] The matrix read value represents an estimate of the number of read events for pages in a block-die combination. A block-die combination represents a specific block of the memory device. Once the matrix read value for a block-die combination reaches a threshold, the memory subsystem controller can perform a data integrity scan of the pages associated with that block-die combination.

[0025] In some implementations, the counter value may be maintained in volatile memory and periodically transferred to non-volatile memory. Matrix readout values ​​may be determined in volatile memory and periodically and / or transferred to non-volatile memory after the memory subsystem is powered off. When the memory subsystem is powered on, the matrix readout values ​​stored in non-volatile memory may be transferred to volatile memory, where matrix readout interference operations may be performed.

[0026] In embodiments, the memory subsystem controller may utilize enhanced direct memory access (DMA) capabilities. A controller with enhanced DMA capabilities can be configured to perform direct memory transfers from a source memory region to a destination memory region and can perform basic arithmetic using an arithmetic logic unit (ALU). In an embodiment, the ALU capable of DMA can perform the read value matrix calculations described above. Furthermore, matrix read values ​​can be transferred using DMA from one region of volatile memory (e.g., DRAM buffer) to another region of volatile memory, and ultimately to a non-volatile memory device. Newly determined matrix read values ​​can be added to matrix read values ​​stored in non-volatile memory, and the memory subsystem controller can use the added matrix read values ​​to determine whether the read value of a block-die combination has reached a threshold. The memory subsystem controller can use DMA capabilities to perform a scan of pages associated with block-die combinations whose associated matrix read values ​​have reached or exceeded the threshold. Additionally, the ALU features of the enhanced DMA controller can perform read matrix value calculations.

[0027] The advantages of this disclosure include, but are not limited to, reducing the number of read counters, thus reducing the memory space used to maintain the read counters and freeing up memory space for other data. By using a matrix to estimate the read count for each block-die combination, embodiments of this disclosure maintain a single 32-bit counter for the total read counter, a 16-bit counter for the number of dies in the memory device, and a 16-bit counter for the number of blocks per die in the memory device. This significantly reduces the amount of memory space consumed by the read counters. Furthermore, Quality of Service (QoS) is improved by reducing the number of data integrity scans performed on at-risk pages and by using a memory subsystem controller with enhanced direct memory access (DMA) capabilities. DMA efficiently transfers counter values ​​from one memory region to another while bypassing processing devices (e.g., the CPU) in the memory subsystem. Coupled with the ALU characteristics of DMA, this reduces the processor workload required to implement matrix read interference schemes, thereby improving overall system QoS.

[0028] Figure 1 This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0029] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0030] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., computer contained in a vehicle, industrial equipment or networked commercially available device), or such computing device that includes memory and processing power.

[0031] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, and magnetic connections.

[0032] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and to read data from memory subsystem 110.

[0033] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)). The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance by combining stackable cross-grid data access arrays. Furthermore, compared to many flash-based memories, crosspoint non-volatile memories can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND-type flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0038] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware, such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0039] The memory subsystem controller 115 may include processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0040] In some embodiments, local memory 119 may include memory registers storing memory pointers, acquired data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or a processor or controller separate from the memory subsystem).

[0041] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0042] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local media controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] Memory subsystem 110 includes a matrix read interference component 113, which can populate a read interference matrix with estimated read values ​​of block-to-die combinations and identify behavioral problems in block-to-die combinations to be scanned. In some embodiments, memory subsystem controller 115 includes at least a portion of matrix read interference component 113. In some embodiments, matrix read interference component 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of matrix read interference component 113 and is configured to perform the functionality described herein.

[0045] The matrix read interference component 113 can maintain multiple read counters. The read counters may include a total read counter for the memory device, a die read counter for each die associated with the memory device, and multiple block read counters, wherein the number of block read counters is equal to the number of blocks for each die associated with the memory device.

[0046] For each detected page read event (e.g., a read operation), the matrix read interference component 113 increments the total read counter, as well as the die read counter and block read counter associated with the specified block of the page read event. The read operation may contain a logical block address storing data to be read. The matrix read interference component 113 translates the logical block address into a physical block address. The physical block address may be defined by the intersection of word lines and bit lines, and may specify the physical block number and physical die number storing the data to be read. The matrix read interference component 113 increments the die read counter for the physical die number specified by the physical block address, and also increments the block read counter for the physical block number specified by the physical block address. For example, if the detected read operation will read data stored at die number 253 and block number 1,104, then the matrix read interference component 113 increments the die read counter number 253, the block read counter number 1,104, and the total read counter.

[0047] The matrix read interference component 113 can use a counter to populate the read interference matrix. Values ​​in the read interference matrix represent an estimate of the number of read events received for each block. Read interference matrix values ​​can be stored in non-volatile memory (e.g., memory device 130). The matrix read interference component 113 can identify read interference matrix values ​​that satisfy predefined criteria (e.g., satisfying and / or exceeding a threshold limit). The matrix read interference component 113 identifies blocks (using block-die combinations in the matrix) whose associated read matrix values ​​satisfy the criteria and can perform media management operations on one or more pages associated with the identified blocks. The media management operations may include performing a scan of one or more pages associated with the identified blocks to determine the error rate of one or more pages. If the identified block contains one or more pages with an error rate exceeding an error threshold limit (i.e., a scan failure), the matrix read interference component 113 can refresh the block by repositioning the data stored at the block-die combination.

[0048] In this implementation, the memory subsystem controller 115 may be enhanced with direct memory access (DMA) capabilities. The matrix read-mapping component 113 may utilize DMA capabilities to efficiently transfer data from one memory region to another (e.g., transferring counter values ​​within volatile memory, and / or transferring matrix values ​​between volatile and non-volatile memory). Furthermore, the matrix read-mapping component 113 may utilize the ALU component of the DMA-enhanced memory subsystem controller to efficiently compute read matrix values. Further details regarding the operation of the matrix read-mapping component 113 are described below.

[0049] Figure 2This section describes an example workflow of a matrix read interference component 113 with enhanced direct memory access (DMA) capability according to some embodiments of the present disclosure. The matrix read component 113 may maintain a matrix of estimated number of read events for each memory device in the memory subsystem. The matrix read component 113 may maintain a read counter 210 in tightly coupled memory (TCM). The counter 210 may include a total read counter 212, which increments in response to each read page event detected by the memory device. A die counter 214 may include a plurality of die counters. The number of die counters is related to the number of dies stored on the memory device. For example, for a memory subsystem having dies ranging from 8 to 256, the total number of die counters stored in the die counter 214 will be 256. A block counter 216 may include a plurality of block counters. The number of block counters is related to the number of blocks per die. For example, for a memory subsystem storing 1,352 blocks per die, the block counter 216 may store 1,352 block counters. In this example, counter 210 may maintain one total read counter (RC) 212, 256 die read counters (DC) 214, and 1,352 block read counters (BC) 216. In some implementations, the total read counter (RC) 212 may be a 32-bit counter, and the die read counters (DC) 214 and the block read counters (BC) 216 may be 16-bit counters. In response to the detection of a page read event, each associated counter increments by a specified value (e.g., increments by 1); that is, the total read counter, the die read counter associated with the block specified in the page read event, and the block read counter associated with the block specified in the page read event each increment in response to the detection of a page read event.

[0050] The matrix read interference component 113 can transfer the read counter value from counter 210 from the TCM to another area of ​​volatile memory, such as DRAM buffer 220. The counter value can be transferred from the TCM to the DRAM buffer after garbage collection, once the read counter reaches its maximum value after a predetermined time period and / or at another time. When the counter value is transferred from the TCM to the DRAM buffer, the counter value in counter 210 is reset. In an embodiment, the TCM counter can be preloaded with a reset value. The following section discusses... Figure 3 Describe additional details regarding the preloaded values.

[0051] Once the matrix readout interference component 113 transfers the value of counter 210 to the DRAM temporary storage 220, the matrix readout interference component 113 calculates the matrix readout value 224. For example... Figure 2 As shown, this can be achieved by allocating a share of read events occurring for a specific die. Multiplied by the share of read events occurring for a specific block And multiply the result by the total read count value. The matrix read value is calculated to be 224. That is, for the block-die combination MN, the matrix read value is... ,in This represents the die counter value of die N. Here, RC represents the block counter value of block M, and RC represents the total read counter value. In the implementation, the matrix read interference component 113 can calculate the matrix read value 224 by multiplying the die counter value by the block counter value and then dividing by the total read counter value, i.e., .

[0052] Matrix read-and-hold component 113 can transfer matrix read values ​​224 to another area of ​​volatile memory, such as DRAM storage 230. Add-hold-and-hold component 232 can add the matrix read value 224 received from DRAM storage 220 to an existing matrix read value in DRAM storage 230. The matrix value in add-hold-and-hold 232 can be transferred to non-volatile memory 240 after a memory subsystem power-off event and optionally at predetermined time intervals. After a memory subsystem power-on event, the matrix read value stored in non-volatile memory 240 can be transferred to DRAM storage 230. Matrix read-and-hold component 113 can perform read-and-hold operations based on the matrix read values ​​stored in DRAM storage 230. The read-and-hold operation includes media management of the risk page. For example, a read interference operation may include performing a data integrity scan on risky pages (i.e., pages associated with block-die combinations having matrix read values ​​exceeding a certain threshold) and relocating data stored on blocks that fail the data integrity scan (i.e., blocks where the error rate of one or more risky pages is higher than a certain threshold error rate value).

[0053] The workflow of the matrix read interference component 113 can be enhanced using a memory subsystem controller with direct memory access (DMA) capability. The memory subsystem controller with enhanced DMA capability can efficiently transfer matrix read values ​​224 from DRAM buffer 220 to DRAM store 230 and between DRAM store 230 and non-volatile memory 240. Furthermore, the memory subsystem controller with enhanced DMA capability can perform certain ALU operations. Specifically, the memory subsystem controller with enhanced DMA capability can calculate the matrix read value 224 in DRAM buffer 220 by performing the arithmetic calculations described above. Additionally, the memory subsystem controller with enhanced DMA capability can perform an add-hold and store 232 feature by adding the matrix read value 224 to the matrix value in DRAM store 230. The memory subsystem controller with enhanced DMA capability can also perform read interference operations, i.e., comparing the read matrix value with a read value threshold limit to determine whether to perform a data integrity scan. Additionally, the memory subsystem controller with enhanced DMA capabilities can transfer matrix values ​​stored in non-volatile memory 240 to DRAM storage 230, and can preload counter values ​​in DRAM buffer 220. All these functions reduce processor workload and improve overall system service quality when performed by the memory subsystem controller with enhanced DMA capabilities.

[0054] Figure 3 This is a flowchart illustrating an example method 300 for reading an interference matrix according to some embodiments of the present disclosure. Method 300 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 300 is performed by… Figure 1 The matrix reading interference component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0055] At operation 310, the processing logic maintains a plurality of die read counters. Each of the plurality of die read counters may be associated with a corresponding die of the memory device. At operation 320, the processing logic maintains a plurality of block read counters. The number of block read counters may be equal to the number of blocks of each die associated with the memory device. For example, for a memory device having 256 dies and each die having 1,352 blocks, the processing logic maintains 256 die read counters and 1,352 block read counters. In an embodiment, the die read counters and block read counters are 16-bit counters.

[0056] At operation 330, the processing logic maintains a total read counter associated with the memory device. In this implementation, the total read counter is a 32-bit counter. The total read counter, die read counter, and block read counter can be maintained in tightly coupled memory.

[0057] The processing logic can detect page read events, such as read operations from the host system. A page read event may contain a logical block address. The processing logic can, for example, use a logical-to-physical (L2P) mapping data structure (e.g., an L2P table) to translate the logical block address into a physical block address. The physical block address may specify the physical block from which data is to be read and the raw die. The processing logic can identify the block read counter associated with the block at the physical block address and the raw die read counter associated with the raw die at the physical block address. In response to receiving a page read event, the processing logic may increment the identified block read counter by a specified value (e.g., increment by one), increment the identified raw die read counter by a specified value (e.g., increment by one), and increment the total read counter by a specified value (e.g., increment by one).

[0058] At operation 340, the processing logic determines the value of the block read counter and the value of the die read counter for a specified block of the memory device.

[0059] At operation 350, the processing logic determines an estimated number of read events associated with a specified block of the memory device based on the values ​​of the block read counter, the die read counter, and the total read counter. To determine the estimated number of read events associated with the specified block, the processing logic multiplies the die read counter value by the block read counter value and divides it by the total read counter value. The matrix read value is rounded to the nearest integer.

[0060] In an embodiment, the processing logic may transfer the values ​​of the total read counter, the block read counter, and the die read counter from the TCM to a temporary storage area of ​​the volatile memory device. The processing logic may then determine an estimated number of read events in the temporary storage area of ​​the volatile memory device and may store the estimated number of read events in the volatile memory device. The processing logic may add the newly determined estimated number of read events to the estimated number of read events stored in the volatile memory device. In response to the processing logic detecting a power-off event in the memory device, the processing logic may transfer the estimated number of read events to a non-volatile memory device. Alternatively, the processing logic may transfer the estimated number of read events to the non-volatile memory device at predetermined time intervals or in response to another event.

[0061] At operation 360, in response to determining that the estimated number of read events associated with a specified block meets a predefined criterion, the processing logic performs a media management operation on one or more pages associated with the specified block of the memory device. The predefined criterion may be a read value threshold limit, such that the processing logic performs a media management operation on one or more pages associated with a specified block where the estimated number of read events exceeds the read value threshold limit. In some embodiments, the media management operation may be a scan of one or more pages associated with the specified block to determine the error rate of one or more pages. The scan may be a data integrity check to verify that the data stored at one or more pages associated with the specified block does not contain errors exceeding the error threshold criterion. For example, the scan may determine the raw bit error rate (RBER) of one or more pages associated with the specified block, and the error threshold criterion may be an RBER limit.

[0062] In an embodiment, in response to an estimated number of read events determined for each block of the memory device, the processing logic may reset the total read counter, the plurality of die read counters, and the plurality of block read counters. After resetting the counters and / or before starting the counters, the processing logic may preload the counters with a specified value. In some embodiments, the processing logic may add preloaded counts within a specified range. Some read workloads may be performed in such a manner that most read interference counters reach read value threshold limits simultaneously or approximately simultaneously. This phenomenon is sometimes referred to as a read interference scan storm and can adversely affect the performance of the memory subsystem. To avoid read interference scan storms, the processing logic may offset the counters with various preloaded read values. The offset values ​​may be random values ​​within a predefined range or may be incremented. For example, the processing logic may preload a first die read counter with a value of 100 and increment the offset value for each subsequent die read counter. The processing logic may similarly preload block read counters with offset values ​​within a predefined range. The processing logic may preload the total read counter to match the offset values ​​added to the die counters and block counters.

[0063] In an embodiment, the processing logic may preload counter values ​​to account for any inaccuracies in the estimated number of read events in the matrix. Using a matrix to estimate the number of read events for each block-die combination, rather than having a dedicated counter for each block in the memory device, may produce read counts that are less accurate than conventional read counts. The processing logic may apply a 6-sigma random read offset. In an embodiment, a finite 6-sigma read offset may be in the range of 250 to 500 counts. This preloaded count allows the processing logic to scan blocks at or below a read value threshold limit, and avoids situations where the actual read count is higher than the read value threshold limit. The processing logic may add a first preloaded count to the total read counter, add a first preloaded count set to the die read counter, and add a second preloaded count set to the block read counter. Each preloaded count in the first preloaded count set is added to one of the die read counters, and each preloaded count in the second preloaded count set is added to one of the block read counters.

[0064] In an embodiment, asynchronous power loss events can cause the loss of current read counts. Therefore, in response to detecting an asynchronous power loss event, the processing logic can preload counters to compensate for the risk of losing a currently estimated number of read events. The processing logic can add a first preload count to the total read counter and a second preload count to each of a plurality of block read counters. In an embodiment, the processing logic can add a third preload count to each of a plurality of die read counters. To avoid losing current block read counts, these preload count values ​​can be relatively high. For example, the preload count added to the total read counter can be 50,000, and the preload count added to each block read counter can be a fraction of 50,000. In another instance, the preload count added to each block read counter can be 50,000, and the preload count added to the total read counter can be 50,000 multiplied by the number of blocks.

[0065] In response to determining that the error rate of one or more pages meets the error threshold criterion (i.e., the scan fails because the error rate of one or more pages exceeds the error threshold limit), the processing logic relocates the data stored in the specified block to another block.

[0066] On the other hand, in response to determining that the error rate of each of one or more pages does not meet the error threshold criterion (i.e., the scan passes because the error rate of each scanned page does not exceed the error threshold limit), the processing logic will retain the data stored at the specified block. However, there is a high probability that at least one of the one or more pages associated with the specified block is close to failure. To ensure timely capture of failures, the processing logic may add a preload count to each counter associated with the specified block after the scan passes. Thus, the processing logic may add a first preload count to the total read counter, a second preload count to the die read counter associated with the specified block, and a third preload count to the block read counter associated with the specified block. The first preload count added to the total read counter should be equal to the second preload count plus the third preload count. The preload count may be a specified share of the criterion, such as 25%, 50%, or 75% of the read value threshold limit. This added preload count may result in an additional number of read counts on the weakened block being reduced.

[0067] Figure 4 This is a flowchart illustrating an example method 400 for reading an interference matrix using a controller with DMA capability, according to some embodiments of this disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 400 is performed by… Figure 1 The matrix reading interference component 113 is executed. Although shown in a specific order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0068] At operation 410, the processing logic receives one or more block read counter values, one or more die read counter values, and a total read counter value from the memory device.

[0069] At operation 420, the processing logic determines a plurality of estimated numbers of read events. Each estimated number of read events is associated with a block of the memory device and is based on one of the block read counter values ​​(i.e., the block read counter value associated with the block), one of the die read counter values ​​(i.e., the die read counter value associated with the block), and the total read counter value.

[0070] To determine the estimated number of read events, for each specified block, the processing logic multiplies the block read counter value of the specified block by the die read counter value of the specified block and divides it by the total read counter value. The matrix read value is rounded to the nearest integer.

[0071] In an embodiment, the processing logic receives an existing estimated number of read events stored in non-volatile memory. The processing logic may add the plurality of estimated numbers of read events to the existing estimated number of read events to determine an updated summed estimated number of read events. The processing logic may periodically (e.g., at a predetermined schedule, such as every hour) or in response to a determined event, such as a power outage event of the memory subsystem, transmit the summed estimated number of read events to the non-volatile memory device.

[0072] At operation 430, the processing logic identifies one or more blocks whose associated estimated number of read events satisfies a predefined criterion. The predefined criterion may be a read value threshold limit, such that the processing logic identifies blocks whose associated estimated number of read events satisfies and / or exceeds the read value threshold limit.

[0073] At operation 440, the processing logic performs a media management operation on one or more pages associated with each identified block for which the estimated number of read events meets predefined criteria. Performing the media management operation may include performing a scan of the one or more pages associated with each identified block for which the estimated number of read events meets predefined criteria to determine the error rate of the one or more pages. The scan may be a data integrity check to verify that the data stored at the one or more pages associated with the block does not contain errors exceeding an error threshold criterion. For example, the scan may determine the raw bit error rate (RBER) of the one or more pages associated with the block-die combination, and the error threshold criterion may be the RBER limit.

[0074] In an embodiment, in response to determining that the error rate of the one or more pages meets the error threshold criterion (i.e., the scan fails because the error rate of the one or more pages exceeds the error threshold limit), the processing logic relocates the data stored at the identified block to another block-die combination.

[0075] On the other hand, in response to determining that the error rate of each of one or more pages does not meet the error threshold criterion (i.e., the scan passes because the error rate of each scanned page does not exceed the error threshold limit), the processing logic will retain the data stored at the block. However, there is a high probability that at least one of the one or more pages associated with the identified block is close to a fault. To ensure timely fault capture, the processing logic may add a preload count to each counter associated with the identified block after the scan passes. Thus, the processing logic may add a first preload count to the total read counter, a second preload count to the die read counter associated with the identified block, and a third preload count to the block read counter associated with the identified block. The first preload count added to the total read counter should be equal to the second preload count plus the third preload count. The preload count may be a specified share of the criteria, such as 25%, 50%, or 75% of the read value threshold limit. This added preload count may result in an additional number of read counts on the weakened block being reduced.

[0076] In embodiments, the processing logic can preload counters with specified values. In some implementations, the processing logic can add preloaded counts within a specified range. Some read workloads can be performed such that most read interference counters reach their read value threshold limits simultaneously or approximately simultaneously. This phenomenon is sometimes referred to as a read interference scan storm and can adversely affect the performance of the memory subsystem. To avoid read interference scan storms, the processing logic can offset the counters with various preloaded read values. The offset values ​​can be random values ​​within a predefined range or can be incremented. For example, the processing logic can preload a first die read counter with a value of 100 and increment the offset value for each subsequent die read counter. The processing logic can similarly preload block read counters with offset values ​​within a predefined range. The processing logic can preload the total read counter to match the offset values ​​added to the die counter and block counter.

[0077] In an embodiment, the processing logic may preload counter values ​​to account for any inaccuracies in the estimated number of read events in the matrix. Using a matrix to estimate the number of read events for each block-die combination, rather than having a dedicated counter for each block in the memory device, may produce read counts that are less accurate than conventional read counts. The processing logic may apply a 6-sigma random read offset. In an embodiment, a finite 6-sigma read offset may be in the range of 250 to 500 counts. This preloading allows the processing logic to scan blocks at or below a read value threshold limit and avoids situations where the actual read count is higher than the read value threshold limit. The processing logic may add a first preloaded count to the total read counter, add a first preloaded count set to the die read counter, and add a second preloaded count set to the block read counter. Each preloaded count in the first preloaded count set is added to one of the die read counters, and each preloaded count in the second preloaded count set is added to one of the block read counters.

[0078] In an embodiment, asynchronous power loss events can cause the loss of current read counts. Therefore, in response to detecting an asynchronous power loss event, the processing logic can preload counters to compensate for the risk of losing a currently estimated number of read events. The processing logic can add a first preload count to the total read counter and a second preload count to each of a plurality of block read counters. In an embodiment, the processing logic can add a third preload count to each of a plurality of die read counters. To avoid losing current block read counts, these preload count values ​​can be relatively high. For example, the preload count added to the total read counter can be 50,000, and the preload count added to each block read counter can be a fraction of 50,000. In another instance, the preload count added to each block read counter can be 50,000, and the preload count added to the total read counter can be 50,000 multiplied by the number of blocks.

[0079] Figure 5 This describes an example arrangement of memory devices and corresponding read counters within a memory subsystem according to some embodiments of the present disclosure. Generally, the memory subsystem 500 may correspond to... Figure 1 The memory subsystem 110. In some instances, such as Figure 1 The matrix readout interference component 113 described herein is an executable reference. Figure 5 The described operation.

[0080] exist Figure 5In the example architecture, the memory device in the memory subsystem 500 has three dies (die-1510, die-2520, and die-3530). Each die has six blocks. For example, die-1510 has blocks-1511, block-2512, block-3513, block-4514, block-5515, and block-6516. Each block may contain multiple pages. It should be noted that, for ease of explanation, Figure 5 The example architecture is presented in a very simplified manner, and the memory device can have more dies and each die can have more blocks.

[0081] In the implementation, the memory subsystem detects page read events (i.e., read requests from the host system). Page read events may be associated with logical block addresses. For example, a read request may contain a logical block address. The memory subsystem controller may translate the logical block address into a physical block address. The physical block address may contain the block number storing the data to be read and the die number.

[0082] like Figure 5 As described, the memory subsystem controller detects page read events 540, 541, 542, and 543. Page read event 540 contains a logical block address, which, upon translation to a physical block address, directs the memory subsystem controller to read the memory page stored in block-1 511 of die-1 510. Page read event 541 contains a logical block address, which, upon translation to a physical block address, directs the memory subsystem controller to read the memory page stored in block-4 524 of die-2 520. Page read event 542 contains a logical block address, which, upon translation to a physical block address, directs the memory subsystem controller to read the memory page stored in block-5 535 of die-3 530. Page read event 543 contains a logical block address, which, upon translation to a physical block address, directs the memory subsystem controller to read the memory page stored in block-5 525 of die-2 520.

[0083] The memory subsystem controller can identify the read counter associated with each page read event and increment the associated counter. Specifically, in response to detecting a page read event 540, the memory subsystem controller can identify the die counter (DC 554) associated with die number 1 (die number 553) and the block counter (BC 559) associated with block number 1 (block number 560). In response to detecting a page read event 541, the memory subsystem controller can identify the die counter (DC 554) associated with die number 2 (die number 553) and the block counter (BC 559) associated with block number 4 (block number 560). In response to detecting a page read event 542, the memory subsystem controller can identify the die counter (DC 554) associated with die number 3 (die number 554) and the block counter (BC 559) associated with block number 5 (block number 560). In response to the detection of a page read event 543, the memory subsystem controller can identify the die counter (DC 554) associated with die number 2 (die number 554) and the block counter (BC 559) associated with block number 5 (block number 560).

[0084] The memory subsystem controller can increment a counter for each die in matrix 550 in response to detecting each page read event. For example... Figure 5 As shown, the die counter (DC 554) associated with die number 1 (die number 553) displays a total count of 1; the die counter (DC 554) associated with die number 2 (die number 553) displays a total count of 2; and the die counter (DC 554) associated with die number 3 (die number 553) displays a total count of 1. In addition, the block counter (BC 559) associated with block number 1 (block number 560) shows a total count of 1; the block counter (BC 559) associated with block number 2 (block number 560) shows a total count of 0; the block counter (BC 559) associated with block number 3 (block number 560) shows a total count of 0; the block counter (BC 559) associated with block number 4 (block number 560) shows a total count of 1; the block counter (BC 559) associated with block number 5 (block number 560) shows a total count of 2; and the block counter (BC 559) associated with block number 6 (block number 560) shows a total count of 0. The read counter (RC 552) shows a total of 4 read page events received.

[0085] Figure 6A This describes an example of the first step in determining the estimated number of matrix read values ​​representing read events according to an embodiment of the present disclosure. Figure 6A In the matrix 600, the share of readings received for each block-to-die combination is represented. For example... Figure 6AAs shown, the read interference matrix maintains a total read count RC 602; the total read count is 1000. The read interference matrix maintains a die counter for each die in the memory device. The die number is shown in column 603, and the die counter is shown in column 604. Figure 6A In the example described, there are 9 dies in the memory device; this is merely illustrative, and there may be fewer or more dies in the memory device. Column 606 shows the share of readings received for each die, i.e., the die counter value divided by the total read counter value.

[0086] The read interference matrix also maintains a block counter for the number of blocks per die in the memory device. Figure 6A In the example illustrated, each die contains 13 blocks. This is merely illustrative, and each die in a memory device may contain fewer or more blocks. Line 610 shows the block numbers, and line 609 shows the block counter used for each block number. Line 608 shows the share of readings received for each block number, i.e., the value of each block counter divided by the total read counter value.

[0087] Matrix 600 is populated by multiplying the share of readings received for a specific die by the share of readings received for a specific block number. For example, the matrix value of the block stored at die-6 of block-5 is 10% multiplied by 12%, which is 0.01200. As another example, the matrix value of the block stored at die-7 of block-4 is 7% multiplied by 2%, which is 0.00140.

[0088] Figure 6B This describes an example of reading the interference matrix 650 according to embodiments of this disclosure. By using data from... Figure 6A The value of matrix 600 is multiplied by the total read count value 652 and rounded to the nearest integer to generate read interference matrix 650. For example, for a block represented by block-die combination block-5 and die-6, Figure 6A The value in matrix 600 described is 0.01200. The total read count RC 652 is 1,000. Therefore, the matrix read value for block-die combination block-5 and die-6 is 0.01200 × 1,000 = 12. As another example, the matrix 600 value for block-die combination block-4 and die-7 is 0.00140. This value multiplied by the total read count is 0.00140 * 1,000 = 1.4, rounded to the nearest integer 1. Therefore, the read interference matrix 650 value for block-die combination block-4 and die-7 is 1. The matrix read values ​​stored in matrix 650 represent the estimated number of read events associated with each block of the memory device.

[0089] Matrix readout interference components (e.g., from) Figure 1The matrix readout interference component 113) identifies blocks in matrix 650 whose matrix readout values ​​satisfy and / or exceed predefined criteria, such as a readout value threshold limit (i.e., block-die combinations in the matrix). For example, if the readout value threshold limit is set to 50, the matrix readout interference component may identify block-die combinations Block-8 Die-3 and Block-8 Die-4 in matrix 650 as satisfying and / or exceeding the readout value threshold limit. The matrix readout interference component may then scan the pages associated with the identified blocks (Block-8 Die-3 and Block-8 Die-4) to determine the page error rate, and may refresh the blocks having one or more pages with an error rate exceeding the error rate threshold.

[0090] Figure 7 This describes an instance machine of computer system 700, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110, or may be used to perform controller operations (e.g., execute an operating system to perform operations corresponding to...). Figure 1 (Operation of matrix readout interference component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer-to-peer (or distributed) network machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, operating at the capacity of a server or client machine in a client-server network environment.

[0091] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0092] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0093] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0094] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0095] In one embodiment, instruction 726 includes instructions for implementing a matrix readout interference component (e.g., Figure 1 The matrix readout interference component 113) contains functional instructions. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0096] Some parts of the previously described algorithms and symbolic representations of operations on data bits within computer memory have been presented. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. In this paper, and generally in general, algorithms are conceived as self-consistent sequences of operations that produce desired results. An operation is an operation that requires physical manipulation of a physical quantity. Typically (but not always), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that it is sometimes convenient to refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for common use.

[0097] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient notations for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities in the registers and memories of a computer system into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage systems.

[0098] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for the desired purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0099] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods described herein. The structures of various such systems will be presented as set forth in the description below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0100] This disclosure may be provided as a computer program product or software, which may include machine-readable media on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable storage media such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0101] In the foregoing description, embodiments of this disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for performing memory operations, comprising: maintaining, by a processing device, a plurality of die read counters, wherein each die read counter of the plurality of die read counters is associated with a respective die of a memory device; maintaining a plurality of bank read counters; maintaining a total read counter associated with the memory device; determining, for a specified bank of the memory device, a value of a bank read counter and a value of a die read counter; determining, based on the value of the bank read counter, the value of the die read counter, and a value of the total read counter, an estimated number of read events associated with the specified bank of the memory device; and in response to determining that the estimated number of read events satisfies a predefined criterion, performing a media management operation for one or more pages associated with the specified bank of the memory device, wherein the media management operation comprises a scan of the one or more pages associated with the specified bank to determine an error rate of the one or more pages.

2. The method of claim 1, wherein a number of the plurality of bank read counters is equal to a number of banks per die associated with the memory device.

3. The method of claim 1, wherein determining the estimated number of read events associated with the specified bank of the memory device comprises multiplying the value of the bank read counter by the value of the die read counter and dividing by the value of the total read counter.

4. The method of claim 1, further comprising: detecting a read page event associated with a logical block address; converting the logical block address to a physical block address, wherein the physical block address identifies a bank and a die; identifying a bank read counter of the plurality of bank read counters associated with the bank; identifying a die read counter of the plurality of die read counters associated with the die; and incrementing the identified bank read counter, the identified die read counter, and the total read counter.

5. The method of claim 1, further comprising: in response to detecting a power down event of the memory device, transmitting the estimated number of read events associated with the specified bank to a non-volatile memory device.

6. The method of claim 1, wherein performing the media management operation for the one or more pages associated with the specified bank of the memory device comprises: performing the scan of the one or more pages associated with the specified bank; determining, based on the scan, the error rate of the one or more pages associated with the specified bank; in response to determining that the error rate of one of the one or more pages satisfies an error threshold criterion, relocating data stored at the specified bank to another bank; and in response to determining that the error rate of each of the one or more pages does not satisfy the error threshold criterion, adding a first preload count to the total read counter, adding a second preload count to the die read counter associated with the specified block, and adding a third preload count to the block read counter associated with the specified block, wherein each preload count is a specified share of the criterion.

7. The method of claim 1, further comprising: adding a first preload count to the total read counter; adding a first set of preload counts to the plurality of die read counters, wherein each preload count of the first set of preload counts is added to one of the die read counters of the plurality of die read counters; and adding a second set of preload counts to the plurality of block read counters, wherein each preload count of the second set of preload counts is added to one of the block read counters of the plurality of block read counters, wherein each preload count is within a specified range.

8. The method of claim 1, further comprising: in response to detecting an asynchronous power loss event, adding a first preload count to the total read counter and adding a second preload count to each block read counter of the plurality of block read counters.

9. A memory system, comprising: a plurality of memory devices; a processing device operably coupled with the plurality of memory devices; and a direct memory access (DMA) controller operably coupled with the plurality of memory devices to perform operations comprising: receiving, from one or more memory devices of the plurality of memory devices, one or more block read counter values, one or more die read counter values, and a total read counter value; determining a plurality of estimated numbers of read events, wherein each estimated number of read events is associated with a block of the memory devices and is based on one of the block read counter values, one of the die read counter values, and the total read counter value; identifying one or more blocks for which an associated estimated number of read events satisfies a predefined criterion; and performing media management operations for one or more pages associated with each identified block for which the associated estimated number of read events satisfies the predefined criterion, wherein performing the media management operations comprises performing a scan of the one or more pages associated with each identified block for which the associated estimated number of read events satisfies the predefined criterion to determine an error rate of the one or more pages.

10. The memory system of claim 9, wherein determining the plurality of estimated numbers of read events comprises, for each specified block, multiplying the block read counter value of the specified block by the die read counter value of the specified block and dividing by the total read counter value.

11. The memory system of claim 9, further comprising: receiving, from a non-volatile memory device, existing estimated numbers of read events; ​ ​ determining an added read event by adding the plurality of estimated numbers of read events to the existing estimated number of read events; and transmitting the added read event to the non-volatile memory device.

12. The memory system of claim 9, wherein performing the media management operation comprises: performing the scan of the one or more pages associated with each identified block for which the associated estimated number of read events satisfies the predefined criteria; determining the error rate of the one or more pages based on the scan; relocating data stored at the identified block to another block in response to determining that the error rate of one of the one or more pages satisfies an error threshold criterion; and adding a first preload count to the total read counter, adding a second preload count to the die read counter associated with the identified block, and adding a third preload count to the block read counter associated with the identified block in response to determining that the error rate of each of the one or more pages does not satisfy the error threshold criterion, wherein each preload count is a specified share of the criteria.

13. The memory system of claim 9, further comprising: adding a first preload count to the total read counter value; adding a first set of preload counts to the die read counter values, wherein each preload count of the first set of preload counts is added to one of the die read counter values; and adding a second set of preload counts to block read counter values, wherein each preload count of the second set of preload counts is added to one of the block read counter values, wherein each preload count is within a specified range.

14. The memory system of claim 9, further comprising: adding a first preload count to the total read counter value and a second preload count to each block read counter value in response to determining an asynchronous power loss event.

15. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: maintaining a plurality of die read counters, wherein each die read counter of the plurality of die read counters is associated with a respective die of a memory device; maintaining a plurality of block read counters; maintaining a total read counter associated with the memory device; determining a value of a block read counter and a value of a die read counter for a specified block of the memory device; based on the value of the block read counter, the value of the die read counter, and a value of the total read counter, determining an estimated number of read events associated with the specified block of the memory device; and in response to determining that the estimated number of read events satisfies a predefined criterion, performing a media management operation of one or more pages associated with the specified block of the memory device, wherein the media management operation comprises a scan of the one or more pages associated with the specified block to determine an error rate of the one or more pages.

16. The non-transitory computer-readable storage medium of claim 15, wherein a number of the plurality of block read counters is equal to a number of blocks per die associated with the memory device.

17. The non-transitory computer-readable storage medium of claim 15, wherein determining the estimated number of read events associated with the specified block of the memory device comprises multiplying the value of the block read counter by the value of the die read counter and dividing by the value of a total read counter.

18. The non-transitory computer-readable storage medium of claim 15, further comprising: detecting a read page event associated with a logical block address; converting the logical block address to a physical block address, wherein the physical block address identifies a block and a die; identifying a block read counter of the plurality of block read counters associated with the block; identifying a die read counter of the plurality of die read counters associated with the die; and incrementing the identified block read counter, the identified die read counter, and the total read counter.

19. The non-transitory computer-readable storage medium of claim 15, further comprising: determining the error rate of the one or more pages associated with the specified block; in response to determining that the error rate of one of the one or more pages satisfies an error threshold criterion, relocating data stored at the specified block to another block; and in response to determining that the error rate of each of the one or more pages does not satisfy the error threshold criterion, adding a first preload count to the total read counter, adding a second preload count to the die read counter associated with the specified block, and adding a third preload count to the block read counter associated with the specified block, wherein each preload count is a specified share of the criterion.

20. The non-transitory computer-readable storage medium of claim 15, further comprising: adding a first preload count to the total read counter; adding a first set of preload counts to the plurality of die read counters, wherein each preload count of the first set of preload counts is added to one of the die read counters of the plurality of die read counters; and adding a second set of preload counts to the plurality of block read counters, wherein each preload count of the second set of preload counts is added to one of the block read counters of the plurality of block read counters, wherein each preload count is within a specified range.

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