Chip testing method and device thereof, computer equipment and readable storage medium thereof

Abstract

The application relates to a chip testing method and device, computer equipment and readable storage medium thereof. The chip testing method comprises the following steps: applying a test signal to a to-be-tested chip; sending a data signal to the to-be-tested chip; the to-be-tested chip enters a test mode based on the test signal and the data signal, and test voltage adjustment is performed on the to-be-tested chip. According to the chip testing method provided by the application, each to-be-tested chip enters the test mode only by the test signal and the data signal, so that the data signal information of the to-be-tested chip can be utilized to realize independent control of the test mode of the to-be-tested chip, and then independent control of the test voltage of the to-be-tested chip is realized. In this way, the test voltage can be more accurately adjusted, and the reliability level of chip testing is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip testing method and apparatus, a computer device and a readable storage medium thereof. Background Technology

[0002] Semiconductor device testing involves measuring electrical parameters on wafer-level integrated circuits to verify specification consistency and assess acceptable electrical performance. Wafer Level Burn-In (WLBI), as a measure of semiconductor device aging, plays a crucial role in reducing aging testing costs and achieving Known Good Die (KGD) during semiconductor device fabrication.

[0003] However, the conditions for each chip cannot be adjusted in wafer-level aging tests, resulting in a decline in test performance. Summary of the Invention

[0004] Therefore, it is necessary to provide a chip testing method and apparatus, a computer device and a readable storage medium.

[0005] To achieve the above objectives, this application provides a chip testing method, comprising:

[0006] Apply a test signal to the chip under test;

[0007] A data signal is sent to the chip under test (DUT), and the DUT enters a test mode based on the test signal and the data signal. The test voltage of the DUT is then adjusted.

[0008] In one embodiment, the chip under test is provided with test pins and data pins;

[0009] The chip under test receives the test signal through the test pin and the data signal through the data pin.

[0010] In one embodiment, applying a test signal to the chip under test includes:

[0011] The test signal is sent simultaneously to multiple chips under test; the multiple chips under test are located on the same wafer under test.

[0012] In one embodiment, the chip under test (DUT) is provided with a receiving module; the step of sending a data signal to the DUT, and the DUT entering a test mode based on the test signal and the data signal, includes:

[0013] The receiving module generates an internal test signal based on the test signal and the data signal; the chip under test enters the test mode based on the internal test signal.

[0014] In one embodiment, the receiving module includes an AND gate.

[0015] In one embodiment, the chip under test is provided with a test mode register;

[0016] When the chip under test (DUT) is configured in addressing mode, the step of sending a data signal to the DUT, and the DUT entering a test mode based on the test signal and the data signal, and adjusting the test voltage of the DUT includes:

[0017] The test mode register sets the chip under test to test mode according to the test signal;

[0018] The chip under test receives the data signal after a preset time period following receiving the test signal;

[0019] After the data signal is held for a preset latching time, the test voltage of the chip under test is adjusted according to the test command carried in the test signal.

[0020] In one embodiment, the test command includes a test voltage value;

[0021] The step of adjusting the test voltage of the chip under test according to the test command carried in the test signal includes:

[0022] The original voltage value of the chip under test is adjusted to the test voltage value according to the test command carried in the test signal.

[0023] In one embodiment, the chip under test has a voltage regulation circuit, which includes multiple load elements;

[0024] The step of adjusting the original voltage value of the chip under test to the test voltage value according to the test command carried in the test signal includes:

[0025] The chip under test adjusts the number of load elements connected to the voltage regulation circuit or adjusts the regulation frequency of the voltage regulation circuit according to the test voltage value.

[0026] In one embodiment, the preset time period includes the sum of additional delay time, write delay time, and parity check time.

[0027] In one embodiment, adjusting the test voltage of the chip under test according to the test command carried in the test signal includes:

[0028] Send a data strobe signal to the chip under test;

[0029] After a preset latching time is received, the data strobe signal triggers the data signal to become valid;

[0030] The test voltage of the chip under test is adjusted according to the test instructions carried in the test signal.

[0031] In one embodiment, the preset latching time is the time for transmitting half the burst length of the data strobe signal.

[0032] This application also provides a chip testing apparatus, including:

[0033] A test signal transmitting module, wherein the test signal generating module is used to apply a test signal to the chip under test;

[0034] A data signal transmission module is used to send a data signal to the chip under test, and the chip under test enters a test mode based on the test signal and the data signal.

[0035] A voltage regulation module is connected to the chip under test and is used to regulate the test voltage of the chip under test.

[0036] In one embodiment, the test signal transmitting module applies the test signal to the chip under test through the test pin of the chip under test;

[0037] The data signal transmission module sends the data signal to the chip under test through the data pin of the chip under test.

[0038] In one embodiment, the test signal transmitting module simultaneously transmits the test signal to multiple chips under test located on the same wafer under test.

[0039] In one embodiment, the test signal carries a test command;

[0040] The voltage regulation module adjusts the test voltage of the chip under test according to the test command.

[0041] In one embodiment, the test command includes a test voltage value;

[0042] The voltage adjustment module adjusts the original voltage value of the chip under test to the test voltage value according to the test command carried in the test signal.

[0043] In one embodiment, the chip under test has a voltage regulation circuit;

[0044] The voltage regulation module controls the chip under test to adjust the number of load elements connected to the voltage regulation circuit or adjust the regulation frequency of the voltage regulation circuit according to the test command carried in the test signal.

[0045] In one embodiment, the chip testing apparatus further includes a data strobe signal sending module, which is used to send a data strobe signal to the chip under test to trigger the data signal to be valid.

[0046] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program that can run on the processor, and the processor executes the program to implement the steps of the chip testing method provided in any of the above embodiments.

[0047] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the chip testing method provided in any of the above embodiments.

[0048] The chip testing method and apparatus, computer equipment, and readable storage medium of this application have at least the following beneficial effects:

[0049] The chip testing method provided in this application requires that each chip under test (DUT) be controlled by both a test signal and a data signal to enter the test mode. This allows for independent testing of each DUT using its data signal information, thereby enabling independent control of the test voltage. This allows for more precise adjustment of the test voltage and improves the reliability of chip testing.

[0050] The chip testing apparatus provided in this application sends data signals to the chip under test (DUT) via a data signal transmission module. These data signals, along with the test signals applied to the DUT by the test signal generation module, jointly control the DUT to enter the test mode. This allows for independent control of the DUT's entry into the test mode using its data signal information, thereby enabling independent control of the DUT's test voltage. This allows for more precise adjustment of the test voltage, improving the reliability of chip testing.

[0051] The computer device provided in this application can implement the steps of the chip testing method provided in any of the above embodiments. Therefore, the computer device can also achieve the technical effects that the aforementioned chip testing method can achieve, and will not be described in detail here.

[0052] The computer-readable storage medium provided in this application can implement the steps of the chip testing method provided in any of the above embodiments. Therefore, the computer-readable storage medium can also achieve the technical effects that the aforementioned chip testing method can achieve, and will not be described in detail here. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0054] Figure 1 This is a schematic diagram of a chip testing device.

[0055] Figure 2 A flowchart illustrating a chip testing method provided in one embodiment of this application;

[0056] Figure 3 In one embodiment of the chip testing method provided in this application, the timing diagram of the chip under test entering the test mode is jointly controlled by the test signal and the data signal;

[0057] Figure 4 A flowchart of step S2 in a chip testing method provided in one embodiment of this application;

[0058] Figure 5 A schematic diagram of a voltage regulation circuit in a chip testing method provided in one embodiment of this application;

[0059] Figure 6 A flowchart of step S23 in a chip testing method provided in one embodiment of this application;

[0060] Figure 7 A timing diagram of step S23 in a chip testing method provided in one embodiment of this application;

[0061] Figure 8 This is a schematic diagram of the structure of a chip testing device provided in one embodiment of this application.

[0062] Explanation of reference numerals in the attached figures:

[0063] 100. Chip under test; 101. Test signal transmission module; 102. Data signal transmission module; 103. Voltage regulation module; 104. Data strobe signal transmission module. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] It should be understood that when an element is referred to as "connected to," it may be directly connected to other elements, or there may be intervening elements. It should also be understood that, in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "below" or "under" or "beneath" of other elements will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "under" can include both upper and lower orientations. Furthermore, a device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0067] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0068] In WLBI testing of Dynamic Random Access Memory (DRAM), the power supply voltage of each chip under test (DUT) needs to be adjusted to a fixed value. Traditionally, the same test signal is used to uniformly adjust the test voltage of all DUTs on the same wafer.

[0069] Due to variations in manufacturing processes, the actual deviation between the power supply voltage and the target value varies for each chip under test (DUT), resulting in different applicable test voltage values ​​for each DUT. Please refer to [link / reference]. Figure 1In WLBI testing, due to the unique connection method, each chip under test (DUT) has only its data signal pins connected independently to the test instrument and controllable independently; all other pins are shared by all DUTs. This leads to a problem: when the test instrument sends a test signal containing test commands and a test voltage value, it actually controls all DUTs simultaneously, causing the test voltages of all DUTs to change together. This means that the test voltage of each DUT cannot be independently controlled, reducing the accuracy of test voltage adjustment and thus affecting the test results.

[0070] Please see Figure 2 To address the aforementioned problems, this application provides a chip testing method, which specifically includes the following steps:

[0071] S1: Apply a test signal to the chip under test.

[0072] S2: Send a data signal to the chip under test. The chip under test enters the test mode based on the test signal and the data signal, and the test voltage is adjusted for the chip under test.

[0073] The aforementioned chip testing method requires both test and data signals to enter test mode for each chip under test. This allows for independent control of the test mode and, consequently, the test voltage of the chip using its data signal information. This enables more precise adjustment of the test voltage and improves the reliability of chip testing.

[0074] As an example, the chip under test may include, but is not limited to, Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM).

[0075] This application does not impose specific limitations on the structure of the chip under test. In one embodiment, the chip under test is provided with test pins and data pins; the chip under test can receive test signals through the test pins and data signals through the data pins.

[0076] As used in this application, the terms "data pin" or "test pin" refer to a pin of the chip under test (DUT) defined by the DUT's specifications for exchanging data signals and test signals.

[0077] It should be understood that there can be multiple test pins and data pins on the chip under test. Any test pin can be selected to receive test signals according to actual operating requirements; similarly, any data pin can be selected to receive data signals according to actual operating requirements.

[0078] It should also be understood that test pins may include pins dedicated to performing debugging operations (e.g., TMSC pins or TCKC pins), or critical pins on the chip under test, such as clock pins, may be brought out and used as some test pins.

[0079] In one embodiment, multiple chips under test are located on the same wafer under test.

[0080] Based on the above embodiments, step S1 may include: simultaneously sending test signals to multiple chips under test located on the same wafer under test.

[0081] Taking chip A and chip B located on the same wafer under test as an example, since the test pins of each chip under test are simultaneously connected to the signal transmitting end of the test instrument, the test instrument will simultaneously send test signals to multiple chips under test (including chip A and chip B) located on the same wafer under test. Because in this application, the chip under test requires both test signals and data signals to enter the test mode, such as... Figure 3 As shown, the test signal will only be truly recognized and activated by either chip under test (DUT) a or chip under test (DUT b) when the data signal of either DUT a or DUT b is also at a high level. In this example, if it is necessary to adjust the test voltage of a certain DUT chip, it is only necessary to pull the data signals of the other DUT chips low.

[0082] A data signal is sent to the chip under test (DUT). The DUT enters the test mode based on the test signal and the data signal, and the test voltage is adjusted for the DUT.

[0083] This application does not specifically limit the method by which the chip under test enters the test mode based on the test signal and the data signal in step S2. The following describes the method of the chip under test entering the test mode in some possible embodiments of this application.

[0084] In one embodiment, the chip under test may be equipped with a receiving module.

[0085] Based on the above embodiments, step S2 may include: the receiving module generating an internal test signal based on the test signal and the data signal; the internal test signal is configured such that the chip under test can enter the test mode based on the internal test signal.

[0086] It should be noted that this application does not specifically limit the form of the receiving module. As an example, the receiving module may include, but is not limited to, an AND gate.

[0087] In one embodiment, the first receiving end of the receiving module is connected to the test pin to receive the test signal sent by the test pin; the second receiving end of the receiving module is connected to the data pin to receive the test signal sent by the test pin; the output end of the receiving module is connected to the test mode register inside the chip under test, and the test mode register configures the chip under test to enter the test mode according to the internal test signal output by the receiving module.

[0088] The following combination Figure 3 The embodiment of the receiving module including AND gates will be described in more detail. In this embodiment, the test mode is triggered when the data signal is at a high level.

[0089] An AND gate can include at least a first input, a second input, and an output. Taking chip under test (DUT) a as an example, the first input of the AND gate can be used to receive the test signal of the DUT, the second input of the AND gate can be used to receive the data signal of the DUT a, and the output of the AND gate can be used to output the internal test signal.

[0090] When a test signal is applied to the chip under test (DUT), the test signal is connected to the first input of the AND gate. When the data signal of the DUT is at a low level, a low level is connected to the second input of the AND gate. At this time, the output of the AND gate outputs a low level, and the DUT will not enter the test mode.

[0091] When the data signal of the chip under test (a) becomes high, the second input of the AND gate changes from low to high, and the chip under test (a) can enter the test mode.

[0092] It is understood that in this embodiment, a high-level data signal is a condition for effectively triggering the test mode; a low-level data signal is invalid. Furthermore, the duration the data signal remains high should be the same as the time required for the test mode to function.

[0093] In one embodiment, the chip under test may be configured with a test mode register.

[0094] Based on the above embodiments, please refer to Figure 4 When the chip under test is configured in addressing mode, step S2 may specifically include the following steps:

[0095] S21: The test mode register configures the chip under test to test mode according to the test signal.

[0096] S22: The chip under test receives the data signal after a preset time period of receiving the test signal.

[0097] S23: After the data signal is held for a preset latching time, the test voltage of the chip under test is adjusted according to the test instructions carried in the test signal.

[0098] The aforementioned chip testing method utilizes the addressing mode of the chip under test to achieve the purpose of testing each chip individually. As an example, the addressing modes involved in this application may include Per-DRAM Addressability (PDA) mode.

[0099] For step S21, this application does not specifically limit the form of the test mode register. As an example, the test mode register can generate control signals for the internal adjustment circuit of the chip under test (DUT) based on different test signals, adjust the internal adjustment circuit of the DUT according to the control signals, and output the test results. The addressing mode of the DUT is implemented by configuring the addressing mode register inside the DUT. By inputting an addressing signal into the addressing mode register, the addressing mode register recognizes the addressing signal and configures the DUT to enter the single-chip addressable mode.

[0100] The chip under test includes, but is not limited to, the DRAM chips in fourth-generation memory modules (DDR4 SDRAM, or DDR4 for short). DDR4 consists of multiple DRAM chips, and any DRAM chip on the memory module can be operated individually via PDA mode. PDA enable is achieved by writing a high level to bit A4 of the MR3 mode register inside the DRAM chip.

[0101] For step S22, this application does not specifically limit the form and duration of the preset time period. As an example, the preset time period may include, but is not limited to, the sum of additional latency (AL), CASwrite latency (CL), and parity latency (PL).

[0102] For step S23, this application does not specifically limit the form of the test instruction.

[0103] As an example, test instructions may include, but are not limited to, test voltage values.

[0104] Based on the above example, step S23 may include: adjusting the original voltage value of the chip under test to the test voltage value according to the test instruction carried in the test signal.

[0105] This application does not specifically limit the magnitude of the original voltage value. As an example, the original voltage value can be 1V to 5V; for example, the magnitude of the original voltage value can be 1V, 2V, 3V, 4V or 5V, etc.

[0106] For example, test commands can be numerical strings that can be converted through logic levels, such as 0000, 0001, and 0010. Each test command represents a different target voltage value; for example, 0000 represents 0.1V, 0001 represents 0.2V, and 0010 represents 0.3V. During the test, the initial voltage value of the chip under test is first obtained, which can be obtained based on other test commands. If the initial voltage value is detected to be 1V, and the target voltage value is higher than the initial voltage value, a signal such as 0010 is input to continuously increase the initial voltage value until it reaches the target voltage. During other functional tests, the chip under test is kept operating at the target voltage, improving the chip testing efficiency.

[0107] In one embodiment, the chip under test (DUT) may further include a voltage regulation circuit; this voltage regulation circuit may include multiple load elements. Based on the above embodiments, the step of adjusting the original voltage value of the DUT to the test voltage value according to the test command carried in the test signal may specifically include:

[0108] The chip under test can adjust the number of load components connected to the voltage regulation circuit or adjust the regulation frequency of the voltage regulation circuit according to the test voltage value.

[0109] This application does not specifically limit the form of the voltage regulation circuit. As an example, the voltage regulation circuit may include, but is not limited to, a power supply boost circuit or an on-die termination (ODT) circuit.

[0110] Please see Figure 5 , Figure 5 The diagram shown illustrates a voltage regulation circuit in one embodiment of this application. In this embodiment, the load element may include multiple regulating resistors connected to the voltage regulation circuit.

[0111] The voltage regulation circuit may include multiple regulation branches, and each regulation branch includes at least one regulation resistor and one switching transistor. The first terminal of the switching transistor is connected to the original voltage value V. DD The second terminal of the switching transistor is connected to one end of the regulating resistor, and the control terminal of the switching transistor is connected to the test signal; the other end of the regulating resistor is grounded.

[0112] As mentioned earlier, there can be multiple test pins on the chip under test. In this embodiment, any number of test pins can be selected to receive test signals based on the number of adjustment branches included in the voltage regulation circuit; similarly, a corresponding number of test signals can be connected based on the number of adjustment branches included in the voltage regulation circuit. For example, ... Figure 5As shown, the voltage regulation circuit includes four regulation branches, allowing selection of any four test pins to receive test signal 1, test signal 2, test signal 3, or test signal 4, respectively. These test signals can be used to control the on / off state of the corresponding switching transistors, thereby controlling whether the corresponding regulating resistors are connected to or disconnected from the voltage regulation circuit.

[0113] Please see Figure 6 As an example, step S23 may also include the following steps:

[0114] S231: Send a data strobe signal to the chip under test.

[0115] S232: After a preset latching time for the received data signal, the data strobe signal triggers the data signal to become valid.

[0116] S233: Adjusts the test voltage of the chip under test according to the test instructions carried in the test signal.

[0117] It should be understood that all Mode Register Set (MRS) instructions in PDA mode are validated using the data signal DQ0, which can be acquired via the data strobe signal DQS. The chip under test (DUT) can use the data strobe signal DQS to determine whether it receives the read data signal DQ0, thus determining whether the MRS instruction should be executed. For example, if the data strobe signal DQS acquires a low level (DQ0), the MRS instruction is executed; if the data strobe signal DQS acquires a high level (DQ1), the MRS instruction is not executed.

[0118] This application does not specify the exact duration of the preset latch time in step S232. As an example, the preset latch time can be determined based on the data strobe signal and the burst length (BL) of the chip under test. For instance, if data signals are acquired via the rising and / or falling edges of the data strobe signal, the preset latch time could be the time it takes for the data strobe signal to transmit half the burst length. Please refer to [link to relevant documentation]. Figure 7 This is shown as a timing diagram of step S23 in one possible embodiment. If the burst length is 8, the data signal is acquired on the rising edge of the data strobe signal. After acquiring 4 DQ0 cycles (4 data strobe signal cycles), the test instruction is determined to be executed to ensure accurate instruction reception and execution. It is understood that this is necessary... Figure 7 A low level must be sent during the time period indicated between a and b; otherwise, the MRS instruction cannot be executed, and the configuration will fail.

[0119] This application also provides a chip testing apparatus according to some embodiments. Please refer to... Figure 8The chip testing device may include a test signal transmission module 101, a data signal transmission module 102, and a voltage regulation module 103.

[0120] The test signal transmission module 101 can be used to apply a test signal to the chip under test 100, and the data signal transmission module 102 can be used to send a data signal to the chip under test 100. The chip under test 100 can enter the test mode based on the aforementioned test signal and data signal. The voltage adjustment module 103 is connected to the chip under test 100 and can be used to adjust the test voltage of the chip under test 100.

[0121] The aforementioned chip testing apparatus can send data signals to the chip under test (DUT) 100 via the data signal transmission module 102. These data signals, along with the test signals applied to the DUT 100 by the test signal generation module, jointly control the DUT 100 to enter the test mode. This allows for independent control of the DUT 100's test mode using its data signal information, and consequently, independent control of its test voltage. This enables more precise adjustment of the test voltage, improving the reliability of chip testing.

[0122] In one embodiment, the test signal transmission module 101 can apply a test signal to the chip under test 100 through the test pins of the chip under test 100. Simultaneously, the data signal transmission module 102 can also transmit data signals to the chip under test 100 through the data pins of the chip under test 100.

[0123] It should be noted that there can be multiple test pins and data pins on the chip under test. Based on this, the test signal transmission module 101 can send test signals to the valid test pins of the chip under test according to the actual situation of the chip under test; similarly, the data signal transmission module 102 can also send data signals to the valid data pins of the chip under test according to the actual situation of the chip under test.

[0124] In one embodiment, the test signal sending module 101 can simultaneously send test signals to multiple chips under test 100 located on the same wafer under test.

[0125] Taking chip A and chip B located on the same wafer under test as an example, the test pins of each chip under test are simultaneously connected to the transmitting end of the test signal transmitting module 101. The test signal transmitting module 101 can simultaneously send test signals to multiple chips under test (including chip A and chip B) located on the same wafer under test. Since the chips under test in this application require both test signals and data signals to enter the test mode, such as... Figure 3As shown, the test signal will only be truly recognized and activated by either chip under test (DUT) a or chip under test (DUT b) when the data signal of either DUT a or DUT b is also at a high level. In this example, if it is necessary to adjust the test voltage of a certain DUT chip, it is only necessary to pull the data signals of the other DUT chips low.

[0126] As mentioned earlier, the test signal can carry test commands. Based on this, the voltage adjustment module 103 can adjust the test voltage of the chip under test 100 according to the test commands.

[0127] As mentioned earlier, the test command may include a test voltage value. Based on this, the voltage adjustment module 103 can adjust the original voltage value of the chip under test 100 to the test voltage value according to the test command carried in the test signal.

[0128] As mentioned earlier, the chip under test 100 may have a voltage regulation circuit.

[0129] The voltage regulation circuit can be connected to multiple load components. Based on this, the voltage regulation module 103 can control the chip under test 100 to adjust the number of load components connected to the voltage regulation circuit or adjust the regulation frequency of the voltage regulation circuit according to the test command carried in the test signal.

[0130] Specifically, when the original voltage value of the chip under test 100 is lower than the test voltage value, the original voltage value of the chip under test 100 can be adjusted to the test voltage value by reducing the load components connected to the voltage regulation circuit or reducing the regulation frequency of the voltage regulation circuit; when the original voltage value of the chip under test 100 is higher than the test voltage value, the original voltage value of the chip under test 100 can be adjusted to the test voltage value by increasing the load components of the voltage regulation circuit or increasing the regulation frequency of the voltage regulation circuit.

[0131] Please continue reading. Figure 5 The load element may include multiple regulating resistors connected to the voltage regulation circuit. The voltage regulation circuit includes multiple regulating branches, and each regulating branch includes at least one regulating resistor and one switching transistor. The first terminal of the switching transistor is connected to the original voltage value V. DD The second terminal of the switching transistor is connected to one end of the regulating resistor, and the control terminal of the switching transistor is connected to the test signal; the other end of the regulating resistor is grounded.

[0132] As mentioned earlier, the chip under test can have multiple test pins. The appropriate number of test pins can be selected to receive test signals based on the number of regulation branches in the voltage regulation circuit. Furthermore, the voltage regulation module 103 can send a corresponding number of test signals based on the number of regulation branches in the voltage regulation circuit. For example, ... Figure 5As shown, the voltage regulation circuit includes four regulation branches, allowing any four test pins to be selected to receive test signal 1, test signal 2, test signal 3, or test signal 4, respectively. These test signals can be used to control the on / off state of the corresponding switching transistors, thereby controlling the corresponding regulating resistors to be connected to or disconnected from the voltage regulation circuit. Based on this, the voltage regulation module 103 can control the on / off state of the corresponding switching transistors according to the test commands carried in test signal 1, test signal 2, test signal 3, or test signal 4, thereby controlling the corresponding regulating resistors to be connected to the voltage regulation circuit.

[0133] Please continue reading. Figure 8 In one embodiment, the chip testing apparatus may further include a data strobe signal transmitting module 104. The data strobe signal transmitting module 104 can be used to send a data strobe signal to the chip under test 100, which can be used to trigger a data signal to be valid.

[0134] The chip testing apparatus provided in the above embodiments can determine whether the read data signal DQ0 is received using the data strobe signal DQS, thereby determining whether the MRS instruction is executed. For example, if the data strobe signal DQS detects that the data signal DQ is low (DQ0), the MRS instruction is executed; if the data strobe signal DQS detects that the data signal DQ is high (DQ1), the MRS instruction is not executed.

[0135] This application also provides a computer device according to some embodiments, which is capable of implementing the steps of the chip testing method provided in any of the above embodiments. Therefore, the computer device can also achieve the technical effects that the aforementioned chip testing method can achieve, and will not be described in detail here.

[0136] This application also provides a computer-readable storage medium according to some embodiments, which can implement the steps of the chip testing method provided in any of the above embodiments. Therefore, the computer-readable storage medium can also achieve the technical effects that the aforementioned chip testing method can achieve, and will not be described in detail here.

[0137] It should be noted that the chip testing method and chip testing device in the embodiments of this application can be applied to, but are not limited to, the field of DRAM testing.

[0138] It should also be noted that the chip testing devices in the embodiments of this application can all be used to implement the corresponding chip testing methods. Therefore, the technical features between the method embodiments and the device embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can understand the technical content of the present invention.

[0139] It should be understood that, although Figure 2 , Figure 4 and Figure 6 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 , Figure 4 and Figure 6 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0140] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0141] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A chip testing method, characterized in that, include: Apply a test signal to the chip under test; A data signal is sent to the chip under test (DUT), and the DUT enters a test mode based on the test signal and the data signal. The test voltage of the DUT is then adjusted. The chip under test is equipped with a test mode register; When the chip under test (DUT) is configured in addressing mode, the step of sending a data signal to the DUT, and the DUT entering a test mode based on the test signal and the data signal, and adjusting the test voltage of the DUT includes: The test mode register sets the chip under test to test mode according to the test signal; The chip under test receives the data signal after a preset time period following receiving the test signal; After the data signal is held for a preset latching time, the test voltage of the chip under test is adjusted according to the test command carried in the test signal.

2. The chip testing method according to claim 1, characterized in that, The chip under test is equipped with test pins and data pins; The chip under test receives the test signal through the test pin and the data signal through the data pin.

3. The chip testing method according to claim 1, characterized in that, Applying a test signal to the chip under test includes: The test signal is sent simultaneously to multiple chips under test; the multiple chips under test are located on the same wafer under test.

4. The chip testing method according to any one of claims 1 to 3, characterized in that, The chip under test (DUT) is equipped with a receiving module; the step of sending a data signal to the DUT, and the DUT entering a test mode based on the test signal and the data signal, includes: The receiving module generates an internal test signal based on the test signal and the data signal; the chip under test enters the test mode based on the internal test signal.

5. The chip testing method according to claim 4, characterized in that, The receiving module includes an AND gate.

6. The chip testing method according to claim 1, characterized in that, The test command includes the test voltage value; The step of adjusting the test voltage of the chip under test according to the test command carried in the test signal includes: The original voltage value of the chip under test is adjusted to the test voltage value according to the test command carried in the test signal.

7. The chip testing method according to claim 6, characterized in that, The chip under test has a voltage regulation circuit, which includes multiple load elements. The step of adjusting the original voltage value of the chip under test to the test voltage value according to the test command carried in the test signal includes: The chip under test adjusts the number of load elements connected to the voltage regulation circuit or adjusts the regulation frequency of the voltage regulation circuit according to the test voltage value.

8. The chip testing method according to claim 1, characterized in that, The preset time period includes the sum of additional delay time, writing delay time, and parity check time.

9. The chip testing method according to claim 1, characterized in that, The step of adjusting the test voltage of the chip under test according to the test command carried in the test signal includes: Send a data strobe signal to the chip under test; After a preset latching time is received, the data strobe signal triggers the data signal to become valid; The test voltage of the chip under test is adjusted according to the test instructions carried in the test signal.

10. The chip testing method according to claim 9, characterized in that, The preset latching time is the time it takes for the data strobe signal to transmit half the burst length.

11. A chip testing device, characterized in that, The chip testing device includes: A test signal transmitting module, wherein the test signal generating module is used to apply a test signal to the chip under test; wherein the test signal carries a test instruction; A data signal transmission module is provided, which is used to send a data signal to the chip under test (DUT), and the DUT enters a test mode based on the test signal and the data signal; wherein, the DUT receives the data signal after receiving the test signal for a preset time period; A voltage regulation module, connected to the chip under test, is used to regulate the test voltage of the chip under test according to the test command; The chip under test is equipped with a test mode register; The test mode register is used to set the chip under test to test mode according to the test signal; The chip under test receives the data signal after a preset time period of receiving the test signal.

12. The chip testing apparatus according to claim 11, characterized in that, The test signal transmitting module applies the test signal to the chip under test through the test pin of the chip under test; The data signal transmission module sends the data signal to the chip under test through the data pin of the chip under test.

13. The chip testing apparatus according to claim 11, characterized in that, The test signal sending module simultaneously sends the test signal to multiple chips under test located on the same wafer under test.

14. The chip testing apparatus according to claim 11, characterized in that, The test command includes the test voltage value; The voltage adjustment module adjusts the original voltage value of the chip under test to the test voltage value according to the test command carried in the test signal.

15. The chip testing apparatus according to claim 14, characterized in that, The chip under test has a voltage regulation circuit; The voltage regulation module controls the chip under test to adjust the number of load elements connected to the voltage regulation circuit or adjust the regulation frequency of the voltage regulation circuit according to the test command carried in the test signal.

16. The chip testing apparatus according to claim 15, characterized in that, It also includes a data strobe signal sending module, which is used to send a data strobe signal to the chip under test to trigger the data signal to be valid.

17. A computer device comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the chip testing method according to any one of claims 1 to 10.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the chip testing method according to any one of claims 1 to 10.

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