Semiconductor device and method for manufacturing the same

Abstract

The present application provides a semiconductor device and a method for manufacturing the same. The manufacturing method includes: forming an insulating dielectric layer on a substrate; etching the insulating dielectric layer to form a plurality of hole rows spaced apart along a first direction, each hole row including a plurality of holes spaced apart along a second direction; forming select control gates in the holes in a one-to-one correspondence to form a plurality of select control gate rows distributed along the first direction; etching away at least a portion of the insulating dielectric layer between two adjacent select control gate rows to form a trench, wherein the bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes the sidewall of the select control gate; and forming at least a gate oxide layer and a gate in the trench in sequence. In this method, since the position and shape of the formed select control gate have changed, in the subsequent process of forming the trench, only the insulating dielectric layer needs to be etched, avoiding the step of simultaneously etching the insulating dielectric layer and the select control gate to form the trench, thereby reducing the process difficulty of etching the trench.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and more specifically, to a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system. Background Art

[0002] With the continuous development of 3D NAND technology, the number of layers in three-dimensional memory has increased, from 24, 32, and 64 layers to high-level stacked structures exceeding 100 layers. This can significantly increase storage density and reduce the price per unit memory cell. However, as the number of layers gradually increases, the difficulty of etching the trench becomes extremely large. Therefore, a technical solution that can reduce the difficulty of trench etching is urgently needed. Summary of the Invention

[0003] The main purpose of the present application is to provide a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory and a storage system to solve the problem of high difficulty in etching the grooves in the technical solutions known to the inventors.

[0004] According to one aspect of an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, comprising: forming an insulating dielectric layer on a substrate; etching the insulating dielectric layer to form a plurality of rows of holes spaced apart along a first direction, each row of holes including a plurality of holes spaced apart along a second direction, each hole exposing the substrate, the first direction and the second direction being perpendicular, and the first direction and the second direction being perpendicular to the depth direction of the hole respectively; forming select control gates in the holes in a one-to-one correspondence to form a plurality of rows of select control gates spaced apart along the first direction, each row of select control gates including a plurality of select control gates spaced apart along the second direction; etching away at least a portion of the insulating dielectric layer between two adjacent rows of select control gates to form a trench, the bottom wall of the trench being the insulating dielectric layer, and at least one sidewall of the trench including a sidewall of the select control gate; and forming at least a gate oxide layer and a gate in the trench in sequence.

[0005] Optionally, a line connecting center points of any two holes belonging to different hole rows is not on a straight line in the first direction.

[0006] Optionally, etching away at least a portion of the insulating dielectric layer between two adjacent selection control gate rows to form a groove includes: using dry etching to remove a portion of the insulating dielectric layer between two adjacent selection control gate rows to form a preliminary groove, wherein the sidewall of the preliminary groove is the insulating dielectric layer; and using wet etching to remove the remaining portion of the insulating dielectric layer between two adjacent selection control gate rows, so that the preliminary groove forms a groove.

[0007] Optionally, the two sidewalls of the prepared trench are respectively a first sidewall and a second sidewall, the two selection control gate rows on both sides of the prepared trench are respectively a first selection control gate row and a second selection control gate row, the first selection control gate row is located on one side of the first sidewall, the second selection control gate row is located on a side of the second sidewall away from the first sidewall, the width of the insulating dielectric layer between the first selection control gate row and the first sidewall in the first direction is a first width, the width of the insulating dielectric layer between the second selection control gate row and the second sidewall in the first direction is a second width, the first width is greater than the second width, and wet etching is used to remove at least a portion of the remaining insulating dielectric layer between two adjacent selection control gate rows so that the prepared trench forms a trench, including: using wet etching to remove a portion of the insulating dielectric layer between the first sidewall and the first selection control gate row, and the entire insulating dielectric layer between the second sidewall and the second selection control gate row, to form the trench having only one sidewall including the sidewall of the selection control gate.

[0008] Optionally, the two sidewalls of the preliminary trench are respectively a first sidewall and a second sidewall, the two selection control gate rows on both sides of the preliminary trench are respectively a first selection control gate row and a second selection control gate row, the first selection control gate row is located on one side of the first sidewall, the second selection control gate row is located on a side of the second sidewall away from the first sidewall, the width of the insulating dielectric layer between the first selection control gate row and the first sidewall in the first direction is a first width, the width of the insulating dielectric layer between the second selection control gate row and the second sidewall in the first direction is a second width, the first width is equal to the second width, and wet etching is used to remove the remaining portion of the insulating dielectric layer between two adjacent selection control gate rows to form a trench whose sidewalls include the sidewalls of the selection control gate, including: using wet etching to remove all of the insulating dielectric layer between the first sidewall and the first selection control gate row, and all of the insulating dielectric layer between the second sidewall and the second selection control gate row, to form the trench whose two sidewalls respectively include the sidewalls of the selection control gate.

[0009] Optionally, at least a gate oxide layer and a gate are sequentially formed in the trench, comprising: sequentially forming a barrier layer, the gate oxide layer and the gate in the trench.

[0010] Optionally, the substrate is a silicon substrate, and forming a selection control gate in each of the holes to form a plurality of selection control gate rows includes: forming the selection control gate on the exposed silicon substrate using a selective epitaxial growth method.

[0011] Optionally, after at least a gate oxide layer and a gate are sequentially formed in the trench, the method further comprises: planarizing the structure after the gate is formed.

[0012] Optionally, the method further includes: forming a source region and a drain region in the selection control gate, the source region and the drain region being located at two ends of the selection control gate respectively; and forming a source electrode and a drain electrode on an exposed surface of the source region and an exposed surface of the drain region respectively.

[0013] Optionally, the gate is made of titanium nitride.

[0014] According to another aspect of an embodiment of the present invention, a semiconductor device is provided. The semiconductor device is formed by using any one of the above-mentioned manufacturing methods.

[0015] According to another aspect of the embodiments of the present invention, a semiconductor device is provided, comprising: an insulating dielectric layer, wherein a plurality of hole rows and trenches are provided in the insulating dielectric layer and are spaced apart along a first direction, each hole row comprising a plurality of spaced holes, the trenches being located between two adjacent hole rows and having bottom walls of the trenches being the insulating dielectric layer, each hole row comprising a plurality of holes spaced apart along a second direction, the first direction being perpendicular to the second direction, and the first direction and the second direction being perpendicular to the depth direction of the holes, respectively; a plurality of selection control gate rows distributed along the first direction, each selection control gate row comprising a plurality of selection control gates distributed along the second direction, the selection control gates being located in the holes in a one-to-one correspondence, and at least one sidewall of the trench comprising a sidewall of the selection control gate; and gate structures being located in the trenches in a one-to-one correspondence, the gate structures comprising at least a gate oxide layer and the gate electrode sequentially disposed on the substrate, and one gate structure being in contact with one sidewall of each selection control gate in one selection control gate row.

[0016] Optionally, a line connecting center points of any two holes belonging to different hole rows is not on a straight line in the first direction.

[0017] Optionally, only one of the two sidewalls of the trench includes a sidewall of the select control gate.

[0018] Optionally, the two sidewalls of the trench respectively include sidewalls of the selection control gate.

[0019] Optionally, the gate structure includes a barrier layer, the gate oxide layer and the gate arranged in sequence.

[0020] Optionally, the semiconductor device further includes a source region, a drain region, a source electrode and a drain electrode, the source region and the drain region are located in the hole and are respectively located on both sides of the selection control gate, the source electrode is located on the surface of the source region away from the selection control gate, and the drain electrode is located on the surface of the drain region away from the selection control gate.

[0021] According to another aspect of an embodiment of the present invention, a three-dimensional memory is provided, comprising any one of the aforementioned semiconductor devices or a semiconductor device obtained by any one of the aforementioned manufacturing methods.

[0022] According to another aspect of an embodiment of the present invention, a storage system is provided, including a storage controller and the three-dimensional memory, wherein the three-dimensional memory is configured to store data, and the storage controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

[0023] In an embodiment of the present invention, an insulating dielectric layer is first formed on a substrate. Then, the insulating dielectric layer is etched to form a plurality of rows of holes spaced apart along a first direction, each row of holes having a plurality of holes spaced apart along a second direction. Select control gates are formed in the holes, thereby forming a plurality of rows of select control gates spaced apart along the first direction. The insulating dielectric layer between two adjacent rows of select control gates is then removed by etching to form a trench, wherein the bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes the sidewall of the select control gate. Finally, a gate oxide layer and a gate are sequentially formed in the trench. In this method, since the position and shape of the formed select control gate are changed, in the subsequent trench formation process, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the select control gate to form the trench, thereby reducing the difficulty of the trench etching process. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings that constitute part of this application are used to provide a further understanding of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0025] Figures 1 to 4 A structural schematic diagram showing a process for manufacturing a semiconductor device with a three-dimensional gate structure according to an embodiment of the present application is shown;

[0026] Figure 5 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown;

[0027] Figures 6 to 9 A schematic structural diagram showing a semiconductor device manufacturing process of the present application is shown;

[0028] Figure 10A structural schematic diagram of a mobile phone according to an embodiment of the present application is shown.

[0029] The above drawings include the following reference numerals:

[0030] 10. Insulating dielectric layer; 11. Selective control gate; 12. Barrier layer; 13. Gate; 14. Gate oxide layer; 15. Selective control gate row; 16. Trench; 17. Three-dimensional memory; 18. Mobile phone. DETAILED DESCRIPTION

[0031] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element or intervening elements may be present. Moreover, in the specification and claims, when it is described that an element is "connected to" another element, the element may be "directly connected to" the other element or "connected to" the other element through a third element.

[0035] At present, the trench etching of semiconductor devices with three-dimensional gate structures is very difficult. The inventors have found that the manufacturing process of semiconductor devices with three-dimensional gate structures generally includes: first, depositing an insulating dielectric layer on the substrate to form a Figure 1 The structure shown ( Figure 1After that, the insulating dielectric layer is etched to form a plurality of spaced trenches, and the trenches allow the substrate to leak out, and a selection control gate is grown in the trenches to form Figure 2 The structure shown in FIG. ; then, the insulating dielectric layer and the selection control gate are etched to form multiple trenches, forming Figure 3 Finally, a barrier layer, a gate oxide layer, and a gate are formed in the trench to form Figure 4 However, trench etching in the above method is extremely difficult for the following two reasons: 1. During the trench etching process, the insulating dielectric layer and the select gate need to be etched simultaneously. The insulating dielectric layer and the select gate are made of different materials, but the selectivity ratio of these two materials must be the same; 2. The remaining materials are also the same. Without a barrier layer, it is difficult to ensure that the insulating dielectric layer and the select gate are not removed.

[0036] In order to solve the problem of extremely high difficulty in trench etching, in a typical embodiment of the present application, a method for manufacturing a semiconductor device, a semiconductor device, a three-dimensional memory, and a storage system are provided.

[0037] According to an embodiment of the present application, a method for manufacturing a semiconductor device is provided. Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor according to an embodiment of the present application. Figure 5 As shown, the method includes the following steps:

[0038] Step S101, forming an insulating dielectric layer 10 on a substrate, forming Figure 1 The structure shown ( Figure 1 is a top view);

[0039] Step S102: etching the insulating dielectric layer 10 to form a plurality of rows of holes spaced apart along a first direction, each row of holes including a plurality of holes spaced apart along a second direction, each hole exposing the substrate, the first direction being perpendicular to the second direction, and the first direction and the second direction being perpendicular to the depth direction of the hole.

[0040] Step S103, forming selection control gates 11 in the holes one by one, forming a plurality of selection control gate rows 15 distributed along the first direction, each of the selection control gate rows 15 including a plurality of the selection control gates 11 spaced apart along the second direction, such as Figure 6 The structure shown;

[0041] Step S104: etching away at least a portion of the insulating dielectric layer 10 between two adjacent select control gate rows 15 to form a trench 16. The bottom wall of the trench 16 is the insulating dielectric layer 10, and at least one sidewall of the trench 16 includes a sidewall of the select control gate 11. Figure 7The structure shown is formed by removing at least a portion of the insulating dielectric layer 10 between two adjacent selection control gate rows 15;

[0042] Step S105, forming at least a gate oxide layer 14 and a gate 13 in the trench 16 in sequence, forming a Figure 8 The structure shown.

[0043] In the above method, an insulating dielectric layer is first formed on a substrate. Then, the insulating dielectric layer is etched to form a plurality of rows of holes spaced apart along a first direction, each row of holes having a plurality of holes spaced apart along a second direction. Select control gates are formed in the holes, thereby forming a plurality of rows of select control gates spaced apart along the first direction. The insulating dielectric layer between two adjacent rows of select control gates is then removed by etching to form a trench, wherein the bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes the sidewall of the select control gate. Finally, a gate oxide layer and a gate are sequentially formed in the trench. In this method, since the position and shape of the formed select control gate are changed, only the insulating dielectric layer needs to be etched during the subsequent trench formation process, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the select control gate to form the trench, thereby reducing the difficulty of the trench etching process.

[0044] In one embodiment of the present application, the line connecting the center points of any two holes belonging to different hole rows is not on the straight line in the first direction. In this embodiment, the line connecting the center points of any two holes belonging to different hole rows is not on the straight line in the first direction, indicating that the holes in the different hole rows are staggered, increasing the distance between the holes in different hole rows (a smaller distance is likely to affect each other), thereby reducing the risk of leakage. In addition, the staggering increases the distance between the two holes belonging to the upper and lower rows, respectively, so that a middle groove with a larger critical dimension can be subsequently produced, thereby facilitating the implementation of subsequent processes.

[0045] In another embodiment of the present application, Figure 7 As shown, etching to remove at least a portion of the insulating dielectric layer 10 between two adjacent select control gate rows 15 to form a trench includes dry etching to remove a portion of the insulating dielectric layer 10 between the two adjacent select control gate rows 15 to form a preliminary trench, the sidewalls of the preliminary trench being the insulating dielectric layer 10; and wet etching to remove the remaining at least a portion of the insulating dielectric layer 10 between the two adjacent select control gate rows 15, so that the preliminary trench forms a trench 16. In this embodiment, this method is used to remove at least a portion of the insulating dielectric layer between two adjacent select control gate rows because only the insulating dielectric layer is removed, without removing the select control gate portion, thereby making the removal of the portion more accurate.

[0046] Of course, in actual applications, the above etching method is not limited to dry etching or wet etching, and other etching methods may also be used. Those skilled in the art may choose according to actual conditions.

[0047] In another embodiment of the present application, the two sidewalls of the above-mentioned preliminary trench are respectively a first sidewall and a second sidewall, the two selection control gate rows on both sides of the above-mentioned preliminary trench are respectively a first selection control gate row and a second selection control gate row, the above-mentioned first selection control gate row is located on one side of the above-mentioned first sidewall, and the above-mentioned second selection control gate row is located on a side of the above-mentioned second sidewall away from the above-mentioned first sidewall, the width of the above-mentioned insulating dielectric layer between the above-mentioned first selection control gate row and the above-mentioned first sidewall in the above-mentioned first direction is a first width, and the width of the above-mentioned insulating dielectric layer between the above-mentioned second selection control gate row and the above-mentioned second sidewall in the above-mentioned first direction is a second width, and the above-mentioned first width is greater than the above-mentioned second width, and wet etching is used to remove at least a portion of the above-mentioned insulating dielectric layer remaining between two adjacent above-mentioned selection control gate rows, so that the above-mentioned preliminary trench forms a trench, including: using wet etching to remove a portion of the above-mentioned insulating dielectric layer between the above-mentioned first sidewall and the above-mentioned first selection control gate row, and the entire above-mentioned insulating dielectric layer between the above-mentioned second sidewall and the above-mentioned second selection control gate row, to form the above-mentioned trench with only one sidewall including the sidewall of the above-mentioned selection control gate. In this embodiment, one side wall of the above-mentioned groove includes an insulating dielectric layer, and one side wall includes the side wall of the selection control gate. This part of the insulating dielectric layer can block metal ions, so that there is no need to fill the blocking layer in the subsequent groove, and it can also achieve a good insulation effect and alleviate the leakage problem.

[0048] In another embodiment of the present application, the two sidewalls of the above-mentioned preliminary trench are respectively the first sidewall and the second sidewall, the two selection control gate rows on both sides of the above-mentioned preliminary trench are respectively the first selection control gate row and the second selection control gate row, the first selection control gate row is located on one side of the above-mentioned first sidewall, and the second selection control gate row is located on the side of the above-mentioned second sidewall away from the above-mentioned first sidewall, the width of the above-mentioned insulating dielectric layer between the above-mentioned first selection control gate row and the above-mentioned first sidewall in the above-mentioned first direction is the first width, the width of the above-mentioned insulating dielectric layer between the above-mentioned second selection control gate row and the above-mentioned second sidewall in the above-mentioned first direction is the second width, and the above-mentioned first width is equal to the above-mentioned second width, and wet etching is used to remove the remaining portion of the above-mentioned insulating dielectric layer between two adjacent above-mentioned selection control gate rows to form a trench whose sidewalls include the sidewalls of the above-mentioned selection control gate, including: using wet etching to remove all the above-mentioned insulating dielectric layer between the above-mentioned first sidewall and the above-mentioned first selection control gate row, and all the above-mentioned insulating dielectric layer between the above-mentioned second sidewall and the above-mentioned second selection control gate row, to form the above-mentioned trench whose two sidewalls respectively include the sidewalls of the above-mentioned selection control gate. In order to further enhance the conductivity of the semiconductor device, in this embodiment, the two side walls of the above-mentioned trench are divided into the side walls of the selected control gate. This removal method is simpler to operate than the method in the above-mentioned embodiment. However, since all the insulating dielectric layers between the two control gate rows are removed, the distance between the gate and the control gate row is small, so leakage problems may occur.

[0049] In order to avoid the occurrence of leakage problems, such as Figure 9 As shown, in another embodiment of the present application, at least a gate oxide layer 14 and a gate 13 are formed in sequence in the above-mentioned groove, including forming a blocking layer 12, the above-mentioned gate oxide layer 14 and the above-mentioned gate 13 in sequence in the above-mentioned groove, that is, the blocking layer is formed first, and then the gate oxide layer and the gate are formed on the surface of the blocking layer, so that the diffusion of ions is blocked by the blocking layer, thereby alleviating the leakage problem.

[0050] In another embodiment of the present application, the substrate is a silicon substrate, and the selective control gates 11 are formed in each of the holes to form a plurality of selective control gate rows 15, including forming the selective control gates 11 on the exposed silicon substrate using a selective epitaxial growth method. Of course, in practical applications, the substrate material is not limited to silicon and can also be other materials, such as germanium. If other compounds are selected as the substrate, the selective epitaxial growth method cannot be used to form the selective control gates on the substrate.

[0051] In another embodiment of the present application, after at least the gate oxide layer 14 and the gate 13 are sequentially formed in the trench, the method further includes planarizing the structure after the gate 13 is formed. In this embodiment, planarizing the structure after the gate is formed can form a flat semiconductor device, facilitating subsequent processes on the flat surface.

[0052] The above-mentioned planarization process may adopt a chemical mechanical polishing process. Of course, in actual applications, other processes may also be adopted, and those skilled in the art may select one according to actual conditions.

[0053] In another embodiment of the present application, the above method also includes: forming a source region and a drain region in the above selection control gate, and the above source region and drain region are respectively located at the two ends of the above selection control gate; and forming a source electrode and a drain electrode on the exposed surface of the above source region and the exposed surface of the above drain region, respectively.

[0054] In another embodiment of the present application, the material of the gate 13 includes titanium nitride. During the semiconductor manufacturing process, fluorine used in the subsequent deposition of metal tungsten can attack the gate oxide layer, causing holes in the oxide layer, which may lead to leakage problems. Titanium nitride can block fluorine from attacking the gate oxide layer, alleviating the leakage problem or reducing the possibility of leakage, further ensuring good performance of the device.

[0055] In practical applications, the material of the gate electrode of the present application is not limited to titanium nitride, but may be other materials. Those skilled in the art may select other suitable materials as the gate electrode material according to actual conditions.

[0056] In another typical embodiment of the present application, a semiconductor device is provided. The semiconductor device is formed by any of the above-mentioned manufacturing methods.

[0057] The semiconductor device is formed using any of the aforementioned fabrication methods. In this fabrication method, an insulating dielectric layer is first formed on a substrate. The insulating dielectric layer is then etched to form a plurality of rows of holes spaced apart along a first direction, each row of holes having a plurality of holes spaced apart along a second direction. Select control gates are formed in the holes, thereby forming a plurality of rows of select control gates spaced apart along the first direction. The insulating dielectric layer between two adjacent rows of select control gates is then removed by etching to form a trench, wherein the bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes a sidewall of the select control gate. Finally, a gate oxide layer and a gate are sequentially formed in the trench. In this method, since the position and shape of the formed select control gate are changed, only the insulating dielectric layer needs to be etched during the subsequent trench formation process, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the select control gate to form the trench, thereby reducing the difficulty of the trench etching process.

[0058] In another typical embodiment of the present application, a semiconductor device is provided, such as Figure 8 As shown, the semiconductor device includes an insulating dielectric layer 10, a plurality of selection control gate rows 15 and a gate structure, wherein the insulating dielectric layer 10 is provided with a plurality of hole rows and trenches spaced apart along a first direction, each of the hole rows includes a plurality of spaced holes, the trenches are located between two adjacent hole rows and the bottom wall of the trenches is the insulating dielectric layer 10, each of the hole rows includes a plurality of holes spaced apart along a second direction, the first direction is perpendicular to the second direction, and the first direction and the second direction are respectively perpendicular to the depth direction of the holes; a plurality of holes are spaced apart along the upper and lower directions. The selection control gate rows 15 are distributed in the first direction, and each of the selection control gate rows 15 includes a plurality of the selection control gates 11 distributed along the second direction. The selection control gates 11 are located in the holes one by one, and at least one sidewall of the trench includes the sidewall of the selection control gate 11; the gate structures are located in the trenches one by one, and the gate structures include at least a gate oxide layer 14 and the gate 13 sequentially arranged on the substrate, and one gate structure contacts one sidewall of each of the selection control gates 11 in one of the selection control gate rows 15.

[0059] The semiconductor device includes an insulating dielectric layer, multiple rows of select control gates, and a gate structure. The insulating dielectric layer includes multiple rows of holes and trenches spaced apart along a first direction, each row of holes including multiple holes spaced apart. The trenches are located between two adjacent rows of holes, and the bottom walls of the trenches are the insulating dielectric layer. Each row of holes includes multiple holes spaced apart along a second direction. Multiple rows of select control gates are distributed along the first direction, each row of select control gates including multiple select control gates distributed along the second direction. The select control gates are positioned one-to-one within the holes, and at least one sidewall of the trenches includes a sidewall of the select control gate. The gate structures are positioned one-to-one within the trenches, and the gate structures include at least a gate oxide layer and a gate electrode sequentially disposed on a substrate. A gate structure contacts one sidewall of each select control gate within a row of select control gates. In this semiconductor structure, a portion of the insulating dielectric layer remains between two adjacent rows of select control gates. This portion of the insulating dielectric layer can block metal ions, eliminating the need for a barrier layer to be filled in the subsequent trenches, while still providing good insulation and mitigating leakage issues.

[0060] In one embodiment of the present application, the line connecting the center points of any two holes belonging to different hole rows is not on the straight line in the first direction. In this embodiment, the line connecting the center points of any two holes belonging to different hole rows is not on the straight line in the first direction, indicating that the holes in the different hole rows are staggered, increasing the distance between the holes in different hole rows (a smaller distance is likely to affect each other), thereby reducing the risk of leakage. In addition, the staggering increases the distance between the two holes belonging to the upper and lower rows, respectively, so that a middle groove with a larger critical dimension can be subsequently produced, thereby facilitating the implementation of subsequent processes.

[0061] In another embodiment of the present application, only one of the two sidewalls of the trench comprises the sidewall of the select control gate. In this embodiment, one sidewall of the trench comprises an insulating dielectric layer, and one sidewall comprises the sidewall of the select control gate. This insulating dielectric layer can block metal ions, thereby eliminating the need for a barrier layer in subsequent trenches and providing good insulation, thereby alleviating leakage issues.

[0062] In one embodiment of the present application, the two sidewalls of the trench each comprise the sidewalls of the select control gate. In this embodiment, the two sidewalls of the trench each comprise the sidewalls of the select control gate. This removal method is simpler to operate than the method in the above embodiment. However, since all insulating dielectric layers between the two control gate rows are removed, the distance between the gate and the control gate rows is reduced, which may cause leakage.

[0063] In order to avoid the occurrence of leakage problems, such as Figure 9 As shown, in another embodiment of the present application, the gate structure includes a barrier layer 12, a gate oxide layer 14, and a gate 13 arranged in sequence. In this embodiment, the barrier layer blocks the diffusion of ions, thereby alleviating the leakage problem.

[0064] In another embodiment of the present application, the above-mentioned semiconductor device also includes a source region, a drain region, a source electrode and a drain electrode, the above-mentioned source region and the above-mentioned drain region are located in the above-mentioned hole and are respectively located on both sides of the above-mentioned selection control gate, the above-mentioned source electrode is located on the surface of the above-mentioned source region away from the above-mentioned selection control gate, and the above-mentioned drain electrode is located on the surface of the above-mentioned drain region away from the above-mentioned selection control gate.

[0065] In another typical embodiment of the present application, a three-dimensional memory is provided, comprising any one of the above-mentioned semiconductor devices or a semiconductor device obtained by any one of the above-mentioned manufacturing methods.

[0066] In another typical embodiment of the present application, a storage system is provided, including a storage controller and the above-mentioned three-dimensional memory, wherein the above-mentioned three-dimensional memory is configured to store data, and the above-mentioned storage controller is coupled to the above-mentioned three-dimensional memory and configured to control the above-mentioned three-dimensional memory.

[0067] The above-mentioned storage system includes a storage controller and the above-mentioned three-dimensional memory, the above-mentioned three-dimensional memory is configured to store data, the above-mentioned storage controller is coupled to the above-mentioned three-dimensional memory and is configured to control the above-mentioned three-dimensional memory, and the above-mentioned three-dimensional memory includes any of the above-mentioned semiconductor devices or a semiconductor device obtained using any of the above-mentioned manufacturing methods. Since the position and shape of the selected control gate formed in this semiconductor device are changed, in the subsequent process of forming a trench, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the selected control gate to form the trench, thereby reducing the process difficulty of etching the trench.

[0068] In actual applications, the above storage system may be a Solid State Disk (SSD).

[0069] An embodiment of the present application further provides an electronic device, including: the above-mentioned three-dimensional memory.

[0070] The above-mentioned electronic device includes the above-mentioned three-dimensional memory, and the above-mentioned three-dimensional memory includes any of the above-mentioned semiconductor devices or a semiconductor device obtained using any of the above-mentioned manufacturing methods. Since the position and shape of the selected control gate formed in the semiconductor device have changed, in the subsequent process of forming the groove, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the selected control gate to form the groove, thereby reducing the process difficulty of etching the groove.

[0071] In an embodiment of the present application, the electronic device includes at least one of the following: a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, an in-vehicle device, a wearable device, and a mobile power bank. In this embodiment, the memory device using the semiconductor structure of the present application can be applied to any electronic device. Because the semiconductor structure of the present application has a relatively late breakdown problem, the performance of the electronic device using this semiconductor structure is further improved. Figure 10 A schematic diagram of the structure of a mobile phone according to an embodiment of the present application is shown. Figure 10 As shown, the mobile phone 18 includes a three-dimensional memory 17 using the semiconductor structure of the present application.

[0072] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the technical solution of the present application will be described below with reference to specific embodiments.

[0073] Example

[0074] The method for manufacturing the semiconductor device includes:

[0075] like Figure 1 As shown, an insulating dielectric layer 10 is formed on a substrate, the substrate is a silicon substrate, and the material of the insulating dielectric layer 10 is silicon dioxide; the insulating dielectric layer 10 is etched to form a plurality of spaced hole rows, each of the above-mentioned hole rows includes a plurality of spaced holes, and each of the above-mentioned holes exposes the substrate; select control gates 11 are formed in the holes one by one, forming a plurality of select control gate rows 15, forming as shown in FIG. Figure 6 etching to remove at least a portion of the insulating dielectric layer 10 between two adjacent select control gate rows 15 to form a trench, Figure 7 The structure shown is formed by removing at least part of the insulating dielectric layer between two adjacent selection control gate rows 15; at least a gate oxide layer 14 and a gate 13 are sequentially formed in the trench to form a structure as shown in FIG. Figure 8 In the structure shown, the gate 13 is made of titanium nitride, and the gate oxide layer 14 is made of silicon dioxide.

[0076] In the above-mentioned semiconductor device, since the pattern and manufacturing process of etching the trench are changed, the steps of simultaneously etching the insulating dielectric layer and selecting the control gate are avoided, thereby reducing the process difficulty of etching the trench.

[0077] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0078] 1) In the manufacturing method of the present application, first, an insulating dielectric layer is formed on a substrate, then the insulating dielectric layer is etched to form a plurality of rows of holes spaced apart along a first direction, each row of holes having a plurality of holes spaced apart along a second direction, a selection control gate is formed in the hole, thereby forming a plurality of selection control gate rows spaced apart along the first direction, and the insulating dielectric layer between two adjacent selection control gate rows is etched away to form a trench, the bottom wall of the trench being the insulating dielectric layer, and at least one sidewall of the trench including the sidewall of the selection control gate, and finally, a gate oxide layer and a gate are sequentially formed in the trench. In this method, since the position and shape of the formed selection control gate have changed, in the subsequent process of forming the trench, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the selection control gate to form the trench, thereby reducing the process difficulty of etching the trench.

[0079] 2) The semiconductor device of the present application is formed using any of the above-mentioned manufacturing methods. In this manufacturing method, first, an insulating dielectric layer is formed on a substrate. Then, the insulating dielectric layer is etched to form a plurality of hole rows spaced apart along a first direction, each hole row having a plurality of holes spaced apart along a second direction. Select control gates are formed in the holes, thereby forming a plurality of select control gate rows spaced apart along the first direction. The insulating dielectric layer between two adjacent select control gate rows is etched away to form a trench. The bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes the sidewall of the select control gate. Finally, a gate oxide layer and a gate are sequentially formed in the trench. In this method, since the position and shape of the formed select control gate have changed, in the subsequent process of forming the trench, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the select control gate to form the trench, thereby reducing the process difficulty of etching the trench.

[0080] 3) The semiconductor device of the present application includes an insulating dielectric layer, multiple selection control gate rows, and a gate structure, wherein the insulating dielectric layer is provided with multiple hole rows and trenches spaced apart along a first direction, each hole row including multiple spaced holes, the trenches being located between two adjacent hole rows and having the bottom wall of the trenches being the insulating dielectric layer, and each hole row including multiple holes spaced apart along a second direction; multiple selection control gate rows distributed along the first direction, each selection control gate row including multiple selection control gates distributed along the second direction, the selection control gates being located one-to-one in the holes, at least one sidewall of the trench including the sidewall of the selection control gate; and gate structures being located one-to-one in the trenches, the gate structures including at least a gate oxide layer and a gate sequentially disposed on the substrate, a gate structure contacting one sidewall of each selection control gate in a selection control gate row. In this semiconductor structure, a portion of the insulating dielectric layer remains between two adjacent selection control gate rows, and this portion of the insulating dielectric layer can act as a barrier to metal ions, thereby eliminating the need to fill a barrier layer in the subsequent trenches and achieving a good insulation effect, thereby alleviating leakage problems.

[0081] 4) The storage system of the present application includes a storage controller and the above-mentioned three-dimensional memory, the above-mentioned three-dimensional memory is configured to store data, the above-mentioned storage controller is coupled to the above-mentioned three-dimensional memory and is configured to control the above-mentioned three-dimensional memory, the above-mentioned three-dimensional memory includes any of the above-mentioned semiconductor devices or a semiconductor device obtained by any of the above-mentioned manufacturing methods. Since the position and shape of the formed selection control gate of the semiconductor device have changed, in the subsequent process of forming the groove, only the insulating dielectric layer needs to be etched, thereby avoiding the step of simultaneously etching the insulating dielectric layer and the selection control gate to form the groove, thereby reducing the process difficulty of etching the groove.

[0082] The foregoing description is merely a preferred embodiment of the present application and is not intended to limit the present application. Persons skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming an insulating dielectric layer on the substrate; Etching the insulating dielectric layer to form a plurality of hole rows spaced apart along a first direction, each hole row including a plurality of holes spaced apart along a second direction, each hole exposing the substrate, the first direction being perpendicular to the second direction, and the first direction and the second direction being perpendicular to the depth direction of the hole; forming selection control gates in the holes in a one-to-one correspondence, forming a plurality of selection control gate rows distributed along the first direction, each of the selection control gate rows including a plurality of the selection control gates distributed at intervals along the second direction; Etching and removing at least a portion of the insulating dielectric layer between two adjacent rows of the select control gates to form a trench, wherein a bottom wall of the trench is the insulating dielectric layer, and at least one sidewall of the trench includes a sidewall of the select control gate; At least a gate oxide layer and a gate are formed in sequence in the trench.

2. The method according to claim 1, characterized in that A line connecting the center points of any two holes belonging to different hole rows is not on a straight line in the first direction.

3. The method according to claim 1, characterized in that Etching and removing at least a portion of the insulating dielectric layer between two adjacent selection control gate rows to form a trench, comprising: removing a portion of the insulating dielectric layer between two adjacent selection control gate rows by dry etching to form a preliminary trench, wherein the sidewall of the preliminary trench is the insulating dielectric layer; Wet etching is used to remove at least a portion of the remaining insulating dielectric layer between two adjacent selection control gate rows, so that the prepared trench forms a trench.

4. The method according to claim 3, characterized in that The two sidewalls of the preliminary trench are respectively a first sidewall and a second sidewall, the two selection control gate rows on both sides of the preliminary trench are respectively a first selection control gate row and a second selection control gate row, the first selection control gate row is located on one side of the first sidewall, and the second selection control gate row is located on a side of the second sidewall away from the first sidewall, the width of the insulating dielectric layer between the first selection control gate row and the first sidewall in the first direction is a first width, and the width of the insulating dielectric layer between the second selection control gate row and the second sidewall in the first direction is a second width, and the first width is greater than the second width. Wet etching is used to remove at least a portion of the remaining insulating dielectric layer between two adjacent selection control gate rows, so that the prepared trench forms a trench, including: using wet etching to remove a portion of the insulating dielectric layer between the first sidewall and the first selection control gate row, and the entire insulating dielectric layer between the second sidewall and the second selection control gate row, to form the trench with only one sidewall including the sidewall of the selection control gate.

5. The method according to claim 3, characterized in that The two sidewalls of the preliminary trench are respectively a first sidewall and a second sidewall, the two selection control gate rows on both sides of the preliminary trench are respectively a first selection control gate row and a second selection control gate row, the first selection control gate row is located on one side of the first sidewall, and the second selection control gate row is located on a side of the second sidewall away from the first sidewall, the width of the insulating dielectric layer between the first selection control gate row and the first sidewall in the first direction is a first width, the width of the insulating dielectric layer between the second selection control gate row and the second sidewall in the first direction is a second width, the first width is equal to the second width, and wet etching is used to remove the remaining portion of the insulating dielectric layer between two adjacent selection control gate rows to form a trench whose sidewalls include the sidewalls of the selection control gates, including: Wet etching is used to remove the entire insulating dielectric layer between the first sidewall and the first selection control gate row, and the entire insulating dielectric layer between the second sidewall and the second selection control gate row, to form the trench whose two sidewalls respectively include the sidewalls of the selection control gate.

6. The method according to claim 5, characterized in that At least a gate oxide layer and a gate are sequentially formed in the trench, comprising: A barrier layer, the gate oxide layer and the gate are sequentially formed in the trench.

7. The method according to any one of claims 1 to 6, characterized in that The substrate is a silicon substrate, and a selection control gate is formed in each of the holes to form a plurality of selection control gate rows, including: The selection control gate is formed on the exposed silicon substrate by adopting a selective epitaxial growth method.

8. The method according to any one of claims 1 to 6, characterized in that After forming at least a gate oxide layer and a gate in sequence in the trench, the method further comprises: The structure after forming the gate is planarized.

9. The method according to any one of claims 1 to 6, characterized in that The method further comprises: forming a source region and a drain region in the selection control gate, wherein the source region and the drain region are respectively located at two ends of the selection control gate; A source electrode and a drain electrode are formed on the exposed surface of the source region and the exposed surface of the drain region, respectively.

10. The method according to any one of claims 1 to 6, characterized in that The gate is made of titanium nitride.

11. A semiconductor device, characterized in that: The semiconductor device is formed by the manufacturing method according to any one of claims 1 to 9.

12. A semiconductor device, characterized in that: include: an insulating dielectric layer, wherein the insulating dielectric layer is provided with a plurality of hole rows and grooves spaced apart along a first direction, each hole row including a plurality of spaced holes, the grooves being located between two adjacent hole rows and having bottom walls formed by the insulating dielectric layer, each hole row including a plurality of holes spaced apart along a second direction, the first direction being perpendicular to the second direction, and the first direction and the second direction being perpendicular to depth directions of the holes; a plurality of selection control gate rows distributed along the first direction, each of the selection control gate rows comprising a plurality of the selection control gates distributed along the second direction, the selection control gates being located in the holes in a one-to-one correspondence, and at least one sidewall of the trench comprising a sidewall of the selection control gate; The gate structures are located in the trenches in a one-to-one correspondence. The gate structures at least include a gate oxide layer and a gate arranged in sequence. One of the gate structures contacts a sidewall of each of the selection control gates in one selection control gate row.

13. The semiconductor device according to claim 12, wherein: A line connecting the center points of any two holes belonging to different hole rows is not on a straight line in the first direction.

14. The semiconductor device according to claim 12, wherein: Only one of the two sidewalls of the trench includes a sidewall of the select control gate.

15. The semiconductor device according to claim 12, wherein The two sidewalls of the trench respectively include sidewalls of the selection control gate.

16. The semiconductor device according to claim 15, wherein: The gate structure includes a barrier layer, a gate oxide layer and a gate which are sequentially arranged.

17. The semiconductor device according to any one of claims 12 to 16, characterized in that The semiconductor device also includes a source region, a drain region, a source electrode and a drain electrode. The source region and the drain region are located in the hole and are respectively located on both sides of the selection control gate. The source electrode is located on the surface of the source region away from the selection control gate, and the drain electrode is located on the surface of the drain region away from the selection control gate.

18. A three-dimensional memory, characterized in that: A semiconductor device comprising any one of claims 12 to 16 or a semiconductor device obtained by the manufacturing method of any one of claims 1 to 9.

19. A storage system, characterized in that: The invention comprises a memory controller and the three-dimensional memory of claim 18 , wherein the three-dimensional memory is configured to store data, and the memory controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory.

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