Thermal oxidation method and manufacturing method of semiconductor device

Abstract

The present application discloses a thermal oxidation method and manufacturing method for semiconductor devices. The thermal oxidation method includes: performing at least one temperature-raising oxidation process during the temperature-raising phase of thermal oxidation; performing at least one temperature-lowering oxidation process during the temperature-lowering phase of thermal oxidation; and simultaneously performing a constant-temperature oxidation process and a thermal annealing process during the constant-temperature phase of thermal oxidation, wherein the at least one temperature-raising oxidation process, the at least one temperature-lowering oxidation process, and the constant-temperature oxidation process jointly form an oxide layer, and the thermal annealing process is used for high-temperature push-up of the doped region. The thermal oxidation method utilizes multiple temperature stages of thermal treatment to perform multiple oxidation processes in combination to improve oxidation efficiency, reduce the process time of thermal oxidation, and thus increase production capacity.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and more particularly, to a thermal oxidation method and a manufacturing method of a semiconductor device. Background Art

[0002] During the manufacturing process of semiconductor devices, after ion implantation is used to form the doped regions, other processes, including high-temperature junction push-up and thermal oxidation, are generally required. The high-temperature junction push-up process, also known as thermal annealing, utilizes high temperatures to drive dopants into the semiconductor lattice and diffuse them within the semiconductor substrate to alter the dopant concentration profile and junction depth, thereby changing the electrical properties of the device. Thermal oxidation is one of the fundamental technologies in semiconductor device manufacturing. Thermal oxidation involves heat-treating the semiconductor substrate at high temperatures in an atmosphere of oxygen or water vapor to form an oxide layer. The oxide layer of a semiconductor device can serve as an interlayer dielectric layer, and its quality and thickness have a significant impact on the withstand voltage characteristics of the semiconductor device. Proper process control can ensure that the oxide layer has high quality, stable, and desired dielectric properties.

[0003] The above-mentioned high-temperature push-in process for the doped region and the thermal oxidation process for forming the oxide layer can both be completed using a high-temperature furnace. In order to increase production capacity, the two processes can be combined, for example, a high-temperature push-in process is performed during the thermal oxidation process. However, the thermal oxidation method of the prior art is relatively more suitable for the growth of thin oxide layers, but for thick oxide layers, it takes a long time and is not efficient, thereby restricting the improvement of product production capacity. For example, for some planar devices, when making a guard ring (GR), it is necessary to form an interlayer dielectric layer with a thickness of 10,000 to 25,000 angstroms, and in addition, a separate high-temperature push-in process is required, which makes the process time-consuming, even up to more than 15 hours.

[0004] Therefore, it is desired to further improve the thermal oxidation method of semiconductor devices to increase the efficiency and productivity of manufacturing semiconductor devices. Summary of the Invention

[0005] In view of this, an object of the present invention is to provide a thermal oxidation method and a manufacturing method for semiconductor devices, wherein multiple oxidation processes are combined and performed in the heating, constant temperature and cooling stages of thermal oxidation to improve the efficiency of the oxidation process, reduce the process time of thermal oxidation, and thus improve the production capacity of semiconductor devices.

[0006] According to one aspect of the present invention, there is provided a method for thermal oxidation of a semiconductor device, comprising:

[0007] During the temperature rise phase of thermal oxidation, performing at least one temperature rise oxidation process;

[0008] During the cooling stage of thermal oxidation, at least one cooling oxidation process is performed;

[0009] During the constant temperature stage of thermal oxidation, constant temperature oxidation treatment and thermal annealing treatment are performed simultaneously.

[0010] The at least one temperature-raising oxidation treatment, the at least one temperature-lowering oxidation treatment and the constant-temperature oxidation treatment together form an oxide layer, and the thermal annealing treatment is used for high-temperature push-in of the doped region.

[0011] Preferably, at least one temperature-raising oxidation treatment and at least one temperature-lowering oxidation treatment are performed in a high-temperature zone in the temperature-raising stage and a high-temperature zone in the temperature-lowering stage, respectively.

[0012] Preferably, the temperature range of the high temperature zone is greater than 900 degrees Celsius.

[0013] Preferably, the at least one elevated temperature oxidation treatment comprises one selected from the following oxidation processes: dry oxygen oxidation and wet oxygen oxidation.

[0014] Preferably, the at least one elevated temperature oxidation treatment comprises dry oxygen oxidation and wet oxygen oxidation performed in sequence.

[0015] Preferably, the dry oxygen oxidation is performed in the first heating stage from the time the boat enters the furnace tube to the time the furnace temperature reaches 900-1050 degrees Celsius, with a heating rate of 3-5 degrees Celsius / min.

[0016] Preferably, the wet oxygen oxidation is performed in a second temperature rising stage from 900-1050 degrees Celsius to 1150-1200 degrees Celsius, with a heating rate of 1-2 degrees Celsius / min.

[0017] Preferably, the at least one temperature reduction oxidation treatment comprises one selected from the following oxidation processes: wet oxygen oxidation and chlorine-doped oxidation.

[0018] Preferably, the at least one temperature-lowering oxidation treatment comprises wet oxygen oxidation and chlorine-doped oxidation performed in sequence.

[0019] Preferably, the wet oxygen oxidation is performed in a first cooling stage from 1150-1200 degrees Celsius to 1070-1100 degrees Celsius, with a cooling rate of 1-2 degrees Celsius / min.

[0020] Preferably, the chlorine-doped oxidation is performed in a second cooling stage from 1070-1100 degrees Celsius to 900-1050 degrees Celsius, with a cooling rate of 2-3 degrees Celsius / min.

[0021] Preferably, the process further includes a boat-entering process and a boat-outing process, wherein the furnace temperature during the boat-entering process is 750 degrees Celsius-800 degrees Celsius, and the furnace temperature during the boat-outing process is 750 degrees Celsius-800 degrees Celsius.

[0022] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0023] forming a doped region around a cell region of a semiconductor device;

[0024] forming an oxide layer by the thermal oxidation method described in the first aspect; and

[0025] Remove part of the oxide layer to expose the cell area.

[0026] The doped region is a doped region of the guard ring, and the doped region is subjected to thermal annealing treatment during the constant temperature stage of thermal oxidation.

[0027] Preferably, the semiconductor device is selected from any one of a Schottky diode, a vertical double diffused metal oxide semiconductor field effect transistor, and an insulated gate bipolar transistor.

[0028] According to the semiconductor device manufacturing method of an embodiment of the present invention, since multiple oxidation processes are combined in different stages of thermal oxidation, the oxide layer is grown using the temperature rise and temperature fall stages of the thermal oxidation process, thereby improving the efficiency of oxide layer film formation. Furthermore, the oxide layer is grown during the constant temperature stage while achieving a high-temperature push-through effect. The above-described thermal treatment process can form an interlayer dielectric layer with a thickness of 10,000 to 25,000 angstroms. For example, for an interlayer dielectric layer with a thickness of 18,000 angstroms, the thermal oxidation process can reduce the total process time by 4 hours, increasing production capacity by approximately 30%.

[0029] In a preferred embodiment, the thermal oxidation process combination is optimized at different stages of thermal oxidation. During the temperature rise stage of thermal oxidation, dry oxidation is sequentially used to begin growing a high-quality oxide layer, and then wet oxidation is used to grow the oxide layer. During the temperature drop stage of thermal oxidation, wet oxidation is sequentially used to grow the oxide layer, and then chlorine-doped oxidation is used to bind the mobile ions in the oxide layer. Therefore, the dry oxygen oxidation and chlorine-doped oxidation processes selected at the beginning and end of thermal oxidation are beneficial to the growth quality of the oxide layer, and the wet oxygen oxidation process selected in the middle of thermal oxidation is beneficial to the rapid growth of the oxide layer. Therefore, by utilizing the preferred oxidation process combination of the three stages of thermal oxidation, both the growth efficiency and the growth quality of the oxide layer can be taken into account.

[0030] Furthermore, during the constant temperature stage of the thermal treatment, the dopants in the guard ring enter and diffuse into the semiconductor lattice, achieving the desired dopant concentration profile and junction depth. Because the thermal treatment step includes the high-temperature junction-push-down process for the guard ring, a separate high-temperature junction-push-down process is not required, further saving process time. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0032] Figure 1 Shows a schematic structural diagram of a Schottky diode.

[0033] Figure 2 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0034] Figure 3 Show Figure 2 Flowchart of a thermal oxidation process of a semiconductor manufacturing method is shown.

[0035] Figure 4a and Figure 4b Schematic curves showing the temperature change over time according to a thermal oxidation method in the prior art and a thermal oxidation method according to an embodiment of the present invention are shown respectively.

[0036] Figure 5 Example graphs showing temperature changes over time according to a thermal oxidation method in the prior art and a thermal oxidation method according to an embodiment of the present invention are shown. DETAILED DESCRIPTION

[0037] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0038] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0039] To describe a situation where an element is directly located on another layer or region, this document uses the expression "A is directly on B" or "A is on and adjacent to B." In this application, "A is directly located in B" means that A is located in B and is directly adjacent to B, rather than that A is located in a doped region formed in B.

[0040] Many specific details of the present invention are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without these specific details.

[0041] The present invention may be embodied in various forms, some examples of which are described below.

[0042] Figure 1 Shows a schematic structural diagram of a Schottky diode.

[0043] The Schottky diode 10 includes a semiconductor substrate 11 , an epitaxial layer 12 on the front surface of the semiconductor substrate 11 , an anode metal 15 on the epitaxial layer 12 , and a cathode metal 16 on the back surface of the semiconductor substrate 11 .

[0044] The semiconductor substrate 11 and the epitaxial layer 12 are each composed of silicon, for example, and are each doped to an N-type. To form an N-type semiconductor layer or region, an N-type dopant (e.g., P, As) may be implanted into the semiconductor layer or region. The anode metal 15 and the cathode metal 16 are each composed of, for example, any metal material selected from aluminum, silver, copper, gold, platinum, molybdenum, tungsten, nickel, and titanium. The Schottky diode 10 utilizes a Schottky barrier formed by the contact between the anode metal 15 and the epitaxial layer 12 to provide unidirectional conductivity from the anode metal 15 to the cathode metal 16.

[0045] Furthermore, the Schottky diode 10 further includes a guard ring doping region 13 located in the epitaxial layer 12 and an interlayer dielectric layer 14 located on the epitaxial layer 12 .

[0046] The doped region 13 of the guard ring is, for example, a P-type doped region. In order to form a P-type semiconductor layer or region, a P-type dopant (for example, B) can be doped into the semiconductor layer and region. The interlayer dielectric layer 14 is, for example, composed of silicon oxide, and this interlayer dielectric layer is also called field oxide. The doped region 13 of the guard ring extends downward from the surface of the epitaxial layer 12, thereby forming a cell region of the Schottky diode 10 around a portion of the epitaxial layer 12. Inside the cell region, the anode metal 15 and the epitaxial layer 12 are in direct contact with each other to form a Schottky barrier. Outside the cell region, the interlayer dielectric layer 14 separates the anode metal 15 and the epitaxial layer 12 from each other.

[0047] In the Schottky diode 10, the doping type of the doped region 13 of the guard ring is opposite to the doping type of the epitaxial layer 12, and the two form a PN junction. When the Schottky diode 10 is in operation, the PN junction between the doped region 13 of the guard ring and the epitaxial layer 12 is reverse biased, which can reduce the edge surface peak electric field of the Schottky barrier. Therefore, the function of the guard ring is to improve the withstand voltage characteristics of the Schottky diode 10. As the withstand voltage characteristics of the Schottky diode 10 improve, the thickness of the interlayer dielectric layer 14 also needs to be increased accordingly to withstand higher voltage drops. If the thickness of the interlayer dielectric layer 14 is too small, the device may fail due to breakdown of the interlayer dielectric layer 14. Therefore, the thickness of the interlayer dielectric layer 14 is also an important structural parameter for improving the withstand voltage characteristics of the Schottky diode 10.

[0048] Figure 2 FIG. 1 is a flow chart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 Taking the Schottky diode shown in the figure as an example, main steps S01 to S05 of the semiconductor device manufacturing method are further described.

[0049] In step S01 , an epitaxial layer 12 is formed on a semiconductor substrate 11 .

[0050] For example, epitaxial layer 12 is formed using a known deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Semiconductor substrate 11 and epitaxial layer 12 are each composed of, for example, single-crystal silicon and are each doped to an N-type. Generally, epitaxial layer 12 is lightly doped relative to semiconductor substrate 11.

[0051] In step S02 , a guard ring doping region 13 is formed in the epitaxial layer 12 .

[0052] For example, a known ion implantation process is used to form the doped region 13 of the guard ring. The doped region 13 of the guard ring is, for example, a P-type doped region. In order to form a P-type semiconductor layer or region, a P-type dopant (e.g., B) can be doped into the semiconductor layer and region. By controlling the parameters of the ion implantation, such as the implantation energy and dose, the desired depth and the desired doping concentration can be achieved. The doped region 13 of the guard ring extends downward from the surface of the epitaxial layer 12, thereby forming a cell region of the Schottky diode 10 around a portion of the epitaxial layer 12.

[0053] In step S03 , the interlayer dielectric layer 14 is formed by thermal oxidation. The thermal oxidation process includes a high-temperature push-up stage of the guard ring, and therefore, no separate high-temperature push-up process is required.

[0054] In this step, the wafers that have completed the above steps are placed on a boat and then sent together into a high-temperature furnace for thermal oxidation.

[0055] Before thermal oxidation, the furnace temperature is set to 750-800° C. Compared with the existing boat entry temperature of 600-650° C., the boat entry temperature of the embodiment of the present invention can save 20-30 minutes of preheating time from the boat entering the furnace tube to the start of oxidation.

[0056] After thermal oxidation, the furnace temperature is set to 750-800°C at a cooling rate of 3-4°C / min. Compared to the existing boat exit temperature of 600-650°C, the boat exit temperature of the embodiment of the present invention can save 40-50 minutes of cooling time from the end of oxidation to boat removal.

[0057] The thermal oxidation process is divided into a temperature rise phase, a constant temperature phase, and a temperature drop phase. Unlike conventional thermal oxidation, the semiconductor device manufacturing method according to an embodiment of the present invention combines multiple oxidation processes in the three phases of the thermal oxidation process to improve oxidation process efficiency and reduce the thermal oxidation process time.

[0058] The various oxidation processes mentioned above include dry oxygen oxidation, wet oxygen oxidation, and chlorine-doped oxidation. In dry oxygen oxidation, oxygen is introduced into a high-temperature furnace, and silicon oxide is generated by a chemical reaction between silicon and oxygen. In wet oxygen oxidation, a mixture of oxygen and hydrogen is introduced into a high-temperature furnace, and silicon oxide is generated by a chemical reaction between silicon and an oxidant (oxygen and water vapor). In chlorine-doped oxidation, oxygen and a chlorine-containing compound (such as hydrogen chloride) are introduced into a high-temperature furnace, and silicon oxide is generated by a chemical reaction between silicon, oxygen, and the chlorine-containing compound.

[0059] Among the various oxidation processes mentioned above, wet oxygen oxidation has a relatively high reaction rate. Compared to wet oxygen oxidation, dry oxygen oxidation and chlorine-doped oxidation produce denser silicon oxide structures, with highly uniform and reproducible oxide layers. Furthermore, chlorine-doped oxidation can produce chlorine-containing silicon oxide, thereby reducing mobile ion contamination, such as mobile sodium ions, in the silicon oxide, improving the electrical performance and reliability of semiconductor devices.

[0060] In step S04 , a portion of the interlayer dielectric layer 14 is removed to expose the surface of the epitaxial layer 12 .

[0061] In this step, a photoresist layer is formed on the interlayer dielectric layer 14 and then etched. This etching can be done using dry etching methods such as ion milling, plasma etching, reactive ion etching, or laser ablation, or by selective wet etching using an etchant solution, etching downward from the opening in the photoresist mask to form an opening in the interlayer dielectric layer 14. Due to the selectivity of the etching, the etching can stop at the surface of the epitaxial layer 12. Finally, the photoresist layer is removed by dissolving in a solvent or ashing.

[0062] This step forms an opening in the interlayer dielectric layer 14 to expose the surface of the epitaxial layer 12. Generally, the edge of the opening in the interlayer dielectric layer 14 is located above the guard ring 13, and the two together define the cell region of the Schottky diode 10.

[0063] In step S05 , the anode metal 15 and the cathode metal 16 are formed.

[0064] In this step, anode metal 15 is formed on the surface of epitaxial layer 12 and cathode metal 16 is formed on the back surface of semiconductor substrate 11 by, for example, sputtering.

[0065] The anode metal 15 and cathode metal 16 are each composed of, for example, any metal material selected from aluminum, silver, copper, gold, platinum, molybdenum, tungsten, nickel, and titanium. The anode metal 15 contacts the epitaxial layer 12 to form a Schottky barrier. Within the cell region surrounded by the guard ring, the anode metal 15 and the epitaxial layer 12 are in direct contact with each other, thereby forming a Schottky barrier. Outside the cell region surrounded by the guard ring, an interlayer dielectric layer 14 separates the anode metal 15 from the epitaxial layer 12.

[0066] According to the semiconductor device manufacturing method of an embodiment of the present invention, by combining multiple oxidation processes at different stages of thermal oxidation, both the quality and growth efficiency of the oxide layer can be balanced. In particular, utilizing the temperature rise and temperature fall stages of thermal oxidation to grow the oxide layer can further improve the oxide layer growth efficiency. The above-described thermal treatment process can form an interlayer dielectric layer having a thickness of 10,000 to 25,000 angstroms, and in particular, an interlayer dielectric layer having a thickness of 15,000 to 25,000 angstroms.

[0067] Furthermore, during the constant temperature stage of the thermal treatment, the dopants in the guard ring enter and diffuse into the semiconductor lattice to achieve the desired concentration profile and junction depth. Because the thermal treatment step includes the high-temperature junction-push-down process for the guard ring, a separate high-temperature junction-push-down process is not required, further saving process time.

[0068] Figure 3 Show Figure 2 The flow chart of the thermal oxidation process of the semiconductor manufacturing method is shown. Figure 3 Further described in Figure 2 Detailed steps of step S03.

[0069] Step S03 includes sub-steps S11 to S15. Steps S11 and S12 are the first and second temperature-raising oxidations, respectively, and are performed sequentially during the temperature-raising phase of the heat treatment. Step S13 is the constant temperature oxidation. Steps S14 and S15 are the first and second temperature-lowering oxidations, respectively, and are performed sequentially during the temperature-lowering phase of the heat treatment.

[0070] In step S11, the thermal oxidation temperature rise phase includes a first temperature rise phase from the time the boat enters the furnace tube to the time the furnace temperature reaches 900-1050°C, typically 1000-1050°C, with a temperature rise rate of 3-5°C / min. The first temperature rise oxidation phase involves introducing oxygen into the high-temperature furnace, and dry oxygen oxidation is performed during the first temperature rise phase.

[0071] In step S12, the thermal oxidation temperature rise stage includes a second temperature rise stage from 900-1050°C to 1150-1200°C at a rate of 1-2°C / min. The second temperature rise oxidation includes introducing a mixed gas of oxygen and hydrogen into the high-temperature furnace, and performing wet oxygen oxidation during the temperature rise process of the second temperature rise stage.

[0072] In step S13, the constant temperature stage of thermal oxidation includes maintaining the temperature at 1150-1200° C. for 80-100 minutes. The constant temperature oxidation includes introducing a mixed gas of oxygen and hydrogen into the high temperature furnace and performing wet oxygen oxidation during the constant temperature stage.

[0073] Furthermore, the constant-temperature stage of thermal oxidation also serves as a high-temperature push-in process for the guard ring. Dopants in the guard ring diffuse into the semiconductor lattice to achieve the desired dopant concentration profile and junction depth. Because the thermal treatment step includes the high-temperature push-in process for the guard ring, a separate high-temperature push-in process is not required, further reducing process time.

[0074] In step S14, the thermal oxidation cooling stage includes a first cooling stage from 1150-1200°C to 1070-1100°C at a cooling rate of 1-2°C / min. The first cooling oxidation stage includes introducing a mixed gas of oxygen and hydrogen into the high-temperature furnace, and performing wet oxygen oxidation during the cooling process of the first cooling stage.

[0075] In step S15, the thermal oxidation cooling stage includes a second cooling stage from 1070-1100°C to 900-1050°C at a cooling rate of 2-3°C / min. The second cooling oxidation stage involves introducing a mixed gas of oxygen and a chlorine-containing compound into the high-temperature furnace, and performing chlorine-doped oxidation during the cooling process of the second cooling stage. Typically, the temperature in the second cooling stage is reduced from 1070-1100°C to 1030-1050°C.

[0076] Figure 4a and Figure 4b Schematic curves showing the temperature change over time according to a thermal oxidation method in the prior art and a thermal oxidation method according to an embodiment of the present invention are shown respectively. Figure 5 Example graphs showing temperature changes over time according to a thermal oxidation method in the prior art and a thermal oxidation method according to an embodiment of the present invention are shown.

[0077] According to the thermal oxidation method of the prior art, the heating stage, constant temperature stage and cooling stage in the thermal oxidation process are used for preheating, constant temperature oxidation and cooling, respectively. According to the thermal oxidation method of an embodiment of the present invention, oxidation treatment is performed in the heating stage, constant temperature stage and cooling stage in the thermal oxidation process. The high temperature zone (above 900°C) in the heating stage and the cooling stage is used to provide an effective oxidation reaction time. The growth of the oxide layer by using the heating stage, constant temperature stage and cooling stage of thermal oxidation can significantly improve the growth efficiency of the oxide layer.

[0078] Compared to the process time T1 of the thermal oxidation method in the prior art, the process time T2 of the thermal oxidation method according to the embodiment of the present invention is significantly reduced.

[0079] The above heat treatment process can form an interlayer dielectric layer with a thickness of 10,000 to 25,000 angstroms. Figure 5 The reduction in process time is primarily due to a significant reduction in the constant temperature phase. By optimizing these process methods and conditions, production efficiency has been significantly improved while maintaining process quality. For example, for an interlayer dielectric layer with a thickness of 18,000 angstroms, the thermal oxidation step reduces the total process time by 4 hours, increasing production capacity by approximately 30%.

[0080] In the above embodiment, the main steps of the semiconductor device manufacturing method are described using a Schottky diode as an example. The Schottky diode includes a Schottky barrier formed between an anode metal and an epitaxial layer. In alternative embodiments, some steps may be omitted depending on the device structure. For example, if a Schottky barrier is formed between the anode metal and the semiconductor substrate, the step of forming an epitaxial layer on the semiconductor substrate may be omitted.

[0081] Generally, in semiconductor manufacturing, low-temperature oxidation is typically used to precisely control oxide film thickness and junction depth, avoiding the effects of high temperatures during oxidation that could affect dopant concentration distribution and junction depth. During the push-through junction process, inert gases such as nitrogen or argon are introduced as ambient gases to prevent other ambient gases (e.g., oxygen) from participating in the reaction and affecting dopant concentration distribution and junction depth. In the embodiments of the present invention, however, oxygen and water vapor (hydrogen and oxygen reactants) are used as ambient gases, balancing high-temperature oxidation and high-temperature push-through junction processes. This allows for a thicker interlayer dielectric layer while ensuring that the dopant concentration distribution and junction depth meet process requirements.

[0082] It should be understood that the above-described heat treatment method is not limited to Schottky diodes and can also be applied to any semiconductor device in which a guard ring and an interlayer dielectric layer are formed in sequence. For example, in products such as vertical double-diffused metal oxide semiconductor field-effect transistors (VDMOS) and insulated gate bipolar transistors (IGBTs), where the guard ring surrounds the cell region and the interlayer dielectric layer is located above the doped region of the guard ring, the above-described heat treatment method can also be used to form the interlayer dielectric layer and perform high-temperature push-through of the guard ring doped region during the heat treatment process.

[0083] It should also be noted that high-temperature pushing and unwinding are inevitable during the heating and cooling stages of the thermal oxidation. However, compared with the constant temperature stage, the high-temperature pushing and unwinding during the heating and cooling stages are negligible, so they will not be further explained.

[0084] It should be noted that, in this document, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, but do not necessarily require or imply any actual relationship or order between these entities or operations.

[0085] The embodiments of the present invention are described above, and all details are not exhaustive, nor is the invention limited to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. These embodiments are selected and described in detail in this specification in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for thermal oxidation of a semiconductor device, comprising: During the temperature rise phase of thermal oxidation, at least one temperature rise oxidation process is performed, wherein the at least one temperature rise oxidation process comprises one selected from the following oxidation processes: dry oxygen oxidation and wet oxygen oxidation; In the cooling stage of thermal oxidation, at least one cooling oxidation process is performed, wherein the at least one cooling oxidation process comprises one selected from the following oxidation processes: wet oxygen oxidation and chlorine-doped oxidation; During the constant temperature stage of thermal oxidation, constant temperature oxidation treatment and thermal annealing treatment are performed simultaneously. The at least one temperature-raising oxidation treatment, the at least one temperature-lowering oxidation treatment, and the constant-temperature oxidation treatment together form an oxide layer, the thickness of the oxide layer is 10,000 angstroms to 25,000 angstroms, and the thermal annealing treatment is used for high-temperature push-in of the doped region; The at least one temperature-raising oxidation treatment and the at least one temperature-lowering oxidation treatment are performed in a high temperature zone of the temperature-raising stage and a high temperature zone of the temperature-lowering stage, respectively. The temperature range of the high temperature zone is greater than 900°C.

2. The thermal oxidation method according to claim 1, wherein The at least one elevated temperature oxidation process includes dry oxygen oxidation and wet oxygen oxidation performed in sequence.

3. The thermal oxidation method according to claim 2, wherein: The dry oxygen oxidation is performed in the first heating stage from the time the boat enters the furnace tube to the time the furnace temperature reaches 900-1050° C., with a heating rate of 3-5° C. / min.

4. The thermal oxidation method according to claim 2, wherein: The wet oxygen oxidation is performed in the second temperature rising stage from 900-1050° C. to 1150-1200° C. at a heating rate of 1-2° C. / min.

5. The thermal oxidation method according to claim 1, wherein The at least one temperature-lowering oxidation treatment includes wet oxygen oxidation and chlorine-doped oxidation performed in sequence.

6. The thermal oxidation method according to claim 5, wherein: The wet oxygen oxidation is performed in a first cooling stage from 1150-1200° C. to 1070-1100° C. at a cooling rate of 1-2° C. / min.

7. The thermal oxidation method according to claim 5, wherein: The chlorine-doped oxidation is performed in a second cooling stage from 1070-1100° C. to 900-1050° C., with a cooling rate of 2-3° C. / min.

8. The thermal oxidation method according to any one of claims 1 to 7, wherein: It also includes a process of entering the boat and a process of leaving the boat, wherein the furnace temperature during entering the boat is 750°C-800°C, and the furnace temperature during leaving the boat is 750°C-800°C.

9. A method for manufacturing a semiconductor device, comprising: forming a doped region around a cell region of a semiconductor device; Forming an oxide layer using the thermal oxidation method according to any one of claims 1 to 8; as well as removing a portion of the oxide layer to expose the cell region, The doped region is a doped region of a guard ring, and a thermal annealing process is performed on the doped region during the constant temperature stage of the thermal oxidation.

10. The manufacturing method according to claim 9, wherein: The semiconductor device is selected from any one of a Schottky diode, a vertical double diffused metal oxide semiconductor field effect transistor, and an insulated gate bipolar transistor.

Images