Methods for fabricating vacuum bonding components and chip packages

Abstract

This invention provides a method for preparing a vacuum bonding component and a chip package. The bonding component includes a suction cup carrier and a sealing gasket. The suction cup carrier has a bearing surface and a non-bearing surface. A negative pressure adsorption channel is provided on the bearing surface, and a flow guiding channel connected to the negative pressure adsorption channel is provided inside the suction cup carrier. An air extraction channel is provided on the non-bearing surface, so that the air extraction channel and the flow guiding channel are interconnected. The sealing gasket with an airtight through-hole is detachably disposed on the bearing surface, so that the airtight through-hole is interconnected with the negative pressure adsorption channel, forming a bearing area for supporting the chip package. This invention solves the problem of residual bonding adhesive in the chip package in the prior art, improves the reliability of the chip package, and also reduces the cost of raw materials and the process control cost of debonding.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and more specifically to a method for preparing vacuum bonding components and chip packages. Background Technology

[0002] In existing industrial production, in the fabrication process of chip fan-out packaging structures, a carrier with a high Young's modulus is added as a process carrier for chip packaging, providing mechanical support against gravity for the fabrication of multilayer high-density RDL layers. The addition of the carrier usually involves attaching a layer of ultraviolet bonding film to the carrier. After the chip packaging process is completed, the ultraviolet light reacts with the photosensitizer in the bonding film, causing the bonding film to debond from the carrier and the chip packaging substrate, thereby achieving the purpose of separating the carrier from the chip package.

[0003] However, during the debonding process, the components of the bonding adhesive layer usually cannot fully react chemically with ultraviolet light. Therefore, after debonding, bonding adhesive residue is usually left on the chip package, which has an extremely adverse effect on the chip's signal transmission, power supply, and the reliability of the chip package.

[0004] It is evident that existing chip packaging methods suffer from residual bonding adhesive, which adversely affects signal transmission and power supply, thereby reducing the reliability of the chip package. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the vacuum bonding component and chip package preparation method provided by the present invention solves the problem of residual bonding adhesive in the chip package in the prior art, improves the reliability of the chip package, and reduces the cost of raw materials and the process control cost of debonding.

[0006] In a first aspect, the present invention provides a vacuum bonding component, the bonding component comprising: a suction cup carrier and a sealing gasket; the suction cup carrier having a bearing surface and a non-bearing surface, the bearing surface having a negative pressure adsorption channel, the suction cup carrier having a guide channel communicating with the negative pressure adsorption channel, the non-bearing surface having an air extraction channel, and the air extraction channel communicating with the guide channel; the sealing gasket having an airtight through hole and being detachably disposed on the bearing surface, wherein the airtight through hole communicating with the negative pressure adsorption channel, forming a bearing area for bearing a chip package.

[0007] Optionally, the sealing gasket may comprise an elastic material.

[0008] Secondly, the present invention provides a method for fabricating a chip package, the method comprising: providing a vacuum bonding component; providing a chip, placing the passive surface of the chip in the bearing area of ​​the vacuum bonding component, wherein conductive interconnect pillars are disposed on the active surface of the chip, and the passive surface of the chip is a crystalline silicon substrate with a mirror effect obtained by precision grinding; performing a vacuum treatment on the vacuum bonding component through a vacuum channel; sequentially fabricating a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the conductive interconnect pillars; and releasing the vacuum adsorption force through the vacuum channel to remove the vacuum bonding component, thereby obtaining a chip package.

[0009] Optionally, a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls are sequentially fabricated on the conductive interconnect pillars, including: filling the chip with molding compound to form an encapsulation layer, such that the upper surface of the encapsulation layer is at the same level as the top of the conductive interconnect pillars; and sequentially fabricating a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the upper surface of the encapsulation layer.

[0010] Optionally, after sequentially fabricating a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the conductive interconnect pillars, the method further includes: applying a protective film to the tin-based alloy solder balls.

[0011] Thirdly, the present invention provides a method for preparing a chip package, the method comprising: providing a vacuum bonding component; providing a metal foil and covering the carrier area of ​​the vacuum bonding component with the metal foil; performing a vacuum treatment on the vacuum bonding component through a vacuum channel; preparing a metal wiring layer on the metal foil, so that the conductive interconnect pillars on the active surface of the chip are electrically interconnected with the metal wiring layer; releasing the vacuum adsorption force through the vacuum channel and removing the vacuum bonding component to obtain a pre-package; preparing conductive pillars and tin-based alloy solder balls on the surface of the metal foil on the pre-package to obtain the chip package.

[0012] Optionally, before releasing the vacuum adsorption force through the air extraction channel, the method further includes: filling the chip with molding compound to form an encapsulation layer, such that the upper surface of the encapsulation layer is at the same level as the passive surface of the chip.

[0013] Optionally, before filling the chip with molding compound to form an encapsulation layer, the method further includes: bottom filling the conductive interconnect pillars to obtain an underfill layer.

[0014] Optionally, conductive pillars and tin-based alloy solder balls are prepared on the surface of the metal foil on the pre-package to obtain a chip package, including: preparing an organic solder resist film on the surface of the metal foil on the pre-package; and preparing conductive pillars and tin-based alloy solder balls by photolithography opening, cleaning and copper electroplating processes on the organic solder resist film to obtain the chip package.

[0015] Optionally, the sealing gasket material includes silicone; and / or the metal foil includes copper foil; and / or the encapsulation layer material includes epoxy resin.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] This invention provides stress buffering between the suture carrier and the chip to be packaged through a sealing gasket. A vacuum negative pressure is created between the negative pressure adsorption channel, flow channel, and air extraction channel built into the suture carrier and the airtight through-hole of the sealing gasket, achieving a tight fit between the chip to be packaged, the sealing gasket, and the suture carrier. Furthermore, when chip packaging is complete, gas is injected through the air extraction channel to reduce the pressure difference between the suture carrier and the external atmosphere, releasing the vacuum adsorption force and thus removing the vacuum bonding components to obtain the chip package. Therefore, this invention eliminates the bonding adhesive residue problem present in existing industrial production, improving the reliability of the chip package. Moreover, this embodiment does not use the bonding adhesive film and debonding process in the prior art, reducing raw material costs and debonding process control costs. Attached Figure Description

[0018] Figure 1 The figure shown is a structural schematic diagram of a vacuum bonding component provided in an embodiment of the present invention;

[0019] Figure 2 The diagram shown is a flowchart illustrating a method for fabricating a chip package according to an embodiment of the present invention.

[0020] Figure 3 The diagram shown is a schematic of placing a chip to be packaged on a vacuum bonding component according to an embodiment of the present invention;

[0021] Figure 4 The diagram shown is a schematic diagram of an embodiment of the present invention for preparing an encapsulation layer;

[0022] Figure 5 The diagram shown is a schematic diagram of a method for preparing a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls according to an embodiment of the present invention.

[0023] Figure 6 The diagram shown is a schematic diagram of a protective film application according to an embodiment of the present invention;

[0024] Figure 7 The diagram shown is a schematic representation of a chip package according to an embodiment of the present invention.

[0025] Figure 8 The diagram shown is a flowchart illustrating another method for preparing a chip package according to an embodiment of the present invention.

[0026] Figure 9 The diagram shown is a schematic diagram of placing a metal foil on a vacuum bonding component according to an embodiment of the present invention;

[0027] Figure 10 The diagram shown is a schematic representation of the fabrication of a metal wiring layer and pads according to an embodiment of the present invention.

[0028] Figure 11 The diagram shown is a connection diagram between a metal wiring layer and a chip to be packaged according to an embodiment of the present invention.

[0029] Figure 12 The diagram shown is a schematic diagram of the preparation of a filler layer and an encapsulation layer according to an embodiment of the present invention;

[0030] Figure 13 The diagram shown is a structural schematic of another chip package provided in an embodiment of the present invention. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In a first aspect, the present invention provides a vacuum bonding component, specifically including the following embodiments:

[0033] Example 1

[0034] Figure 1 The diagram shown is a structural schematic of a vacuum bonding component provided in an embodiment of the present invention; as follows: Figure 1 As shown, the vacuum bonding component includes:

[0035] Suction cup carrier 10 and sealing gasket 11;

[0036] The suction cup carrier 10 has a bearing surface and a non-bearing surface. The bearing surface is provided with a negative pressure adsorption channel 10a. The suction cup carrier 10 is provided with a guide channel 10b that is connected to the negative pressure adsorption channel 10a. The non-bearing surface is provided with an air extraction channel 10c, so that the air extraction channel 10c and the guide channel 10b are interconnected.

[0037] The sealing gasket 11 has an airtight through hole 12 and is detachably disposed on the bearing surface, wherein the airtight through hole 12 is interconnected with the negative pressure adsorption channel 10a to form a bearing area for bearing the chip package.

[0038] In this embodiment, the sealing gasket comprises an elastic material.

[0039] It should be noted that the suction cup carrier 10 in this embodiment is provided with a negative pressure adsorption channel 10a, a flow channel 10b and an air extraction channel 10c that are interconnected. The negative pressure adsorption channel 10a is connected through the airtight through hole 12 in the sealing gasket 11, thereby forming a carrier area for carrying the chip package.

[0040] During the preparation of the chip package, the chip to be packaged is placed in the carrier area, and the vacuum bonding component is evacuated. Air is then drawn away from the vacuum bonding component through the airtight through-hole 12, the negative pressure adsorption channel 10a, the flow channel 10b, and the air extraction channel 10c in sequence. Under the action of external atmospheric pressure, the chip to be packaged, the sealing gasket 11, and the suction cup carrier 10 are tightly bonded together. The tight bonding force between the three depends on the negative pressure established by the vacuum. The elastic characteristics of the sealing gasket can provide a buffer layer that plays a sealing role for the establishment of the vacuum negative pressure cavity.

[0041] When the chip packaging is completed, gas is injected through the evacuation channel 10c to reduce the pressure difference between the suction cup carrier 10 and the outside atmosphere, thereby releasing the vacuum adsorption force and removing the vacuum bonding component to obtain the chip package.

[0042] Compared with the prior art, this embodiment has the following beneficial effects:

[0043] In this embodiment, the sealing gasket 11 provides stress buffering between the suction cup carrier 10 and the chip to be packaged. A vacuum negative pressure is created between the negative pressure adsorption channel 10a, the flow channel 10b, the air extraction channel 10c built into the suction cup carrier 10 and the airtight through-hole of the sealing gasket 11, achieving a tight fit between the chip to be packaged, the sealing gasket 11, and the suction cup carrier 10. Furthermore, when the chip packaging is complete, gas is injected through the air extraction channel 10c to reduce the pressure difference between the suction cup carrier 10 and the external atmospheric pressure, releasing the vacuum adsorption force and thus removing the vacuum bonding component to obtain the chip package. Therefore, this embodiment does not require the use of bonding adhesive film, eliminating the bonding adhesive residue problem present in existing industrial production and improving the reliability of the chip package. Moreover, this embodiment does not employ the bonding adhesive film and debonding process of existing technologies, reducing raw material costs and debonding process control costs.

[0044] In this embodiment, the non-load-bearing surface includes, but is not limited to, the bottom surface or sidewall of the suction cup carrier 10.

[0045] In this embodiment, the sealing gasket 11 is an elastic silicone material, and the passive surface of the chip is a crystalline silicon substrate with a mirror effect obtained by precision grinding. The silicone material has a certain elasticity to bond the suction cup carrier 10 and the chip together. The elastic silicone material can absorb the stress caused by the tight bonding between the passive surface of the chip silicon substrate with high Young's modulus and the suction cup carrier 10.

[0046] Secondly, the present invention provides a method for preparing a chip package, specifically including the following embodiments:

[0047] Example 2

[0048] Figure 2 The diagram shown is a flowchart illustrating a method for fabricating a chip package according to an embodiment of the present invention; as follows: Figure 2 As shown, the preparation method specifically includes:

[0049] Step S101: Provide a vacuum bonding component;

[0050] Step S102: Provide a chip, and place the passive surface of the chip in the bearing area of ​​the vacuum bonding component, wherein the active surface of the chip is provided with conductive interconnect pillars, and the passive surface of the chip is a crystalline silicon substrate with a mirror effect obtained by precision grinding.

[0051] Step S103: Vacuum treatment is performed on the vacuum bonding component through the air extraction channel;

[0052] Step S104: Sequentially fabricate a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the conductive interconnect pillars;

[0053] Step S105: Release the vacuum adsorption force through the air extraction channel, remove the vacuum bonding component, and obtain the chip package.

[0054] In this embodiment, a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls are sequentially fabricated on the conductive interconnect pillars. This includes: filling the chip with molding compound to form an encapsulation layer, such that the upper surface of the encapsulation layer is at the same level as the top of the conductive interconnect pillars; and sequentially fabricating a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the upper surface of the encapsulation layer.

[0055] In this embodiment, after sequentially preparing a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the conductive interconnect pillars, the method further includes: applying a protective film to the tin-based alloy solder balls.

[0056] It should be noted that, as Figure 3As shown, the passive surface of the chip 100 to be packaged is attached to the chuck carrier 10 through the sealing gasket 11. The vacuum bonding component is vacuumed until the passive surface of the chip, the sealing gasket 11 and the chuck carrier 10 can be tightly attached together. The active surface of the chip corresponds to the conductive interconnect post 20, and the passive surface of the chip is a crystalline silicon substrate with a mirror effect obtained by precision grinding.

[0057] In this embodiment, the airtight through-hole 12 on the sealing gasket 11 is located within the crystalline silicon substrate of the passive surface of the chip, and the airtight through-hole 12 corresponds one-to-one with the negative pressure adsorption channel 10a, allowing air to circulate between the two.

[0058] like Figure 4 As shown, the chip is filled with molding compound to form an encapsulation layer 13, which completely covers the conductive interconnect post 20. The encapsulation layer 13 is then thinned until the conductive interconnect post 20 is exposed, so that the upper surface of the encapsulation layer 13 is at the same level as the top of the conductive interconnect post 20.

[0059] like Figure 5 As shown, a metal wiring layer 21, pads 22a, conductive pillars 23 and tin-based alloy solder blocks are prepared on the encapsulation layer 13, and the tin-based alloy solder blocks are formed into tin-based alloy solder balls 24 in a high-temperature reflow process.

[0060] like Figure 6 As shown, a protective film 14 is attached to the tin-based alloy solder ball 24. The chip package is adsorbed along the protective film 14, and gas is slowly introduced into the vacuum channel 10c to reduce the pressure difference between the internal channel of the suction cup carrier 10 and the external atmospheric pressure, thereby releasing the vacuum adsorption force and removing the suction cup carrier 10. The surface of the sealing gasket 11 contacts the passive surface of the chip, the hermetically sealed through-hole 12, and part of the encapsulation layer 13. Since the contact area between the sealing gasket 11 and the encapsulation layer 13 is relatively small, the mechanical force required to tear the sealing gasket 11 can be increased until the sealing gasket 11 is removed. Then, the protective film 1414 is removed, resulting in the package as shown. Figure 7 The chip package shown.

[0061] Compared with the prior art, this embodiment has the following beneficial effects:

[0062] In existing industrial production, the chip package and carrier are bonded together using a bonding adhesive film. After the chip packaging process is completed, the bonding adhesive film and carrier are peeled off from the chip package through debonding. However, during the debonding process, the components of the bonding adhesive layer often cannot fully react chemically with ultraviolet light, resulting in bonding adhesive residue on the chip package that comes into contact with the bonding adhesive film. In this embodiment, an elastic silicone sealing gasket 11 provides stress buffering for the passive surfaces of the chuck carrier 10 and the chip, and a negative pressure adsorption channel 1 is built into the chuck carrier 10. A vacuum negative pressure is constructed between the flow channel 10a, the air extraction channel 10c, and the airtight through-holes 12 arranged on the elastic silicone sealing gasket 11. The elastic characteristics of the elastic silicone sealing gasket can provide a buffer layer that plays a sealing role for the establishment of the vacuum negative pressure cavity, so as to achieve a tight fit between the suction cup carrier 10, the elastic silicone sealing gasket 11, and the passive surface of the chip. Therefore, there is no problem of bonding adhesive residue in existing industrial production. Since bonding adhesive film and debonding process are not used, the cost of raw materials and the process control cost of debonding are also reduced.

[0063] Thirdly, the present invention provides another method for preparing a chip package, specifically including the following embodiments:

[0064] Example 3

[0065] Figure 8 The diagram shown is a flowchart illustrating another method for fabricating a chip package according to an embodiment of the present invention; as follows: Figure 8 As shown, the preparation method specifically includes:

[0066] Step S201: Provide a vacuum bonding component;

[0067] Step S202: Provide a metal foil and cover the bearing area of ​​the vacuum bonding component with the metal foil;

[0068] Step S203: Vacuum treatment is performed on the vacuum bonding component through the vacuum extraction channel;

[0069] Step S204: Prepare a metal wiring layer on the metal foil to make the conductive interconnect pillars on the active surface of the chip interconnected with the metal wiring layer.

[0070] Step S205: Release the vacuum adsorption force through the air extraction channel, remove the vacuum bonding component, and obtain the pre-packaged body;

[0071] Step S206: Conductive pillars and tin-based alloy solder balls are prepared on the surface of the metal foil on the pre-packaged body to obtain the chip package.

[0072] In this embodiment, before releasing the vacuum adsorption force through the air extraction channel, the method further includes: filling the chip with molding compound to form an encapsulation layer, such that the upper surface of the encapsulation layer is at the same level as the passive surface of the chip.

[0073] In this embodiment, before filling the chip with molding compound to form an encapsulation layer, the method further includes: bottom filling the conductive interconnect pillars to obtain an underfill layer.

[0074] In this embodiment, conductive pillars and tin-based alloy solder balls are fabricated on the surface of the metal foil on the pre-packaged body to obtain a chip package. This includes: fabricating an organic solderability preservative layer on the surface of the metal foil on the pre-packaged body; and performing photolithography opening, cleaning, and copper electroplating processes on the organic solderability preservative layer to fabricate conductive pillars and tin-based alloy solder balls to obtain the chip package. The metal foil at the opening of the organic solderability preservative layer is positioned to correspond to and interconnect with the conductive pillars.

[0075] In this embodiment, the material of the sealing gasket includes silicone; and / or the metal foil includes copper foil; and / or the material of the encapsulation layer includes epoxy resin.

[0076] It should be noted that, as Figure 9 As shown, the metal foil 30 is attached to the suction cup carrier 10 through the sealing gasket 11. The vacuum bonding component is vacuumed until the metal foil 30, the sealing gasket 11, and the suction cup carrier 10 are tightly attached together. The airtight through hole 12 on the sealing gasket 11 corresponds to the negative pressure adsorption channel 10a, allowing air to circulate between them. The metal foil 30 is preferably a copper foil with excellent conductivity.

[0077] like Figure 10 As shown, the surface of the metal foil 30 is deoxidized, and a metal wiring layer 21 and a bonding pad 22b are prepared on this surface; as Figure 11 As shown, the conductive interconnect pillars 20 of the chip correspond to the connecting pads 22b; wherein, the part where the conductive interconnect pillars 20 and the connecting pads 22b contact is a tin-based alloy solder block, and a conductive interconnection is formed between the conductive interconnect pillars 20 and the connecting pads 22b during the high-temperature reflow process.

[0078] like Figure 12 As shown, a protective adhesive is applied to the bottom of the conductive interconnect pillar 20 of the chip to obtain a bottom filler layer 15. The chip is then encapsulated with epoxy resin to obtain an encapsulation layer 13. The encapsulation layer 13 is then thinned until the crystalline silicon substrate on the passive surface of the chip is exposed, so that the upper surface of the encapsulation layer 13 is at the same level as the passive surface of the chip.

[0079] Further, the base surface where the passive surface of the adsorption chip is located is subjected to adsorption, and gas is slowly introduced into the evacuation channel to reduce the pressure difference between the internal channel of the chuck carrier 10 and the external atmospheric pressure, thereby relieving the vacuum adsorption force. Then, the sealing gasket 11 and the chuck carrier 10 are slidably removed. An organic solderability preservative is prepared on the surface of the metal foil 30, and the organic solderability preservative at the corresponding part of the conductive pillar is removed by photolithography and cleaning processes. Then, the conductive pillar and tin-based alloy solder block are prepared by electroplating copper. The subsequent high-temperature reflow process melts the tin-based alloy solder block and forms tin-based alloy solder balls 24 under the action of surface tension, thus preparing the desired product. Figure 13 The chip packaging structure shown is as follows: the metal foil 30 is preferably copper foil; the ground layer in the metal wiring layer 21 is electrically interconnected with the metal foil 30, which has an electromagnetic shielding effect on the signal transmission of the chip.

[0080] Compared with the prior art, this embodiment has the following beneficial effects:

[0081] In this embodiment, the sealing gasket 11 provides a stress buffer for the metal foil 30 on the suction cup carrier 10, achieving a tight fit between the metal foil 30, the sealing gasket 11, and the suction cup carrier 10. Compared with the existing industrial production process of chip packages, this embodiment does not require debonding the bonding film, so there is no problem of bonding adhesive residue. In addition, the metal foil 30 is electrically interconnected with the ground layer in the metal wiring layer 21, which has an electromagnetic shielding effect on the signal transmission of the chip.

[0082] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for preparing a chip package, characterized in that, The method includes: Provide vacuum bonding components; A chip is provided, wherein conductive interconnect pillars are disposed on the active surface of the chip, and the passive surface of the chip is a crystalline silicon substrate with a mirror effect obtained by precision grinding. The vacuum bonding component is vacuumed through the air extraction channel; A metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls are sequentially fabricated on the conductive interconnect pillars. The vacuum adsorption force is released through the air extraction channel, the vacuum bonding component is removed, and a chip package is obtained. The vacuum bonding component includes: Suction cup carrier and sealing gasket; The suction cup carrier has a bearing surface and a non-bearing surface. The bearing surface is provided with a negative pressure adsorption channel, and the suction cup carrier is provided with a guide channel connected to the negative pressure adsorption channel. The non-bearing surface is provided with an air extraction channel, and the air extraction channel is connected to the guide channel. The sealing gasket has an airtight through hole and is detachably disposed on the bearing surface, wherein the airtight through hole is interconnected with the negative pressure adsorption channel to form a bearing area for bearing the chip package; wherein the passive surface of the chip is placed in the bearing area of ​​the vacuum bonding component.

2. The method for preparing a chip package as described in claim 1, characterized in that, The sealing gasket comprises an elastic material.

3. The method for preparing a chip package as described in claim 1, characterized in that, A metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls are sequentially fabricated on the conductive interconnect pillars, including: The chip is filled with molding compound to form an encapsulation layer, so that the upper surface of the encapsulation layer is at the same level as the top of the conductive interconnect pillar; A metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls are sequentially prepared on the upper surface of the encapsulation layer.

4. The method for preparing a chip package as described in claim 1, characterized in that, After sequentially fabricating a metal wiring layer, pads, conductive pillars, and tin-based alloy solder balls on the conductive interconnect pillars, the method further includes: A protective film is applied to the tin-based alloy solder ball.

5. A method for preparing a chip package, characterized in that, The method includes: Provide vacuum bonding components; The vacuum bonding component includes: Suction cup carrier and sealing gasket; The suction cup carrier has a bearing surface and a non-bearing surface. The bearing surface is provided with a negative pressure adsorption channel, and the suction cup carrier is provided with a guide channel connected to the negative pressure adsorption channel. The non-bearing surface is provided with an air extraction channel, and the air extraction channel is connected to the guide channel. The sealing gasket has an airtight through hole and is detachably disposed on the bearing surface, wherein the airtight through hole is interconnected with the negative pressure adsorption channel to form a bearing area for bearing the chip package. A metal foil is provided to cover the carrier area of ​​the vacuum bonding member; A chip is provided, wherein conductive interconnect pillars are disposed on the active surface of the chip; A metal wiring layer is prepared on the metal foil, the chip is disposed on the metal wiring layer, and the conductive interconnect pillars on the active surface of the chip are made to be electrically interconnected with the metal wiring layer. The vacuum bonding component is vacuumed through the air extraction channel; The vacuum adsorption force is released through the air extraction channel, the vacuum bonding component is removed, and a pre-packaged body is obtained. Conductive pillars and tin-based alloy solder balls are prepared on the surface of the metal foil on the pre-packaged body to obtain the chip package.

6. The method for preparing a chip package as described in claim 5, characterized in that, Before releasing the vacuum suction force through the air extraction channel, the method further includes: The chip is filled with molding compound to form an encapsulation layer, such that the upper surface of the encapsulation layer is at the same level as the passive surface of the chip.

7. The method for preparing a chip package as described in claim 6, characterized in that, Before filling the chip with molding compound to form an encapsulation layer, the method further includes: The conductive interconnect pillars are bottom-filled to obtain a bottom filler layer.

8. The method for preparing a chip package as described in claim 6, characterized in that, Conductive pillars and tin-based alloy solder balls are fabricated on the surface of the metal foil on the pre-packaged body to obtain a chip package, comprising: An organic solder resist film is prepared on the surface of the metal foil on the pre-packaged body; The organic solder mask is subjected to photolithography opening, cleaning, and copper electroplating processes to prepare conductive pillars and tin-based alloy solder balls, thereby obtaining the chip package.

9. The method for preparing a chip package as described in claim 6, characterized in that, The materials of the sealing gasket include silicone; and / or, the metal foil includes copper foil; and / or, the encapsulation layer includes epoxy resin.

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