Package and method of forming the same

Abstract

Methods include forming a first package assembly, the forming process including forming a first plurality of openings in a first dielectric layer; depositing a first metal material into the first plurality of openings; performing a planarization process on the first metal material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer; and selectively depositing a second metal material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads includes the plurality of metal pads and a corresponding portion of the second metal material. The first package assembly is bonded to a second package assembly. Embodiments of the present application also relate to packages and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to packages and methods of forming the same. Background Technology

[0002] In wafer-to-wafer bonding technology, various methods have been developed to bond two packaged components (such as wafers) together. Available bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, etc. In hybrid bonding, the metal pads of the two wafers are bonded to each other by direct metal-to-metal bonding, and the oxide surface of one wafer is bonded to the oxide surface or silicon surface of the other wafer.

[0003] Wafer-to-wafer bonding requires high coplanarity at the bonding surfaces. For example, the bonding surface of a metal pad needs to be coplanar with the bonding surface of the dielectric layer to enable both direct metal bonding and fusion bonding. However, achieving coplanarity is difficult. For instance, the top surface of a wafer is typically planarized using a chemical mechanical polishing (CMP) process. However, CMP processes suffer from depression issues. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a package, including: forming a first package assembly, including: forming a first plurality of openings in a first dielectric layer; depositing a first metal material into the first plurality of openings; performing a planarization process on the first metal material and the first dielectric layer to form a first plurality of metal pads in the first dielectric layer; selectively depositing a second metal material on the first plurality of metal pads to form a first plurality of bonding pads, wherein the first plurality of bonding pads includes corresponding portions of the first plurality of metal pads and the second metal material; and bonding the first package assembly to a second package assembly, wherein the first plurality of bonding pads are bonded to the second package assembly.

[0005] Other embodiments of this application provide a package including: a first package assembly including: a first dielectric layer; a first metal pad in the first dielectric layer, wherein the first metal pad includes a first metal material; and a fill metal layer extending from the top surface of the first dielectric layer into the first metal pad, wherein the fill metal layer includes a second metal material different from the first metal material.

[0006] Further embodiments of this application provide a package comprising: a first package assembly including: a first dielectric layer; and a first metal pad in the first dielectric layer, wherein the first metal pad includes a first metal material; a second package assembly including: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer, wherein the second metal pad includes a second metal material; and a metal layer extending into the first metal pad, wherein the metal layer includes an alloy, and the alloy includes a third metal material different from the first metal material, and the metal layer is located between the first metal pad and the second metal pad. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1 to 13 This is a cross-sectional view of an intermediate stage in forming a package assembly using wafer-to-wafer bonding, according to some exemplary embodiments.

[0009] Figure 14 This is a cross-sectional view of a package assembly using die-to-wafer bonding according to some exemplary embodiments.

[0010] Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17 , Figure 18A and Figure 18B An enlarged view of the bonding pads during a bonding process according to some exemplary embodiments is shown.

[0011] Figure 19 The process flow for forming a package is shown according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Packages and methods of forming thereof are provided. According to some embodiments of the invention, a package assembly is formed including a surface dielectric layer and metal pads in the surface dielectric layer. A planarization process is performed to make the top surfaces of the surface dielectric layer and the metal pads flush. A conductive filler layer is selectively deposited on the metal pads to fill recesses in the metal pads, thereby achieving better bonding in subsequent bonding of the package assembly to another package assembly. The embodiments discussed herein are intended to provide examples to enable the making or use of the subject matter of the invention, and modifications can be readily understood by those skilled in the art while remaining within the intended scope of the different embodiments. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0015] Figures 1 to 13 A cross-sectional view is shown illustrating an intermediate stage in the formation of a package via a wafer-to-wafer bonding process according to some embodiments of the present invention. In such... Figure 19 The process flow 200 shown also schematically reflects the corresponding process.

[0016] Figure 1 A cross-sectional view is shown during the formation of the encapsulation component 2. (As shown in the image) Figure 19In the illustrated process flow 200, the corresponding process is shown as process 202. According to some embodiments of the invention, the package assembly 2 is a device wafer, including active devices such as transistors and / or diodes, and possibly passive devices such as capacitors, inductors, resistors, etc. The package assembly 2 may include a plurality of chips 4, one of which is shown. Chip 4 is alternatively referred to below as a (device) die. According to some embodiments of the invention, the device die 4 is a logic die, which may be a central processing unit (CPU) die, a microcontroller unit (MCU) die, an input / output (IO) die, a baseband (BB) chip, an application processor (AP) chip, etc. The device die 4 may also be a memory die such as a dynamic random access memory (DRAM) die or a static random access memory (SRAM) die.

[0017] According to an optional embodiment of the invention, package assembly 2 is an interposer wafer that has no active devices and may or may not include passive devices. In the following discussion, the device wafer is discussed as an example of package assembly 2, but embodiments of the invention can also be applied to other types of package assemblies, such as interposer wafers. Furthermore, package assembly 2 can be a reconfigurable wafer, including discrete device dies encapsulated in a sealant such as a molding compound.

[0018] According to some embodiments of the present invention, the package assembly 2 includes a semiconductor substrate 20. The semiconductor substrate 20 may be formed of crystalline silicon, crystalline germanium, crystalline silicon-germanium, and / or III-V compound semiconductors such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, etc. The semiconductor substrate 20 may also be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. Shallow trench isolation (STI) regions (not shown) may be formed in the semiconductor substrate 20 to isolate active regions within the semiconductor substrate 20. Although not shown, vias may be formed to extend into the semiconductor substrate 20, and these vias are used to electrically interconnect components on opposite sides of the package assembly 2.

[0019] According to some embodiments of the present invention, the package assembly 2 includes integrated circuit devices 22 formed on the top surface of a semiconductor substrate 20. Examples of integrated circuit devices 22 may include complementary metal-oxide-semiconductor (CMOS) transistors, resistors, capacitors, diodes, etc. Details of the integrated circuit devices 22 are not shown here. According to an alternative embodiment, the package assembly 2 is used to form an interposer layer, wherein the substrate 20 may be a semiconductor substrate or a dielectric substrate.

[0020] Interlayer dielectric (ILD) 24 is formed above semiconductor substrate 20 and fills the space between the gate stacks of transistors (not shown) in integrated circuit device 22. According to some embodiments, ILD 24 is formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), silicon oxide, etc. ILD 24 can be formed using spin coating, flowable chemical vapor deposition (FCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), etc.

[0021] Contact plug 28 is formed in ILD 24 and serves to electrically connect integrated circuit device 22 to conductive components thereon. According to some embodiments of the invention, contact plug 28 is formed of a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multiple layers thereof. Forming contact plug 28 may include forming contact openings in ILD 24, filling the contact openings with conductive material, and performing planarization (such as a chemical mechanical polishing (CMP) process) to make the top surface of contact plug 28 flush with the top surface of ILD 24.

[0022] Interconnect structure 30 is located above ILD 24 and contact plug 28. Interconnect structure 30 includes dielectric layer 32 and metal lines 34 and vias 36 formed in dielectric layer 32. Dielectric layer 32 is optionally referred to below as inter-metal dielectric (IMD) layer 32. According to some embodiments of the invention, at least the lower dielectric layer in dielectric layer 32 is formed of a low-k dielectric material with a dielectric constant (k value) of less than about 3.0 or about 2.5. Dielectric layer 32 may be formed of black diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. According to optional embodiments of the invention, some or all of dielectric layer 32 is formed of non-low-k dielectric materials, such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon carbonitride oxycarbonate (SiOCN), etc. According to some embodiments of the present invention, forming the dielectric layer 32 includes depositing a dielectric material containing a pore-forming agent, followed by a curing process to remove the pore-forming agent, thus leaving the remaining dielectric layer 32 porous. An etch stop layer (not shown), which may be formed of silicon carbide, silicon nitride, etc., is formed between the IMD layers 32 and is not shown for simplicity.

[0023] Metal lines 34 and vias 36 are formed in dielectric layer 32. Metal lines 34 at the same level are collectively referred to below as metal layers. According to some embodiments of the invention, interconnect structure 30 includes multiple metal layers interconnected vias 36. Metal lines 34 and vias 36 may be formed of copper, aluminum, silver, or alloys thereof, and may also be formed of other metals. Formation processes may include single-damascene and dual-damascene processes. In a single-damascene process, trenches are first formed in the corresponding dielectric layer 32, and then the trenches are filled with a conductive material. A planarization process, such as CMP, is then performed to remove excess conductive material above the top surface of the IMD layer, thereby leaving metal lines in the trenches. In a dual-damascene process, trenches and via openings are formed in the IMD layer, with the via openings located below and connected to the trenches. Conductive material is then filled into the trenches and via openings to form metal lines and vias, respectively. The conductive material may include a diffusion barrier layer and a copper-containing metal material above the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0024] Metal line 34 includes the metal line in the top metal layer. The corresponding dielectric layer 32 (denoted as 32A) on which the top metal layer is located may be formed of a non-low-k dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc. Dielectric layer 32A may also be formed of a low-k dielectric material, which may be selected from a similar material to the underlying IMD layer 32.

[0025] According to some embodiments of the present invention, dielectric layers 38, 40, and 42 are formed above the top metal layer. Dielectric layers 38 and 42 may be formed of silicon oxide, silicon oxynitride, silicon oxycarbide, etc. Dielectric layer 40 is formed of a dielectric material different from the dielectric material of dielectric layer 42. For example, dielectric layer 42 may be formed of a silicon-containing dielectric material such as silicon oxide, silicon oxynitride, silicon oxycarbide, etc.

[0026] refer to Figure 2 This forms a through-hole opening 44 and a groove 46. Figure 19 In the illustrated process flow 200, the corresponding process is shown as process 204. To form the via opening 44 and the trench 46, photoresist (not shown) and / or a hard mask (not shown) may be formed on the dielectric layer 42 and patterned to define the patterns of the via opening 44 and the trench 46. According to some embodiments of the invention, an anisotropic etching process is performed to form the trench 46, and the etching stops at the etch stop layer 40. Another anisotropic etching is then performed to form the via opening 44 by etching the exposed etch stop layer 40 and a portion of the underlying dielectric layer 38. According to some embodiments of the invention, the etch stop layer 40 is not formed, and the via opening 44 and the trench 46 are formed in a single dielectric layer. A timing pattern may be used to perform the etching to allow the etching (for forming the trench 46) to stop at an intermediate level between the top and bottom surfaces of a single dielectric layer.

[0027] Figure 3 This illustrates the filling of conductive material. In, as shown... Figure 19 In the process flow 200 shown, the corresponding process is shown as process 206. First, a conductive diffusion barrier layer 48 is formed. According to some embodiments of the invention, the diffusion barrier layer 48 is formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The diffusion barrier layer 48 can be formed, for example, using atomic layer deposition (ALD), physical vapor deposition (PVD), etc. The diffusion barrier layer 48 includes a first portion above the surface dielectric layer 42, and a second portion at the bottom and sidewalls of the trench 46 and on the via opening 44.

[0028] Next, a metal material 50 is deposited, for example, by electrochemical plating (ECP). The metal material 50 fills the remaining portions of the trench 46 and the via opening 44. The metal material 50 also includes portions above the top surface of the surface dielectric layer 42. The metal material 50 may include copper or copper alloys, tungsten, aluminum, silver, alloys thereof, or other metal materials that can be diffused in a subsequent annealing process, thereby enabling the formation of a metal-to-metal direct bond.

[0029] Next, as Figure 4 As shown, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess portions of the metal material 50 and the diffusion barrier layer 48 until the dielectric layer 42 is exposed. Figure 19 In the process flow 200 shown, the corresponding process is indicated as process 208. The remaining portion of the diffusion barrier layer 48 and the metal material 50 includes vias 52 and metal pads 54'. Throughout this specification, the metal pads 54' are also referred to as bonding pads 54'.

[0030] The planarization process aims to produce a flat top surface, wherein the top surface of the bonding pad 54' is coplanar with the top surface of the dielectric layer 42. However, due to various process factors, such as pattern loading effects and differences between the etch rate and mechanical polishing rate of the bonding pad 54' and the dielectric layer 42, as well as their different responses to the paste, non-planar surfaces may be produced. For example, Figure 4 This illustrates the recess effect that occurs during the CMP process, and the groove 55 is formed to extend into the metal pad 54'. Furthermore, minute grooves (roughness) may exist on the top surface of the bonding pad 54'. The roughness of the top surface of the bonding pad 54' can be greater than about 1 μm, which is greater than the maximum permissible roughness for wafer-to-wafer bonding. Therefore, according to some embodiments, such as... Figure 15A , Figure 15B , Figure 16A and Figure 16B As shown, an additional layer is deposited on the surface of the bonding pad 54' to reduce non-coplanarity and roughness issues.

[0031] Figure 15A An enlarged cross-sectional view of a portion of a bonding pad 54' and a corresponding dielectric layer 42 according to some embodiments of the present invention is shown. Each bonding pad 54' (and as...) Figure 4 The through-hole 52 shown below includes a diffusion barrier layer 48 and a metallic material 50 surrounded by the diffusion barrier layer 48. The metallic material 50 may include an edge portion and an intermediate portion between the edge portions, the top surface of which is lower than the top surface of the edge portion, thereby forming a groove 55. The groove 55 may have a depth D1 greater than about 0.1 μm, and the depth D1 may be in the range between about 0.1 μm and about 3 μm. Figure 15B It shows a similar structure, except that it forms as Figure 15A In addition to the depression shown, microgrooves 55 are also formed. It should be noted that depressions and microgrooves 55 can occur simultaneously on the same structure, and the surface of the depression also includes microgrooves.

[0032] refer to Figure 16A A conductive filler layer 58 is selectively deposited on the bonding pad 54'. The conductive filler layer 58 may be formed of one or more metals and is optionally referred to as a metal filler layer 58. Throughout this specification, the bonding / metal pad 54' and the corresponding overlying metal filler layer 58 are collectively referred to as the bonding pad 54. Figure 5 The corresponding package component 2 is shown in the figure, wherein details of the bonding pad 54 can be found in the figure. Figure 16A The filler metal layer 58 is deposited using a selective deposition method such as plating, which may include electrochemical plating (ECP), chemical plating, etc. Thus, the filler metal layer 58 is selectively deposited on a metallic material such as bonding pads 54', but not on a dielectric material such as dielectric layer 42. According to some embodiments, the current density used for the plating process may be in the range of 0.1 ASD (amperes per square decimeter) to about 5.0 ASD.

[0033] The amount of filler metal layer 58 deposited on each bonding pad 54 is controlled so that the filler metal layer 58 fills the groove 55 with as little excess as possible. Figure 15A The highest point TMP of the fill metal layer 58 may be higher than the top surface of the surface dielectric layer 42. To make the volume of the fill metal layer 58 the same as the volume of the corresponding recess 55, the lowest point LMP of the top surface of the fill metal layer 58 may be lower than the top surface 42T of the surface dielectric layer 42. In other words, the recess 55 may have a small portion not filled by the fill metal layer 58, and the excess portion of the fill metal layer 58 above the surface 42T compensates for the unfilled portion. The appropriate volume of the fill metal layer 58 can be determined by measuring the dimensions of the recess 55 and the bonding pad 54.

[0034] The filler metal layer 58 may be formed of or comprise a material selected from Cu, Sn, In, Ag, SnAg, their alloys, and / or composite layers thereof. According to some embodiments, the material of the filler metal layer 58 is selected based on the material of the bonding pad 54 such that the coefficient of thermal expansion (CTE) of the filler metal layer 58 is close to the CTE of the bonding pad 54'. For example, the ratio |(CTE58 – CTE54')| / CTE58 may be less than about 0.2 and may be less than about 0.1, where the value |(CTE58 – CTE54')| is the absolute value of (CTE58 – CTE54'). Furthermore, the CTE difference |(CTE58 – CTE54')| may be less than about 10 x 10 at 20°C. -5 / K. Because CTEs CTE58 and CTE54' are close to each other, the resulting joint structure is less prone to problems caused by CTE mismatch, which may include fragmentation, delamination, etc.

[0035] According to some embodiments of the present invention, the melting point of the filler metal layer 58 is lower than the melting point of the bonding pad 54'. For example, when the metal pad 54' is formed of or includes copper, the filler metal layer 58 may be formed of or include Sn, In, Ag, or alloys thereof. According to some embodiments, the melting point difference (MP54' – MP58) is greater than about 100°C, greater than about 200°C, or greater than about 500°C, wherein the melting points MP54' and MP58 are the thickness of the bonding pad 54' and the melting point of the filler metal layer 58, respectively. The melting point difference (MP54' – MP58) may also be in the range between about 100°C and about 800°C.

[0036] According to some embodiments, the filler metal layer 58 is formed of a homogeneous material. According to alternative embodiments, each filler metal layer 58 may be a composite layer comprising two or more sublayers, wherein the sublayers are formed of different materials from each other. For example, as... Figure 16A As shown, each filler layer 58 may include sublayer 58A and sublayer 58B formed of different materials. According to some embodiments of the invention, sublayer 58A is a diffusion barrier layer formed of or including Ti, Ta, TiN, TaN, Ni, etc. Sublayer 58B may be formed of Cu, Sn, In, Ag, SnAg, etc., or alloys thereof. According to alternative embodiments, sublayers 58A and 58B are formed of different materials and may diffuse into each other via solid-liquid diffusion in subsequent bonding processes. For example, sublayer 58A may be formed of In or Cu, while sublayer 58B may be formed of Cu (when sublayer 58 is formed of In) or In (when sublayer 58 is formed of Cu).

[0037] Figure 16BA filler metal layer 58 is shown that, according to some embodiments, fully or partially fills the groove 55, wherein the groove is a microgroove rather than a depression. Although not shown separately... Figure 16A Sublayers 58A and 58B are shown, but they can also be formed.

[0038] refer to Figure 5 The diagram shows a bonding pad 54' (not shown, see below). Figure 16A The bonding pad 54 and the corresponding filler metal layer 58 above it.

[0039] Figure 6 The diagram illustrates the formation of a wafer 100, which includes a device die 112. According to some embodiments of the invention, the device die 112 is a logic die, which may be a CPU die, MCU die, I / O die, baseband die, AP die, etc. The device die 112 may also be a memory die. The wafer 100 includes a semiconductor substrate 114, which may be a silicon substrate. Through-silicon vias (TSVs) 116 (sometimes referred to as semiconductor vias or vias) are formed extending into the semiconductor substrate 114. The TSVs 116 are used to connect devices and metal lines formed on the front side (bottom side shown) of the semiconductor substrate 114 to the back side, as shown in subsequent figures. Furthermore, the device die 112 includes interconnect structures 130 for connecting active and passive devices (if any) within the device die 112. The interconnect structures 130 include metal lines and vias (not shown).

[0040] Wafer 100 may include dielectric layers 138 and 142 and an etch stop layer 140 between dielectric layers 138 and 142. Bonding pads 154 and vias 152 are formed in layers 138, 140, and 142. Figure 19 In the process flow 200 shown, the corresponding process is shown as process 210. The materials and formation processes of dielectric layers 138 and 142, etch stop layer 140, bonding pad 154 and via 152 are similar to their corresponding portions in device die 4, and therefore will not be repeated here.

[0041] Figure 17 An enlarged view of a bonding pad 154 according to some embodiments is shown. The bonding pad 154 includes a diffusion barrier layer 148 and a metallic material 150. The structure, material, and formation method of the bonding pad 154 and the via 152 may be similar to... Figure 16AThe structure, materials, and formation methods of the bonding pad 54 and via 52 are shown. According to some embodiments, the bonding pad 154 includes a metal pad 154' and a filler layer 158 on the metal pad 154'. The formation process and corresponding materials of the filler layer 158 may be the same as those of the filler metal layer 58, and will not be repeated here. According to an optional embodiment, the bonding pad 154 includes a metal pad 154' and does not include a filler layer 158. According to an optional embodiment, a filler metal layer 158 is formed on the metal pad 154', while no filler metal layer is deposited on the metal pad 54'.

[0042] refer to Figure 6 and Figure 17 The wafer 100 is placed on the package assembly 2, aligning the bonding pads 154 with the corresponding bonding pads 54. The wafer 100 is then pressed against the package assembly 2, wherein this pressing process is performed by... Figure 17 Arrow 60 indicates that encapsulation components 2 and 100 are heated, as shown in the image. Figure 17 Curve 62 is shown in the figure. According to some embodiments, the pressure is below approximately 1,000 kgf / cm². 2 This pressure is lower than that used in conventional wafer-to-wafer bonding processes. The force can be reduced by using a filler layer 58 / 158 with a lower melting point. Additionally, in wafer-to-wafer bonding processes, the wafer temperature can be between approximately 100°C and approximately 200°C. The bonding duration can be between approximately 1 hour and approximately 2 hours.

[0043] Next, as Figure 7 As shown, wafer 100 is bonded to package assembly 2 via hybrid bonding. Bonding pads 154 are bonded to corresponding bonding pads 54 via metal-to-metal bonding, wherein bonding pads 154 are bonded to bonding pads 54 via interdiffusion bonding. Surface dielectric layer 142 in wafer 100 is bonded to surface dielectric layer 42 in package assembly 2 via, for example, fusion bonding of Si-O-Si bonds formed between surface dielectric layer 142 and surface dielectric layer 42.

[0044] Figure 18A An enlarged view of the bonding process as a result of the bonding process is shown, forming interdiffusion regions that subsequently form alloy regions. Remaining portions of the filler metal layers 58 and / or 158 may or may not be present. According to some embodiments, the wafer temperature during the bonding process is equal to or higher than the melting point of one or both of the filler metal layers 58 and 158. This results in at least partial or complete melting of one or both of the filler metal layers 58 and 158. Throughout this specification, the term "partially melted" means that the corresponding layer has a mixture of molten and unmelted portions.

[0045] As described above, the filler metal layers 58 and 158 can be monolayers formed of the same material such as Cu, Sn, In Ag, SnAg, etc. Therefore, during at least partial melting, the filler metal layers 58 (or 158) diffuse into each other and bond together. According to an alternative embodiment, the filler metal layers 58 and 158 are monolayers formed of different materials. Therefore, the different materials diffuse into each other and form an alloy. For example, in... Figure 17 In the diagram, the dashed line between sublayers 58A and 58B indicates that layer 58 may be a single layer or comprise multiple layers formed of a homogeneous material, and the dashed line between sublayers 158A and 158B indicates that layer 158 may be a single layer or comprise multiple layers formed of a homogeneous material. According to another optional embodiment, one of the filler metal layers 58 and 158 is formed of or comprises indium, having a melting point of approximately 156°C. Therefore, indium melts or partially melts during the bonding process and diffuses into another material (such as copper) via solid-liquid diffusion to form an alloy, wherein the alloy may be In... x Cu y Alloy. In x Cu y The alloy can have a melting point above about 600°C, which is higher than that of indium. Therefore, the resulting alloy is more stable and can undergo subsequent thermal processes (if any) without melting or cracking.

[0046] exist Figure 18A In this context, the resulting metal layers are designated as metal layers 59 / 58 / 158 to indicate that the layer between the metal pad 54' and the corresponding upper metal pad 154' can be the metal layer 59 of the alloy region, or may include bonded filler metal layers 58 and 158 (which are separate layers forming a distinguishable interface) if no alloy is formed. Metal layers 59 / 58 / 158 may also include unmelted / unalloyed portions of the metal layer 59 and metal layers 58 and / or 158 of the alloy region.

[0047] Figure 18B An embodiment is shown where microgrooves are formed; therefore, the filler metal layers 58 and 158 also have the shape of microgrooves. Similarly, the filler metal layers 58 and 158 may form the metal layer 59 of the alloy region, or remain as separating layers (formed from different materials) with distinguishable interfaces. The metal pads 54 and 154 may contact each other, as... Figure 18B As shown, or by spacing the metal layers 58 and 158 (if not alloyed) or the metal layers 59 of the alloy region apart from each other.

[0048] According to some embodiments where one or both of the filler metal layers 58 and 158 are formed of composite layers, the different sublayers in the filler metal layers 58 and 158 can diffuse into each other to form an alloy. For example, according to some embodiments, the top sublayer of filler layer 58 is formed of In, and the bottom sublayer of filler layer 158 is formed of Cu, which can form an alloy during the bonding process. Unmelted and alloyed diffusion barrier layers may also be present. For example, in Figure 18A In this process, the resulting bonding region includes diffusion layers 58A and 158A and metal layers 59 / 58 / 158 between them (wherein, 58 / 158 is actually 58B / 158B). According to an alternative embodiment where each of the diffusion layers 58 and 158 is a single layer and forms an alloy region, the metal layer 59 of the alloy region may contact the top surface of the bonding pad 54' and the bottom surface of the bonding pad 154'.

[0049] According to some embodiments, certain portions of metal pads 54' and 154' are in physical contact with and bonded to each other. For example, as... Figure 18A As shown, the edge portions of metal pads 54' and 154' are joined together to form an interface. In a top view of the bonding structure, the interface formed between the pair of metal pads 54' and 154' can form a ring that surrounds the metal layers 59 / 58 / 158. According to other embodiments, the metal pads 54' and 154' are completely spaced apart from each other by the metal layers 59 / 58 / 158 and do not contact each other. It should be understood that due to process variations, on the same bonding wafer and in the same resulting package, some other metal pads 54' and 154' may be in physical contact with each other and bonded to each other, while some other metal pads 54' and 154' are completely spaced apart by the metal layers 59 / 58 / 158.

[0050] According to an optional embodiment, one of the fill metal layers 58 and 158 is formed for the corresponding packaging components 2 and 100. Figure 6 ), without forming another. Therefore, fill layer 58 or 158 fills the two recesses in the bonding pads 54' and 154'.

[0051] refer to Figure 8 According to some embodiments, after the bonding process, the thin wafer 100 may undergo back-side grinding until the via 116 is exposed. Next, refer to... Figure 9 This forms the redistribution line (RDL) 72 and the dielectric layer 74. Figure 19In the illustrated process flow 200, the corresponding process is shown as process 214. According to some embodiments of the invention, the dielectric layer 74 is formed of an oxide such as silicon oxide, a nitride such as silicon nitride, etc. The RDL 72 can be formed using a damascene process, including: etching the dielectric layer 74 to form an opening, depositing a conductive barrier layer in the opening, plating a metal material such as copper or a copper alloy, and performing planarization to remove excess portions of the metal material.

[0052] Figure 10 The formation of the passivation layer, metal pads, and the dielectric layer above is shown. It should be understood that the structure shown may take different forms than those illustrated, and the structure shown is an example. Figure 19 In the process flow 200 shown, the corresponding process is also shown as process 214. A passivation layer 76 (sometimes referred to as passivation-1) is formed over the dielectric layer 74, and a via 78 is formed in the passivation layer 76 for electrical connection to the RDL 72. A metal pad 80 is formed over the passivation layer 76 and is electrically connected to the RDL 72 through the via 78. The metal pad 80 can be an aluminum pad or an aluminum-copper pad, and other metal materials can be used.

[0053] Similarly, Figure 10 As shown, passivation layer 82 (sometimes referred to as passivation-2) is formed over passivation layer 76. Each of passivation layers 76 and 82 can be a single layer or a composite layer, and can be formed of a non-porous material. According to some embodiments of the invention, one or both of passivation layers 76 and 82 are composite layers comprising a silicon oxide layer and a silicon nitride layer (not shown separately) above the silicon oxide layer. Passivation layers 76 and 82 can also be formed of other non-porous dielectric materials, such as undoped silicate glass (USG), silicon oxynitride, etc.

[0054] Next, the passivation layer 82 is patterned such that certain portions of the passivation layer 82 cover the edge portions of the metal pad 80, and certain portions of the metal pad 80 are exposed through openings in the passivation layer 82. A polymer layer 84 is then formed and patterned to expose the metal pad 80. The polymer layer 84 may be formed from polyimide, polybenzoxazole (PBO), etc.

[0055] refer to Figure 11 A passivated interconnect (PPI) 86 is formed. The formation process may include forming a metal seed layer and a patterned mask layer (not shown) over the metal seed layer, and depositing the PPI 86 in the patterned mask layer. The patterned mask layer and the portion of the metal seed layer overlapping the patterned mask layer are then removed in an etching process. A polymer layer 88 is then formed, which may be formed from PBO, polyimide, etc.

[0056] refer to Figure 12This forms an under-bump metal (UBM) 90 and an electrical connector 92. The UBM 90 and electrical connector 92 extend into the polymer layer 88 to connect to the PPI 86. According to some embodiments of the invention, each UBM 90 includes a barrier layer (not shown) and a seed layer (not shown) above the barrier layer. The barrier layer may be a titanium layer, a titanium nitride layer, a tantalum layer, a tantalum nitride layer, or a layer formed of a titanium alloy or a tantalum alloy. The material of the seed layer may include copper or a copper alloy. The UBM 90 may also include other metals, such as silver, gold, aluminum, palladium, nickel, nickel alloys, tungsten alloys, chromium, chromium alloys, and combinations thereof.

[0057] The formation process for forming the UBM 90 and the electrical connector 92 may include: depositing a blanket UBM layer, forming and patterning a mask (which may be a photoresist, not shown), with a portion of the blanket UBM layer exposed through openings in the mask. After forming the UBM 90, the illustrated package is placed in a plating solution (not shown), and a plating process is performed to form the electrical connector 92 on the UBM 90. According to some embodiments of the invention, the electrical connector 92 includes a solderless portion (not shown) that is not melted in a subsequent reflow process. The solderless portion may be formed of copper and is therefore referred to hereinafter as a copper bump, although it may be formed of other solderless materials. Each electrical connector 92 may also include a capping layer (not shown) selected from a nickel layer, a nickel alloy, a palladium layer, a gold layer, a silver layer, or multiple layers thereof. The capping layer is formed over the copper bump. Electrical connector 92 may also include a solder cap, which may be formed of Sn-Ag alloy, Sn-Cu alloy, Sn-Ag-Cu alloy, etc., and may be lead-free or lead-containing.

[0058] The structure formed in the previous steps is called the reconstructed wafer 94. Then, a die dicing (splitting) step is performed on the reconstructed wafer 94 to separate it into multiple packages 96. (As shown in...) Figure 19 In the process flow 200 shown, the corresponding process is indicated as process 222. One of the packages 96 is in Figure 13 As shown in the image.

[0059] Figure 13 The package shown is formed via a wafer-to-wafer bonding process. According to an alternative embodiment, the wafer and bonding pads formed according to embodiments of the invention can also be used in die-to-wafer or die-to-die bonding processes. For example, Figure 14This illustrates a package formed based on a die-to-wafer bonding process. In the corresponding formation process, device dies 112 are first sawn from a corresponding wafer into discrete dies, which are then bonded to package assembly 2 via die-to-wafer bonding. Gap filler materials 160 and 162 are then formed to fill the gaps between device dies 112. According to some embodiments, gap filler material 160 comprises a silicon nitride layer, and gap filler material 162 comprises an oxide such as silicon oxide. After the bonding process, a planarization process is performed to remove excess gap filler materials 160 and 162 and expose vias 116. Next, vias 170 are formed to electrically connect to some of the bonding pads 54. It should be understood that these bonding pads 54 may have, for example... Figure 16A The structure shown may include a metal pad 54' formed of a first material and a fill metal layer 58 formed of a second material different from the first material. The via 170 contacts the bonding pad 54 and may contact the fill metal layer 58 and / or the metal pad 54', as shown. Figure 16A As shown. In subsequent processes, RDL 72, dielectric layer 74, and the components thereon are formed to form reconstructed wafer 94. A dicing process can be performed to cut the reconstructed wafer 94 into individual packages 96.

[0060] In the embodiments shown above, some processes and components are discussed according to some embodiments of the present invention to form a three-dimensional (3D) package. Other components and processes may also be included. For example, test structures may be included to assist in the verification testing of the 3D package or 3DIC device. Test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing can be performed on intermediate structures as well as the final structure. Furthermore, the structures and methods disclosed herein can be used in conjunction with test methods that combine intermediate verification with known good dies to increase yield and reduce costs.

[0061] Embodiments of the present invention have several advantageous features. By selectively forming a filling conductive layer on top of the bonding pads, the grooves of the bonding pads can be filled, resulting in better quality of the bonding process.

[0062] According to some embodiments of the present invention, the method includes: forming a first package assembly, the forming process including: forming a first plurality of openings in a first dielectric layer; depositing a first metal material into the first plurality of openings; performing a planarization process on the first metal material and the first dielectric layer to form a first plurality of metal pads in the first dielectric layer; and selectively depositing a second metal material on the first plurality of metal pads to form a first plurality of bonding pads, wherein the first plurality of bonding pads includes corresponding portions of the first plurality of metal pads and the second metal material. The method further includes bonding the first package assembly to a second package assembly, wherein the first plurality of bonding pads are bonded to the second package assembly. In an embodiment, the second package assembly includes: a second dielectric layer, wherein the first dielectric layer is bonded to the second dielectric layer; and a second plurality of bonding pads in the second dielectric layer, wherein the second plurality of bonding pads are bonded to the first plurality of bonding pads. In an embodiment, both the first plurality of metal pads and the second metal material in the first plurality of bonding pads are in contact with the second plurality of bonding pads. In an embodiment, during the deposition of the first metal material, the first metal material is not deposited on the exposed surface of the first dielectric layer. In one embodiment, the selective deposition of the second metal material includes: depositing a first sublayer comprising a first metal; and depositing a second sublayer over the first sublayer, wherein the second sublayer comprises a second metal different from the first metal. In another embodiment, the method further includes forming the second package assembly, including: forming a second plurality of openings in a second dielectric layer; depositing a third metal material into the second plurality of openings; performing an additional planarization process on the third metal material and the second dielectric layer to form a second plurality of metal pads in the second dielectric layer; and selectively depositing a fourth metal material on the second plurality of metal pads to form a second plurality of bonding pads, wherein the first plurality of bonding pads are bonded to the second plurality of bonding pads. In one embodiment, during the bonding, the second metal material is at least partially melted. In one embodiment, during the bonding, the second metal material forms an alloy with the material of the second plurality of bonding pads in the second package assembly. In one embodiment, a first melting point of the second metal material is lower than a second melting point of the material of the second plurality of bonding pads. In one embodiment, the selective deposition of the second metal material includes a plating process. In one embodiment, the bonding is performed when the temperature of the first and second packaging components is below about 200°C, and the second metal material melts in the bonding.

[0063] According to some embodiments of the present invention, a package includes: a first package assembly, the first package assembly comprising: a first dielectric layer; a first metal pad in the first dielectric layer, wherein the first metal pad comprises a first metal material; and a filler metal layer extending from a top surface of the first dielectric layer into the first metal pad, wherein the filler metal layer comprises a second metal material different from the first metal material. In an embodiment, the first metal material has a first melting point, and the second metal material has a second melting point lower than the first melting point. In an embodiment, the second melting point is lower than about 200°C. In an embodiment, the package further includes a diffusion barrier layer between the filler metal layer and the first metal pad. In an embodiment, the package further includes a second package assembly, the second package assembly comprising: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer and bonded to the first metal pad, wherein the filler metal layer further extends into the second metal pad.

[0064] According to some embodiments of the present invention, a package includes a first package assembly and a second package assembly. The first package assembly includes: a first dielectric layer; and a first metal pad in the first dielectric layer, wherein the first metal pad includes a first metal material. The second package assembly includes: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer, wherein the second metal pad includes a second metal material; and a metal layer extending into the first metal pad, wherein the metal layer includes an alloy, and the alloy includes a third metal material different from the first metal material, and the metal layer is located between the first metal pad and the second metal pad. In an embodiment, the first metal pad has a recessed groove, and the metal layer extends into the recessed groove. In an embodiment, the first metal pad is physically bonded to the second metal pad. In an embodiment, the first metal pad is physically separated from the second metal pad by the metal layer.

[0065] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method of forming a package, comprising: Forming a first package assembly, the formation of the first package assembly comprising: forming a plurality of first openings in a first dielectric layer; depositing a first metal material into the plurality of first openings; performing a planarization process on the first metal material and the first dielectric layer to form a plurality of first metal pads in the first dielectric layer, wherein one of the plurality of first metal pads includes a first edge portion and a first intermediate portion recessed more than the corresponding first edge portion; and selectively depositing a second metal material on the plurality of first metal pads to form a plurality of first bonding pads, wherein the plurality of first bonding pads includes the plurality of first metal pads and corresponding portions of the second metal material; and The first package assembly is bonded to the second package assembly, wherein, prior to bonding, the first dielectric layer includes a first top surface, and the second metal material includes a second top surface, wherein the second top surface includes a first point below the first top surface and a second point above the first top surface, and the second metal material includes a second edge portion and a second intermediate portion recessed more than the corresponding second edge portion, wherein the plurality of first bonding pads are bonded to the second package assembly.

2. The method according to claim 1, wherein, The second packaging component includes: A second dielectric layer, wherein the first dielectric layer is bonded to the second dielectric layer; and A plurality of second bonding pads are provided in the second dielectric layer, wherein the plurality of second bonding pads are bonded to the plurality of first bonding pads.

3. The method according to claim 2, wherein, Both the plurality of first metal pads and the second metal material in the plurality of first bonding pads are in contact with the plurality of second bonding pads.

4. The method according to claim 1, wherein, In the deposition of the first metal material, the first metal material is not deposited on the exposed surface of the first dielectric layer.

5. The method according to claim 1, wherein, The selective deposition of the second metallic material includes: The deposition includes a first sublayer of the first metal; and A second sublayer is deposited over the first sublayer, wherein the second sublayer comprises a second metal different from the first metal.

6. The method of claim 1, further comprising forming the second packaging component, including: Multiple second openings are formed in the second dielectric layer; A third metallic material is deposited into the plurality of second openings; An additional planarization process is performed on the third metal material and the second dielectric layer to form a plurality of second metal pads in the second dielectric layer; as well as A fourth metal material is selectively deposited on the plurality of second metal pads to form a plurality of second bonding pads, wherein the plurality of first bonding pads are bonded to the plurality of second bonding pads.

7. The method according to claim 1, wherein, In the joining process, the second metal material is at least partially melted.

8. The method according to claim 1, wherein, In the bonding process, the second metal material forms an alloy with the material of a plurality of second bonding pads in the second package assembly.

9. The method according to claim 8, wherein, The first melting point of the second metallic material is lower than the second melting point of the material of the plurality of second bonding pads.

10. The method according to claim 1, wherein, The selective deposition of the second metallic material includes a plating process.

11. The method according to claim 1, wherein, The bonding is performed when the temperature of the first and second packaging components is below 200°C, and the second metal material melts in the bonding.

12. A package comprising: A first packaging assembly, comprising: a first dielectric layer; a first metal pad in the first dielectric layer, wherein the first metal pad comprises a first metal material; and a filler metal layer extending from the top surface of the first dielectric layer into the first metal pad, wherein the filler metal layer comprises a second metal material different from the first metal material. The first metal pad includes an edge portion and a middle portion that is recessed more than the corresponding edge portion, wherein the middle portion has a plurality of recessed grooves.

13. The package according to claim 12, wherein, The first metallic material has a first melting point, and the second metallic material has a second melting point lower than the first melting point.

14. The package according to claim 13, wherein, The second melting point is below 200°C.

15. The package of claim 12, further comprising a diffusion barrier layer between the filler metal layer and the first metal pad.

16. The package of claim 12, further comprising a second packaging assembly, the second packaging assembly comprising: The second dielectric layer is bonded to the first dielectric layer; as well as A second metal pad is located in the second dielectric layer and bonded to the first metal pad, wherein the filler metal layer further extends into the second metal pad.

17. A package comprising: A first packaging assembly, the first packaging assembly comprising: a first dielectric layer; and a first metal pad, wherein the first metal pad comprises a first metal material, wherein the first metal pad comprises an edge portion and a middle portion recessed more than the corresponding edge portion, and wherein the middle portion has a plurality of recessed grooves; A second packaging assembly, the second packaging assembly comprising: a second dielectric layer bonded to the first dielectric layer; and a second metal pad in the second dielectric layer, wherein the second metal pad comprises a second metal material; and A metal layer extends into the first metal pad, wherein the metal layer comprises an alloy, and the alloy comprises a third metal material different from the first metal material, and the metal layer is located between the first metal pad and the second metal pad.

18. The package according to claim 17, wherein, The metal layer extends into the recessed groove.

19. The package according to claim 17, wherein, The first metal pad is physically bonded to the second metal pad.

20. The package according to claim 17, wherein, The first metal pad is physically separated from the second metal pad through the metal layer.

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