Semiconductor devices and manufacturing methods thereof

Abstract

A semiconductor device and a method for manufacturing the same include: forming a semiconductor feature on a substrate, the semiconductor feature including a conductive region; forming a dielectric layer on the semiconductor feature; patterning the dielectric layer to form a contact opening to expose an upper surface of the conductive region; forming a monolayer on the dielectric layer to maintain the exposure of the upper surface of the conductive region; and depositing a conductive material within the contact opening.

Description

Technical Field

[0001] This invention relates to a semiconductor technology, and more particularly to a semiconductor device and a method of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have resulted in generation after generation of integrated circuits, each with smaller and more complex circuits than the previous generation. Throughout the development of integrated circuits, functional density (e.g., the number of interconnects per chip area) has generally increased, while geometric dimensions (e.g., the smallest component (or wiring) that can be formed using manufacturing processes) have decreased. This miniaturization process typically brings many benefits due to increased production efficiency and reduced associated costs.

[0003] As devices miniaturize, manufacturers have begun using new and different materials and / or combinations of materials to facilitate miniaturization. Miniaturization, either alone or in combination with new and different materials, has also led to challenges that were not present in previous generations at larger geometries. Summary of the Invention

[0004] In some embodiments, in one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a substrate, the semiconductor feature including a conductive region; forming a dielectric layer on the semiconductor feature; patterning the dielectric layer to form a contact opening exposing an upper surface of the conductive region; forming a monolayer on the dielectric layer to maintain the exposed upper surface of the conductive region; and depositing a conductive material within the contact opening.

[0005] In some embodiments, a method of manufacturing a semiconductor device includes: forming a first dielectric layer on a substrate; forming a first opening in the first dielectric layer to expose the substrate; forming a first conductive feature in the first opening, the first conductive feature including a metal; forming a second dielectric layer on the first dielectric layer and the first conductive feature, wherein, when forming the second dielectric layer, the second dielectric layer includes exposed hydroxyl groups having a first concentration; forming a second opening in the second dielectric layer to expose the first conductive feature; flowing a monolayer precursor on the second dielectric layer to form a monolayer on the second dielectric layer, wherein, after forming the monolayer, the second dielectric layer includes exposed hydroxyl groups having a second concentration less than the first concentration; and flowing a metal precursor on the second dielectric layer to deposit a metal feature in the second opening and on the first conductive feature.

[0006] In some embodiments, a semiconductor device includes: a first conductive feature embedded in a substrate; a first dielectric layer disposed on the first conductive feature; a second conductive feature extending through the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; a self-aligned monolayer disposed on the second dielectric layer; and a third conductive feature extending through the second dielectric layer, a portion of the self-aligned monolayer being sandwiched between the second dielectric layer and the third conductive feature. Attached Figure Description

[0007] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 and Figure 16 A cross-sectional schematic diagram illustrating an intermediate manufacturing stage of the interconnect structure of an integrated circuit according to some embodiments is shown.

[0008] Figure 17 and Figure 18 A cross-sectional schematic diagram of an intermediate manufacturing stage of a semiconductor device according to some embodiments is shown.

[0009] The reference numerals in the attached figures are explained as follows:

[0010] 50: Base

[0011] 54: Source and Drain Regions

[0012] 58: Fins

[0013] 60: FinFET device

[0014] 62: Shallow Trench Isolation (STI) Area

[0015] 64: (Replaces) the conductive gate layer

[0016] 66: (Replaces) gate dielectric layer

[0017] 68: Gate structure

[0018] 72: Spacer wall

[0019] 74: Lower layer contact plug

[0020] 76: First Inner Dielectric Layer (ILD)

[0021] 78: Second Inner Dielectric Layer (ILD)

[0022] 80, 130, 280: Opening

[0023] 84, 184, 284: Self-aligned monolayer

[0024] 90, 150, 190, 250, 290: Conductive materials

[0025] 92, 192: Upper contact plug

[0026] 100: Wafer

[0027] 108: Etching Stop Layer

[0028] 110: Intermetallic Dielectric (IMD) Layer

[0029] 124: Buffer layer

[0030] 126: Masking layer

[0031] 140, 240: Barrier Layer

[0032] 142, 242: Lining

[0033] 160: Conductive wire

[0034] 170: Cap layer

[0035] 260: Metallized wiring

[0036] 262: Metallized Interlayer Connection Window

[0037] 274: Lower layer conductive feature components

[0038] 278: Dielectric layer

[0039] 292: Upper conductive feature component Detailed Implementation

[0040] The following disclosure provides numerous different embodiments or examples for implementing various feature components of the present invention. The following disclosure provides specific examples of the various components and their arrangements to simplify the present disclosure. Of course, these are merely illustrative examples and are not intended to define the invention as intended. For example, if the following disclosure describes forming a first feature component on or above a second feature component, it indicates that it includes embodiments where the formed first feature component and the second feature component are in direct contact, and also includes embodiments where additional feature components may be formed between the first feature component and the second feature component, so that the first feature component and the second feature component may not be in direct contact. Furthermore, reference numerals and / or words are repeated in the various examples of this disclosure. Repetition is for simplification and clarity, and not to specify the relationships between the various embodiments and / or configurations discussed.

[0041] Furthermore, spatial terms such as "below," "under," "down," "above," and "upper" are used here to readily express the relationship between elements or features in the diagrams illustrated in this specification and other elements or features. These spatial terms cover not only the orientation shown in the diagrams but also different orientations of the device during use or operation. The device may have different orientations (rotated 90 degrees or other orientations), and the spatial symbols used herein have corresponding interpretations. Where applicable, the term "substantially" may also include "overall," "completely," "all," etc., as used in the embodiments. Where applicable, the term "substantially" may also refer to 90% or higher, such as 95% or higher, particularly 99% or higher, including 100%.

[0042] According to some embodiments, the formation of conductive features, such as contact plugs located on the gate electrode and source / drain regions, offers numerous advantages. For example, certain conductive features can be formed without a conductive barrier layer. After forming an opening within the dielectric layer for the conductive feature, the dielectric layer can be processed to improve the selectivity of the conductive material to be deposited within the opening and on the dielectric layer.

[0043] The performance of integrated circuits with conductive features located therein can be improved in several ways. First, the conductivity of the conductive features can be improved by forming a substantially conductive material. That is, it is not necessary to bond the conductive material to the conductance barrier layer. Second, the conductivity of the conductive features can be improved by eliminating grain boundaries, which would otherwise form between the conductive material and the conductance barrier layer. Third, the performance of integrated circuits can be improved because the rate at which metals (e.g., from the barrier layer or conductive material) are deposited on the dielectric layer and thus mix or diffuse into the dielectric layer is low.

[0044] Furthermore, by replacing the formation of a barrier layer with a chemical treatment of a dielectric layer prior to the formation of conductive features, semiconductor manufacturing processes can be made more efficient and costs reduced. For example, in some cases, forming a barrier layer can utilize multiple deposition cycles of alternating precursors to form a complete monolayer of the conductive barrier layer, such that the complete monolayer includes complete coverage of the underlying surface. According to some embodiments, the process described herein can be a faster process than forming a conductive barrier layer and can be performed at low temperatures (thus reducing the thermal budget), as described in the following embodiments. In some embodiments, the proposed surface properties can be achieved in a single cycle of each precursor.

[0045] Furthermore, conductive feature components with high aspect ratios can be formed, as illustrated in the embodiments below. The increase in thickness within the dielectric opening due to the processing of the dielectric layer is negligible compared to the thickness of the conductive barrier layer deposited within the dielectric opening. Therefore, conductive material has more space for more efficient deposition, and there is less buildup at the top of the opening, thus allowing conductive material to be deposited within narrower and deeper openings.

[0046] Figures 1 to 16 A cross-sectional schematic diagram is shown illustrating an intermediate manufacturing stage of the conductive features and interconnect structures of an integrated circuit according to some embodiments. Figures 1 to 6 and Figures 14 to 16 The diagram illustrates a contact plug with an internal connection structure formed using a single damascene process. Figures 7 to 13 The diagram illustrates the wires and metallization layers (including metallized wiring and metallized vias) used to form the internal interconnect structure using single damascene or dual processes.

[0047] Figure 1 A schematic cross-sectional view of a semiconductor structure on wafer 100, comprising a substrate 50 (e.g., a semiconductor substrate) on which various electronic devices may be formed, is illustrated according to some embodiments. In the following figures, a multilayer interconnect system may be formed on the various electronic devices and substrate 50. As will be described in detail below, Figure 1 A fin field-effect transistor (FinFET) device 60 formed on a substrate 50 is illustrated. In subsequent figures, multiple interconnect layers are formed thereon. Planar transistors, gate-all-around (GAA) transistors, and other types of devices are also covered within the scope of this disclosure.

[0048] Figure 1The substrate 50 illustrated may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer that serves as the active layer of the SOI substrate. The active layer and bulk semiconductor, both composed of semiconductors, typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, and similar materials), or alloys thereof (e.g., Ga...). x Al 1-x As, Ga x Al 1-x N、In x Ga 1- x As and similar materials, oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3 and similar materials), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed orientation substrates.

[0049] Figure 1 The FinFET device 60 is illustrated as a three-dimensional metal-oxide-semiconductor field-effect transistor (MOSFET) structure, formed within fin-shaped strips of semiconductor protrusions (referred to as fins 58). Figure 1 The cross-section shown is parallel to the current flow direction between the source and drain regions 54 along the longitudinal axis of the fin. The fin 58 can be formed by patterning the substrate using lithography and etching techniques. For example, spacer image transfer (SIT) patterning techniques can be used. In this method, a sacrificial layer is formed on the substrate, and a mandrel is formed using a suitable lithography and etching process. Spacers are formed beside the mandrel using a self-aligned process. The sacrificial layer is then removed by a suitable selective etching process. Each remaining spacer can then act as a hard mask, forming the corresponding fin 58 by etching a trench within the substrate 50, for example, using reactive ion etching (RIE). Figure 1 A single fin 58 is shown, however the base 50 may include any number of fins.

[0050] Figure 1The diagram illustrates shallow trench isolation (STI) regions 62 formed along the two opposite sidewalls of fin 58. The STI regions 62 are formed by depositing one or more dielectric materials (e.g., silicon oxide) to completely fill the trenches around the fin, followed by recessing the upper surface of the dielectric material. The dielectric material of the STI regions 62 can be deposited using high-density plasma chemical vapor deposition (HDP-CVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or similar methods, or combinations thereof. Following deposition, an annealing or curing process can be performed. In some cases, the STI regions 62 may include a liner, for example, a thermally oxidized liner grown on a silicon oxide surface. The recessing process can be, for example, a planarization process (e.g., chemical mechanical polishing (CMP)) followed by a selective etching process (e.g., wet etching or dry etching, or a combination thereof), which can recess the upper surface of the dielectric material located in the shallow trench isolation (STI) region 62, causing the upper portion of the fin 58 to protrude from the surrounding insulating shallow trench isolation (STI) region 62. In some cases, the patterned hard mask used to form the fin 58 can also be removed by the planarization process.

[0051] In some embodiments, Figure 1The gate structure 68 of the FinFET device 60 illustrated is a high-k metal gate (HKMG) gate structure, which can be formed using a post-gate fabrication process. In the post-gate process, after forming the shallow trench isolation (STI) region 62, a sacrificial dummy gate structure (not shown) is formed. The dummy gate structure may include a dummy gate dielectric layer, a dummy gate electrode, and a hard mask. First, a dummy gate dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a similar material) may be deposited. Next, a dummy gate dielectric material (e.g., amorphous silicon, polycrystalline silicon, or a similar material) may be deposited on the dummy gate material, followed by planarization (e.g., by chemical mechanical polishing (CMP)). A hard mask layer (e.g., silicon nitride, silicon carbide, or a similar material) may be formed on the dummy gate material. The dummy gate structure is fabricated by patterning a hard mask and transferring the pattern to the dummy gate dielectric and dummy gate material using appropriate lithography and etching techniques. The dummy gate structure can extend along multiple sides of the protruding fins 58 and between the fins 58 located on the surface of the shallow trench isolation (STI) region 62. As described below, the dummy gate structure can be made from... Figure 1 The gate structure 68 shown in the figure is replaced. Figure 1 The gate structure 68 shown on the right (see top of fin 58) is an example of an active gate structure that extends along the sidewall of fin 58 and is located on the portion of fin 58 that protrudes above the shallow trench isolation (STI) region 62. Figure 1 The gate structure 68 shown on the left is an example of a gate structure extending over a shallow trench isolation (STI) region 62, for example, located between two adjacent fins 58. The material used to form the dummy gate structure and the hard mask can be deposited using any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or similar methods, or by thermal oxidation of the semiconductor surface or a combination thereof.

[0052] The source and drain regions 54 and spacer 72 forming the FinFET device 60 are shown in the diagram. Figure 1In this context, for example, a self-aligned dummy gate structure can be used. The spacer wall 72 can be formed by depositing and anisotropically etching a spacer dielectric layer after the dummy gate structure is completed. The spacer dielectric layer may include one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, similar materials, or combinations thereof. The anisotropic etching process removes the spacer dielectric layer from the top of the dummy gate structure, leaving the spacer wall 72 extending laterally along the sidewalls of the dummy gate structure to a localized surface of the fin 58 (e.g., ...). Figure 1 The surface of the shallow trench isolation (STI) area 62 (as shown on the right) Figure 1 (As shown on the left side).

[0053] The source and drain regions 54 are semiconductor regions of the contact fin 58. In some embodiments, the source and drain regions 54 may include a heavily doped region and a relatively lightly-doped drain (LDD) extension region. The heavily doped region is separated from the dummy gate structure by a spacer wall 72. The lightly-doped drain (LDD) region may be formed prior to the formation of the spacer wall 72 and thus extends below the spacer wall 72. In some embodiments, it further extends into local semiconductor below the dummy gate structure. For example, the lightly-doped drain (LDD) region may be formed by implanting dopants (e.g., As, P, B, In, or similar substances) using an ion implantation process.

[0054] The source and drain regions 54 may include epitaxially grown regions. For example, after forming a lightly doped drain (LDD) region, a spacer 72 may be formed. Subsequently, heavily doped source and drain regions can be formed self-aligned to the spacer 72. In particular, the heavily doped source and drain regions can be formed by first etching the fins to form grooves, and then depositing crystalline semiconductor material within the grooves using a selective epitaxial growth (SEG) process. This material can fill the grooves and typically extends beyond and above the original surface of the fins, forming a protruding source-drain structure, such as... Figure 1 As illustrated in the figure. Crystalline semiconductor materials can be in elemental form (e.g., Si or Ge or similar) or alloy form (e.g., Si). 1-x C x or Si 1-x Ge x Si 1-x-y Ge x C ySelective epitaxial growth (SEG) processes can use any suitable epitaxial growth method, such as vapor phase / solid phase / liquid phase epitaxy (VPE, SPE, LPE) or metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) or similar methods. High doses of dopant (e.g., from 10...) 14 cm -2 Up to 10 16 cm -2 The heavily doped source and drain regions 54 can be introduced in situ during selective epitaxial growth (SEG), or via an ion implantation process after selective epitaxial growth (SEG), or via a combination thereof. The source and drain regions 54 can be formed by other processes, such as ion implantation of dopants or similar substances.

[0055] Please refer to Figure 1 A first interlayer dielectric (ILD) layer 76 is deposited on the above structure. In some embodiments, prior to depositing the interlayer dielectric (ILD) material, a contact etch stop layer (CESL) (not specifically illustrated) composed of a suitable dielectric material (e.g., silicon nitride, silicon carbide, or similar materials or combinations thereof) may be deposited. A planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove excess interlayer dielectric (ILD) material and any remaining hard masking material from the upper surface of the dummy gate material to form an upper surface in which the upper surface of the dummy gate material is exposed and is substantially coplanar with the upper surface of the first interlayer dielectric (ILD) layer 76.

[0056] Then, drawn on Figure 1The high-k metal gate (HKMG) gate structure 68 is formed by first removing dummy gate structures using one or more etching techniques, thereby forming a groove between the corresponding spacer walls 72. Next, a substituted gate dielectric layer 66 composed of one or more dielectric layers and a substituted conductive gate layer 64 composed of one or more conductive materials are sequentially deposited to completely fill the groove. The gate dielectric layer 66 includes, for example, a high-dielectric material, such as oxides and / or silicates of metals (e.g., oxides and / or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, and other metals), silicon nitride, silicon oxide, similar materials, or combinations thereof, or multiples thereof. In some embodiments, the conductive gate layer 64 may be a multilayer metal gate stack, including a barrier layer, a work function layer, and a gate fill layer sequentially formed on top of the gate dielectric layer 66. Example materials for the barrier layer include TiN, TaN, Ti, Ta, or similar materials, or multiple combinations thereof. The work function layer may include TiN, TaN, Ru, Mo, and Al for p-type FETs, and Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, and Zr for n-type FETs. Other suitable work function materials or combinations thereof or multiples thereof may also be used. The gate fill layer filling the remainder of the trench may include metals such as Cu, Al, W, Co, Ru, similar materials or combinations thereof or multiples thereof. The material used to form the gate structure may be deposited by any suitable method, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), electrochemical plating (ECP), electroless plating, and / or similar methods. Excess portions of the gate structure layers (conductive gate layer 64 and gate dielectric layer 66) may be used, for example, removed from the upper surface of the first inner dielectric (ILD) layer 76 by a chemical mechanical polishing (CMP) process. The resulting structure, such as Figure 1 As shown, it may have substantially coplanar surfaces, including a first inner dielectric (ILD) layer 76, spacers 72, and the remaining portion of the high-k metal gate (HKMG) gate layer (i.e., the exposed upper surface of the gate structure layers (conductive gate layer 64 and gate dielectric layer 66)). The gate structure layers (conductive gate layer 64 and gate dielectric layer 66) are embedded between the corresponding spacers 72.

[0057] like Figure 1 As illustrated, the electrodes of the electronic device formed within the substrate 50 can be electrically connected to conductive features of the first inner connection layer (formed in subsequent figures) using conductive connectors (e.g., lower contact plug 74) formed through the intermediate dielectric layer. Figure 1 In the example illustrated, the lower contact plug 74 is electrically connected to the source and drain regions 54 of the FinFET device 60. The lower contact plug 74 can be formed using photolithography. For example, a patterned mask can be formed on the first inner dielectric (ILD) layer 76 and used to etch openings (extending to the first inner dielectric (ILD) layer 76) to expose portions of the source and drain regions 54. In some embodiments, an anisotropic dry etching process can be used, wherein etching is performed in two successive steps. The etchant used in the first step of the etching process has a higher etch rate on the material of the first inner dielectric (ILD) layer 76 than on the material of the contact etch stop layer (CESL), which is formed as a substrate on the upper surface of the source and drain regions 54, which are composed of heavily doped regions. Once the first step of the etching process exposes the contact etch stop layer (CESL), a second step of the etching process can be performed, in which the etchant can be switched to selectively remove the contact etch stop layer (CESL). Although a first inner dielectric (ILD) layer 76 is illustrated, embodiments having two or more inner dielectric (ILD) layers are also covered within the scope of this disclosure.

[0058] In some embodiments, a conductive liner may be formed within an opening in the first inner dielectric (ILD) layer 76. The opening is then filled with a conductive filler material. The liner includes a barrier metal to reduce the diffusion of conductive material from the underlying contact socket 74 outwards into the surrounding dielectric material. In some embodiments, the liner may include two barrier metal layers. A first barrier metal layer contacts the semiconductor material of the source and drain regions 54 and may subsequently chemically react with the heavily doped semiconductor of the source and drain regions 54 to form a low-resistance ohmic contact. Unreacted metal may then be removed. For example, if the heavily doped semiconductor of the source and drain regions 54 is silicon or a silicon-germanium alloy semiconductor, the first barrier metal layer may include Ti, Ni, Pt, Co, other suitable metals, or alloys thereof. The second barrier metal layer of the conductive liner may additionally include other metals (e.g., TiN, TaN, Ta, or other suitable metals or alloys thereof). Any acceptable deposition technique (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, similar methods, or any combination thereof) can be used to deposit a conductive filler material (e.g., W, Al, Cu, Ru, Ni, Co, alloys of these, similar materials, or any combination thereof) on the conductive layer to fill the contact opening. Next, a planarization process (e.g., chemical mechanical polishing (CMP)) can be used to remove all excess conductive material from the surface of the first inner dielectric (ILD) layer 76. The resulting conductive plug extends to the first inner dielectric (ILD) layer 76 and forms the lower contact plug 74, physically and electrically connecting to the electrodes of an electronic device, such as... Figure 1 The diagram illustrates a three-gate fin field-effect transistor (FinFET). In this example, the contacts of the electrode above the shallow trench isolation (STI) region 62 and the contacts of the electrode above the fin 58 are formed simultaneously using the same fabrication steps. However, in other embodiments, these two types of contacts may be formed separately.

[0059] exist Figure 2 In this process, a second inner dielectric (ILD) layer 78 may be deposited on top of the first inner dielectric (ILD) layer 76 (e.g., Figure 1(As shown). In some embodiments, prior to depositing the inner layer dielectric (ILD) material, another contact etch stop layer (CESL) (not specifically shown) composed of a suitable dielectric material (e.g., silicon nitride, silicon carbide, or similar combinations thereof) may be deposited. A planarization process (e.g., chemical mechanical polishing (CMP)) may be performed to remove excess inner layer dielectric (ILD) material, forming a smooth upper surface. In some embodiments, the insulating material forming the first inner layer dielectric (ILD) layer 76 and the second inner layer dielectric (ILD) layer 78 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), or boron-doped phosphosilicate glass (BPSG). Undoped silicate glass (USG), low-k dielectric materials (e.g., fluorosilicate glass (FSG), silicon oxycarbonate (SiOCH), carbon-doped oxides). Oxide (CDO), flowable oxide, or porous oxide (e.g., xerogels / aerogels) or similar or combinations thereof. The insulating material used to form the first inner dielectric (ILD) layer 76 and the second inner dielectric (ILD) layer 78 can be deposited using any suitable method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), plasma-enhanced chemical vapor deposition (PECVD), sub-atmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), spin coating, and / or similar methods or combinations thereof. In some embodiments, one or more etch stop layers (not specifically shown) are also formed on the structure above and / or below the illustrated inner dielectric (ILD) layers.

[0060] exist Figure 3In this embodiment, an opening 80 is formed within the second inner dielectric (ILD) layer 78. Fabrication of the opening 80 may include performing a lithography process to etch a mask layer (not specifically shown) to form the initial opening. The lithography process may include forming a photoresist (also not specifically shown) on the mask layer, patterning the photoresist having an opening corresponding to the opening 80, extending the opening 80 through the mask layer, and then removing the photoresist. The opening 80 extends to the second inner dielectric (ILD) layer 78 using an acceptable etching technique. In one embodiment, the opening 80 is formed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the second inner dielectric (ILD) layer 78 without significantly etching the mask layer. The etching process continues until the opening 80 exposes a contact etch stop layer (CESL) (not specifically shown). For example, the etching process may include using plasma to form a reactive material from an etchant gas. In some embodiments, the plasma may be a remote plasma. The etching gas may include fluorocarbon chemicals, such as C4F6 / CF4 / C5F and NF3 / O2 / Ar / H3 / H2, similar compounds, or combinations thereof. In some embodiments, the etchant uses a fluorocarbon chemical with O2 or Ar as the carrier gas. The contact etch stop layer (CESL) portion within the opening 80 is removed to expose the underlying contact plug 74. The contact etch stop layer (CESL) can be removed using anisotropic wet or dry etching that is selective to the material of the contact etch stop layer (CESL). For example, the contact etch stop layer (CESL) can be removed using anisotropic wet etching, which uses an etching reactant (e.g., H2O2). The etching process used to remove the contact etch stop layer (CESL) may differ from the etching process used to form the opening 80 (e.g., different etchants and / or other etching process parameters may be used).

[0061] like Figure 3 As illustrated in the enlarged portion, in some embodiments, after the second inner layer dielectric (ILD) layer 78 is formed and patterned, the second inner layer dielectric (ILD) layer 78 may have a concentration of hydroxyl (-OH) groups extending from the exposed surface. The concentration of exposed hydroxyl groups may be approximately 1 × 10⁻⁶. 14 hydroxyl group / cm 2 Up to 7×10 14 hydroxyl group / cm 2 Between, for example, approximately 4 × 10 14 hydroxyl group / cm 2In some embodiments, after patterning the second inner dielectric (ILD) layer 78, a cleaning process is performed, which increases the density of hydroxyl groups extending from the exposed surface. The cleaning process may include cleaning the wafer using materials such as hydrogen peroxide (H₂O₂), ammonium hydroxide (NH₄OH), ammonium peroxide ((NH₄)₂O₂), water, diluted hydrofluoric acid (dHF), or similar and / or combinations thereof (e.g., Standard Clean 1 (SC1) comprising ammonium hydroxide, hydrogen peroxide, and water (APM solution)). After the cleaning process, the concentration of exposed hydroxyl groups may be approximately 1 x 10⁻⁶. 15 hydroxyl group / cm 2 Up to 7x10 15 hydroxyl group / cm 2 Between, for example, approximately 4x10 15 hydroxyl group / cm 2 .

[0062] exist Figure 4 In this process, a self-aligned monolayer (SAM) 84 is formed on the second inner dielectric (ILD) layer 78. As described later, the SAM 84 protects the second inner dielectric (ILD) layer 78 (or a portion of the second inner dielectric (ILD) layer 78) from metal growth in subsequent steps by increasing the selectivity between metal growth on the metal surface and the surface of the second inner dielectric (ILD) layer 78 and / or the SAM 84. The SAM 84 can be formed by reacting a monolayer precursor with hydroxyl groups extending from the surface of the second inner dielectric (ILD) layer 78. In some embodiments, the reaction product may include attached portions that replace hydrogen atoms or completely replace hydroxyl groups. The hydrogen atoms or hydroxyl groups are then removed from the environment. As a result of the reaction, the product may form a monolayer along the surface of the second inner dielectric (ILD) layer 78. When the SAM 84 is formed together, the attached portions may be laterally bonded to each other or may include separated portions. In the latter case, the separated portions may be chemically attractive to each other. Therefore, the term "single layer" refers to the case where the attached functional groups cover the surface of the second inner dielectric (ILD) layer 78 even if the newly attached functional groups do not bond together to form a continuous chemical structure.

[0063] In some embodiments, the self-aligned monolayer 84 is formed by flowing a silicon-containing monolayer precursor through the surface of the second inner dielectric (ILD) layer 78. For example... Figure 4As shown in the magnified portion, the hydroxyl groups exposed on the surface of the monolayer precursor and the second inner dielectric (ILD) layer 78 undergo an exchange reaction, resulting in silylation of the surface of the second inner dielectric (ILD) layer 78. Silicon from the monolayer precursor adheres to the second inner dielectric (ILD) layer 78. The monolayer precursor may have the following chemical structure:

[0064]

[0065] R1 is a functional group including hydroxide (-OH), and each of R2, R3, and R4 is a functional group, such as a hydrophobic functional group, including functional groups of methyl (-CH3), ethyl (-CH2CH3), nitrogen, amino anion (-NH2), benzene, imidazole, or similar compounds. R2, R3, and R4 may include the same or different functional groups. In the silylation reaction, the R1 functional group combines with hydrogen in the hydroxyl group attached to the second inner dielectric (ILD) layer 78. The resulting R1-H product is gaseous and detaches from the second inner dielectric (ILD) layer 78 for subsequent removal from the system. The silicon in the remaining portion of the precursor is bonded to oxygen from the hydroxyl group.

[0066] In some embodiments, the self-aligned monolayer 84 is formed by flowing a non-reactive (or substantially non-reactive) monolayer precursor onto the surface of the second inner dielectric (ILD) layer 78. The monolayer precursor may include, for example, an organic molecule that does not significantly react with the second inner dielectric (ILD) layer 78, including hydroxyl groups exposed along the surface of the second inner dielectric (ILD) layer 78. Instead, the organic molecule may be selectively deposited on the second inner dielectric (ILD) layer 78 and not formed on the exposed lower contact plug 74 or gate electrode 64. In some embodiments, the organic molecule forms hydrogen bonds with the hydroxyl groups. Although the organic molecule may not react, it may be attracted to the second inner dielectric (ILD) layer 78, particularly along the exposed hydroxyl groups on the surface of the second inner dielectric (ILD) layer 78. The organic molecule may include hydrophobic molecules, including hydrocarbons such as alkanes (e.g., hexane, heptane, octane, cyclohexane), benzene rings or the like, or other molecules or functional groups that do not contain hydroxyl or oxygen.

[0067] As a result of forming a self-aligned monolayer 84 comprising hydrophobic molecules or hydrophobic functional groups, the surface of the second inner dielectric (ILD) layer 78 can be converted from hydrophilic to hydrophobic. Before the formation of the self-aligned monolayer 84 and before cleaning the second inner dielectric (ILD) layer 78, the contact angle between the exposed surface of the second inner dielectric (ILD) layer 78 and water is measured to be approximately between 3° and 5°. After the formation of the self-aligned monolayer 84, the exposed surface of the second inner dielectric (ILD) layer 78 (including the self-aligned monolayer 84) is measured to have a larger contact angle with water, approximately between 10° and 15°.

[0068] exist Figure 5 In this process, conductive material 90 fills the opening 80. The conductive material 90 can be a metallic material, including metals or metal alloys, such as tungsten, cobalt, copper, or alloys thereof. The conductive material 90 can be formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar methods, and is formed by flowing a metal precursor onto wafer 100. For example, the metal precursor may include a metal-containing molecule, such as tungsten hexafluoride (WF6). The growth of the conductive material 90 involves, for example, an exchange reaction between the metal precursor and hydrogen in the environment, such that fluorine from the metal precursor (e.g., in the case of tungsten hexafluoride (WF6)) combines with hydrogen to form hydrofluoric acid (HF) or combines with fluorine to form fluorine (F2), while tungsten from the metal precursor adheres to the underlying metal (e.g., the exposed gate electrode 64, the lower contact plug 74, or the deposited portion of the conductive material 90).

[0069] The advantages of the self-aligned monolayer 84 include the elimination of the need for a seed layer or conductive barrier layer (e.g., titanium nitride or tantalum nitride) before the growth of the conductive material 90. Typically, to ensure complete coverage, a seed layer or conductive barrier layer needs to be thicker than the self-aligned monolayer 84. Therefore, without a seed layer or barrier layer, the conductive material 90 has more entry and growth space within the opening 80, allowing for a higher aspect ratio, such as between approximately 0.4 and 0.8, for example, approximately 0.6. Furthermore, during deposition, the conductive material 90 is selectively deposited on the underlying metal (e.g., gate electrode 64 and lower contact plug 74) rather than on the second inner dielectric (ILD) layer 78 and the self-aligned monolayer 84. Since nucleation sites are primarily on the gate electrode 64 and lower contact plug 74, the loss of selectivity in nucleation and deposition on the second inner dielectric (ILD) layer 78 is prevented or reduced, thus improving process efficiency (e.g., shorter process time) and increasing yield.

[0070] exist Figure 6In this process, the upper contact plug 92 is formed by planarizing the conductive material 90, the self-aligned monolayer 84, and the second inner dielectric (ILD) layer 78 (e.g., chemical mechanical polishing (CMP)). This results in the upper contact plug 92 and the upper surfaces of the second inner dielectric (ILD) layer 78 being flush. Furthermore, the self-aligned monolayer 84 can be removed from the upper surface of the second inner dielectric (ILD) layer 78 while still being directly sandwiched between the second inner dielectric (ILD) layer 78 and the upper contact plug 92. Therefore, without a seed layer or conductive barrier layer, the upper contact plug 92 entirely comprises the material of the conductive material 90, thereby improving its conductivity during use of the completed semiconductor device.

[0071] In some embodiments, particularly when organic molecules are used to form the self-aligned monolayer 84, a cleaning step may be used to remove the self-aligned monolayer 84 from the upper surface of the second inner dielectric (ILD) layer 78. In those embodiments, a planarization step may be performed after the cleaning step, or the planarization step may be selective if the deposited conductive material 90 has sufficiently formed the upper contact plug 92. The cleaning step may include cleaning the wafer 100 using deionized water (DI), diluted hydrofluoric acid (dHF), similar substances, or any combination thereof.

[0072] exist Figure 7 In this process, an etch stop layer 108 is formed on the second inner dielectric (ILD) layer 78 and the upper contact plug 92. The etch stop layer 108 may be formed of silicon carbide, silicon nitride, silicon oxynitride, silicon carbide nitride, or similar materials. The etch stop layer 108 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-on dielectric, similar processes, or combinations thereof.

[0073] Please refer to Figure 7An inter-metal dielectric (IMD) layer 110 is formed on the etch stop layer 108. The IMD layer 110 may be a film formed of a low-k dielectric material having a k-value lower than about 3.0. Alternatively, the IMD layer 110 may be a film formed of an extra-low-k (ELK) dielectric material having a k-value lower than about 2.5. In some embodiments, the IMD layer 110 may be formed of an oxygen- and / or carbon-containing low-k dielectric material, a hydrogen silsesquioxane (HSQ), a methylsilsesquioxane (MSQ), or similar materials. The material of the etch stop layer 108 has high etch selectivity with the intermetallic dielectric (IMD) layer 110, so the etch stop layer 108 can be used to stop the etching of the intermetallic dielectric (IMD) layer 110 in subsequent process steps.

[0074] In some embodiments, the intermetallic dielectric (IMD) layer 110 is formed of a porous material, such as SiOCN, SiCN, SiOC, SiOCH, or similar materials, and can be formed from a precursor layer initially formed on the etch stop layer 108. The precursor layer may include a matrix material and a pore-forming agent inserted within the matrix material, or it may include a matrix material without a pore-forming agent. In some embodiments, the precursor layer can be formed by co-depositing the matrix and the pore-forming agent using a process such as plasma-enhanced chemical vapor deposition (PECVD), wherein the matrix material and the pore-forming agent are deposited simultaneously, thus forming a precursor layer of mixed matrix material and pore-forming agent. However, as will be understood by those skilled in the art, co-deposition using a simultaneous plasma-enhanced chemical vapor deposition (PECVD) process is not the only process that can be used to form the precursor layer. Any suitable process can also be used, such as premixing the matrix material and the pore-forming agent material into a liquid and then spin-coating the mixture onto the etch stop layer 108.

[0075] The matrix material or substrate dielectric material can be formed using processes such as plasma-enhanced chemical vapor deposition (PECVD), however any suitable process can be used, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or even spin coating. Plasma-enhanced chemical vapor deposition (PECVD) processes can utilize precursors such as methyldiethoxysilane (DEMS), but other precursors can also be used, such as other silanes, alkylsilanes (e.g., trimethylsilane and tetramethylsilane), alkoxysilanes (e.g., methyltriethoxysilane (MTEOS), methyltrimethoxysilane (MTMOS), methyldimethoxysilane (MDMOS), trimethylmethoxysilane (TMMOS) and dimethyldimethoxysilane (DMDMOS)), linear siloxanes and cyclic siloxanes (e.g., octamethylcyclotetrasiloxane (OMCTS) and tetramethylcyclotetrasiloxane (TMCTS)), combinations of these or similar. However, as will be understood by those skilled in the art, the materials and processes listed herein are for illustrative purposes only and are not intended to limit the embodiments, as any other suitable matrix precursor may be used.

[0076] The porogen can be a molecule that can be removed from the matrix material after solidification to form pores within the matrix, thereby reducing the overall dielectric constant of the intermetallic dielectric (IMD) layer 110. The porogen can be a material large enough to form pores, yet small enough that the size of each pore does not excessively displace the matrix material. Therefore, the porogen can include organic molecules such as alpha-terpinene ATRP (1-isopropyl-4-methyl-1,3-cyclohexadiene), cyclooctane (boat-shaped), or 1,2-bis(triethoxysilane)ethanesilane.

[0077] After the precursor layer and the porogen dispersed within the matrix material are formed, the porogen is removed from the matrix material to create pores within it. In one embodiment, the porogen is removed by annealing, which decomposes and vaporizes the porogen material, causing it to diffuse and leave the matrix material, leaving a structurally intact porous dielectric material as the intermetallic dielectric (IMD) layer 110. For example, annealing may be performed at a temperature in the range of approximately 200°C to 500°C (e.g., approximately 400°C) for approximately 10 to 600 seconds (e.g., approximately 200 seconds). Alternatively, other suitable processes may be used to remove the porogen, such as irradiating the porogen with ultraviolet (UV) radiation to decompose it, or using microwaves to decompose it.

[0078] exist Figure 8 In this process, a film stack is formed on the intermetallic dielectric (IMD) layer 110. According to some embodiments, the film stack is used to form conductive lines electrically connected to the upper contact plug 92. The film stack includes a buffer layer 124 and a masking layer 126. In some embodiments, the film stack includes one or more buffer layers and masking layers, which may be formed alternately.

[0079] A buffer layer 124 is formed on the intermetallic dielectric (IMD) layer 110, and a mask layer 126 is formed on the buffer layer 124. The buffer layer 124 may be formed of a dielectric material, such as silicon oxide, and may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), spin-coating dielectric processes, or similar methods. The mask layer 126 may be formed of a material including metals (e.g., titanium nitride, titanium, tantalum nitride, tantalum, or similar materials), and may be formed by physical vapor deposition (PVD), radio frequency physical vapor deposition (RFPVD), atomic layer deposition (ALD), or similar methods. In a subsequent process step, the mask layer 126 is patterned. Then, the mask layer 126 is used as an etching mask, wherein the pattern of the mask layer 126 is used to etch the intermetallic dielectric (IMD) layer 110. The buffer layer 124 reduces stress between the intermetallic dielectric (IMD) layer 110 and the masking layer 126.

[0080] exist Figure 9 In this process, an opening 130 is formed within the mask layer 126. The fabrication of the opening 130 may include performing a photolithography process to etch the mask layer 126 to form the initial opening. The photolithography process may include forming a photoresist (not specifically shown) on the mask layer 126, patterning the photoresist to correspond to the opening of the opening 130, extending the opening 130 through the mask layer 126, and then removing the photoresist.

[0081] exist Figure 10In this embodiment, opening 130 extends through buffer layer 124 and intermetallic dielectric (IMD) layer 110. Opening 130 can be extended using an acceptable etching technique. In one embodiment, opening 130 is formed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the intermetallic dielectric (IMD) layer 110 without significantly etching the masking layer 126. The etching process continues until opening 130 exposes etch stop layer 108. For example, the etching process may include using plasma to form reactive material from an etchant gas. In some embodiments, the plasma may be a remote plasma. The etchant gas may include fluorocarbon chemistry, such as C4F6 / CF4 / C5F and NF3 / O2 / Ar / H3 / H2, similar compounds, or combinations thereof. In some embodiments, the etchant uses a fluorocarbon chemistry with O2 or Ar as the carrier gas.

[0082] exist Figure 11 In the process, a portion of the etch stop layer 108 within the opening 130 is removed to expose the underlying upper contact plug 92. The etch stop layer 108 can be removed using anisotropic wet or dry etching that is selective to the material of the etch stop layer 108. For example, anisotropic wet etching (which uses an etchant such as H2O2) can be used to remove the etch stop layer 108. The etching process used to remove the etch stop layer 108 may differ from the etching process used to form the opening 130 (e.g., different etchants and / or other etching process parameters may be used).

[0083] exist Figure 12 In this process, a barrier layer 140 is formed on the exposed surface of wafer 100 and within opening 130. According to some embodiments, the fabrication of the barrier layer 140 may include physical vapor deposition (PVD), atomic layer deposition (ALD), or a combination thereof. In some exemplary deposition processes, Ar is introduced into a corresponding deposition reaction chamber (not shown) on which wafer 100 is placed to sputter metal ions (e.g., titanium (Ti+) or tantalum (Ta+)) or uncharged atoms (e.g., titanium (Ti) or tantalum (Ta)) from a corresponding target (not shown) used in physical vapor deposition (PVD). Nitrogen may be added to the process gas. The sputtered metal ions are deposited on wafer 100 to form the barrier layer 140, which is conductive. Direct current and / or radio frequency (RF) power may be applied during the deposition of the barrier layer 140. After deposition, the barrier layer 140 includes a portion located directly above the intermetallic dielectric (IMD) layer 110, a portion located on the sidewall of the opening 130 (e.g., the sidewall of the mask layer 126, buffer layer 124, intermetallic dielectric (IMD) layer 110 and etch stop layer 108), and a portion located at the bottom of the opening 130.

[0084] Please refer to Figure 12A substrate 142 is formed on the exposed surface of the wafer 100 and within the opening 130. The substrate 142 may be formed of cobalt, tantalum, titanium, tantalum nitride, titanium nitride, ruthenium, or similar materials, and may be formed by a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), similar methods, or combinations thereof.

[0085] Conductive material 150 is deposited on the substrate 142 and fills the opening 130. Excess conductive material 150 may also be formed along the upper surface of the substrate 142. The conductive material 150 may be a metallic material, including metals or metal alloys, such as copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof. In some embodiments, the fabrication of the conductive material 150 includes depositing a thin sublayer (not shown) that may include copper or a copper alloy, and filling the remainder of the opening 130 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electrochemical plating (ECP) (e.g., high-voltage electrochemical plating (ECP)), or electroless plating.

[0086] According to some embodiments, a deposition method (e.g., physical vapor deposition (PVD)) can be used to form the conductive material 150 within the opening 130. For example, a first copper deposition can be performed at room temperature, followed by a reflow process of about 1 minute to about 5 minutes at about 150°C to about 300°C. One or more copper deposition and reflow processes can be performed after the first cycle. In general, there can be one to five or more alternating cycles of deposition and reflow processes.

[0087] Please refer to Figure 12 A planarization process can be performed to remove excess conductive material 150, substrate 142, and barrier layer 140, thereby forming conductive lines 160 within the opening 130. Additionally, the planarization process can remove remaining portions of the masking layer 126 and buffer layer 124, thus exposing the intermetallic dielectric (IMD) layer 110. The planarization process can be grinding or chemical mechanical polishing (CMP), and can be performed until the upper surfaces of the conductive material 150, substrate 142, barrier layer 140, and intermetallic dielectric (IMD) layer 110 are flush, or substantially flush. The conductive lines 160 include remaining portions of the conductive material 150 and remaining portions of the substrate 142 and barrier layer 140 extending along the sidewalls and bottom of the conductive material 150. Therefore, the conductive lines 160 are physically and electrically connected to the upper contact plug 92.

[0088] A capping layer 170 can be deposited on the intermetallic dielectric (IMD) layer 110, barrier layer 140, substrate 142, and conductive material 150 using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), electrochemical plating (ECP), electroless plating, and / or similar methods. The capping layer 170 may include cobalt, ruthenium, similar substances, or any combination thereof. The capping layer 170 can be considered as part of the conductive line 160. According to some embodiments, the capping layer 170 is deposited using chemical vapor deposition (CVD). Deposition may use a cobalt precursor comprising a molecule of cobalt attached to carbon, oxygen, hydrogen, or a combination thereof. After the material of the capping layer 170 is deposited, excess portions can be removed by any suitable method, such as lithography. Therefore, a photoresist (not specifically shown) can be formed and patterned on the material of the capping layer 170 to expose portions of the material of the capping layer 170 that are not directly above the conductive lines 160 (e.g., the substrate 142 and the conductive material 150). These exposed portions can then be removed by etching or any suitable method. In some embodiments, the capping layer 170 is selectively deposited on the conductive material 150. Alternatively, partial capping layers 170 may also be deposited on the substrate 142 (and possibly the barrier layer 140). The capping layer 170 can be deposited using any technique associated with the barrier layer 140, the substrate 142, or the conductive material 150. According to some embodiments, the thickness of the capping layer 170 may be approximately [missing information - likely a specific value]. to between.

[0089] According to some embodiments, and not specifically illustrated, prior to the deposition of the capping layer 170, approximately the upper portion of the conductive lines 160 (e.g., conductive material 150 and substrate 142) can be etched and recessed. to Between. Next, the capping material can be deposited on the above structure and fill the grooves by one of the methods listed above (e.g., selective deposition by chemical vapor deposition (CVD)).

[0090] exist Figure 13 In this process, an etch stop layer 208 is formed on the intermetallic dielectric (IMD) layer 110 and the conductive line 160. The etch stop layer 208 can be formed from similar materials and through similar processes, as described above in relation to the etch stop layer 108.

[0091] Please refer to Figure 13An intermetallic dielectric (IMD) layer 210 is formed on the etch stop layer 208. The IMD layer 210 can be formed from similar materials and through similar processes, as described above with respect to the IMD layer 110. The material of the etch stop layer 208 has a high etch selectivity to the IMD layer 210, therefore the etch stop layer 208 can be used to stop the etching of the IMD layer 210 in subsequent process steps.

[0092] A film stack is formed on the intermetallic dielectric (IMD) layer 210. According to some embodiments, the film stack is used to form metallized wiring and dielectric connection windows electrically connected to the conductive line 160. The film stack (not specifically shown) includes a buffer layer and a masking layer. In some embodiments, the film stack includes one or more buffer layers and masking layers, which may be formed alternately. The buffer layer and masking layer may be formed from similar materials and similar processes, as described above with respect to buffer layer 124 and masking layer 126.

[0093] Then, openings (not specifically shown) are formed within the aforementioned masking layer, extending through the aforementioned buffer layer, intermetallic dielectric (IMD) layer 210, and etch stop layer 208. These openings can be formed and extended using acceptable etching techniques and etchants associated with the openings 130. These openings expose the underlying conductive lines 160 (specifically, capping layer 170, if used). The etch stop layer 208 can be removed using anisotropic wet or dry etching that is selective to the material of the etch stop layer 208. For example, anisotropic wet etching (using an etchant such as H2O2) can be used to remove the etch stop layer 208. The etching process used to remove the etch stop layer 208 may differ from the etching process used to form the aforementioned openings (e.g., different etchants and / or other etching process parameters may be used).

[0094] As illustrated, the opening can be patterned using a dual damascene process. Therefore, the upper part of the opening accommodates the metallized wiring 260, while the lower part of the opening accommodates the metallized dielectric connection window 262 to electrically connect the metallized wiring 260 to the conductive line 160 located below.

[0095] A barrier layer 240 and a liner 242 are formed within the opening. The barrier layer 240 may be formed from similar materials and through similar processes, as described above with respect to the barrier layer 140. The liner 242 may be formed from similar materials and through similar processes, as described above with respect to the liner 142.

[0096] Please refer to Figure 13The conductive material 250 is filled into the opening and along the upper surface of the liner 242, and a planarization process is performed to remove excess conductive material 250, liner 242, and barrier layer 240 to form metallized wiring 260 and metallized dielectric connection window 262. The conductive material 250 can be formed from similar materials and through similar processes, as described above with respect to conductive material 150.

[0097] According to some embodiments, a deposition method (e.g., physical vapor deposition (PVD)) can be used to form the conductive material 250 within the opening. For example, a first copper deposition can be performed at room temperature, followed by a reflow process of approximately 1 minute to approximately 5 minutes at approximately 150°C to approximately 300°C. One or more copper deposition and reflow processes can be performed after the first cycle. In general, there can be one to five alternating cycles of deposition and reflow processes.

[0098] The planarization process removes excess conductive material 250, substrate 242, and barrier layer 240, thereby forming metallized wiring 260 and metallized dielectric connection window 262. Additionally, the planarization process removes remaining portions of the masking layer and buffer layer, thus exposing the intermetallic dielectric (IMD) layer 210. The planarization process can be grinding or chemical mechanical polishing (CMP), and can be performed until the upper surfaces of the conductive material 250, substrate 242, barrier layer 240, and intermetallic dielectric (IMD) layer 210 are flush, or substantially flush. The metallized wiring 260 and metallized dielectric connection window 262 include remaining portions of the conductive material 250 and remaining portions of the substrate 242 and barrier layer 240 extending along the sidewalls and bottom of the conductive material 250. The metallized wiring 260 is electrically connected to the conductive line 160 through the metallized dielectric connection window 262.

[0099] Furthermore, a capping layer 270 can be formed on the substrate 242 of the conductive material 250 and the metallized wiring 260. The capping layer 270 can be formed from a similar material (e.g., cobalt) and through a similar process, as described above with respect to the capping layer 170. The capping layer 270 can be considered as part of the metallized wiring 260. The capping layer 270 can have approximately [missing information - likely a measurement range]. to The thickness between.

[0100] After completing the metallized wiring 260 and the metallized interlayer connection window 262, additional metallized wiring (not specifically shown), such as the conductive line 160 or the metallized wiring 260 as described above, can be formed on the metallized wiring 260 using similar materials and similar processes. Connectors (also not specifically shown) can then be formed on the additional metallized wiring.

[0101] exist Figure 14In some embodiments, the second inner dielectric (ILD) layer 78 (as described above) Figures 1-3 The fabrication process may involve a relatively low concentration or density of hydroxyl groups along the exposed surface. Therefore, during the fabrication of the self-aligned monolayer 184, the monolayer precursor selectively reacts with or is attracted to isolated or fragmented hydroxyl groups, resulting in the formation of separations or fragments of the self-aligned monolayer 184 on the second inner dielectric (ILD) layer 78, such as... Figure 14 As illustrated in the figure. In some embodiments, the self-aligned monolayer 184 is fabricated by deposition of non-reactive organic molecules. The self-aligned monolayer 184 may form separations or fragments near and above isolated or isolated hydroxyl groups because the organic molecules are attracted to these regions without forming chemical bonds. The result of forming a silanized second inner dielectric (ILD) layer 78 or a self-aligned monolayer 84 comprising hydrophobic molecules is that the surface of the second inner dielectric (ILD) layer 78 can be changed from hydrophilic to hydrophobic.

[0102] exist Figure 15 In this process, a conductive material 190 is filled within the opening 80. The conductive material 190 can be formed from similar materials and through similar processes and mechanisms, as described above regarding the conductive material 90. Although there may be some uneven surface morphology (e.g., due to separation of the self-aligned monolayer 184), the growth of the conductive material 190 is generally carried out as described above when the self-aligned monolayer 184 provides a more uniform surface morphology. The benefits associated with not requiring a seed layer or barrier layer also apply.

[0103] exist Figure 16 In this process, the upper contact plug 192 is formed by planarizing (e.g., chemical mechanical polishing (CMP)) the conductive material 190, the self-aligned monolayer 184, and the second inner dielectric (ILD) layer 78. Therefore, the upper surfaces of the upper contact plug 192 and the second inner dielectric (ILD) layer 78 will be flush. Furthermore, the self-aligned monolayer 184 is removed from the upper surface of the second inner dielectric (ILD) layer 78 while still being directly sandwiched between the second inner dielectric (ILD) layer 78 and the upper contact plug 192. The formed upper contact plug 192 will achieve the aforementioned... Figures 5-6 Similar benefits. After forming the upper contact plug 192, the remaining processes follow the procedures outlined above. Figures 7-13 The same steps as described below.

[0104] In the above embodiments, the same or similar materials and processes are described for forming the conductive line 160 and the metallized wiring 260 with metallized dielectric connection window 262. Furthermore, compared to the corresponding step of forming the conductive line 160, one or more steps of forming the metallized wiring 260 with metallized dielectric connection window 262 may be performed using different materials and / or processes.

[0105] Figures 17-18 The illustration shows a cross-sectional schematic of an intermediate manufacturing stage of conductive feature components (e.g., plugs, contact pads, etc.) according to some embodiments. The conductive feature components may be the same as or similar to those described above, or may be conductive feature components formed in other steps of the semiconductor manufacturing process (e.g., patterning dielectric layers to form conductive feature components that couple underlying elements to subsequently formed upper elements or subsequently bonded semiconductor packages).

[0106] exist Figure 17 In this embodiment, a dielectric layer 278 has been formed on a substrate 250. The substrate 250 may be a semiconductor substrate or any film layer representing a previously formed semiconductor component. The dielectric layer 278 may be one or more layers, including materials such as silicon nitride, silicon oxide, silicon nitride oxide, similar materials, or any combination thereof. An underlying conductive feature 274 may have been formed within an opening 280 in the dielectric layer 278. In some embodiments, the underlying conductive feature 274 may have been formed on the substrate 250, and one or more layers of the dielectric layer 278 may have been formed around the underlying conductive feature 274.

[0107] As described above regarding other features, an exposed surface of dielectric layer 278 may include hydroxyl groups (-OH), which may reduce the selectivity for subsequent deposition of another conductive material into opening 280. Dielectric layer 278 may be modified in a manner similar to that described above. Figure 3 The cleaning process described in the relevant instructions is to increase the concentration of hydroxyl groups on the exposed surface along dielectric layer 278.

[0108] exist Figure 18 In this process, a self-aligned monolayer (SAM) 284 is formed on the dielectric layer 278. As described above, the self-aligned monolayer 284 protects the dielectric layer 278 (or a portion of the dielectric layer 278) from metal growth by increasing the selectivity between the growth of the conductive material 290 on the underlying conductive feature 274 and its growth on the surface of the dielectric layer 278 and / or the self-aligned monolayer 284 during the deposition of the conductive material 290. Similarly, as described above, the self-aligned monolayer 284 can be formed by reacting a monolayer precursor with hydroxyl groups extending from the surface of the dielectric layer 278 or by non-reactive molecules that are attracted and adsorbed onto the dielectric layer 278 (especially the hydroxyl groups of the dielectric layer 278) through flow.

[0109] After forming the self-aligned monolayer 284, conductive material 290 can be selectively deposited on the lower conductive feature 274, with a minimum amount of conductive material 290 deposited on the dielectric layer 278 or the self-aligned monolayer 284. Additionally, as described above, a planarization step or other process steps (not specifically shown) can be performed to form the conductive material 290 as the upper conductive feature 292.

[0110] The embodiments offer numerous advantages. Forming a self-aligned monolayer 84 / 184 / 284 on the second inner dielectric (ILD) layer 78 (or dielectric layer 278) improves selectivity for depositing conductive material 90 / 190 directly above the openings 80 / 280 and metals (e.g., metals within the gate electrode 64, lower contact plug 74, and conductive feature 274). For example, the self-aligned monolayer 84 / 184 / 284 may include silanization of hydroxyl groups along the exposed surface of the second inner dielectric (ILD) layer 78. Alternatively, the self-aligned monolayer 84 / 184 / 284 may include non-reactive chemicals attracted to or adsorbed onto or near the hydroxyl groups. In either case, the lack of exposed hydroxyl groups to attract the metal precursors used to form the conductive material 90 / 190 reduces or prevents the deposition of conductive material 90 / 190 onto the second inner dielectric (ILD) layer 78 (or dielectric layer 278).

[0111] Furthermore, the self-aligned monolayer 84 / 184 / a284 sandwiched between the second inner dielectric (ILD) layer 78 and the conductive material 90 / 190 / 290 (and the final upper contact plug 92 / 192) is thinner than the barrier layer (e.g., TiN or TaN) used in the upper contact plug or upper conductive feature 92 / 192 / 292. Therefore, the upper contact plug or upper conductive feature 92 / 192 / 292 has improved performance and reliability because the conductive material 90 / 190 / 290 includes a significant portion (substantially or nearly 100%) of the area located within the opening 80 / 280. Whether the self-aligned monolayer 84 / 184 / 284 includes silanization of hydroxyl groups or non-reactive chemicals that attract or adsorb to (or near) hydroxyl groups, forming the self-aligned monolayer 84 / 184 / 284 is more efficient, cheaper, and / or more effective than forming a conductive barrier layer. In addition, conductive materials 90 / 190 / 390 can be deposited with higher efficiency to form more reliable and efficient conductive feature components 92 / 192 / 292.

[0112] In one embodiment, a method of manufacturing a semiconductor device includes: forming a semiconductor feature on a substrate, the semiconductor feature including a conductive region; forming a dielectric layer on the semiconductor feature; patterning the dielectric layer to form a contact opening exposing an upper surface of the conductive region; forming a monolayer on the dielectric layer, maintaining the exposed upper surface of the conductive region; and depositing a conductive material within the contact opening. In one embodiment, prior to forming the monolayer, the dielectric layer includes an exposed surface having hydroxyl groups. In one embodiment, the method further includes: performing a chemical treatment on the dielectric layer prior to forming the monolayer. In one embodiment, the chemical treatment increases the hydroxyl concentration on an upper surface of the dielectric layer. In one embodiment, after forming the monolayer, the upper surface of the conductive region remains without a monolayer. In one embodiment, the monolayer is chemically bonded to the dielectric layer. In one embodiment, the method further includes: prior to forming the monolayer, an upper surface of the dielectric layer having a first contact angle with water; and after forming the monolayer, a bonding surface between the dielectric layer and the monolayer having a second contact angle with water, the second contact angle being larger than the first contact angle. In one embodiment, after depositing the conductive material, the upper surface of the monolayer remains free of conductive material.

[0113] In another embodiment, a method of manufacturing a semiconductor device includes: forming a first dielectric layer on a substrate; forming a first opening in the first dielectric layer to expose the substrate; forming a first conductive feature in the first opening, the first conductive feature including a metal; forming a second dielectric layer on the first dielectric layer and the first conductive feature, wherein, when forming the second dielectric layer, the second dielectric layer includes exposed hydroxyl groups having a first concentration; forming a second opening in the second dielectric layer to expose the first conductive feature; flowing a monolayer precursor on the second dielectric layer to form a monolayer on the second dielectric layer, wherein, after forming the monolayer, the second dielectric layer includes exposed hydroxyl groups having a second concentration, the second concentration being less than the first concentration; and flowing a metal precursor on the second dielectric layer to deposit a metal feature in the second opening and on the first conductive feature. In one embodiment, the method further includes: performing a chemical treatment before flowing the monolayer precursor, wherein after the chemical treatment, the second dielectric layer includes exposed hydroxyl groups having a third concentration greater than a first concentration. In one embodiment, the second dielectric layer includes silicon oxide. In one embodiment, before flowing the monolayer precursor, the metal precursor has a first selectivity for metals relative to the second dielectric layer, wherein after flowing the monolayer precursor, the metal precursor has a second selectivity for metals relative to the second dielectric layer, the second selectivity being greater than the first selectivity. In one embodiment, the metal feature includes tungsten. In one embodiment, the monolayer precursor reacts with the exposed hydroxyl groups. In one embodiment, the monolayer precursor is attracted to the exposed hydroxyl groups without bonding. In one embodiment, the monolayer precursor is an organic molecule.

[0114] In another embodiment, a semiconductor device includes: a first conductive feature embedded in a substrate; a first dielectric layer disposed on the first conductive feature; a second conductive feature extending through the first dielectric layer; a second dielectric layer disposed on the first dielectric layer; a self-aligned monolayer disposed on the second dielectric layer; and a third conductive feature extending through the second dielectric layer, a portion of the self-aligned monolayer being sandwiched between the second dielectric layer and the third conductive feature. In one embodiment, the aforementioned portion of the self-aligned monolayer is continuous over a substantial distance from the upper surface to the lower surface of the second dielectric layer. In one embodiment, the self-aligned monolayer is chemically bonded to the second dielectric layer. In one embodiment, the self-aligned monolayer comprises a molecule that is different from the materials of the second dielectric layer, the second conductive feature, and the third conductive feature.

[0115] The foregoing summary describes the feature components of several embodiments of the present invention, enabling those skilled in the art to more readily understand the nature of this disclosure. Anyone skilled in the art should understand that this disclosure can be readily used as a basis for changes or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Anyone skilled in the art will also understand that equivalent structures described above do not depart from the spirit and scope of this disclosure, and that modifications, substitutions, and refinements can be made without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device, comprising: A semiconductor feature is formed on a substrate, the semiconductor feature including a conductive region; A dielectric layer is formed on the semiconductor feature; The dielectric layer is patterned to form a contact opening that exposes an upper surface of the conductive region; Forming a monolayer on the dielectric layer includes flowing a non-reactive monolayer precursor onto the upper surface of the conductive region that remains exposed; and A conductive material is deposited inside the contact opening.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the dielectric layer includes an exposed surface having hydroxyl groups before the monolayer is formed.

3. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: Before the formation of this monolayer, the dielectric layer undergoes a chemical treatment.

4. The method of manufacturing a semiconductor device as claimed in claim 3, wherein the chemical treatment increases the concentration of a hydroxyl group on an upper surface of the dielectric layer.

5. The method of manufacturing a semiconductor device as claimed in claim 1, wherein after the monolayer is formed, the upper surface of the conductive region remains free of the monolayer.

6. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the monolayer is chemically bonded to the dielectric layer.

7. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: Before the formation of this monolayer, an upper surface of the dielectric layer has a first contact angle with water; as well as After the monolayer is formed, the dielectric layer and one of the bonding surfaces of the monolayer have a second contact angle with water, the second contact angle being greater than the first contact angle.

8. The method of manufacturing a semiconductor device as claimed in claim 1, wherein after the conductive material is deposited, an upper surface of the monolayer remains free of the conductive material.

9. A method for manufacturing a semiconductor device, comprising: A first dielectric layer is formed on a substrate; A first opening is formed within the first dielectric layer to expose the substrate; A first conductive feature is formed in the first opening, the first conductive feature comprising a metal; A second dielectric layer is formed on the first dielectric layer and the first conductive feature, wherein when the second dielectric layer is formed, the second dielectric layer includes exposed hydroxyl groups having a first concentration; A second opening is formed within the second dielectric layer to expose the first conductive feature component; A monolayer precursor is flowed onto the second dielectric layer to form a monolayer on the second dielectric layer, wherein after the monolayer is formed, the second dielectric layer includes exposed hydroxyl groups having a second concentration, the second concentration being less than the first concentration; and A metal precursor is flowed onto the second dielectric layer to deposit a metal feature in the second opening and on the first conductive feature.

10. The method of manufacturing a semiconductor device as claimed in claim 9, further comprising: Before the flow of the monolayer precursor, a chemical treatment is performed, and after the chemical treatment, the second dielectric layer includes exposed hydroxyl groups with a third concentration greater than the first concentration.

11. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the second dielectric layer comprises silicon oxide.

12. The method of manufacturing a semiconductor device as claimed in claim 9, wherein before the monolayer precursor is flowed, the metal precursor has a first selectivity for a metal relative to the second dielectric layer, wherein after the monolayer precursor is flowed, the metal precursor has a second selectivity for that metal relative to the second dielectric layer, the second selectivity being greater than the first selectivity.

13. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the metal feature component comprises tungsten.

14. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the monolayer precursor reacts with the exposed hydroxyl groups.

15. The method of manufacturing a semiconductor device as claimed in claim 9, wherein the monolayer precursor is attracted to the exposed hydroxyl groups without bonding.

16. The method of manufacturing a semiconductor device as claimed in claim 15, wherein the monolayer precursor is an organic molecule.

17. A semiconductor device, comprising: A first conductive feature component is embedded in a substrate; A first dielectric layer is disposed on the first conductive feature component; A second conductive feature extends through the first dielectric layer; A second dielectric layer is disposed on the first dielectric layer; A self-aligned monolayer is disposed on the second dielectric layer, wherein the self-aligned monolayer comprises organic molecules that do not react with the second dielectric layer; and A third conductive feature extends through the second dielectric layer, and a portion of the self-aligned monolayer is sandwiched between the second dielectric layer and the third conductive feature.

18. The semiconductor device of claim 17, wherein the portion of the self-aligned monolayer is continuous over a substantial distance from an upper surface of the second dielectric layer to a lower surface of the second dielectric layer.

19. The semiconductor device of claim 17, wherein the self-aligned monolayer is chemically bonded to the second dielectric layer.

20. The semiconductor device of claim 17, wherein the organic molecule is different from the material of the second dielectric layer, the material of the second conductive feature, and the material of the third conductive feature.

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