Semiconductor structure and method of forming the same

Abstract

The method includes depositing a dielectric layer, depositing a plurality of core strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of core strips to form a plurality of mask groups. Each of the plurality of core strips and two of the plurality of spacers form a mask group of the plurality of mask groups. The method also includes forming a mask strip connecting two adjacent mask groups of the plurality of mask groups, etching the dielectric layer using the plurality of mask groups and the mask strip collectively as an etch mask to form a trench in the dielectric layer, and filling a conductive material into the trench to form a plurality of conductive features. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor structures and methods of forming them. Background Technology

[0002] Metal-oxide-semiconductor (MOS) devices are fundamental components in integrated circuits. Recent developments in MOS devices include the formation of a replacement gate, which comprises a high-k gate dielectric and a metal gate electrode above the high-k gate dielectric. Forming the replacement gate typically involves depositing a high-k gate dielectric layer and a metal layer over the high-k gate dielectric layer, followed by a chemical mechanical polishing (CMP) process to remove excess portions of the high-k gate dielectric layer and the metal layer. The remaining portion of the metal layer forms the metal gate.

[0003] Interconnect components are then formed. For example, source / drain contact plugs and gate plugs are formed to connect to the source / drain region and the metal gate, respectively. Metal lines and vias are also formed above and connected to the device below. As the device is scaled down, the linewidth of the interconnect components and the spacing between the interconnect components become smaller and smaller. As a result, the optical proximity effect becomes more severe, and the line ends of the interconnect components become rounded. This reduces the effective contact area of ​​the interconnect components available for bonding the conductive components above, and increases the contact resistance. Summary of the Invention

[0004] Some embodiments of this application provide a method for forming a semiconductor structure, including: depositing a dielectric layer; depositing a plurality of mandrel strips over the dielectric layer; forming a plurality of spacers on the sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group among the plurality of mask groups; forming a mask strip connecting two adjacent mask groups among the plurality of mask groups; using the plurality of mask groups and the mask strips together as an etching mask to etch the dielectric layer and form trenches in the dielectric layer; and filling the trenches with a conductive material to form a plurality of conductive components.

[0005] Other embodiments of this application provide a semiconductor structure including: a semiconductor substrate; a dielectric layer located above the semiconductor substrate; a first conductive member including: a first end, wherein the first end is curved and has a first radius; and a second end opposite to the first end, wherein the second end is curved and has a second radius smaller than the first radius; a second conductive member spaced apart from the first end of the first conductive member by a first portion of the dielectric layer, wherein the second conductive member has a first distance from the first end; and a third conductive member spaced apart from the second end of the first conductive member by a second portion of the dielectric layer, wherein the third conductive member has a second distance from the second end, and the second distance is smaller than the first distance, and wherein the first conductive member, the second conductive member, and the third conductive member have a longitudinal direction aligned with the same straight line.

[0006] Further embodiments of this application provide a semiconductor structure including: a plurality of conductive components having a longitudinal direction aligned with a straight line, wherein the plurality of conductive components includes a first end component, a second end component, and at least one intermediate conductive component between the first end component and the second end component, and the first end component includes: a first end facing away from the second end component, wherein the first end has a first angle; and a second end facing the second end component, wherein the second end has a second angle that is sharper than the first angle; and a dielectric layer, wherein the upper portions of the plurality of conductive components are located in the dielectric layer. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figures 1-8 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 18 , Figure 23 and Figure 34 Perspective and cross-sectional views are shown in the formation of fin field-effect transistors (FinFETs) and interconnect components according to some embodiments.

[0009] Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B and Figure 11C Top view and perspective view of a metal gate being cut according to some embodiments are shown.

[0010] Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C Top and perspective views are shown in the formation and cutting of source / drain contact plugs according to some embodiments.

[0011] Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B and Figure 22C Top and perspective views of a cut in a single tessellation structure according to some embodiments are shown.

[0012] Figure 24 , Figure 25A , Figure 25B , Figure 26A , Figure 26B , Figures 27-29 , Figure 30A , Figure 30B and Figures 31-33 Top view and perspective view of the formation of the mosaic structure according to some embodiments are shown.

[0013] Figure 35 and Figure 36 The shape of a conductive component according to some embodiments is shown.

[0014] Figure 37 A conductive component layer in a wafer according to some embodiments is shown.

[0015] Figure 38 A process flow for forming FinFETs and interconnect components according to some embodiments is shown. Specific implementation methods

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] FinFETs, corresponding interconnects, and methods for forming the FinFETs and cutting the corresponding interconnects are provided. According to some embodiments of the invention, the interconnects include a metal gate, source / drain contact plugs, metal wires, etc., formed first, and then cut into shorter portions. The corners of the conductive components are sharper using the forming process provided by the embodiments of the invention. It should be understood that while FinFETs are used as examples, other types of transistors and corresponding interconnects are also within the scope of the invention. The embodiments discussed herein are intended to provide examples enabling the manufacture or use of the subject matter of the invention, and modifications that can be made while remaining within the intended scope of the different embodiments will be readily understood by those skilled in the art. In the various views and illustrative embodiments, the same reference numerals are used to denote the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0019] Figures 1-8 , Figure 12A , Figure 12B , Figure 13A , Figure 13B , Figure 18 , Figure 23 and Figure 34 Perspective and cross-sectional views of intermediate stages in the formation of the FinFET and the interconnect components described above, according to some embodiments of the present invention, are shown. The corresponding processes are also schematically illustrated in... Figure 38 The process flow shown is as follows.

[0020] Figure 1 A perspective view of the initial structure formed on wafer 10 is shown. Wafer 10 includes a substrate 20. Substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. Substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed extending from the top surface of substrate 20 into substrate 20. Corresponding processes are described in... Figure 38 The process flow 200 is shown as process 202. The portion of substrate 20 located between adjacent STI regions 22 is referred to as semiconductor strip 24. The top surface of semiconductor strip 24 and the top surface of STI region 22 may be substantially flush with each other. According to some embodiments of the invention, semiconductor strip 24 is part of the original substrate 20, and therefore the material of semiconductor strip 24 is the same as that of substrate 20. According to an alternative embodiment of the invention, semiconductor strip 24 is a replacement strip formed by etching the portion of substrate 20 located between STI regions 22 to form a groove and performing an epitaxial process to grow another semiconductor material in the groove. Therefore, semiconductor strip 24 is formed of a semiconductor material different from that of substrate 20. According to some embodiments, semiconductor strip 24 is formed of silicon germanium, silicon carbon, or group III-V compound semiconductor materials.

[0021] STI region 22 may include a pad oxide (not shown), which may be a thermal oxide layer formed by thermal oxidation of a surface layer of substrate 20. The pad oxide may also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. STI region 22 may also include a dielectric material located above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0022] refer to Figure 2 This causes the STI region 22 to be recessed, so that the top of the semiconductor strip 24 protrudes above the top surface 22T of the remaining portion of the STI region 22 to form a protruding fin 24'. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 204. Etching can be performed using a dry etching process, for example, using NF3 and NH3 as etching gases. According to an alternative embodiment of the invention, the recess of the STI region 22 is performed using a wet etching process. For example, the etching chemicals may include a diluted HF solution.

[0023] In the above embodiments, fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0024] Reference Figure 3 The dummy gate stack 30 is formed to extend on the top surface and sidewalls of the (protruding) fin 24'. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 206. The dummy gate stack 30 may include a dummy gate dielectric (not shown) located on the sidewall of the protruding fin 24', and a dummy gate electrode 34 located above the respective dummy gate dielectric. The dummy gate dielectric may include silicon oxide. The dummy gate electrode 34 may be formed using polysilicon or other materials. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 located above the corresponding dummy gate electrode 34. The hard mask layer 36 may be formed of silicon nitride, silicon oxide, silicon oxynitride, or multiple layers thereof. The dummy gate stack 30 may span over one or more protruding fins 24' and / or STI regions 22. The dummy gate stack 30 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fin 24'.

[0025] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 206. According to some embodiments of the invention, the gate spacer 38 is formed of a dielectric material such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multi-layer structure including multiple dielectric layers.

[0026] Then an etching process is performed to etch the portion of the protruding fin 24' that is not covered by the dummy gate stack 30 and the gate spacer 38, thereby producing Figure 4 The structure is shown. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 208. The recess can be anisotropic, and therefore the portion of fin 24' located directly below the dummy gate stack 30 and gate spacer 38 is protected and not etched. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22T of the STI region 22. The space left by the etched protruding fin 24' and semiconductor strip 24 is referred to as a groove 40. The groove 40 is located on opposite sides of the dummy gate stack 30.

[0027] Next, as Figure 5 As shown, epitaxial regions (source / drain regions) 42 are formed by selectively growing (by epitaxy) semiconductor material in the groove 40. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 210. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ during the epitaxial process. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. According to an optional embodiment of the invention, the epitaxial region 42 includes III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the trench 40 is filled with the epitaxial region 42, further epitaxial growth of the epitaxial region 42 causes the epitaxial region 42 to extend horizontally and can form a small facet. Further growth of the epitaxial region 42 can also cause adjacent epitaxial regions 42 to merge with each other. Voids (air gaps) 44 may be generated. According to some embodiments of the present invention, the formation of the epitaxial region 42 can be completed while the top surface of the epitaxial region 42 is still wavy, or when the top surface of the merged epitaxial regions 42 has become flat. This can be achieved by means of... Figure 6 This is achieved by further growth on the epitaxial region 42, as shown.

[0028] Following the epitaxial process, the epitaxial region 42 can be further implanted with p-type or n-type impurities to form the source and drain regions, also referred to by reference numeral 42. According to an optional embodiment of the invention, when the epitaxial region 42 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation process is skipped.

[0029] Figure 7 A perspective view of the structure after the formation of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48 is shown. The corresponding process is as follows: Figure 38The process flow 200 is shown as process 212. CESL 46 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or other deposition processes. ILD 48 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as chemical mechanical polishing (CMP) or mechanical polishing, can be performed to make the top surfaces of ILD 48, dummy gate stack 30, and gate spacer 38 flush with each other.

[0030] Next, the dummy gate stack 30, which includes the hard mask layer 36, the dummy gate electrode 34, and the dummy gate dielectric, is replaced with a replacement gate stack 56, which includes the metal gate electrode 54 and the gate dielectric 52. Figure 8 As shown. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 214. When forming the replacement gate stack 56, the hard mask layer 36 and the dummy gate electrode 34 (e.g., ...) are first removed in one or more etching processes. Figure 7 (As shown) and a dummy gate dielectric, thereby creating trenches / openings between gate spacers 38. The top surface and sidewalls of the protruding semiconductor fin 24' are exposed to the created trenches.

[0031] Next, as Figure 8 As shown, a perspective view illustrates the formation of a replacement gate dielectric layer 52 extending into the trench between the gate spacers 38. According to some embodiments of the invention, each gate dielectric layer 52 includes an interface layer (IL) 52' as its lower portion. Figure 12B The gate dielectric layer 52' ​​contacts the exposed surface of the corresponding protruding fin 24'. IL 52' may include an oxide layer, such as a silicon oxide layer, formed by thermal oxidation, chemical oxidation, or deposition processes of the protruding fin 24'. The gate dielectric layer 52 may also include a high-k dielectric layer 52" formed above IL 52'. The high-k dielectric layer 52" may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the sidewalls of the gate spacer 38. According to some embodiments of the invention, the high-k dielectric layer is formed using ALD or CVD.

[0032] Further reference Figure 8 Gate electrode 54 (also in) Figure 12B(Shown in image) Formed on gate dielectric 52. Gate electrode 54 includes stacked conductive layers. Layers in the stacked conductive layers are not shown individually, but the stacked conductive layers can be distinguished from each other. The stacked conductive layers can be deposited using conformal deposition methods such as ALD or CVD. The stacked conductive layers may include a diffusion barrier layer (sometimes also called a binder layer) and one (or more) work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of or include titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layers determine the work function of the gate and include at least one layer, or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer and a TiN layer above the TaN layer. After depositing the work-function layer, a binder layer is formed, which can be another TiN layer. The binder layer may or may not completely fill the trenches left by the removed dummy gate stack.

[0033] The deposited gate dielectric and conductive layers are formed as conformal layers extending into the trench and including a portion above ILD 48. Next, if the adhesive layer does not completely fill the trench, a metal material is deposited to fill the remaining trench. For example, the metal material may be formed of or include tungsten or cobalt. Subsequently, a planarization process, such as a CMP process or a mechanical polishing process, is performed to remove portions of the gate dielectric layer, the stacked conductive layers, and the metal material above ILD 48. As a result, gate electrode 54 and gate dielectric 52 are formed. Gate electrode 54 and gate dielectric 52 are collectively referred to as replacement gate stack 56. At this point, the top surfaces of replacement gate stack 56, gate spacer 38, CESL 46, and ILD 48 can be substantially coplanar.

[0034] After formation, the gate stack 56 is cut into shorter gate stacks, wherein dielectric isolation regions 62 are formed to electrically isolate the shorter gate stacks 56 from each other. The corresponding process is as follows: Figure 38 The process flow shown in 200 is illustrated as process 216. Shorter gate stacks can belong to different FinFETs. Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 13A and Figure 13B Top and perspective views of a cut metal gate according to some embodiments are shown. The figures are numbered with the characters “A”, “B”, or “C”. The character “A” indicates that the corresponding figure shows a top view. The character “B” indicates that the corresponding figure shows a reference section “BB” in the corresponding top view. The character “C” indicates that the corresponding figure shows a reference section “CC” in the corresponding top view.

[0035] refer to Figure 9A The diagram shows a top view of two gate stacks 56 and corresponding gate spacers 38. The gate stacks 56 and gate spacers 38 are surrounded by CESL 46 and ILD 48. According to some embodiments, the ends of the gate stacks are rounded due to the smaller pitch and width of the gate stacks. Figure 9B and Figure 9C They respectively show from Figure 9A The cross-sectional views are obtained from reference sections BB and CC. Details of the gate stack are not shown in detail and can be found in reference [reference needed]. Figure 8 turn up.

[0036] refer to Figure 10A , Figure 10B and Figure 10C In the photolithography process, the gate stack 56 is cut, wherein an etching mask 59 (such as photoresist, etc.) is formed. Figure 10A As shown), the gate stack 56 is etched to form an opening 60. The dicing is performed using an etch mask 59 (such as photoresist) that defines the pattern of the opening 60. The opening in the etch mask 59 may extend laterally beyond the edge of the gate stack 56 (instead of being flush with the edge of the gate spacer 38) to reduce line-end rounding. Separated portions of the original identical gate stack 56 are disconnected from each other by the dicing process. The opening 60 may extend into and stop in the underlying STI region 22, or it may extend further into the underlying substrate 20. For example, Figure 8 The dielectric isolation region 62 (filled opening 60) extends into the semiconductor substrate 20. According to some embodiments, the etch gas is selected such that gate spacers 38, CESL 48, and ILD 48 are not etched, and opening 60 is confined between opposing portions of gate spacer 38. According to alternative embodiments, gate spacer 38 and possibly CESL 48 and ILD 48 are also etched, and opening 60 extends into gate spacer 38, and may or may not extend into CESL 46 and ILD 48.

[0037] refer to Figure 11A , Figure 11B and Figure 11CA gate isolation region 62 is formed to fill the opening 60. According to some embodiments, the formation process may include depositing a dielectric material, such as silicon nitride, silicon oxide, silicon oxycarbide, silicon oxynitride, etc., and then performing a planarization process (such as a CMP process or a mechanical polishing process) to remove excess portions of the dielectric material.

[0038] Figure 12A and Figure 12B The formation of a (self-aligned) hard mask 58 according to some embodiments is shown, wherein Figure 12B It shows Figure 12A Reference section 12B-12B. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 218. Forming the hard mask 58 may include performing an etching process to recess the gate stack 56, thereby forming trenches between the gate spacers 38, filling the trenches with a dielectric material, and then performing a planarization process (such as a CMP process or a mechanical polishing process) to remove excess dielectric material. The hard mask 58 may be formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0039] Next, refer to Figure 13A and Figure 13B An etch stop layer 82 and an ILD 84 are deposited. The etch stop layer 82 can be made of silicon nitride, silicon oxynitride (SiO2), silicon oxycarbide (SiO2C), silicon carbonitride (SiCN), aluminum nitride (AlN), or aluminum oxide (AlO2). X ILD 80 can be formed from materials similar to ILD 48, or in multiple layers thereof.

[0040] Figure 13A and Figure 13B A perspective view and a cross-sectional view are also shown, respectively, of the formation of the source / drain silicide region 66 and the contact plug 68. The corresponding process is as follows: Figure 38 The process flow 200 shown is illustrated as process 220. Figure 13B It shows Figure 13A Reference section 13B-13B. The formation process may include etching ILD 84, etching stop layer 82 and ILD 48 to expose a portion of the underlying CESL 46, etching the exposed portion of CESL 46 to expose epitaxial region 42, and depositing metal layer 70. Figure 13B A metal nitride layer (e.g., titanium nitride layer) 72 is deposited, and an annealing process is performed to form source / drain silicide regions 66. Next, a metal material 74, including cobalt, tungsten, etc., can be filled into the remaining portion of the contact opening. Then, a planarization process, such as CMP or mechanical polishing, is performed to remove excess portions of the metal layer 70, metal nitride layer 72, and metal material 74, leaving contact plugs 68. This forms the FinFET 100.

[0041] Next, the source / drain contact isolation region 76 is formed, which is also... Figure 13A As shown in the image. Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B and Figure 17C The top view and cross-sectional view also show the formation process of the contact plug 68 and the source / drain contact isolation region 76. The corresponding process for forming the contact isolation region 76 is as follows: Figure 38 The process flow 200 shown is illustrated as process 222. These processes are briefly described here. Furthermore, the drawing number may be followed by the characters A, B, or C, where character A indicates that the corresponding drawing shows a top view, and characters B or C indicate that the corresponding drawing is obtained from the reference section BB or CC of the corresponding top view.

[0042] refer to Figure 14A , Figure 14B and Figure 14C By etching the ILD 48 above the source / drain region 42 ( Figure 11A The source / drain contact opening 67 is formed by the portions of CESL46 and CESL46. The underlying source / drain region 42 is exposed. Next, refer to... Figure 15A , Figure 15B and Figure 15C This forms the source / drain contact plug 68. Details of the source / drain contact plug 68 can be found in [reference needed]. Figure 13A and Figure 13B turn up. Figure 16A , Figure 16B and Figure 16C A cut (etch) is shown for the source / drain contact plug 68 used to form the opening 77. The cut is performed using an etch mask (such as photoresist) 75, which defines the pattern of the opening 77. The opening in the etch mask 75 may extend laterally beyond the edge of the source / drain contact plug 68 (instead of being flush with the edge of the gate spacer 38) to reduce line-end rounding. (See also...) Figure 13A As illustrated by the source / drain contact isolation region 78, the opening 77 can extend into (and stop within) the STI region 22 or the semiconductor substrate 20. Then, removal is performed as follows: Figure 16A The etching mask 75 shown.

[0043] Figure 17A , Figure 17B and Figure 17CThe diagram illustrates the formation of the source / drain contact isolation region 78, which is also... Figure 13A As shown in the figure. The formation process and materials of the source / drain contact isolation region 78 are similar to those of the gate contact isolation region 62, and will not be described again here.

[0044] Figure 18 The formation of etch stop layer 86 and ILD 88 is illustrated. The formation process and materials of etch stop layer 86 and ILD 88 are similar to those of etch stop layer 82 and ILD 84, respectively. Contact plug 90 and gate contact plug 92 are then formed. The formation process includes etching ILD 88, etch stop layer 86, ILD 84, etch stop layer 82, and hard mask 58 to form openings, depositing conductive material, and then performing a planarization process to remove excess conductive material. The remaining portion of the conductive material forms contact plugs 90 and 92.

[0045] Next, as Figure 18 As shown, an etch stop layer 94 and a dielectric layer 96 are deposited. The etch stop layer 94 can be formed of a material selected from the same group of candidate materials used to form etch stop layers 82 and 86. The dielectric layer 96 can be an ILD, which can be formed of a material selected from the same group of candidate materials used to form ILD 48. Optionally, the dielectric layer 96 is an intermetallic dielectric (IMD). According to some embodiments of the invention, the IMD can be formed of a low-k dielectric material having a dielectric constant (k value) below about 3.0. For example, when the dielectric layer 96 is an IMD, it can be formed of or include carbon-containing low-k dielectric materials, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), etc. The dielectric layer 96 can be porous.

[0046] Conductive components 98A and 98B (which may be metal wires or contact plugs) are formed in dielectric layer 96. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 224. According to some embodiments, the forming process may include a single damascene process, which includes etching a dielectric layer 96 and an etch stop layer 94 to form a trench, filling the trench with a conductive material, and performing a CMP process to remove excess conductive material. Each of the conductive components 98A and 98B may include a diffusion barrier layer 98' and a metal material 98" above the diffusion barrier layer 98'. The diffusion barrier layer 98' may be formed of or include titanium nitride, tantalum nitride, titanium, tantalum, etc. The diffusion barrier layer 98' may have a basin shape, wherein the lower portion is narrower than the corresponding upper portion. The metal material 98" may include copper or a copper alloy. Due to the single damascene process, the conductive components 98A and 98B may be tapered, wherein the upper portion is wider than the corresponding lower portion.

[0047] According to an optional embodiment, conductive components 98A and 98B are formed by a deposition and patterning process, which includes depositing a blanket metal layer and performing a first etching process to pattern the blanket metal layer into conductive components 98A and 98B. An etch stop layer 94 and a dielectric layer 96 are then formed. The etch stop layer 94 may conformally extend on the top surface and sidewalls of the conductive components 98A and 98B. The dielectric layer 96 may have portions overlapping with the conductive components 98A and 98B. The top surface of the dielectric layer 96 may be planar or non-planar.

[0048] Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B , Figure 21C , Figure 22A , Figure 22B and Figure 22C The above reference is shown. Figure 18 The formation of the conductive components 98A and 98B under discussion, and the further cutting of conductive component 98B. These figures show the top view and corresponding cross-sectional view obtained from reference sections B'-B' and C'-C' in the respective top views.

[0049] Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B and Figure 20C As shown Figure 18 The formation of conductive components 98A and 98B is shown. (Reference) Figure 19A , Figure 19B and Figure 19C Etch IMD 96 and etch stop layer 94 to form opening 112. Expose the underlying metal parts 90 and 92. Next, as... Figure 20A , Figure 20B and Figure 20C As shown, conductive components 98A and 98B are formed using a single damascene process to fill opening 112. (Reference) Figure 21A , Figure 21B and Figure 21C An etching mask 114 is formed, and the etching mask 114 has an opening 113. The etching mask 114 and the opening 113 are also... Figure 18 As shown in the figure. An etching mask 114 is used to etch the conductive component 98B such that an opening 115 is formed in the conductive component 98B and extends downward to penetrate the conductive component 98B. According to some embodiments, such as Figure 21AAs shown, the portion of IMD 96 exposed to opening 115 is not etched, and opening 115 is confined within conductive component 98B. According to an alternative embodiment, conductive component 98B, IMD 96, and etch stop layer 94 are etched. The portion of etch stop layer 94 exposed to the removed portion of IMD 96 may or may not be etched through. Opening 115 has the same top-view shape and dimensions as opening 113 in etch mask 114. Conductive component 98B is divided into portions 98B1 and 98B2 by opening 115. Etching mask 114 is then removed.

[0050] After removing the etch mask 114, dielectric material is filled into the opening 113, followed by a planarization process to form the isolation region 116, as shown below. Figure 22A , Figure 22B and Figure 22C As shown. The corresponding process is as follows: Figure 38 The process flow 200 shown is illustrated as process 226. The isolation zone 116 can be formed from S1N, S1C, S1O2, S1CN, S1OC, etc. It should be understood that, although... Figures 21A-22A The conductive component 98B is shown to be cut into two parts, but it can be cut into more parts, such as... Figure 35 As shown (represented by components 150A, 150B, and 150C). According to some embodiments, isolation region 116 has an edge aligned with the edges of conductive portions 98B1 and 98B2. According to alternative embodiments, isolation region 116 extends beyond the edges of conductive portions 98B1 and 98B2 and into IMD 96, and may or may not extend into etch stop layer 94.

[0051] Figure 23 A cross-sectional view of isolation region 116 is shown. Isolation region 116 penetrates dielectric layer 96 and etch stop layer 94 and contacts ILD 88. Both diffusion barrier layer 98' and metal material 98" are cut open such that in each of conductive parts 98B1 and 98B2, diffusion barrier layer 98' extends on one sidewall of metal material 98" and not on the other sidewall of metal material 98". Furthermore, the opposite sidewalls of conductive parts 98B1 and 98B2 can be inclined in the same direction, unlike uncut metal parts such as 98A, where opposite sidewalls are inclined in opposite directions. It should be understood that if in relation to Figure 23 Viewed in a vertical cross-section as shown, the shapes of conductive components 98B1 and 98B2 are substantially the same as those of conductive component 98A. For example, in another cross-sectional view, conductive components 98B1 and 98B2 have opposing sidewalls inclined in opposite directions, and also have diffusion barriers 98' extending on the opposing sidewalls of the metallic material 98". These shapes are the result of the original basin shape of the diffusion barriers 98' before cutting and the cutting process.

[0052] Although not shown in detail, the source / drain contact plug 68 includes a nitride layer 72 and filler metal 74, similar to the case where conductive component 98A includes a diffusion barrier 98' and filler metal 98". Furthermore, the source / drain contact plug 68 is cut, similar to the cutting of conductive component 98B. Therefore, the side view of the cut portion of the source / drain contact plug 68 can be the same as the side view of conductive components 98B1 and 98B2. Additionally, before cutting the source / drain contact plug 68, the nitride layer 72 forms a basin shape similar to that of the diffusion barrier 98'. Therefore, the view of the cut nitride layer 72 will be the same as the view of the diffusion barrier 98'.

[0053] According to some embodiments of forming conductive components 98A and 98B by deposition and patterning (rather than damascene process), the formation of conductive components 98B1 and 98B2 involves two etching (patterning) processes, wherein a first etching process is performed on the blanket metal layer to form conductive components 98A and 98B, and a second etching process is performed on the conductive component 98B to form conductive components 98B1 and 98B2.

[0054] Figure 23 The formation of an etch stop layer 120, a dielectric layer 122 (which may be an IMD), and a hard mask 124 is also shown. The corresponding processes are as follows: Figure 38 The process flow 200 is shown as process 228. According to some embodiments, the etch stop layer 120 is formed using a similar material and a similar method to the etch stop layer 86. The IMD 122 may be formed of or include a low-k dielectric material similar to that of the IMD 96. The hard mask 124 may have a single-layer or multi-layer structure. According to some embodiments, the hard mask 124 has an ONO structure comprising a silicon oxide layer 124A, a silicon nitride layer 124B above the silicon oxide layer 124A, and another silicon oxide layer 124C above the silicon nitride layer 124B.

[0055] Figures 24 to 33 A perspective view is shown of the process for patterning a hard mask 124, etching a dielectric layer 122 and an etch stop layer 120 using the patterned hard mask 124, and forming conductive components in the dielectric layer 122 and the etch stop layer 120.

[0056] Figure 24 It shows Figure 23 The three-dimensional view of dielectric layer 122 and hard mask 124 already shown is presented. Next, as... Figure 25A As shown, a mandrel 126 is formed above the hard mask 124. The corresponding process is as follows: Figure 38The process flow 200 is shown as process 230. According to some embodiments of the invention, the mandrel 126 is formed of amorphous silicon, amorphous carbon, or another material having high etch selectivity relative to the underlying hard mask 124. The mandrel 126 is formed by depositing a blanket layer and then etching (patterning) the blanket layer to form the mandrel 126. The patterning of the mandrel 126 is achieved by forming a patterned photoresist or a three-layer structure. According to some embodiments, such as Figure 25B As shown in the top view, the mandrel 126 includes an elongated strip extending in the Y direction and an elongated strip extending in the X direction, defining an opening in the elongated strip. According to an alternative embodiment, there is no elongated strip extending in the X direction, and all mandrel strips extend in the Y direction. According to these embodiments, a subsequently formed mask strip can be used to define the boundary of the opening in the Y direction.

[0057] refer to Figure 26A and Figure 26B These figures show a perspective view and a top view, respectively, of the spacer 128 formed on the sidewall of the mandrel 126. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 232. According to some embodiments, the formation of spacer 128 includes depositing a conformal spacer layer and performing an anisotropic etching process to remove the horizontal portions of the spacer layer, while retaining the vertical portions of the spacer layer, and is referred to as spacer 128. According to some embodiments of the invention, spacer 128 includes silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, etc. Figure 26B As shown, when the mandrel 126 includes an elongated strip along the X direction, the spacer 128 may include a ring. The formation of the spacer 128 can reduce the size of the area surrounded by the ring, thereby reducing the width of the metal part to be formed in subsequent processes. Throughout the description, each mandrel 126 and the spacer 128 contacting its opposite sidewall are collectively referred to as mask assembly 126 / 128.

[0058] Figure 27 The formation of a stencil layer 130 is shown, which is formed of a material different from that of the mandrel 126, spacer 128, and hard mask 124. This material may include silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, and / or combinations thereof. The stencil layer 130 is deposited to a level above the top surfaces of the mandrel 126 and spacer 128, and subsequently planarized to make its top surfaces flush.

[0059] Next, refer to Figure 28The stencil layer 130 is etched to form an opening 132. The etching process is performed until the underlying mandrel 126, spacer 128, and hard mask 124 are exposed. The exposed mandrel 126, spacer 128, and hard mask 124 are not etched. Although only one opening 132 is shown, multiple openings overlapping the mandrel 126 and spacer 128 can be formed, wherein the multiple openings are parallel to each other and span over the same mask assembly 126 / 128.

[0060] Figure 29 The diagram illustrates the formation of a mask strip 134 in an opening 132, which may include filling the opening 132, followed by a planarization process. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 234. The mask strip 134 may be formed of a material different from the material of the template layer 130, the mandrel 126, the spacer 128 and the hard mask 124, and may be selected from silicon nitride, silicon oxide, silicon carbide, silicon carbonitride, titanium nitride, boron nitride, aluminum oxide, aluminum nitride, etc., or combinations thereof.

[0061] In subsequent processes, forming Figure 30A and Figure 30B The structure is shown. The formation process may include continuing planarization (polishing) of the stencil layer 130 and the mask strip 134. According to some embodiments, the planarization process is stopped by a mandrel 126 and / or spacer 128, which serves as a polishing stop layer. According to an alternative embodiment, the planarization process is stopped before the mandrel 126 and spacer 128 are exposed. The stencil layer 130 is then removed in an etching process without etching the mask strip 134, mandrel 126, and spacer 128. Subsequently, the mask strip 134 may be etched back to reduce its top surface to a level below the top surfaces of the mandrel 126 and spacer 128. Reducing the height of the mask strip 134 can reduce the masking effect in subsequent etching of the mask layer 124, resulting in sharper corners of the openings formed in the mask layer 124. According to an optional embodiment, the mask strip 134 is not etched back, and the top surface of the mask strip 134 is higher than or coplanar with the top surfaces of the mandrel 126 and spacer 128 within the process variation.

[0062] like Figure 30A and Figure 30B As shown, each mask strip 134 is divided into multiple mask strips 134, each mask strip being located between two adjacent mask groups 126 / 128. The mask strips 134 and their connecting mask groups 126 / 128 form an angle 136A that is sharper than the angle 136B formed by the spacer 128. Figure 30B It should be understood that although a single mask strip (divided into multiple sections) is shown, multiple parallel mask strips, indicated by dashed lines, can be formed. The distance between the parallel mask strips 134 determines the length of the subsequently formed metal lines.

[0063] In subsequent processes, the mandrel 126, spacer 128, and mask strip 134 together serve as an etching mask to etch the underlying hard mask 124, such as the hard mask layer 124C within the hard mask 124. The resulting structure is... Figure 31 As shown in the diagram. This forms opening 138. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 236. In a subsequent process, hard mask layers 124B and 124A are etched using a patterned hard mask layer 124C as an etching mask, followed by etching of the dielectric layer 122. Therefore, opening 138 extends into the dielectric layer 122. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 238. The sharper angle 136A ( Figure 30B The rounded corner 136B was also transferred to the dielectric layer 122. Then the hard mask 124 was removed, and... Figure 32 The resulting dielectric layer 122 is shown, in which an opening 138 is formed. It should be understood that the opening 138 may represent a trench for forming a metal wire, and also forms a through-hole opening for forming a via below the metal wire, which is not shown.

[0064] Figure 33 The formation of metal line 142 is shown, which is achieved by depositing diffusion barrier layer 146' (reference). Figure 34 As a conformal layer, the opening is filled with metal material 146”, and then a planarization process is performed to remove excess portions of the barrier layer 146” and the metal material 146”. The corresponding process is as follows: Figure 38 The process flow 200 is shown as process 240. The diffusion barrier layer 146' can be formed of or include Ti, TiN, Ta, TaN, etc. The metallic material 146" can be formed of or include copper or a copper alloy. The resulting metal wire 142 and through-hole 144 are in Figure 34 As shown in the image.

[0065] Figure 34 The deposition of etch stop layer 148 is also shown. Subsequently, more IMDs (e.g., low-k dielectric layers), vias, and metal lines can be formed over metal lines 142. The formation process can employ the process shown in the above embodiments, or it can employ photoresist (instead of mandrels, spacers, stencil layers, and mask strips).

[0066] Figure 35 A top view of conductive component group 150 is shown, which may represent conductive components 56 and 68. Figure 17A ), conductive components 98B (including 98B1 and 98B2, Figure 22A ) and conductive component 142 ( Figure 34 Any of the following. Each conductive component group 150 includes multiple portions, which may include two, three, or more portions separated from each other. The multiple portions have a longitudinal direction aligned with the same straight line 154. For example, the illustrated conductive component 150 includes ends 150A and 150C, and an intermediate portion 150B between ends 150A and 150C. The conductive component group 150 may be initially formed as a long strip and then cut in half, or it may be formed using a mandrel, spacers, and mask strips. Due to the forming process discussed, the end corners of conductive components 150A and 150C may be more rounded, for example, having a radius R1. The inner corners of conductive components 150A, 150B, and 150C facing the other portions of the conductive component group 150 are curved and have a radius R2. According to some embodiments, the ratio R2 / R1 is less than about 0.5 and is in the range between about 0.05 and about 0.5. Furthermore, conductive component portions 150A, 150B, and 150C may have a width W1, and a ratio R1 / W1 greater than about 0.5, and within the range of about 0.5 to about 2.0. On the other hand, the ratio R2 / W2 may be less than about 0.2, and within the range of about 0.05 to about 0.2. Additionally, the radius R2 may be less than about 3 nm, and within the range of about 0.5 nm to about 3 nm.

[0067] exist Figure 35 In this configuration, conductive component group 150 is separated from other conductive components 152 (formed using the same process as conductive component group 150) by a spacing S2. The intra-group spacing S1 between adjacent conductive components in conductive component group 150 is smaller than the inter-group spacing S2. According to some embodiments, the intra-group spacing S1 can be in the range of about 8 nm to about 20 nm. The spacing ratio S2 / S1 can be greater than about 2 and can be greater than about 3.0. The inter-group spacing S3 between conductive component group 150 and other conductive components (also denoted as 150) parallel to conductive component group 150 can be less than about 20 nm, in the range of about 10 nm to about 20 nm, or less than about 20 nm.

[0068] Figure 36 A conductive component 150' formed according to an alternative embodiment of the invention is shown. These embodiments can be formed using conventional processes, for example, without performing the cutting processes for conductive components 56, 68, and 98B. Therefore, the opposite ends of the conductive component 150' all have a radius R1 as described above. Alternatively, these embodiments can be used to form an upper metal layer, as referenced... Figure 37 The upper metal layer shown is discussed. It should be understood that... Figure 35 and Figure 36 The embodiments described herein can coexist on the same layer in the same die and wafer.

[0069] It should be understood that when the mandrel is 126 ( Figure 26B When excluding the portion having a longitudinal direction parallel to the X direction, the corners of ends 150A and 150B can also be defined by mask strip 134 and also have a radius R2. The corresponding angle is also... Figure 35 It is shown in dashed line 155. In these embodiments, the boundary of the end is defined by mask strip 134, rather than the portion of the mandrel 126 whose longitudinal direction is the X direction.

[0070] Figure 37 A scheme for a conductive component layer in wafer 10 is shown. Circuit devices such as transistor 160 are formed on the top surface of semiconductor substrate 20. Contact plugs 56 / 68 are formed therein. Figure 17A The contact (CT) layer of the conductive components 98A, 98B1, and 98B2 is formed. A metal layer M0 is formed above the contact layer, which may include metal wires. The metal layer M0 may correspond to conductive components 98A, 98B1, and 98B2. Figure 34 Multiple metal layers such as M1 to Mn and via layers such as V1 to V(nl) are also formed, where the integer n can be greater than 5 and can be in the range of about 5 and 15. According to some embodiments, the underlying layer such as metal layers M0, M1, M2, etc., can have conductive components formed according to embodiments of the invention. Therefore, the corresponding conductive components can have, for example, Figure 35 The structure shown. The upper layer, such as metal layers Mn, M(nl), M(n-2), etc., can have conductive components formed using conventional damascene processes, and has, for example... Figure 36 The structure is shown. According to some embodiments, a threshold metal layer (such as M3, M4, or M5) may be present, and the conductive components in the threshold metal layer and all metal layers below the threshold metal layer include components formed using a process according to embodiments of the present invention, and have, as Figure 35 The structure shown. However, according to some embodiments, all metal layers above the threshold metal layer can have the following structure: Figure 36 The structure in the middle can also be absent. Figure 36 The structure shown.

[0071] Embodiments of the present invention have several advantageous features. By forming the conductive components using the process of the present invention, at least some of the corners of the conductive components are sharper. The effective area of ​​these conductive components increases due to the increased corner area. The contact resistance between these conductive components and other conductive components bonded to these conductive components can be reduced by more than about 15%. This also results in reduced Joule heating and reduced electromigration.

[0072] According to some embodiments of the present invention, the method includes depositing a dielectric layer; depositing a plurality of mandrel strips over the dielectric layer; forming a plurality of spacers on the sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group within the plurality of mask groups; forming a mask strip connecting two adjacent mask groups within the plurality of mask groups; using the plurality of mask groups and the mask strips together as an etching mask to etch the dielectric layer and form trenches in the dielectric layer; and filling the trenches with a conductive material to form a plurality of conductive components. In an embodiment, forming the plurality of spacers includes depositing a blanket layer and performing an anisotropic etching process on the blanket layer. In an embodiment, forming the mask strips includes: depositing a stencil layer over the plurality of mask groups, wherein the top surface of the stencil layer is higher than the top surface of the plurality of mask groups; forming an opening in the stencil layer, wherein at least two of the plurality of mask groups are exposed through the opening; filling the opening to form the mask strip; and removing the stencil layer. In an embodiment, the method further includes reducing the top surface of the mask strip to be flush with or below the top surface of the plurality of mask groups. In one embodiment, reducing the top surface of the mask strip includes: polishing the mask strip; and after polishing, etching away the mask strip. In another embodiment, a plurality of conductive components have a longitudinal direction aligned with a straight line, and the plurality of conductive components include end strips, each end strip including a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius. In another embodiment, the ratio of the first radius to the second radius is greater than about 2.0. In yet another embodiment, depositing the dielectric layer includes depositing a low-k dielectric layer.

[0073] According to some embodiments of the present invention, the structure includes a semiconductor substrate; a dielectric layer above the semiconductor substrate; a first conductive member including: a first end, wherein the first end is bent and has a first radius; and a second end opposite to the first end, wherein the second end is bent and has a second radius smaller than the first radius; a second conductive member spaced apart from the first end of the first conductive member by a first portion of the dielectric layer, wherein the second conductive member has a first distance from the first end; and a third conductive member spaced apart from the second end of the first conductive member by a second portion of the dielectric layer, wherein the third conductive member has a second distance from the second end, and the second distance is smaller than the first distance, and wherein the first conductive member, the second conductive member, and the third conductive member have a longitudinal direction aligned with the same straight line. In an embodiment, the ratio of the first radius to the second radius is greater than about 2.0. In an embodiment, the first conductive member has a first sidewall and a second sidewall opposite to the first sidewall, and the first conductive member includes a diffusion barrier layer and a metallic material above the diffusion barrier layer, wherein the diffusion barrier layer extends below the metallic material, the first sidewall of the first conductive member includes a sidewall of a vertical portion of the diffusion barrier layer, and the metallic material extends to the second sidewall. In one embodiment, the first conductive component has a first sidewall and a second sidewall opposite to the first sidewall, wherein in a first cross-sectional view of the structure, the first and second sidewalls are inclined in the same direction. In another embodiment, the structure further includes a fourth conductive component in the dielectric layer, wherein the fourth conductive component includes two pairs of opposing sidewalls, and each of the two pairs of opposing sidewalls is inclined in opposite directions. In another embodiment, the first and second conductive components include metal gate stacks. In another embodiment, the first and second conductive components include source / drain contact plugs. In another embodiment, the structure further includes gate spacers that physically contact both the first and second conductive components. In another embodiment, the first and second conductive components include metal lines, and wherein the dielectric layer includes a low-k dielectric material.

[0074] According to some embodiments of the present invention, the structure includes a plurality of conductive members having a longitudinal direction aligned with the same straight line, wherein the plurality of conductive members includes a first end member, a second end member, and at least one intermediate conductive member located between the first end member and the second end member, and the first end member includes: a first end facing away from the second end member, wherein the first end has a first angle; a second end facing the second end member, wherein the second end has a second angle that is sharper than the first angle; and a dielectric layer, wherein the upper portions of the plurality of conductive members are located in the dielectric layer. In an embodiment, each of the at least one intermediate conductive member includes a third end facing the first end member and a fourth end facing the second end member, wherein both the third end and the fourth end are sharper than the first end of the first end member. In an embodiment, the structure further includes an isolation region between the plurality of conductive members, wherein the isolation region is formed of a first dielectric material different from a second dielectric material of the dielectric layer.

[0075] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art will understand that they can readily use this invention as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor structure, comprising: Deposited dielectric layer; Multiple mandrel strips are deposited above the dielectric layer; Multiple spacers are formed on the sidewalls of the plurality of mandrel strips to form a plurality of mask groups, wherein each of the plurality of mandrel strips and two of the plurality of spacers form a mask group among the plurality of mask groups; Form a mask strip connecting two adjacent mask groups among the plurality of mask groups; The dielectric layer is etched using the plurality of mask groups and the mask strip together as an etching mask, and trenches are formed in the dielectric layer; and Conductive material is filled into the trench to form a plurality of conductive components having a longitudinal direction aligned with a straight line, and the plurality of conductive components including end strips, the end strips including a first end and a second end, wherein the first end is curved and has a first radius, and the second end is curved and has a second radius smaller than the first radius.

2. The method according to claim 1, wherein, Forming the plurality of spacers includes depositing a blanket layer and performing an anisotropic etching process on the blanket layer.

3. The method according to claim 1, wherein, Forming the mask strip includes: A template layer is deposited over the plurality of mask groups, wherein the top surface of the template layer is higher than the top surface of the plurality of mask groups; An opening is formed in the template layer, wherein at least two of the plurality of mask groups are exposed through the opening; Fill the opening to form a mask strip; and Remove the template layer.

4. The method according to claim 1, further comprising lowering the top surface of the mask strip to be flush with or lower than the top surface of the plurality of mask groups.

5. The method according to claim 4, wherein, Lowering the top surface of the mask strip includes: Polishing the mask strip; and After polishing, the mask strip is etched away.

6. The method according to claim 1, wherein, The second radius is less than 3 nm.

7. The method according to claim 1, wherein, The ratio of the first radius to the second radius is greater than 2.

0.

8. The method according to claim 1, wherein, Depositing the dielectric layer includes depositing a low-k dielectric layer.

9. A semiconductor structure, comprising: Semiconductor substrate; A dielectric layer is located above the semiconductor substrate; The first conductive component includes: The first end, wherein the first end is curved and has a first radius; and The second end is opposite to the first end, wherein the second end is curved and has a second radius smaller than the first radius; The second conductive component is spaced apart from the first end of the first conductive component by a first portion of the dielectric layer, wherein the second conductive component and the first end have a first distance; A third conductive component is spaced apart from the second end of the first conductive component by a second portion of the dielectric layer, wherein the third conductive component has a second distance from the second end, and the second distance is less than the first distance, and wherein the first conductive component, the second conductive component, and the third conductive component have a longitudinal direction aligned with the same straight line; and The fourth conductive component is located in the dielectric layer. The first conductive component has a first sidewall and a second sidewall opposite to the first sidewall, and the fourth conductive component includes two pairs of opposing sidewalls. In a first cross-sectional view of the semiconductor structure, the first sidewall and the second sidewall of the first conductive component are inclined in the same direction, and each of the two pairs of opposing sidewalls of the fourth conductive component is inclined in opposite directions.

10. The semiconductor structure according to claim 9, wherein, The ratio of the first radius to the second radius is greater than 2.

0.

11. The semiconductor structure according to claim 9, wherein, The first conductive component includes a diffusion barrier layer and a metal material located above the diffusion barrier layer, wherein the diffusion barrier layer extends below the metal material, and a first sidewall of the first conductive component includes a sidewall of a vertical portion of the diffusion barrier layer, and the metal material extends to a second sidewall.

12. The semiconductor structure according to claim 9, wherein, The dielectric layer comprises a low-k dielectric material.

13. The semiconductor structure according to claim 9, wherein, The second radius is less than 3 nm.

14. The semiconductor structure according to claim 9, wherein, The first conductive component and the second conductive component include metal gate stacks.

15. The semiconductor structure according to claim 9, wherein, The first conductive component and the second conductive component include source / drain contact plugs.

16. The semiconductor structure of claim 9 further includes a gate spacer that physically contacts both the first conductive component and the second conductive component.

17. The semiconductor structure according to claim 12, wherein, The first conductive component and the second conductive component include metal wires.

18. A semiconductor structure comprising: A plurality of conductive components having a longitudinal direction aligned with a straight line, wherein the plurality of conductive components includes a first end component, a second end component, and at least one intermediate conductive component between the first end component and the second end component, and the first end component includes: A first end, facing away from the second end component, wherein the first end has a first angle; and The second end, facing the second end component, wherein the second end has a second angle that is sharper than the first angle; and A dielectric layer, wherein the upper portion of a plurality of conductive components is located within the dielectric layer. Each of the at least one intermediate conductive component includes a third end facing the first end component and a fourth end facing the second end component, wherein both the third end and the fourth end are sharper than the first end of the first end component.

19. The semiconductor structure according to claim 18, wherein, The plurality of conductive components include metal wires.

20. The semiconductor structure of claim 18, further comprising an isolation region between the plurality of conductive components, wherein, The isolation region is formed of a first dielectric material that is different from the second dielectric material of the dielectric layer.

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