Thin film transistor, method of manufacturing the same, and array substrate
By setting heat dissipation holes under the channel region of the thin-film transistor and covering them with an insulating or black heat dissipation material layer, the problem of decreased conductivity caused by heat accumulation is solved, achieving effective heat dissipation and preventing leakage current, thus extending the service life of the thin-film transistor.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIHAI HKC OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2022-03-30
- Publication Date
- 2026-05-19
AI Technical Summary
Thin-film transistors generate a lot of heat during long-term operation, which affects their conductivity and leads to display problems.
Heat dissipation holes are provided under the channel region of the thin-film transistor, and the holes are covered with an insulating or black heat dissipation material layer to increase the contact area between the semiconductor layer and the outside world for heat dissipation. At the same time, the protrusions are covered with a light-shielding layer to prevent leakage current.
It effectively dissipates heat from the semiconductor layer, preventing performance degradation, extending service life, reducing self-heating, and preventing leakage current.
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Figure CN114823566B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, and in particular to a thin-film transistor, its fabrication method, and an array substrate. Background Technology
[0002] With advancements in manufacturing technology, thin-film transistors (TFTs) have been widely used in displays to meet the demands for thinner and smaller displays. A TFT typically consists of a gate, drain, source, and channel layer. It controls the voltage at the gate to alter the conductivity of the channel layer, thus creating a conducting or cut-off state between the source and drain.
[0003] Thin-film transistors (TFTs) primarily achieve source-drain conduction through electron migration within the semiconductor layer during operation. However, over long-term operation, the semiconductor layer generates a significant amount of heat, which affects the conductivity of the TFT and leads to a series of display problems. Summary of the Invention
[0004] The purpose of this application is to provide a thin-film transistor, its fabrication method, and an array substrate, with improved performance.
[0005] This application discloses a thin-film transistor, which includes a gate metal layer, an insulating layer covering the gate metal layer, a semiconductor layer disposed on the insulating layer and corresponding to the gate metal layer, a source metal layer disposed on the semiconductor layer, and a drain metal layer disposed on the semiconductor layer and co-located with the source metal layer, wherein a channel region is formed between the drain metal layer and the source metal layer; wherein the semiconductor layer has a heat dissipation hole corresponding to the channel region, the cross-sectional area of the heat dissipation hole is smaller than the cross-sectional area of the channel region, and the heat dissipation hole is connected to the channel region.
[0006] Optionally, the heat dissipation hole penetrates the semiconductor layer and the insulating layer to connect the gate metal layer and the channel region. The thin-film transistor includes a heat dissipation layer, which is an insulating material. The heat dissipation layer covers the inner wall of the heat dissipation hole and the sides of the source metal layer and drain metal layer located in the channel region.
[0007] Optionally, the heat dissipation layer covers the inner wall of the heat dissipation hole, the semiconductor layer, the insulating layer, the source metal layer, and the drain metal layer. The thin film transistor also includes a passivation layer, which covers the heat dissipation layer.
[0008] Optionally, the heat dissipation layer is made of a black heat dissipation material, which may include non-conductive graphene or silicone grease.
[0009] Optionally, the thin-film transistor further includes a light-shielding layer that covers the heat dissipation layer.
[0010] Optionally, the heat dissipation layer is a passivation layer, which covers the inner wall of the heat dissipation hole, the insulating layer, the source metal layer, and the drain metal layer.
[0011] Optionally, the semiconductor layer includes a first overlapping portion, a second overlapping portion, and a protrusion. The first overlapping portion overlaps with the source metal layer, the second overlapping portion overlaps with the drain metal layer, and the protrusion protrudes beyond the source metal layer or the drain metal layer. The thin-film transistor includes a light-shielding layer that covers the protrusion and the semiconductor layer under the channel region. A heat dissipation layer covers the light-shielding layer.
[0012] Optionally, the semiconductor layer includes an intrinsic layer and a doped layer, the doped layer is disposed on the intrinsic layer, the intrinsic layer forms a step corresponding to the protrusion, and the light-shielding layer covers the step, as well as the source metal layer and the drain metal layer.
[0013] This application also discloses a method for fabricating a thin-film transistor, the method comprising the steps of:
[0014] A gate metal layer, an insulating layer, and a semiconductor layer are sequentially formed on a substrate.
[0015] A source metal layer, a drain metal layer, and a channel region are formed on the semiconductor layer; and
[0016] The semiconductor layer and insulating layer are dry-etched away in the corresponding channel region, and heat dissipation holes are formed on the semiconductor layer in the corresponding channel region;
[0017] Wherein, the cross-sectional area of the heat dissipation hole is smaller than the cross-sectional area of the channel region, and the heat dissipation hole is connected to the channel region.
[0018] This application also discloses an array substrate, including a substrate and a thin-film transistor as described above, the thin-film transistor being formed on the substrate.
[0019] Compared to solutions that do not provide heat dissipation for thin-film transistors, this application forms heat dissipation holes by drilling holes in the semiconductor layer under the channel region. It should be noted that the cross-sectional area of the heat dissipation holes should be smaller than the cross-sectional area of the channel region to avoid the holes being too large and affecting the normal operation of the thin-film transistor. The heat dissipation holes allow more of the semiconductor layer to be exposed, increasing the contact area between the semiconductor layer and the outside environment, which is beneficial for dissipating heat from the semiconductor layer in a timely manner and preventing the thin-film transistor from experiencing performance degradation and reduced lifespan due to its own heat generation. Attached Figure Description
[0020] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:
[0021] Figure 1 This is a top view of a thin-film transistor according to the first embodiment of this application;
[0022] Figure 2 This is a cross-sectional view of the thin-film transistor of the first embodiment of this application;
[0023] Figure 3 This is a schematic diagram of a thin-film transistor according to a second embodiment of this application;
[0024] Figure 4 This is a schematic diagram of a thin-film transistor according to the third embodiment of this application;
[0025] Figure 5 This is a schematic diagram of a thin-film transistor according to the fourth embodiment of this application;
[0026] Figure 6 This is a schematic diagram of a thin-film transistor according to the fifth embodiment of this application;
[0027] Figure 7 This is a schematic diagram of a thin-film transistor according to the sixth embodiment of this application;
[0028] Figure 8 This is a schematic diagram of the fabrication method of the thin-film transistor according to the seventh embodiment of this application;
[0029] Figure 9 This is a schematic diagram of the fabrication method of the thin-film transistor according to the eighth embodiment of this application;
[0030] Figure 10 This is a schematic diagram of a thin-film transistor according to the eighth embodiment of this application;
[0031] Figure 11 This is a schematic diagram of the array substrate according to the ninth embodiment of this application.
[0032] Among them, 100 is a thin-film transistor; 110 is a gate metal layer; 120 is an insulating layer; 130 is a semiconductor layer; 131 is a heat dissipation hole; 132 is a first overlapping portion; 133 is a second overlapping portion; 134 is a protrusion; 135 is an intrinsic layer; 136 is a doped layer; 140 is a source metal layer; 150 is a drain metal layer; 160 is a channel region; 170 is a heat dissipation layer; 180 is a light-shielding layer; 190 is a passivation layer; 200 is an array substrate; 210 is a substrate; and 220 is a pixel electrode layer. Detailed Implementation
[0033] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.
[0034] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.
[0035] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0036] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0037] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.
[0038] As a first embodiment of this application, a thin-film transistor 100 is disclosed, such as Figure 1 and Figure 2 As shown, where, Figure 1 This is a top view of a thin-film transistor according to the first embodiment of this application; Figure 2 This is a cross-sectional view of a thin-film transistor 100 according to the first embodiment of this application. The thin-film transistor 100 is generally formed on a substrate 210. The thin-film transistor 100 includes a gate metal layer 110, an insulating layer 120, a semiconductor layer 130, a source metal layer 140, and a drain metal layer 150. The gate metal layer 110 is formed on the substrate 210, and the insulating layer 120 covers the gate metal layer 110. The semiconductor layer 130 is disposed on the insulating layer 120 and corresponds to the gate metal layer 110. The source metal layer 140 is disposed on the semiconductor layer 130; the drain metal layer 150 is disposed on the semiconductor layer 130 and is disposed in the same layer as the source metal layer 140, and a channel region 160 is formed between the drain metal layer 150 and the source metal layer 140; wherein, the semiconductor layer 130 is provided with a heat dissipation hole 131 corresponding to the channel region 160, the cross-sectional area of the heat dissipation hole 131 is less than or equal to the cross-sectional area of the channel region 160, and the heat dissipation hole 131 is connected to the channel region 160.
[0039] Holes are drilled in the semiconductor layer 130 corresponding to the channel region 160 as heat dissipation holes 131. The heat dissipation holes 131 increase the contact area between the semiconductor layer 130 and the outside world, so that the heat generated by the semiconductor layer 130 can be dissipated into the channel region 160 in a timely manner through the inner wall of the heat dissipation holes 131 and the upper surface of the channel region 160 corresponding to the semiconductor layer 130. Furthermore, by hollowing out part of the semiconductor layer 130, the heat generated by itself can be reduced. That is, heat is dissipated by drilling holes, and the self-heating of the TFT device itself is reduced, so as to avoid the performance degradation of the thin film transistor 100 caused by excessive heat and the resulting display problems. In addition, if the thickness of the heat dissipation hole 131 is less than the thickness of the semiconductor layer 130, while ensuring the normal conductivity of the thin film transistor 100, the cross-sectional area of the heat dissipation hole 131 can also be equal to the cross-sectional area of the channel region 160. That is, corresponding to the channel region 160, the surface area of the upper surface of the heat dissipation hole 131 on the semiconductor layer 130 is the same as the area of the upper surface of the remaining uncut semiconductor layer 130. The thickness of the heat dissipation hole 131 can also be set according to the thickness of the semiconductor layer 130.
[0040] like Figure 3 As shown, as a second embodiment of this application, refer to Figure 1 and Figure 3As shown, unlike the first embodiment described above, the heat dissipation hole 131 penetrates the semiconductor layer 130 and the insulating layer 120 to connect the gate metal layer 110 and the channel region 160. In this case, the cross-sectional area of the heat dissipation hole 131 must be smaller than the cross-sectional area of the channel region 160 to ensure the normal migration of electrons in the thin film transistor 100. By penetrating the semiconductor layer 130, the contact area between the semiconductor layer 130 and the outside world can be further increased, and heat dissipation can be carried out more quickly.
[0041] Furthermore, a heat dissipation layer 170 is provided on the inner wall of the heat dissipation hole 131. The heat dissipation layer 170 is mainly formed of insulating material. The heat dissipation layer 170 is in direct contact with the gate metal below the heat dissipation hole 131 of the semiconductor layer 130. At the same time, the heat dissipation layer 170 covers the inner wall of the heat dissipation hole 131 and the sides of the source metal layer 140 and drain metal layer 150 located in the channel region 160. Through the heat dissipation layer 170, the heat on the semiconductor layer 130 can be conducted to the gate metal layer 110, the source metal layer 140 and the drain metal layer 150. The heat can be dissipated from the semiconductor layer 130 more quickly through the metal layer. In particular, since the gate metal layer 110 forms gate lines that cover the entire display area, heat dissipation can be carried out on a large scale for each thin film transistor 100.
[0042] like Figure 4 As shown in the third embodiment of this application, for ease of manufacturing, after the heat dissipation hole 131 is formed, the heat dissipation layer 170 is directly laid on the inner wall of the heat dissipation hole 131, the insulating layer 120, the source metal layer 140, and the drain metal layer 150 to cover the inner wall of the heat dissipation hole 131, the exposed portion of the insulating layer 120, the source metal layer 140, and the drain metal layer 150. Furthermore, to better protect the heat dissipation layer 170, a passivation layer 190 is also provided on the heat dissipation layer 170. The passivation layer 190 is formed using SiNx and also has a certain heat dissipation effect, which can promptly dissipate heat from the heat dissipation layer 170. The absorbed heat is dissipated; of course, the heat dissipation layer 170 can also be a light-shielding heat dissipation layer 170 made of black heat dissipation material, including non-conductive graphene material or silicone grease material, which can block light while dissipating heat. Due to the backlight and reflected light from the outside, stray light forms photogenerated carriers in intrinsic amorphous silicon (Ia-Si) semiconductor, which affects the leakage current of TFT device. By adding a layer of black heat dissipation material on TFT device, the light leakage current of TFT device caused by ambient light is reduced. Then, by using holes, heat is also conducted to metal for heat dissipation, reducing the self-heating of TFT device itself.
[0043] In addition, such as Figure 5As shown, in the thin film transistor 100 of the fourth embodiment of this application, the passivation layer 190 can also be used as the heat dissipation layer 170, that is, the heat dissipation layer 170 is the passivation layer 190. The passivation layer 190 covers the inner wall of the heat dissipation hole 131, the insulating layer 120, the source metal layer 140 and the drain metal layer 150, and transfers the heat of the semiconductor layer 130 to the metal layer for heat dissipation while dissipating heat from the semiconductor layer 130.
[0044] like Figure 6 As shown in the fifth embodiment of this application, a thin-film transistor 100 is disclosed. Generally, during the fabrication of the thin-film transistor 100, the semiconductor layer 130 is wider than the source metal layer 140 and the drain metal layer 150 to allow for better deposition of the source metal layer 140 and the drain metal layer 150. Therefore, a portion of the semiconductor layer 130 protrudes beyond the source metal layer 140 and the drain metal layer 150. Specifically, the semiconductor layer 130 includes a first overlapping portion 132, a second overlapping portion 133, and a protrusion 134. The first overlapping portion 132 overlaps with the source metal layer 140, the second overlapping portion 133 overlaps with the drain metal layer 150, and the protrusion 134 protrudes beyond the source metal layer 140 or the drain metal layer 150. The thin-film transistor 100 includes a light-shielding layer 180, which covers the protrusion 134. 4. The semiconductor layer 130 under the channel region 160, the heat dissipation layer 170 covers the light shielding layer 180, and the heat dissipation layer 170 covers the light shielding layer 180. Unlike the above embodiment, this embodiment provides a light shielding layer 180 while providing a heat dissipation layer 170. The light shielding layer 180 mainly covers the protrusion 134 of the semiconductor layer 130. Since the reflection and refraction of light in the display panel may result in scattered light at different angles, the protrusion of the semiconductor layer 130 can easily be hit by scattered light. When the energy of the photon is equal to or greater than the band gap of the semiconductor, the electron in the valence band absorbs the photon and enters the conduction band, generating electron-hole pairs. The electron moves towards the drain and the hole moves towards the source, thereby causing hole leakage current. Therefore, the light shielding layer 180 is provided to cover the protrusion 134 and the inner wall of the heat dissipation hole 131 to prevent scattered light from entering the semiconductor layer 130 and causing leakage current.
[0045] Furthermore, the semiconductor layer 130 includes an intrinsic layer 135 and a doped layer 136. The doped layer 136 is disposed on the intrinsic layer 135. The intrinsic layer 135 forms a step corresponding to the protrusion 134. The light-shielding layer 180 covers the step, as well as the source metal layer 140 and the drain metal layer 150.
[0046] like Figure 7As shown, as the sixth embodiment of this application, it is an improvement based on the above embodiments. In each thin film transistor 100, a heat dissipation hole 131 is formed by directly drilling holes in the semiconductor layer 130 and the insulating layer 120 corresponding to the channel region 160. The heat dissipation hole 131 is directly connected to the channel region 160. The heat dissipation layer 170 is formed using a black heat dissipation material. The heat dissipation extends from one side of the insulating layer 120, successively covering the left side of the insulating layer 120, the exposed portion on the left side of the semiconductor layer 130, the source metal layer 140, the exposed portion on the right side of the semiconductor layer 130, the entire inner wall of the heat dissipation hole 131, all film layers exposed in the channel region 160, and finally covering the rightmost side of the drain metal layer 150.
[0047] like Figure 8 As shown, as the seventh embodiment of this application, a method for fabricating a thin-film transistor is disclosed. The method for fabricating a thin-film transistor as described in any of the above embodiments includes the following steps:
[0048] S1: A gate metal layer, an insulating layer, and a semiconductor layer are sequentially formed on a substrate.
[0049] S2: A source metal layer, a drain metal layer, and a channel region are formed on the semiconductor layer; and
[0050] S3: The semiconductor layer and insulating layer are dry-etched away in the corresponding channel region, and heat dissipation holes are formed on the semiconductor layer in the corresponding channel region;
[0051] Among them, reference Figure 1 and Figure 2 As shown, the cross-sectional area of the heat dissipation hole 131 is smaller than the cross-sectional area of the channel region 160. The heat dissipation hole 131 is connected to the channel region 160. By forming the heat dissipation hole 131 on the semiconductor layer 130 below the channel region 160, the contact area between the semiconductor layer 130 and the outside world can be increased, and heat can be dissipated to the channel region 160 for heat dissipation more quickly. When the heat dissipation hole 131 is formed, it can directly penetrate the semiconductor layer 130 or not.
[0052] Furthermore, such as Figure 9 As shown in the eighth embodiment of this application, the method for fabricating the thin-film transistor further includes the following steps:
[0053] S4: A heat dissipation layer is formed using non-conductive graphene or silicone grease material, and the heat dissipation layer covers the inner wall of the heat dissipation hole, the semiconductor layer, the insulating layer, the source metal layer, and the drain metal layer.
[0054] S5: A passivation layer is formed on the heat dissipation layer;
[0055] The heat dissipation layer is made of black heat dissipation material, which includes non-conductive graphene material or silicone grease material.
[0056] This application also discloses a thin-film transistor fabrication method, mainly targeting the 4Mask TFT process. Specifically, in the corresponding step S1, a gate metal layer pattern is first formed by sputtering and then exposure and development. Then, a GI insulating layer, an a-Si layer (amorphous silicon, intrinsic layer), and an N+ layer (high-concentration phosphorus (PH3) silicon, doped layer) are formed sequentially by chemical vapor deposition (CVD).
[0057] Corresponding to step S2, the second metal layer (source metal layer and drain metal layer) is deposited by sputtering. Using a half-tone mask, the pattern of the two film layers is created by two etchings and two dry etchings.
[0058] Corresponding to step S3, a separate photomask is used to create the hole, and the a-Si layer, N+ layer and GI layer are dry-etched away. The shape of the hole can be circular or other shapes, without restriction, and the size depends on the design.
[0059] Corresponding to step S4, a pattern of black heat dissipation layer is created by chemical vapor deposition (CVD). Only the black heat dissipation layer 170 in the TFT area is retained, and the rest needs to be etched away. The size of the black heat dissipation layer area must be large enough to completely cover the excess active layer outside the channel.
[0060] Corresponding to step S5, a PV passivation layer 190 is fabricated by chemical vapor deposition (CVD); finally, a pixel electrode layer 220 (indium tin oxide) pattern is fabricated by sputtering, exposure and development.
[0061] This application also discloses a thin-film transistor fabrication method, mainly targeting the 5-mask TFT process. The difference from the 4-mask process is that a GI insulating layer, an a-Si layer (amorphous silicon, intrinsic layer), and an N+ layer (high-concentration phosphorus (PH3) silicon doped layer) are sequentially fabricated by chemical vapor deposition (CVD). Then, a half-tone mask is used to fabricate silicon islands and openings. The a-Si layer, N+ layer, and GI insulating layer are dry-etched away at the openings, while only the a-Si layer and N+ layer need to be dry-etched away at other locations. The shape of the openings can be circular or other shapes, without limitation, and the size depends on the design. Then, the pattern of the second metal layer (source metal layer and drain metal layer) is fabricated by sputtering exposure and development.
[0062] The above process method can yield the following results: Figure 10The thin-film transistor shown in this application differs significantly from traditional manufacturing methods in that a portion of the semiconductor layer 130 is removed from the TFT channel to form a heat dissipation hole 131. A layer of black heat-dissipating material is then added, forming a film structure that can both dissipate heat and block light. This allows the black heat-dissipating material to directly contact the gate metal layer 110, transferring the heat generated by the TFT device to the metal, which then releases the heat, reducing the self-heating of the TFT device. For U-shaped TFTs, self-heating in the U-shaped region is particularly severe; therefore, placing the hole in the U-shaped region itself can reduce self-heating.
[0063] It should be noted that each thin-film transistor 100 is provided with a pixel electrode, and a via is provided for the pixel electrode. The via passes through the passivation layer 190, and the pixel electrode is connected to the drain of the thin-film transistor 100 through the via. In the above embodiment, the light-shielding layer 180 or the heat dissipation layer 170 made of black heat dissipation material covers the side of the via near the channel region 160.
[0064] like Figure 11 As shown, as the ninth embodiment of this application, an array substrate 200 is disclosed, the array substrate 200 including the thin film transistor 100 as described in any of the above embodiments and a substrate 210, the thin film crystal being formed on the substrate 210.
[0065] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.
[0066] It should be noted that the inventive concept of this application can lead to numerous embodiments, but due to space limitations, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. The combination of embodiments or technical features will enhance the original technical effect.
[0067] The technical solution of this application can be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, and MVA (Multi-Domain Vertical Alignment) display panels. Of course, it can also be used in other types of display panels, such as OLED (Organic Light-Emitting Diode) display panels, all of which are applicable to the above solution.
[0068] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.
Claims
1. A thin-film transistor, characterized in that, include: Gate metal layer; An insulating layer is disposed on the gate metal layer; A semiconductor layer is disposed on the insulating layer and corresponds to the gate metal layer; A source metal layer is disposed on the semiconductor layer; as well as A drain metal layer is disposed on the semiconductor layer and is disposed in the same layer as the source metal layer, and a channel region is formed between the drain metal layer and the source metal layer; The semiconductor layer is provided with heat dissipation holes corresponding to the channel region. The cross-sectional area of the heat dissipation holes is smaller than the cross-sectional area of the channel region, and the heat dissipation holes are connected to the channel region. The heat dissipation hole penetrates the semiconductor layer and the insulating layer to connect the gate metal layer and the channel region. The thin film transistor includes a heat dissipation layer, which is an insulating material. The heat dissipation layer is made of black heat dissipation material. The heat dissipation layer covers the inner wall of the heat dissipation hole and the sides of the source metal layer and drain metal layer located in the channel region. The heat dissipation layer conducts heat from the semiconductor layer to the gate metal layer, source metal layer and drain metal layer.
2. A thin-film transistor as described in claim 1, characterized in that, The heat dissipation layer covers the inner wall of the heat dissipation hole, the semiconductor layer, the insulating layer, the source metal layer, and the drain metal layer. The thin film transistor also includes a passivation layer, which covers the heat dissipation layer.
3. A thin-film transistor as described in claim 1, characterized in that, The black heat dissipation material includes non-conductive graphene or silicone grease.
4. A thin-film transistor as described in claim 1, characterized in that, The thin-film transistor also includes a light-shielding layer that covers the heat dissipation layer.
5. A thin-film transistor as described in claim 1, characterized in that, The heat dissipation layer is a passivation layer, which covers the inner wall of the heat dissipation hole, the insulating layer, the source metal layer, and the drain metal layer.
6. A thin-film transistor as described in claim 1, characterized in that, The semiconductor layer includes a first overlapping portion, a second overlapping portion, and a protrusion. The first overlapping portion overlaps with the source metal layer, the second overlapping portion overlaps with the drain metal layer, and the protrusion protrudes from the source metal layer or the drain metal layer. The thin-film transistor includes a light-shielding layer that covers the protrusion and the semiconductor layer under the channel region. The heat dissipation layer covers the light-shielding layer.
7. A thin-film transistor as described in claim 6, characterized in that, The semiconductor layer includes an intrinsic layer and a doped layer. The doped layer is disposed on the intrinsic layer. The intrinsic layer forms a step corresponding to the protrusion. The light-shielding layer covers the step, as well as the source metal layer and the drain metal layer.
8. A method for fabricating a thin-film transistor, wherein the method fabricates a thin-film transistor as described in any one of claims 1-7, characterized in that, Including the following steps: A gate metal layer, an insulating layer, and a semiconductor layer are sequentially formed on a substrate. A source metal layer, a drain metal layer, and a channel region are formed on the semiconductor layer; and The semiconductor layer and insulating layer are dry-etched away in the corresponding channel region, and heat dissipation holes are formed on the semiconductor layer in the corresponding channel region; Wherein, the cross-sectional area of the heat dissipation hole is smaller than the cross-sectional area of the channel region, and the heat dissipation hole is connected to the channel region.
9. The method for fabricating a thin-film transistor as described in claim 8, characterized in that, The method for fabricating the thin-film transistor further includes the following steps: A heat dissipation layer is formed using non-conductive graphene or silicone grease material, and the heat dissipation layer covers the inner wall of the heat dissipation hole, the semiconductor layer, the insulating layer, the source metal layer, and the drain metal layer. A passivation layer is formed on the heat dissipation layer; The heat dissipation layer is made of black heat dissipation material, which includes non-conductive graphene material or silicone grease material.
10. An array substrate, characterized in that, It includes a substrate and a thin-film transistor as described in any one of claims 1-7, wherein the thin-film transistor is formed on the substrate.