Image sensor with improved full well capacity, electronic information device

Abstract

The embodiment of the present application discloses an image sensor and an electronic information device for improving full well capacity. The image sensor comprises: a photodiode formed in a semiconductor substrate; the photodiode comprises at least a first doped layer, a second doped layer and a columnar third doped region; the second doped layer wraps the side and bottom of the third doped region; the first doped layer wraps the side and bottom of the second doped layer; the first doped layer and the second doped layer form a first lateral PN junction; the second doped layer and the third doped region form a second lateral PN junction; wherein the first doped layer and the third doped region have the same conductivity type, and the conductivity type is opposite to that of the second doped layer. The embodiment of the present application replaces the central part of the photodiode with a columnar ion doped region (for example, a P-type layer), so that the image sensor with the epitaxial structure can effectively improve the full well capacity, effectively reduce the depletion potential of the center of the photodiode, avoid the occurrence of lag, and reduce the dark current.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of image sensors, in particular to an image sensor with improved full well capacity and an electronic information device. BACKGROUND

[0002] With the wide application of image sensors, the performance requirements of consumers for image sensors are also increasing, especially the demand for full well capacity (FWC). The increase of pixel full well capacity cannot be achieved without the increase of the dopant amount of the photodiode (PD). The main method of PD doping is ion implantation. In order to further increase the total amount of PD doping, the dose, energy and doping steps of PD doping implantation are increasing.

[0003] With the improvement of the manufacturing process level of image sensors, the pixel size in the sensor array is gradually reduced. However, the performance requirements of image sensors are also increasing. PD with ultra-high doping concentration can provide very high capacitance, which is sufficient to meet the high full well capacity requirement of small size pixels. Therefore, the common idea to improve the full well capacity of pixels at present is to further improve the implantation level of PD. However, for single crystal silicon, the ion implantation process will inevitably cause damage to the silicon lattice and introduce unactivated impurity atoms into the silicon lattice, causing crystal defects. Proper heat treatment can repair the lattice defects of silicon to a certain extent and help the dopant atoms enter the lattice to be activated. However, long-term heat treatment will also cause the diffusion of the dopant elements, which may cause punch-through between devices and affect the independence of device operation. Based on this limitation, the actual process often pursues the lowest heat budget, leaving a certain proportion of unactivated dopant atoms. These unactivated dopant atoms will introduce impurity energy levels in the energy band gap of silicon, becoming the generation center of dark current. The more the dose of ion implantation, the more unactivated dopant atoms are introduced. Therefore, as the designed full well capacity of PD increases, the dark current level of the PD obtained by ion implantation is rising, which limits the further increase of the full well capacity. SUMMARY

[0004] In view of the problems existing in the prior art, the present application provides an image sensor with improved full well capacity by increasing an ion doping region in the center of the photodiode, which at least comprises:

[0005] A photodiode is formed in a semiconductor substrate; the photodiode comprises at least a first doped layer, a second doped layer and a columnar third doped region; the second doped layer wraps the side and bottom of the third doped region; the first doped layer wraps the side and bottom of the second doped layer; the first doped layer and the second doped layer form a first lateral PN junction; the second doped layer and the third doped region form a second lateral PN junction; wherein the first doped layer and the third doped region are of the same conductivity type, and the second doped layer is of the opposite conductivity type.

[0006] In some embodiments, the semiconductor substrate is an intrinsic semiconductor, the photodiode is formed in a recess of the semiconductor substrate; the first doped layer is formed on the sidewall and bottom of the recess by epitaxy; the second doped layer is formed on the sidewall and bottom of the first doped layer by epitaxy; the third doped region fills the gap of the second doped layer by epitaxy.

[0007] In some embodiments, the semiconductor substrate is a doped semiconductor, the photodiode is formed in a recess of the semiconductor substrate; the first doped layer is the sidewall and bottom of the recess; the second doped layer is formed on the sidewall and bottom of the first doped layer by epitaxy; the third doped region fills the gap of the second doped layer by epitaxy.

[0008] In some embodiments, a first intrinsic semiconductor is formed between the second doped layer and the third doped region.

[0009] In some embodiments, a second intrinsic semiconductor is formed between the first doped layer and the second doped layer.

[0010] In some embodiments, a first intrinsic semiconductor is formed between the second doped layer and the third doped region; and a second intrinsic semiconductor is formed between the first doped layer and the second doped layer.

[0011] In some embodiments, the second doped layer serves as a first charge storage region, the image sensor further comprises: an epitaxial layer formed on the semiconductor substrate; a first ion implantation region formed in the corresponding epitaxial layer above the second doped layer, serving as a second charge storage region; the first charge storage region and the second charge storage region are in electrical communication; wherein at least part of the corresponding epitaxial layer above the third doped region is free of the first ion implantation region; a second ion implantation region formed on the surface of the epitaxial layer, serving as a pinning layer; the pinning layer is in electrical communication with the third doped region; the pinning layer is grounded.

[0012] In some embodiments, the second doped layer is N-type; the first doped layer and the third doped region are P-type.

[0013] In some embodiments, the image sensor further comprises: a transistor; a metal interconnection layer; a filter; a microlens.

[0014] The application further provides an electronic information device comprising the image sensor.

[0015] Compared with the prior art, the embodiments of the application have the following beneficial effects:

[0016] The embodiments of the application replace the center part of the photodiode with a columnar ion-doped region (for example, a P-type layer), which can increase the full-well capacity of the photodiode, effectively reduce the depletion potential of the center of the photodiode, avoid the appearance of lag, and reduce the dark current.

[0017] The embodiments of the application add an intrinsic semiconductor layer with a proper thickness between the P-type and N-type doped layers in the photodiode, which can reduce the junction electric field and widen the width of the depletion region.

[0018] The embodiments of the application replace the center part of the photodiode with a columnar ion-doped region (for example, a P-type layer), which can help drive electrons to the shell of the photodiode, make the distance to the floating diffusion region closer, and reduce the difficulty of signal reading. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 is a structural schematic diagram of a front-illuminated image sensor according to an embodiment of the application;

[0020] Figure 2 FIG. 2 is a structural schematic diagram of a back-illuminated image sensor according to an embodiment of the application;

[0021] Figures 3 to 10 FIG. 3 is a structural schematic diagram of a photodiode applied to an image sensor according to different embodiments of the application. DETAILED DESCRIPTION

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some examples or embodiments of the application, and for those skilled in the art, the application can be applied to other similar scenarios without creative labor on the basis of these drawings. Unless it is obvious from the language environment or otherwise stated, the same reference numbers in the drawings represent the same structure or operation.

[0023] As indicated in this invention and the claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0024] It should be clearly understood that the accompanying drawings are for illustrative purposes only and are not intended to limit the scope of the invention. It should also be understood that the drawings are not to scale.

[0025] Figure 1 This is a schematic diagram of the structure of a front-illuminated image sensor according to an embodiment of the present invention.

[0026] like Figure 1 As shown, a front-illuminated image sensor may include a semiconductor substrate 11, a photodiode 12 formed within the semiconductor substrate 11, a plurality of transistors 13, a metal interconnect layer 14 formed on the front side of the semiconductor substrate 11, a filter 15 formed on the metal interconnect layer 14, and a microlens 16 formed on the filter 15. The photodiode 12 is used to generate charge in response to incident light.

[0027] Figure 2 This is a schematic diagram of the structure of a back-illuminated image sensor according to an embodiment of the present invention.

[0028] like Figure 2 As shown, a back-illuminated image sensor may include a semiconductor substrate 11, a photodiode 12 formed within the semiconductor substrate 11, a plurality of transistors 13, a metal interconnect layer 14 formed on the front side of the semiconductor substrate 11, a filter 15 formed on the back side of the semiconductor substrate 11, and a microlens 16 formed on the filter 15. The photodiode 12 is used to generate charge in response to incident light.

[0029] Figures 3 to 10 Different embodiments of the present invention are applied to Figure 1 or Figure 2 The diagram shows the structure of the photodiode in a front-illuminated or back-illuminated image sensor.

[0030] Example 1

[0031] like Figure 3 As shown, the semiconductor substrate 11 is an intrinsic semiconductor.

[0032] The photodiode 12 includes a first doped layer 121, a second doped layer 122 and a columnar third doped region 123. Specifically, the photodiode 12 is formed in a recess of the semiconductor substrate 11. The first doped layer 121 is formed on the sidewall and the bottom of the recess by an epitaxy process; the second doped layer 122 is formed on the sidewall and the bottom of the first doped layer 121 by an epitaxy process; and the third doped region 123 is formed in the gap of the second doped layer 122 by an epitaxy process. The first doped layer 121 wraps the sidewall and the bottom of the second doped layer 122; and the second doped layer 122 wraps the sidewall and the bottom of the third doped region 123.

[0033] The first doped layer 121 and the third doped region 123 have the same conductivity type and the opposite conductivity type of the second doped layer 122. Thus, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; and the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type; the first doped layer 121 and the third doped region 123 are N-type; and the second doped layer 122 is P-type. The second doped layer 122 serves as a first charge storage region for storing the charges generated by the photodiode 12 in response to the incident light.

[0034] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126 and a third ion implantation region 127 for isolating the first ion implantation region 125. The first ion implantation region 125 is formed in the corresponding epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed on the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charges generated by the photodiode 12 in response to the incident light. The first charge storage region and the second charge storage region are electrically connected. The corresponding epitaxial layer 124 above at least part of the third doped region 123 is free of the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since the corresponding epitaxial layer 124 above at least part of the third doped region 123 is free of the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0035] Embodiment Two

[0036] As shown in FIG. 2, the semiconductor substrate 11 is doped with N-type or P-type ions. Figure 4

[0037] As shown in FIG. 3, the photodiode 12 includes a first doped layer 121, a second doped layer 122 and a columnar third doped region 123. Figure 4

[0038] ​​Specifically, the photodiode 12 is formed within a recess in the semiconductor substrate 11. Since the semiconductor substrate 11 itself is a doped semiconductor doped with N-type or P-type ions, the first doped layer 121 can be a partial doped layer on the sidewalls and bottom of the recess. The second doped layer 122 is formed on the sidewalls and bottom of the first doped layer 121 by an epitaxial process; the third doped region 123 is filled in the gaps of the second doped layer 122 by an epitaxial process. The first doped layer 121 covers the sides and bottom of the second doped layer 122; the second doped layer 122 covers the sides and bottom of the third doped region 123.

[0039] In this configuration, the first doped layer 121 and the third doped region 123 have the same conductivity type, which is opposite to that of the second doped layer 122. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type. The second doped layer 122 serves as a first charge storage region, used to store the charge generated by the photodiode 12 in response to incident light.

[0040] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 serving as an isolation layer for the first ion implantation region 125. The first ion implantation region 125 is formed within an epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed above the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charge generated by the photodiode 12 in response to incident light. The first charge storage region and the second charge storage region are electrically connected. At least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0041] Example 3

[0042] like Figure 5 As shown, the semiconductor substrate 11 is an intrinsic semiconductor.

[0043] The photodiode 12 includes a first doped layer 121, a second doped layer 122, a first intrinsic semiconductor layer 128, and a pillar-shaped third doped region 123. Specifically, the photodiode 12 is formed within a recess in the semiconductor substrate 11. The first doped layer 121 is formed on the sidewalls and bottom of the recess using an epitaxial process; the second doped layer 122 is formed on the sidewalls and bottom of the first doped layer 121 using an epitaxial process; the first intrinsic semiconductor layer 128 is formed on the sidewalls and bottom of the second doped layer 122 using an epitaxial process; and the third doped region 123 fills the gaps in the first intrinsic semiconductor layer 128 using an epitaxial process. The first doped layer 121 covers the sides and bottom of the second doped layer 122; the second doped layer 122 covers the sides and bottom of the first intrinsic semiconductor layer 128; and the first intrinsic semiconductor layer 128 covers the sides and bottom of the third doped region 123.

[0044] In this configuration, the first doped layer 121 and the third doped region 123 have the same conductivity type, which is opposite to that of the second doped layer 122. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type. The second doped layer 122 serves as a first charge storage region, used to store the charge generated by the photodiode 12 in response to incident light.

[0045] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 serving as an isolation layer for the first ion implantation region 125. The first ion implantation region 125 is formed within an epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed above the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charge generated by the photodiode 12 in response to incident light. The first charge storage region and the second charge storage region are electrically connected. At least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0046] Example 4

[0047] like Figure 6 As shown, unlike Embodiment 3, the semiconductor substrate 11 itself is a doped semiconductor doped with N-type or P-type ions.

[0048] likeFigure 6 As shown, the photodiode 12 comprises a first doped layer 121, a second doped layer 122, a first intrinsic semiconductor layer 128 and a columnar third doped region 123.

[0049] Specifically, the photodiode 12 is formed in the recess of the semiconductor substrate 11. Since the semiconductor substrate 11 itself is a doped semiconductor doped with N-type or P-type ions, the first doped layer 121 can be a partial doped layer of the sidewall and the bottom of the recess. The second doped layer 122 is formed on the sidewall and the bottom of the first doped layer 121 by an epitaxial process; the first intrinsic semiconductor layer 128 is formed on the sidewall and the bottom of the second doped layer 1222 by an epitaxial process; and the third doped region 123 is filled in the gap of the first intrinsic semiconductor layer 128 by an epitaxial process. The first doped layer 121 wraps the sidewall and the bottom of the second doped layer 122; the second doped layer 122 wraps the sidewall and the bottom of the first intrinsic semiconductor layer 128; and the first intrinsic semiconductor layer 128 wraps the sidewall and the bottom of the third doped region 123.

[0050] The first doped layer 121 and the third doped region 123 have the same conductivity type and the opposite conductivity type of the second doped layer 122. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; and the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type; the first doped layer 121 and the third doped region 123 are N-type; and the second doped layer 122 is P-type. The second doped layer 122 serves as a first charge storage region for storing the charges generated by the photodiode 12 in response to the incident light.

[0051] The photodiode 12 further comprises a first ion implantation region 125, a second ion implantation region 126 and a third ion implantation region 127 as an isolation of the first ion implantation region 125. The first ion implantation region 125 is formed in the corresponding epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed on the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charges generated by the photodiode 12 in response to the incident light. The first charge storage region and the second charge storage region are electrically connected. At least part of the corresponding epitaxial layer 124 above the third doped region 123 is free of the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least part of the corresponding epitaxial layer 124 above the third doped region 123 is free of the first ion implantation region 125, the pinning layer can be electrically connected with the third doped region 123. The pinning layer is grounded.

[0052] Embodiment five

[0053] AsFigure 7 As shown, the semiconductor substrate 11 is intrinsic semiconductor.

[0054] The photodiode 12 includes a first doped layer 121, a second doped layer 122, a second intrinsic semiconductor layer 129, and a columnar third doped region 123. Specifically, the photodiode 12 is formed in the recess of the semiconductor substrate 11. The first doped layer 121 is formed on the sidewall and the bottom of the recess by epitaxy; the second intrinsic semiconductor layer 129 is formed on the sidewall and the bottom of the first doped layer 121 by epitaxy; the second doped layer 122 is formed on the sidewall and the bottom of the second intrinsic semiconductor layer 129 by epitaxy; and the third doped region 123 is formed in the gap of the second doped layer 122 by epitaxy. The first doped layer 121 wraps the sidewall and the bottom of the second intrinsic semiconductor layer 129; the second intrinsic semiconductor layer 129 wraps the sidewall and the bottom of the second doped layer 122; and the second doped layer 122 wraps the sidewall and the bottom of the third doped region 123.

[0055] The first doped layer 121 and the third doped region 123 have the same conductivity type, and the conductivity type of the second doped layer 122 is opposite to that of the first doped layer 121 and the third doped region 123. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; and the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the conductivity type of the second doped layer 122 is N-type; the first doped layer 121 and the third doped region 123 are N-type; and the conductivity type of the second doped layer 122 is P-type. The second doped layer 122 serves as a first charge storage region for storing the charges generated by the photodiode 12 in response to the incident light.

[0056] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 for isolating the first ion implantation region 125. The first ion implantation region 125 is formed in the corresponding epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed on the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charges generated by the photodiode 12 in response to the incident light. The first charge storage region and the second charge storage region are electrically connected. The corresponding epitaxial layer 124 above at least part of the third doped region 123 is free of the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124, and serves as a pinning layer. Since the corresponding epitaxial layer 124 above at least part of the third doped region 123 is free of the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0057] Embodiment six

[0058] As Figure 8As shown, different from the embodiment five, the semiconductor substrate 11 is a doped semiconductor doped with N-type or P-type ions.

[0059] As shown, the photodiode 12 includes a first doped layer 121, a second intrinsic semiconductor layer 129, a second doped layer 122 and a columnar third doped region 123. Figure 8

[0060] Specifically, the photodiode 12 is formed in the recess of the semiconductor substrate 11. Since the semiconductor substrate 11 is a doped semiconductor doped with N-type or P-type ions, the first doped layer 121 can be a partial doped layer of the sidewall and bottom of the recess. The second intrinsic semiconductor layer 129 is formed on the sidewall and bottom of the first doped layer 121 by an epitaxial process; the second doped layer 122 is formed on the sidewall and bottom of the second intrinsic semiconductor layer 129 by an epitaxial process; and the third doped region 123 is filled in the gap of the second doped layer 122 by an epitaxial process. The first doped layer 121 wraps the sidewall and bottom of the second intrinsic semiconductor layer 129; the second intrinsic semiconductor layer 129 wraps the sidewall and bottom of the second doped layer 122; and the second doped layer 122 wraps the sidewall and bottom of the third doped region 123.

[0061] The first doped layer 121 and the third doped region 123 have the same conductivity type and the opposite conductivity type of the second doped layer 122. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; and the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type; the first doped layer 121 and the third doped region 123 are N-type; and the second doped layer 122 is P-type. The second doped layer 122 serves as a first charge storage region for storing the charges generated by the photodiode 12 in response to the incident light.

[0062] ​The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 serving as an isolation layer for the first ion implantation region 125. The first ion implantation region 125 is formed within an epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed above the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charge generated by the photodiode 12 in response to incident light. The first charge storage region and the second charge storage region are electrically connected. At least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0063] Example 7

[0064] like Figure 9 As shown, the semiconductor substrate 11 is an intrinsic semiconductor.

[0065] The photodiode 12 includes a first doped layer 121, a second intrinsic semiconductor layer 129, a second doped layer 122, a first intrinsic semiconductor layer 128, and a columnar third doped region 123. Specifically, the photodiode 12 is formed within a recess in the semiconductor substrate 11. The first doped layer 121 is formed on the sidewalls and bottom of the recess using an epitaxial process; the second intrinsic semiconductor layer 129 is formed on the sidewalls and bottom of the first doped layer 121 using an epitaxial process; the second doped layer 122 is formed on the sidewalls and bottom of the second intrinsic semiconductor layer 129 using an epitaxial process; the first intrinsic semiconductor layer 128 is formed on the sidewalls and bottom of the second doped layer 122 using an epitaxial process; and the third doped region 123 fills the gaps in the first intrinsic semiconductor layer 128 using an epitaxial process. The first doped layer 121 covers the sides and bottom of the second intrinsic semiconductor layer 129; the second intrinsic semiconductor layer 129 covers the sides and bottom of the second doped region 122; and the second doped layer 122 covers the sides and bottom of the first intrinsic semiconductor layer 128. The first intrinsic semiconductor layer 128 encloses the sides and bottom of the third doped region 123.

[0066] In this configuration, the first doped layer 121 and the third doped region 123 have the same conductivity type, which is opposite to that of the second doped layer 122. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction; the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type; the second doped layer 122 is N-type. The second doped layer 122 serves as a first charge storage region, used to store the charge generated by the photodiode 12 in response to incident light.

[0067] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 serving as an isolation layer for the first ion implantation region 125. The first ion implantation region 125 is formed within an epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed above the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing the charge generated by the photodiode 12 in response to incident light. The first charge storage region and the second charge storage region are electrically connected. At least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least a portion of the epitaxial layer 124 above the third doped region 123 does not contain the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0068] Example 8

[0069] like Figure 10 As shown, unlike Embodiment 7, the semiconductor substrate 11 itself is a doped semiconductor doped with N-type or P-type ions.

[0070] like Figure 10 As shown, the photodiode 12 includes a first doped layer 121, a second intrinsic semiconductor layer 129, a second doped layer 122, a first intrinsic semiconductor layer 128, and a columnar third doped region 123.

[0071] Specifically, the photodiode 12 is formed in a recess of the semiconductor substrate 11. The first doped layer 121 is a side wall and a bottom of the recess. The second intrinsic semiconductor layer 129 is formed on the side wall and the bottom of the first doped layer 121 by an epitaxial process. The second doped layer 122 is formed on the side wall and the bottom of the second intrinsic semiconductor layer 129 by an epitaxial process. The first intrinsic semiconductor layer 128 is formed on the side wall and the bottom of the second doped layer 122 by an epitaxial process. The third doped region 123 is formed by filling the gap of the first intrinsic semiconductor layer 128 by an epitaxial process. The first doped layer 121 wraps the side and the bottom of the second intrinsic semiconductor layer 129. The second intrinsic semiconductor layer 129 wraps the side and the bottom of the second doped layer 122. The second doped layer 122 wraps the side and the bottom of the first intrinsic semiconductor layer 128. The first intrinsic semiconductor layer 128 wraps the side and the bottom of the third doped region 123.

[0072] The first doped layer 121 and the third doped region 123 have the same conductivity type, and the conductivity type of the second doped layer 122 is opposite to that of the first doped layer 121 and the third doped region 123. Therefore, the first doped layer 121 and the second doped layer 122 form a first lateral PN junction, and the second doped layer 122 and the third doped region 123 form a second lateral PN junction. Specifically, the first doped layer 121 and the third doped region 123 are P-type, and the conductivity type of the second doped layer 122 is N-type. The first doped layer 121 and the third doped region 123 are N-type, and the conductivity type of the second doped layer 122 is P-type. The second doped layer 122 serves as a first charge storage region for storing charges generated by the photodiode 12 in response to incident light.

[0073] The photodiode 12 further includes a first ion implantation region 125, a second ion implantation region 126, and a third ion implantation region 127 for isolating the first ion implantation region 125. The first ion implantation region 125 is formed in a corresponding epitaxial layer 124 above the second doped layer 122. The epitaxial layer 124 is formed on the semiconductor substrate 11. The first ion implantation region 125 serves as a second charge storage region for storing charges generated by the photodiode 12 in response to incident light. The first charge storage region and the second charge storage region are electrically connected. At least part of the corresponding epitaxial layer 124 above the third doped region 123 is free of the first ion implantation region 125. The second ion implantation region 126 is formed on the surface of the epitaxial layer 124 as a pinning layer. Since at least part of the corresponding epitaxial layer 124 above the third doped region 123 is free of the first ion implantation region 125, the pinning layer can be electrically connected to the third doped region 123. The pinning layer is grounded.

[0074] In the above embodiments, due to the high depletion potential in the center of the photodiode with high full well capacity, for the large pixel size design of the image sensor, it is difficult to completely deplete the photodiode inside only by the first doped layer 121 (for example, P-type layer). Therefore, replacing the center part of the photodiode with the columnar third doped region 123 (for example, P-type layer) can effectively reduce the depletion potential in the center of the photodiode and avoid the occurrence of lag.

[0075] In some embodiments, for the pixel design of the image sensor, the floating diffusion (FD) is usually located on one side of the photodiode and not in the center of the photodiode, so that the electrons flowing from the photodiode to the floating diffusion FD will encounter a potential barrier. When the size of the photodiode is large, the center of the photodiode is far away from the floating diffusion, and it is more difficult to extract electrons. In the above example, introducing the third doped region 123 (for example, P-type layer) in the center of the photodiode can help drive the electrons to the shell of the photodiode, and the distance to the floating diffusion FD becomes closer, reducing the difficulty of signal readout.

[0076] It is obvious to those skilled in the art that the present application is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be regarded as exemplary and non-limiting in any way. In addition, it is obvious that the word "comprising" does not exclude other elements and steps, and the word "one" does not exclude a plurality. The words "first", "second" and the like are used to indicate names and not to indicate any particular order.

Claims

1. An image sensor with improved full well capacity, characterized by, At least comprising: a photodiode formed in a semiconductor substrate; the photodiode at least comprising a first doped layer, a second doped layer and a columnar third doped region; the second doped layer wrapping the side and bottom of the third doped region; the first doped layer wrapping the side and bottom of the second doped layer; the first doped layer and the second doped layer forming a first lateral PN junction; the second doped layer and the third doped region forming a second lateral PN junction; wherein the first doped layer and the third doped region are of the same conductivity type and opposite to the conductivity type of the second doped layer; the second doped layer as a first charge storage region, the image sensor further comprising: an epitaxial layer formed on the semiconductor substrate; a first ion implantation region formed in the epitaxial layer above the second doped layer as a second charge storage region; the first charge storage region electrically connected to the second charge storage region; wherein at least part of the epitaxial layer above the third doped region is free of the first ion implantation region; a second ion implantation region formed on the surface of the epitaxial layer as a pinning layer; the pinning layer electrically connected to the third doped region; the pinning layer grounded.

2. The image sensor of claim 1, wherein: the semiconductor substrate is an intrinsic semiconductor, the photodiode formed in a recess of the semiconductor substrate; the first doped layer is formed on the sidewall and bottom of the recess by epitaxy; the second doped layer is formed on the sidewall and bottom of the first doped layer by epitaxy; the third doped region is filled in the gap of the second doped layer by epitaxy.

3. The image sensor of claim 1, wherein: the semiconductor substrate is a doped semiconductor, the photodiode formed in a recess of the semiconductor substrate; the first doped layer is the sidewall and bottom of the recess; the second doped layer is formed on the sidewall and bottom of the first doped layer by epitaxy; the third doped region is filled in the gap of the second doped layer by epitaxy.

4. The image sensor of any one of claims 1 to 3, a first intrinsic semiconductor formed between the second doped layer and the third doped region.

5. The image sensor of any one of claims 1 to 3, a second intrinsic semiconductor formed between the first doped layer and the second doped layer.

6. The image sensor of any one of claims 1 to 3, a first intrinsic semiconductor formed between the second doped layer and the third doped region; and a second intrinsic semiconductor formed between the first doped layer and the second doped layer.

7. The image sensor of claim 1, wherein, the second doped layer is N-type; the first doped layer and the third doped region are P-type.

8. The image sensor of claim 1, wherein, the image sensor further comprising: a transistor; a metal interconnection layer; a color filter; a microlens.

9. An electronic information device, characterized by comprising: comprising the image sensor of any one of claims 1 to 8.

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