Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a semiconductor layer, a doped nitride semiconductor layer, an undoped III-V semiconductor layer, a channel layer, and a barrier layer. The semiconductor layer has a dislocation extending upward. The doped nitride semiconductor layer is disposed on the semiconductor layer. The undoped III-V semiconductor layer is disposed between the semiconductor layer and the doped nitride semiconductor layer, the undoped III-V semiconductor layer has a lattice density greater than a lattice density of the semiconductor layer, the undoped III-V semiconductor layer has a lattice density greater than a lattice density of the doped nitride semiconductor layer, the undoped III-V semiconductor layer contacts the semiconductor layer to form a first interface, wherein the dislocation extends from the semiconductor layer to the first interface and into the undoped III-V semiconductor layer, the dislocation changes a threading direction at the first interface, wherein an angle of the change of the threading direction at the first interface is at least 30 degrees. The channel layer is disposed on the doped nitride semiconductor layer. The barrier layer is disposed on the channel layer.

Description

[0001] This application is a divisional application of Chinese Patent Application No. 202080001568.9 entitled “Semiconductor Device and Method of Manufacturing Thereof”, filed on June 4, 2020. Technical Field

[0002] This disclosure relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a superlattice layer, a doped III-V semiconductor layer, and an undoped III-V semiconductor layer, and a method of manufacturing the same. Background Technology

[0003] Components including direct bandgap semiconductors, such as semiconductor components including group III-V materials or group III-V compounds, can operate or function under various conditions or environments (e.g., different voltages and frequencies) due to their characteristics.

[0004] The aforementioned semiconductor components may include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), high-electron-mobility transistors (HEMTs), or modulation-doped field effect transistors (MODFETs), etc. Summary of the Invention

[0005] According to one aspect of this disclosure, a semiconductor device is provided, comprising a semiconductor layer, a doped nitride semiconductor layer, an undoped III-V semiconductor layer, a channel layer, and a barrier layer. The semiconductor layer has upwardly extending dislocations. The doped nitride semiconductor layer is disposed on the semiconductor layer. The undoped III-V semiconductor layer is disposed between the semiconductor layer and the doped nitride semiconductor layer, the undoped III-V semiconductor layer having a higher lattice density than the semiconductor layer, and the undoped III-V semiconductor layer contacts the semiconductor layer to form a first interface, wherein the dislocations extend from the semiconductor layer to the first interface and into the undoped III-V semiconductor layer, and the dislocations change their path direction at the first interface, wherein the change in path direction at the first interface is at least 30 degrees. The channel layer is disposed on the doped nitride semiconductor layer. A barrier layer is disposed on the channel layer and in contact with the channel layer, and has a larger band gap than the channel layer.

[0006] According to one aspect of this disclosure, a method for manufacturing a semiconductor device is provided, comprising the following steps: forming a semiconductor layer on a substrate, the semiconductor layer having a top layer; forming an undoped III-V semiconductor layer on the semiconductor layer; forming a doped nitride semiconductor layer on the undoped III-V semiconductor layer, wherein the lattice density of the undoped III-V semiconductor layer is greater than the lattice density of the semiconductor layer, the undoped III-V semiconductor layer having a greater lattice density than the doped nitride semiconductor layer, the undoped III-V semiconductor layer contacting the semiconductor layer to form a first interface, wherein dislocations extend from the semiconductor layer to the first interface and enter the undoped III-V semiconductor layer, the dislocations changing their trajectory direction at the first interface, wherein the angle of change of the trajectory direction at the first interface is at least 30 degrees; forming a channel layer on the doped nitride semiconductor layer; forming a barrier layer on the channel layer and contacting the channel layer, the barrier layer having a larger band gap than the band gap of the channel layer. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, various aspects of this disclosure will be readily understood from the following detailed description. It should be noted that the features may not be drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figure 1The image shown is a side view of a semiconductor device according to some embodiments of this invention.

[0009] Figure 2 The image shown is a partial enlarged view of a semiconductor device according to certain embodiments of this application; and

[0010] Figure 3A , Figure 3B ,and Figure 3C The diagram illustrates several operations for manufacturing a semiconductor device according to certain embodiments of this invention. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. In this disclosure, the description in the following description of a first feature forming on or above a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for the purpose of simplicity and clarity and does not in itself define the relationship between the various embodiments and / or configurations discussed.

[0012] Embodiments of this disclosure are described in detail below. However, it should be understood that many applicable concepts provided in this disclosure can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative and do not limit the scope of this disclosure.

[0013] Direct bandgap materials, such as III-V compounds, may include, but are not limited to, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (InAlAs).

[0014] For semiconductor devices using III-V compounds (such as high electron mobility transistors (HEMTs)), one method to improve leakage current blocking capability (i.e., increase breakdown voltage) is to add a carbon-doped III-V semiconductor layer to the semiconductor device. While adding a carbon-doped III-V semiconductor layer can improve leakage current blocking capability, it may also increase the overall size of the semiconductor device or structure, require consideration of defects caused by material differences between adjacent layers (such as delamination or peel-off), and may increase cost.

[0015] Furthermore, because the lattice arrangement of the carbon-doped III-V semiconductor layer is looser compared to other semiconductor layers in the device (such as superlattice layers), it may not be able to effectively block the diffusion of crystallographic defects (such as dislocations) generated under relatively high voltage environments (such as greater than 200 volts (V)).

[0016] Figure 1 The image shown is a side view of a semiconductor device 1 according to some embodiments of this case.

[0017] like Figure 1 As shown, the semiconductor device 1 may include a substrate 10, a semiconductor layer 11, an undoped III-V semiconductor layer 12, a doped III-V semiconductor layer 13, a III-V semiconductor layer 14, a III-V semiconductor layer 15, a doped III-V semiconductor layer 16, a metal layer 17, a passivation layer 18, a passivation layer 19, a source contact 20, a drain contact 21, a dielectric layer 22, a field plate 23, a dielectric layer 24, a conductor structure 25, a field plate 26, and a dielectric layer 27.

[0018] The substrate 10 may include, for example, but not limited to, silicon (Si), doped silicon (Si), silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor materials. The substrate 10 may include, for example, but not limited to, sapphire, silicon on insulator (SOI), or other suitable materials.

[0019] The semiconductor layer 11 may be disposed on the substrate 10. The semiconductor layer 11 may be disposed between the substrate 10 and the undoped III-V semiconductor layer 12.

[0020] In some embodiments, semiconductor layer 11 may include a buffer layer. In some embodiments, semiconductor layer 11 may include, for example, but not limited to, a superlattice layer. In some embodiments, semiconductor layer 11 may include, for example, but not limited to, nitrides, such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), etc. In some embodiments, semiconductor layer 11 may be used to facilitate lattice match between substrate 10 and layers on substrate 10 (e.g., undoped III-V semiconductor layer 12 and / or doped III-V semiconductor layer 13 located above substrate 10). Semiconductor layer 11 may include a multi-layer structure. Semiconductor layer 11 may include a multi-layer stack. Semiconductor layer 11 may include, for example, but not limited to, alternating stacks of multiple GaN layers and multiple AlGaN layers. In some embodiments, semiconductor layer 11 may reduce the tensile stress of semiconductor device 1. In some embodiments, semiconductor layer 11 can capture electrons diffused from substrate 10 to undoped III-V semiconductor layer 12 and / or doped III-V semiconductor layer 13, thereby improving device performance and reliability. In some embodiments, semiconductor layer 11 can increase breakdown voltage. In some embodiments, semiconductor layer 11 can prevent defects (e.g., dislocations) from propagating from substrate 10 to undoped III-V semiconductor layer 12 and / or doped III-V semiconductor layer 13, thereby preventing dysfunction of semiconductor device 1.

[0021] An undoped III-V semiconductor layer 12 may be disposed on semiconductor layer 11. In other words, the undoped III-V semiconductor layer 12 may be disposed between semiconductor layer 11 and doped III-V semiconductor layer 13. In some embodiments, the lattice density of the undoped III-V semiconductor layer 12 may be greater than that of semiconductor layer 11. In some embodiments, the lattice density of the undoped III-V semiconductor layer 12 may be greater than that of the doped III-V semiconductor layer 13. Detailed structure of the undoped III-V semiconductor layer 12 will be referred to... Figure 2 The description is as follows.

[0022] In some embodiments, the undoped III-V semiconductor layer 12 may include, for example, but not limited to, gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs). In some embodiments, the undoped III-V semiconductor layer 12 may include a nitride semiconductor layer. In some embodiments, the undoped III-V semiconductor layer 12 may include, for example, but not limited to, group III nitrides, such as the compound In. x Al y Ga (1-x-y) N, where x+y≦1 and the compound Al y Ga (1-y) N, where y≦1. In some embodiments, the undoped III-V semiconductor layer 12 may include, for example, but not limited to, two-dimensional (2D) materials. In some embodiments, the undoped III-V semiconductor layer 12 may include, for example, but not limited to, crystalline materials consisting of a single layer of atoms.

[0023] A doped III-V semiconductor layer 13 may be disposed on an undoped III-V semiconductor layer 12. In some embodiments, the doped III-V semiconductor layer 13 may include a nitride semiconductor layer. In some embodiments, the doped III-V semiconductor layer 13 may include, for example, but not limited to, doped gallium nitride (GaN), doped aluminum gallium nitride (AlGaN), doped indium gallium nitride (InGaN), and other doped III-V compounds. In some embodiments, the doped III-V semiconductor layer 13 may include, for example, but not limited to, p-type dopant, n-type dopant, or other dopants. In some embodiments, the dopants of the doped III-V semiconductor layer 13 may include, for example, but not limited to, carbon (C), silicon (Si), germanium (Ge), etc. In some embodiments, the doped III-V semiconductor layer 13 may include, for example, but not limited to, a carbon-doped III-V semiconductor layer.

[0024] The doped III-V semiconductor layer 13 improves leakage current blocking capability, but the lattice arrangement of the doped III-V semiconductor layer 13 is looser compared to the other semiconductor layers of the semiconductor device 1 (e.g., semiconductor layer 11). When the semiconductor device 1 is used in a relatively high voltage environment (e.g., greater than 200 volts (V)), crystal defects (e.g., dislocations) can diffuse from semiconductor layer 11 through the doped III-V semiconductor layer 13 to III-V semiconductor layers 14 and 15 (III-V semiconductor layers 14 and 15 will be described below), causing the semiconductor device 1 to fail.

[0025] This disclosure discloses that by providing an undoped III-V semiconductor layer 12 between the doped III-V semiconductor layer 13 and the semiconductor layer 11, defect density can be reduced without excessively increasing the overall thickness of the device (e.g., the increase in overall thickness is less than 10%). For example, the undoped III-V semiconductor layer 12 provided between the semiconductor layer 11 and the doped III-V semiconductor layer 13 can reduce the dislocation density diffused or propagated from the doped III-V semiconductor layer 13 to the III-V semiconductor layers 14 and 15. For example, the undoped III-V semiconductor layer 12 provided between the semiconductor layer 11 and the doped III-V semiconductor layer 13 can reduce the dislocation density diffused or propagated from the semiconductor layer 11 to the III-V semiconductor layers 14 and 15 via the doped III-V semiconductor layer 13. For example, an undoped III-V semiconductor layer 12 disposed between semiconductor layer 11 and doped III-V semiconductor layer 13 can reduce the dislocation density diffused or traveled from semiconductor layer 11 through doped III-V semiconductor layer 13 to III-V semiconductor layers 14 and 15 by at least one order of magnitude. For example, the undoped III-V semiconductor layer 12 disposed between semiconductor layer 11 and doped III-V semiconductor layer 13 can enable semiconductor device 1 to operate under high voltage conditions (e.g., greater than 200 volts).

[0026] A III-V semiconductor layer 14 may be disposed on a doped III-V semiconductor layer 13. In some embodiments, the III-V semiconductor layer 14 may include, for example, but not limited to, an undoped III-V semiconductor layer. The III-V semiconductor layer 14 may include, for example, but not limited to, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, and aluminum gallium arsenide. In some embodiments, the III-V semiconductor layer 14 may include a nitride semiconductor layer. The III-V semiconductor layer 14 may include, for example, but not limited to, a group III nitride, such as compound In. x Al y Ga (1-x-y) N, where x+y≦1. Group III nitrides may also include, for example, but not limited to, compounds Al. y Ga (1-y) N, where y≦1.

[0027] A III-V semiconductor layer 15 may be disposed on a doped III-V semiconductor layer 13. A III-V semiconductor layer 15 may be disposed on a III-V semiconductor layer 14. In some embodiments, the III-V semiconductor layer 15 may include a nitride semiconductor layer. In some embodiments, the III-V semiconductor layer 15 may include, for example, but not limited to, a III-V nitride, such as compound In. x Al y Ga (1-x-y) N, where x+y≦1. The III-V group semiconductor layer 15 may include, for example, but not limited to, compounds Al. y Ga (1-y) N, where y≦1.

[0028] The III-V semiconductor layer 15 may have a relatively larger band gap than the III-V semiconductor layer 14. For example, the III-V semiconductor layer 14 may include a GaN layer, which may have a band gap of about 3.4 electron volts (eV); and the III-V semiconductor layer 15 may include AlGaN, which may have a band gap of about 4 eV. A heterojunction may be formed between the III-V semiconductor layers 14 and 15, and polarization may occur at the heterojunction with different nitrides. An electron channel region (e.g., a two-dimensional electron gas (2DEG) region) may be formed in the III-V semiconductor layer 14. The III-V semiconductor layer 14 may serve as the channel layer of the semiconductor device 1, and the III-V semiconductor layer 15 may serve as the barrier layer of the semiconductor device 1.

[0029] A doped III-V semiconductor layer 16 may be disposed on the III-V semiconductor layer 15. In some embodiments, the doped III-V semiconductor layer 16 may include, for example, but not limited to, doped gallium nitride, doped aluminum gallium nitride, doped indium gallium nitride, and other doped III-V compounds. In some embodiments, the doped III-V semiconductor layer 16 may include a doped nitride semiconductor layer. In some embodiments, the doped III-V semiconductor layer 16 may include, for example, but not limited to, p-type dopants or other dopants. In some embodiments, the dopants of the doped III-V semiconductor layer 16 may include, for example, but not limited to, magnesium (Mg), zinc (Zn), cadmium (Cd), silicon (Si), germanium (Ge), etc.

[0030] Metal layer 17 may be disposed on doped III-V semiconductor layer 16. In some embodiments, metal layer 17 may include, for example, but not limited to, a refractory metal or a compound thereof. For example, metal layer 17 may include, for example, but not limited to, metals such as niobium (Nb), molybdenum (Mo), tantalum (Ta), tungsten (W), rhenium (Re), titanium (Ti), vanadium (V), chromium (Cr), zirconium (Zr), hafnium (Hf), ruthenium (Ru), osmium (Os), iridium (Ir), or compounds of such metals, such as tantalum nitride (TaN), titanium nitride (TiN), tungsten carbide (WC), etc.

[0031] In some embodiments, the metal layer 17 may serve as a stop layer or protective layer for the doped III-V semiconductor layer 16 during the fabrication of the semiconductor device 1. For example, the metal layer 17 may keep the unexposed surface of the doped III-V semiconductor layer 16 substantially flat during removal techniques (e.g., etching). In some embodiments, the metal layer 17 may help improve bias control of the conductor structure 25. In some embodiments, the metal layer 17 may help improve the gate switching speed. In some embodiments, the metal layer 17 may help reduce leakage current and increase the threshold voltage.

[0032] Conductor structure 25 may be disposed on metal layer 17. In some embodiments, conductor structure 25 may include, for example, but not limited to, a gate structure. In some embodiments, conductor structure 25 may include, for example, but not limited to, a gate metal. In some embodiments, the gate metal of conductor structure 25 may include, for example, but not limited to, titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and its compounds (e.g., but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides, or conductive oxides), metal alloys (e.g., aluminum-copper alloy (Al-Cu)), or other suitable materials.

[0033] Passivation layer 18 may be disposed on III-V semiconductor layer 15. Passivation layer 18 may surround doped III-V semiconductor layer 16. Passivation layer 18 may cover doped III-V semiconductor layer 16. Passivation layer 18 may surround metal layer 17. Passivation layer 18 may cover metal layer 17. Passivation layer 18 may cover a portion of metal layer 17. Passivation layer 18 may surround conductor structure 25. Passivation layer 18 may surround a portion of conductor structure 25. In some embodiments, passivation layer 18 may include, for example, but not limited to, oxides or nitrides. In some embodiments, passivation layer 18 may include, for example, but not limited to, silicon nitride (Si3N4), silicon oxide (SiO2), or other suitable materials. In some embodiments, passivation layer 18 may include, for example, but not limited to, a composite layer of oxides and nitrides, such as Al2O3 / Si3N4, Al2O3 / SiO2, AlN / Si3N4, AlN / SiO2, etc.

[0034] A passivation layer 19 may be disposed on a passivation layer 18. The passivation layer 19 may surround a conductor structure 25. The passivation layer 19 may surround a portion of the conductor structure 25. In some embodiments, the passivation layer 19 may include, for example, but not limited to, the materials listed above for the passivation layer 18.

[0035] The source contact 20 may be disposed on the III-V semiconductor layer 15. The source contact 20 may penetrate the passivation layer 18 and the passivation layer 19 to contact the III-V semiconductor layer 15. The source contact 20 may be partially located in the III-V semiconductor layer 15.

[0036] In some embodiments, the source contact 20 may include, for example, but not limited to, a conductive material. In some embodiments, the source contact 20 may include, for example, but not limited to, a metal, an alloy, a doped semiconductor material (e.g., doped crystalline silicon) or other suitable conductive material.

[0037] The drain contact 21 may be disposed on the III-V semiconductor layer 15. The drain contact 21 may penetrate the passivation layer 18 and the passivation layer 19 to contact the III-V semiconductor layer 15. The drain contact 21 may be partially located in the III-V semiconductor layer 15.

[0038] In some embodiments, the drain contact 21 may include, for example, but not limited to, the materials listed above for the source contact 20.

[0039] Although source contact 20 and drain contact 21 are in Figure 1 The source contact 20, drain contact 21 and conductor structure 25 are respectively disposed on both sides of the conductor structure 25, but the positions of the source contact 20, drain contact 21 and conductor structure 25 may be configured differently in other embodiments of this invention due to design requirements.

[0040] A dielectric layer 22 may be disposed on the passivation layer 19. The dielectric layer 22 may surround the conductor structure 25. The dielectric layer 22 may surround a portion of the conductor structure 25. The dielectric layer 22 may cover the source contact 20. The dielectric layer 22 may cover the drain contact 21. In some embodiments, the dielectric layer 22 may include, for example, but not limited to, the materials listed above for the passivation layer 18. In some embodiments, the dielectric layer 22 may include a material different from the passivation layer 18 and / or the passivation layer 19, such as other dielectric materials.

[0041] Field plate 23 may be disposed on dielectric layer 22. Field plate 23 may be adjacent to conductor structure 25. Field plate 23 may be connected to source contact 20 and / or drain contact 21 through other conductor structures. In some embodiments, field plate 23 may include, for example, but not limited to, a conductive material, such as a metal or alloy.

[0042] Dielectric layer 24 may be disposed on dielectric layer 22 and cover field plate 23. Dielectric layer 24 may surround conductor structure 25. Dielectric layer 24 may surround a portion of conductor structure 25. In some embodiments, dielectric layer 24 may include, for example, but not limited to, the materials listed above for passivation layer 18.

[0043] Field plate 26 may be disposed on dielectric layer 24. Field plate 26 may be spaced apart from field plate 23 via dielectric layer 24. Field plate 26 may be adjacent to conductor structure 25. The projected areas of field plate 26 and field plate 23 on substrate 10 may at least partially overlap. Field plate 26 may be connected to source contact 20 and / or drain contact 21 through other conductor structures. In some embodiments, field plate 26 may include, for example, but not limited to, a conductive material, such as a metal or alloy.

[0044] Dielectric layer 27 may be disposed on dielectric layer 24 and cover field plate 26. Dielectric layer 27 may cover a portion of conductor structure 25. In some embodiments, dielectric layer 27 may include, for example, but not limited to, the materials listed above for passivation layer 18.

[0045] Although this disclosure describes semiconductor device 1 having three dielectric layers (dielectric layer 22, dielectric layer 24, and dielectric layer 27), this disclosure is not limited thereto. For example, in some embodiments, semiconductor device 1 may have any number of dielectric layers depending on device specifications. Although this disclosure describes semiconductor device 1 having two field plates (field plate 23 and field plate 26), this disclosure is not limited thereto. For example, in some embodiments, semiconductor device 1 may have any number of field plates depending on device specifications.

[0046] Reference Figure 2 , Figure 2 The image shown is a partially enlarged view of a semiconductor device according to certain embodiments of this invention. In some embodiments, Figure 2 Part 2 of the semiconductor device shown may be Figure 1 A portion of the semiconductor device 1 shown.

[0047] Semiconductor layer 11 may have a surface 111 in contact with substrate 10. Semiconductor layer 11 may have a surface 112 in contact with undoped III-V semiconductor layer 12. Semiconductor layer 11 may include a multilayer structure and / or a plurality of layers stacked. Semiconductor layer 11 may include a multilayer structure and / or a plurality of layers stacked with two compounds. Semiconductor layer 11 may include a multilayer structure and / or a plurality of layers stacked with alternating layers of two compounds. In some embodiments, each layer in semiconductor layer 11 may include, for example, but not limited to, a plurality of layers with a thickness on the nanometer (nm) scale. For example, semiconductor layer 11 may include a plurality of layers with thicknesses between about 1 nm and about 100 nm. For example, semiconductor layer 11 may include a plurality of layers with thicknesses between about 1 nm and about 50 nm. In some embodiments, the interfaces between the layers in semiconductor layer 11 may be observed using, for example, a transmission electron microscope (TEM). The aforementioned interfaces are not shown in the figures for simplicity. In some embodiments, semiconductor layer 11 may include a top layer 11a. The top layer 11a may be the layer furthest from the substrate 10 among the various layers of semiconductor layer 11. In other words, the top layer 11a may be the layer closest to the undoped III-V semiconductor layer 12 among the various layers of semiconductor layer 11. In other words, the top layer 11a may have a surface 112. The top layer 11a may be a homogeneous layer, for example, the top layer 11a may have a single material. In some embodiments, the top layer 11a may have a substantially homogeneous concentration. In some embodiments, the top layer 11a may have a gradient concentration. The top layer 11a may be in contact with the undoped III-V semiconductor layer 12. The thickness of the top layer 11a may be indicated by "t1". The thickness t1 of the top layer 11a may be measured in a direction substantially perpendicular to surface 111 and / or surface 121. In some embodiments, the thickness t1 of the top layer 11a may be between about 1 nm and about 100 nm, between about 1 nm and about 50 nm, or between about 1 nm and about 10 nm. In some embodiments, the top layer 11a may have the same material as the undoped III-V semiconductor layer 12. In some embodiments, the top layer 11a may have a different material than the undoped III-V semiconductor layer 12. In some embodiments, the interface between the top layer 11a and the undoped III-V semiconductor layer 12, i.e., the interface between surface 112 and surface 121, can be observed using, for example, TEM.

[0048] The undoped III-V semiconductor layer 12 may have a surface 121 in contact with the semiconductor layer 11. The undoped III-V semiconductor layer 12 may have a surface 122 in contact with the doped III-V semiconductor layer 13. The thickness of the undoped III-V semiconductor layer 12 may be indicated by "t2". The thickness t2 of the undoped III-V semiconductor layer 12 may be measured in a direction substantially perpendicular to surfaces 121 and / or 122. In some embodiments, the thickness t2 of the undoped III-V semiconductor layer 12 may be greater than the thickness of each layer in the semiconductor layer 11. For example, the thickness t2 of the undoped III-V semiconductor layer 12 may be at least an order of magnitude greater than the thickness of each layer in the semiconductor layer 11. For example, the thickness of each layer in the semiconductor layer 11 may be at least an order of magnitude smaller than the thickness t2 of the undoped III-V semiconductor layer 12. For example, the thickness t2 of the undoped III-V semiconductor layer 12 may be greater than the thickness t1 of the top layer 11a of the semiconductor layer 11. For example, the thickness t2 of the undoped III-V semiconductor layer 12 may be at least an order of magnitude larger than the thickness t1 of the top layer 11a. Conversely, the thickness t1 of the top layer 11a may be at least an order of magnitude smaller than the thickness t2 of the undoped III-V semiconductor layer 12. In some embodiments, the thickness t2 of the undoped III-V semiconductor layer 12 may be, for example, but not limited to, on the micrometer (μm) scale. For example, the thickness of the undoped III-V semiconductor layer 12 may be between about 0.01 μm and about 1 μm, that is, between about 10 nm and about 1000 nm.

[0049] In some embodiments, the interface between the top layer 11a and the undoped III-V semiconductor layer 12 (i.e., the interface between surface 112 and surface 121) has dislocations. In some embodiments, the dislocations at the interface between the top layer 11a and the undoped III-V semiconductor layer 12 may extend substantially along surface 121 of the undoped III-V semiconductor layer 12. In some embodiments, the dislocations at the interface between the top layer 11a and the undoped III-V semiconductor layer 12 may extend substantially along surface 112 of semiconductor layer 11. For example, as... Figure 2As shown, a dislocation traveling from semiconductor layer 11 generally in one direction (denoted as "d1") toward undoped III-V semiconductor layer 12 changes its travel direction to another direction (denoted as "d2") at the interface between top layer 11a and undoped III-V semiconductor layer 12. In some embodiments, the angle (denoted as "θ", i.e., the angle between directions d1 and d2) at the interface between top layer 11a and undoped III-V semiconductor layer 12 can be at least 30 degrees, at least 37 degrees, at least 40 degrees, at least 50 degrees, at least 60 degrees, at least 70 degrees, or more, for example, 90 degrees.

[0050] In some embodiments, because dislocations change their trajectory direction at the interface between the top layer 11a and the undoped III-V semiconductor layer 12, the dislocation density at the interface between the undoped III-V semiconductor layer 12 and the doped III-V semiconductor layer 13 may be less than the dislocation density at the interface between the undoped III-V semiconductor layer 12 and semiconductor layer 11. In other words, the dislocation density at the surface 122 of the undoped III-V semiconductor layer 12 may be less than the dislocation density at the surface 121 of the undoped III-V semiconductor layer 12. In some embodiments, the dislocation density at the surface 122 of the undoped III-V semiconductor layer 12 may be at least an order of magnitude smaller than the dislocation density at the surface 121 of the undoped III-V semiconductor layer 12. In other words, the proportion of the dislocation density along direction d2 at the interface between the top layer 11a and the undoped III-V semiconductor layer 12 is at least ten percent of the total dislocation density. In some embodiments, all dislocations change their direction of travel to direction d2 at the interface between the top layer 11a and the undoped III-V semiconductor layer 12. Therefore, the dislocation density in the undoped III-V semiconductor layer 12 can be approximately zero. In other words, the undoped III-V semiconductor layer 12 may not have any dislocations.

[0051] In a comparative embodiment excluding the undoped III-V semiconductor layer 12, the top layer 11a directly contacts the doped III-V semiconductor layer 13. The angle of change of dislocations at the interface between the top layer 11a and the doped III-V semiconductor layer 13 is less than 40 degrees, less than 37 degrees, less than 30 degrees, less than 20 degrees, or less. In some embodiments, the path direction of dislocations from the top layer 11a to the doped III-V semiconductor layer 13 changes almost no.

[0052] Compared to the comparative embodiment, the dislocation density of the III-V semiconductor layers 14 and 15 is reduced by at least an order of magnitude. Furthermore, the addition of the undoped III-V semiconductor layer 12 increases the overall thickness of the device (e.g., semiconductor device 1) by less than 10%. Therefore, the addition of the undoped III-V semiconductor layer 12, which is thicker than the individual layers in semiconductor layer 11, will not cause the chip to bend during the manufacturing process due to thermal mismatch or other stresses.

[0053] The doped III-V semiconductor layer 13 may have a surface 131 in contact with the undoped III-V semiconductor layer 12. The doped III-V semiconductor layer 13 may also have a surface 132 in contact with the III-V semiconductor layer 14. In some embodiments, the interface between the doped III-V semiconductor layer 13 and the undoped III-V semiconductor layer 12 (i.e., the interface between surface 122 and surface 131) has dislocations. In some embodiments, the dislocations at the interface between the doped III-V semiconductor layer 13 and the undoped III-V semiconductor layer 12 may extend from the undoped III-V semiconductor layer 12. In some embodiments, the change angle of the dislocations at the interface between the doped III-V semiconductor layer 13 and the undoped III-V semiconductor layer 12 may be approximately zero. In some embodiments, the degree of dislocation at the interface between the doped III-V semiconductor layer 13 and the undoped III-V semiconductor layer 12 may be approximately zero.

[0054] In some embodiments, the addition of an undoped III-V semiconductor layer 12 can reduce the dislocation density on the doped III-V semiconductor layer of a device (e.g., semiconductor device 1) by at least one order of magnitude. For example, it can reduce the threading dislocation density on the doped III-V semiconductor layer 13 from about 10 9 cm -2 Reduced to 1x10 8 cm -2 ~5x10 8 cm -2 For example, reducing the threaded dislocation density on the III-V semiconductor layer 14 from approximately 10-1 9 cm -2 Reduced to 1x10 8 cm -2 ~5x10 8 cm -2 For example, reducing the threaded dislocation density on the III-V semiconductor layer 15 from approximately 10-1 9 cm-2 Reduced to 1x10 8 cm -2 ~5x10 8 cm -2 For example, reducing the threaded dislocation density on the doped III-V semiconductor layer 16 from approximately 10-1 9 cm -2 Reduced to 1x10 8 cm -2 ~5x10 8 cm -2 .

[0055] Figure 3A , Figure 3B and Figure 3C The diagram illustrates several operations for manufacturing a semiconductor device according to certain embodiments of this invention.

[0056] Reference Figure 3A A substrate 10 is provided. Next, a semiconductor layer 11 is formed on the substrate 10. In some embodiments, the semiconductor layer 11 may be formed by, for example, metal-organic chemical vapor deposition (MOCVD), epitaxial growth, or other suitable deposition steps. The semiconductor layer 11 has a surface 111 in contact with the substrate 10 and a surface 112 opposite to the surface 111. The semiconductor layer 11 may include a plurality of layers with thicknesses between about 1 nm and about 100 nm. For example, the semiconductor layer 11 may include a plurality of layers with thicknesses between about 1 nm and about 50 nm. For example, the semiconductor layer 11 may include a top layer 11a. The thickness t1 of the top layer 11a may be between about 1 nm and about 100 nm, between about 1 nm and about 50 nm, or between about 1 nm and about 10 nm.

[0057] Reference Figure 3BAn undoped III-V semiconductor layer 12 is formed on the top layer 11a. In some embodiments, the undoped III-V semiconductor layer 12 can be formed by methods such as chemical vapor deposition (CVD), MOCVD, high-density plasma (HDP) CVD, physical vapor deposition (PVD), epitaxial growth, spin-on coating, and sputtering. The thickness of the undoped III-V semiconductor layer 12 can be indicated by "t2". The thickness t2 of the undoped III-V semiconductor layer 12 can be between about 0.01 μm and about 1 μm, that is, between about 10 nm and about 1000 nm.

[0058] Reference Figure 3C Doped III-V semiconductor layers 13, 14, and 15 are formed on an undoped III-V semiconductor layer 12. In some embodiments, the doped III-V semiconductor layer 13 may be deposited on the undoped III-V semiconductor layer 12. In some embodiments, the III-V semiconductor layer 14 may be deposited on the doped III-V semiconductor layer 13. In some embodiments, the III-V semiconductor layer 15 may be deposited on the III-V semiconductor layer 14.

[0059] Next, a structure such as can be formed on the III-V semiconductor layer 15. Figure 1 The substrate consists of a III-V group semiconductor layer 16 and a metal layer 17. Next, a passivation layer (such as...) can be formed using methods such as CVD, HDPCVD, spin coating, and sputtering. Figure 1 Passivation layers 18 and 19). In some embodiments, openings can be formed via one or more etching processes, and conductive material can be filled into the openings by deposition steps such as CVD, PVD, and electroplating to form source contacts and drain contacts (e.g., ...). Figure 1 Source contact 20 and drain contact 21). In some embodiments, a passivation layer may be formed as shown in the figure. Figure 1 Dielectric layers 22, 24, and 27. In some embodiments, dielectric layers 22, 24, and 27 can be deposited by methods such as CVD, HDPCVD, spin coating, sputtering, etc. The dielectric layer surfaces are then treated with chemical-mechanical planarization (CMP). In some embodiments, openings can be formed via one or more etching processes, and conductive material is filled into the openings through deposition steps such as CVD, PVD, and electroplating to form a conductor structure (e.g., Figure 1 The conductor structure 25). In some embodiments, it can be formed through processes such as photolithography and etching. Figure 1 Plates 23 and 26. The device obtained through the above process can be used with... Figure 1 It is similar to semiconductor device 1.

[0060] As used herein, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” “lower,” “left,” “right,” etc., may be used to describe the relationship between one component or feature and another component or feature as illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. It should be understood that when a component is referred to as “connected to” or “coupled to” another component, it may be directly connected to or coupled to said other component, or there may be an intermediate component.

[0061] As used herein, the terms “approximately,” “substantially,” “largely,” and “about” are used to describe and account for small variations. When used in conjunction with an event or situation, the terms can refer to a situation in which the event or situation has clearly occurred or is very close to occurring. As used herein with respect to a given value or range, the term “about” generally means within ±10%, ±5%, ±1%, or ±0.5% of the given value or range. A range may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise specified, all ranges disclosed herein include endpoints. The term “substantially coplanar” can refer to two surfaces located along the same plane within a few micrometers (μm), such as within 10 μm, 5 μm, 1 μm, or 0.5 μm. When referring to the same numerical value or characteristic, the term can refer to a value within ±10%, ±5%, ±1%, or ±0.5% of the average of said value.

[0062] The foregoing outlines several embodiments and detailed features of this disclosure. The embodiments described in this disclosure can readily serve as the basis for designing or modifying other processes and structures for performing the same or similar purposes and / or obtaining the same or similar advantages of the embodiments introduced herein. These equivalent constructions do not depart from the spirit and scope of this disclosure and various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized by comprising: Include: A semiconductor layer with upwardly extending dislocations; It is disposed on the semiconductor layer via a doped nitride semiconductor layer; An undoped III-V semiconductor layer is disposed between the semiconductor layer and the doped nitride semiconductor layer. The lattice density of the undoped III-V semiconductor layer is greater than that of the semiconductor layer. The undoped III-V semiconductor layer contacts the semiconductor layer to form a first interface. The dislocations extend from the semiconductor layer to the first interface and enter the undoped III-V semiconductor layer. The dislocations change their path direction at the first interface, and the angle of change of the path direction at the first interface is at least 30 degrees. A channel layer is disposed on the doped nitride semiconductor layer; as well as A barrier layer is disposed on the channel layer and in contact with the channel layer, and has a larger band gap than the channel layer.

2. The semiconductor device according to claim 1, wherein The change angle of the path direction of the dislocation at the first interface is 90 degrees.

3. The semiconductor device according to claim 1, wherein The dislocations, after changing their path direction, extend toward the side surface of the undoped III-V semiconductor layer.

4. The semiconductor device according to claim 1, characterized in that, The undoped III-V semiconductor layer has a first surface that contacts the semiconductor layer, and the undoped III-V semiconductor layer has a second surface that is opposite to the first surface and contacts the doped nitride semiconductor layer, wherein the dislocation density at the second surface is less than the dislocation density at the first surface.

5. The semiconductor device according to claim 4, characterized in that, The dislocations extend along the first surface of the undoped III-V semiconductor layer.

6. The semiconductor device according to claim 4, characterized in that, The second surface of the undoped III-V semiconductor layer contacts the doped nitride semiconductor layer to form a second interface, and the dislocation density at the first interface is less than the dislocation density at the second interface.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor layer comprises a multilayer structure consisting of two compounds stacked alternately.

8. The semiconductor device according to claim 7, characterized in that, The multilayer structure of the semiconductor layer includes a top layer, which is the layer closest to the undoped III-V semiconductor layer in the multilayer structure of the semiconductor layer, and the undoped III-V semiconductor layer is thicker than the top layer.

9. The semiconductor device according to claim 8, characterized in that, The top layer has a first thickness, and the undoped III-V semiconductor layer has a second thickness, wherein the first thickness is at least one order of magnitude smaller than the second thickness.

10. The semiconductor device according to claim 9, characterized in that, The first thickness is between 1 nm and 100 nm.

11. The semiconductor device according to claim 9, characterized in that, The second thickness is between 10 nm and 1000 nm.

12. The semiconductor device according to claim 8, characterized in that, The top layer has a different material than the undoped III-V semiconductor layer.

13. The semiconductor device according to claim 12, characterized in that, The top layer has a single material and a homogeneous concentration.

14. The semiconductor device according to claim 7, characterized in that, The interfaces between the layers of the multilayer structure of the semiconductor layer are observable.

15. The semiconductor device according to claim 1, characterized in that, The first interface is observable.

16. A method for manufacturing a semiconductor device, characterized in that, Include: A semiconductor layer is formed on a substrate, the semiconductor layer having a top layer; An undoped III-V semiconductor layer is formed on the semiconductor layer; A doped nitride semiconductor layer is formed on the undoped III-V semiconductor layer, wherein the lattice density of the undoped III-V semiconductor layer is greater than the lattice density of the semiconductor layer, and the lattice density of the undoped III-V semiconductor layer is greater than the lattice density of the doped nitride semiconductor layer. The undoped III-V semiconductor layer contacts the semiconductor layer to form a first interface, wherein dislocations extend from the semiconductor layer to the first interface and enter the undoped III-V semiconductor layer, and the dislocations change their path direction at the first interface, wherein the angle of change of the path direction at the first interface is at least 30 degrees. A channel layer is formed on the doped nitride semiconductor layer; as well as A barrier layer is formed on the channel layer and in contact with the channel layer, and has a larger band gap than the channel layer.

17. The manufacturing method according to claim 16, characterized in that, The change angle of the path direction of the dislocation at the first interface is 90 degrees.

18. The manufacturing method according to claim 16, characterized in that, The dislocations, after changing their path direction, extend toward the side surface of the undoped III-V semiconductor layer.

19. The manufacturing method according to claim 16, characterized in that, The undoped III-V semiconductor layer has a first surface that contacts the semiconductor layer, and the undoped III-V semiconductor layer has a second surface that is opposite to the first surface and contacts the doped nitride semiconductor layer, wherein the dislocation density at the second surface is less than the dislocation density at the first surface.

20. The manufacturing method according to claim 19, characterized in that, The dislocations extend along the first surface of the undoped III-V semiconductor layer.

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