Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: providing a substrate having a plurality of mutually separated fin structures thereon, the fin structures extending along a first direction; forming an initial first gate structure extending along the first direction on each of the fin structures; etching the initial first gate structure so that a top portion of the initial first gate structure is rounded; after etching the initial first gate structure, performing a surface treatment on the top portion and a sidewall connected to the top portion of the initial first gate structure by using an ion implantation process to form a first gate structure, and in a direction perpendicular to a surface of the substrate, a line width of the first gate structure continuously increases from the top portion to a bottom portion of the first gate structure. The performance and reliability of the formed semiconductor device are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the development of semiconductor manufacturing technology, a flash memory with faster access speed has been developed in the field of storage devices. The flash memory has the characteristics of multiple information storage, reading and erasing, and the stored information does not disappear after power off, so the flash memory has become a widely used non-volatile memory in personal computers and electronic devices. NAND flash memory is widely used in fields with high read / write requirements due to its large storage capacity and relatively high performance.

[0003] However, the performance and reliability of the existing semiconductor device still need to be improved. SUMMARY

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof to improve the performance and reliability of the formed semiconductor device.

[0005] To solve the above technical problems, an embodiment of the present application provides a semiconductor structure, comprising: a substrate, the substrate has a plurality of mutually separate fin structures on it, the fin structures extend along a first direction; a first gate structure located on each fin structure and extending along the first direction, the top of the first gate structure is rounded, in a direction perpendicular to the surface of the substrate, the line width of the first gate structure continuously increases from the top to the bottom of the first gate structure, the first gate structure is doped with a first ion and a second ion, and the conductive types of the first ion and the second ion are opposite.

[0006] Optionally, the first ion is an N-type ion, and the second ion is a P-type ion.

[0007] Optionally, the concentration range of the second ion in the first gate structure is 2E15 atoms / cm 3 ~ 5E15 atoms / cm 3 .

[0008] Optionally, further comprising: a dielectric film located on the surface of the first gate structure; a plurality of second gate structures located on the surface of the dielectric film, the extension direction of the second gate structure is perpendicular to the extension direction of the first gate structure.

[0009] Correspondingly, the application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually separated fin structures thereon, the fin structures extending along a first direction; forming an initial first gate structure extending along the first direction on each fin structure; etching the initial first gate structure, so that the top of the initial first gate structure is rounded; after etching the initial first gate structure, performing surface treatment on the top of the initial first gate structure and the sidewall connected with the top by using an ion implantation process, to form a first gate structure, and in a direction perpendicular to the surface of the substrate, the line width of the first gate structure continuously increases from the top to the bottom of the first gate structure.

[0010] Optionally, the parameters of the ion implantation process include: an implantation energy of 1 KeV-3 KeV; an implantation dose of 2E15 atoms / cm 3 ~5E15 atoms / cm 3 ; and an implantation angle of 35 degrees to 55 degrees.

[0011] Optionally, the initial first gate structure is doped with first ions, the ion implantation process implants second ions into the initial first gate structure, and the conductive types of the first ions and the second ions are opposite.

[0012] Optionally, the first ions are N-type ions, and the second ions are P-type ions.

[0013] Optionally, the method further comprises: before forming the initial first gate structure, forming a first dielectric layer on the surface of the substrate and the sidewall of the fin structure.

[0014] Optionally, the method of forming the initial first gate structure comprises: forming a first gate material layer on the top surface of the fin structure and the top surface of the first dielectric layer; forming a plurality of mutually separated first gate mask structures on the first gate material layer; etching the first gate material layer with the first gate mask structures as a mask until the surface of the first dielectric layer is exposed, to form the initial first gate structure.

[0015] Optionally, the method further comprises: after forming the initial first gate structure and before forming the first gate structure, forming a second dielectric layer on the surface of the first dielectric layer and part of the sidewall of the initial first gate structure.

[0016] Optionally, the method further comprises: after forming the first gate structure, forming a dielectric film on the surface of the first gate structure; and forming a plurality of second gate structures on the surface of the dielectric film, the extending direction of the second gate structures being perpendicular to the extending direction of the first gate structure.

[0017] Optionally, the dielectric film comprises a lower dielectric film, a middle dielectric film located on the surface of the lower dielectric film, and an upper dielectric film located on the surface of the middle dielectric film.

[0018] Optionally, the material of the lower dielectric film is oxide, the material of the middle dielectric film is nitride, and the material of the upper dielectric film is oxide.

[0019] Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:

[0020] In the method for forming a semiconductor structure provided by the technical scheme, after etching the initial first gate structure, the top of the initial first gate structure and the sidewall connected with the top are subjected to surface treatment by using an ion implantation process. Since the ion implantation process can cause material loss of the initial first gate structure while the loss amount caused by the loss is small, the control precision of the surface treatment is high, so that the morphology of the initial first gate structure can be fine-tuned by the surface treatment, thereby not only reducing the line width size of the top region of the initial first gate structure, but also accurately controlling the amount of the reduced line width size to reduce the influence of the reduced line width size on the performance of the first gate structure. On this basis, since the morphology of the initial first gate structure is fine-tuned and the line width size of the top region of the initial first gate structure is accurately reduced, the first gate structure with a line width continuously increasing from the top to the bottom is formed, so that the spacing between adjacent first gate structures continuously increases from the top to the bottom of the first gate structure, thereby making the material of the subsequent second gate structure more easily fill in the space between adjacent first gate structures, reducing the risk of forming a hole defect in the second gate structure around the middle or bottom of the first gate structure, and thereby improving the performance and reliability of the semiconductor device.

[0021] Further, since the ion implantation process implants second ions into the initial first gate structure, and the conductive types of the first ions and the second ions are opposite, the width of the depletion layer in the substrate can be increased by implanting the second ions, so that the electrical thickness of the semiconductor structure is increased to reduce the capacitance between the first gate structure and the subsequently formed dielectric film and the second gate structure, thereby reducing the pressure difference between the first gate structure and the substrate to increase the switching times of the semiconductor device, that is, to increase the service life of the semiconductor device. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figures 1-2 is a structure schematic diagram of each step of a method for forming a semiconductor structure;

[0023] Figures 3-10 is a cross-sectional structure schematic diagram of each step of a method for forming a semiconductor structure according to an embodiment of the application. DETAILED DESCRIPTION

[0024] As described in the background, the performance and reliability of the existing semiconductor device still need to be improved.

[0025] The performance and reliability of semiconductor devices still need to be improved.

[0026] It should be noted that the "surface" in the specification is used to describe the relative position relationship in space, and is not limited to whether it is in direct contact.

[0027] Figures 1-2 It is a structure schematic diagram of each step of a semiconductor structure forming method.

[0028] Please refer to Figure 1 , a substrate 100 is provided, which has a plurality of mutually separated fin structures 101 on the substrate 100; a dielectric layer 110 is formed on the surface of the substrate 100 and the sidewall surface of the fin structure 101; a first gate structure material layer 120 is formed on the top surface of the fin structure 101 and the surface of the dielectric layer 110; a plurality of mutually separated mask structures 130 are formed on the first gate structure material layer 120.

[0029] Please refer to Figure 2 , the first gate structure material layer 120 is etched with the mask structure 130 as a mask until the surface of the dielectric layer 110 is exposed, forming a first gate structure 121; a dielectric film (not shown) is formed on the surface of the dielectric layer 110 and the first gate structure 121; a plurality of second gate structures 140 are formed on the surface of the dielectric film, which span the first gate structure 121.

[0030] However, in the above embodiment, in the process of etching the first gate structure material layer 120 with the mask structure 130 as a mask, on the one hand, the top of the first gate structure 121 is protected by the mask structure 130, on the other hand, in the process of forming the higher first gate structure 121, in order to etch to the bottom of the first gate structure material layer 120 to form the first gate structure 121, the high-energy ions in the dry etching process are easy to hit back and forth on the sidewall of the middle part of the first gate structure 121, thus causing the sidewall of the formed first gate structure 121 to be recessed (as shown in region A of Figure 2 Figure 2 ​​

[0031] In order to solve the above problems, another method for forming a semiconductor structure is provided. In the method for forming a semiconductor structure, after forming a first gate structure 121, a side wall around the top of the first gate structure 121 is etched to reduce the size of the top region of the first gate structure 121 and improve the side wall recess. However, due to the low control accuracy of the etching process, it is difficult to control the etching amount during etching, and thus the size of the top region of the first gate structure 121 is easily reduced too much, making it difficult to fine-tune the morphology of the first gate structure 121, thereby affecting the performance of the first gate structure 121 and resulting in poor performance of the semiconductor device.

[0032] To solve the above technical problems, the embodiments of the present application provide a semiconductor structure and a method for forming the same. After etching the initial first gate structure, the top of the initial first gate structure and the side wall connected to the top are treated by ion implantation, so as to improve the morphology of the initial first gate structure and form a first gate structure. In the direction perpendicular to the surface of the substrate, the line width of the first gate structure continuously increases from the top to the bottom of the first gate structure, thereby improving the performance and reliability of the semiconductor structure.

[0033] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0034] Figures 3-10 is a schematic diagram of the cross-sectional structure of each step of the method for forming a semiconductor structure according to an embodiment of the present application.

[0035] Referring to Figure 3 , a substrate 200 is provided.

[0036] The material of the substrate 200 includes a semiconductor material.

[0037] In the present embodiment, the material of the substrate 200 is silicon.

[0038] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, InGaAsP, etc.

[0039] In the present embodiment, the substrate 200 has a plurality of mutually discrete fin structures 201, and the fin structures 201 extend along a first direction (not shown).

[0040] In this embodiment, in the process of forming the fin structure 201, an oxide layer 221 is also formed on the top surface of the fin structure 201.

[0041] Specifically, the method of forming the fin structure 201 and the oxide layer 221 includes: providing an initial substrate (not shown); forming an oxide film (not shown) on the initial substrate; patterning the initial substrate and the oxide film to form the substrate 200, a plurality of fin structures 201 on the substrate 200, and the oxide layer 221 on the top surface of the fin structure 201.

[0042] The material of the oxide layer 221 includes silicon oxide.

[0043] Please refer to Figure 4 A first dielectric layer 210 is formed on the surface of the substrate 200 and the sidewall of the fin structure 201.

[0044] Specifically, the method of forming the first dielectric layer 210 includes: forming an isolation trench 211 (as shown in Figure 3 ) in the initial substrate while patterning the initial substrate and the oxide film to form the fin structure 201; forming a first dielectric material layer (not shown) on the surface of the fin structure 201 in the isolation trench 211, the surface of the first dielectric material layer being higher than the top surface of the fin structure 201; planarizing or etching back the first dielectric material layer until the top surface of the oxide layer 221 is exposed to form the initial first dielectric layer 210.

[0045] The first dielectric layer 210 is an isolation structure for isolating adjacent fin structures 201 and isolating the substrate 200 from other devices.

[0046] In this embodiment, the process of forming the first dielectric material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a flowable chemical vapor deposition process, or a physical vapor deposition process.

[0047] In this embodiment, in the process of planarizing or etching back the first dielectric material layer, the planarization process includes a chemical mechanical polishing process, and the etching back process includes a dry etching process or a wet etching process.

[0048] In this embodiment, the material of the first dielectric layer 210 includes an oxide.

[0049] Next, after forming the first dielectric layer 210, an initial first gate structure extending in a first direction is formed on the fin structure 201. The specific steps of forming the initial first gate structure are described in detail in the following Figures 5-6 .

[0050] Please refer to Figure 5A first gate material layer 222 is formed on the top surface of the fin structure 201 and the top surface of the first dielectric layer 210.

[0051] The first gate material layer 222 is used to provide material for forming an initial first gate structure.

[0052] In this embodiment, the material of the first gate material layer includes polysilicon.

[0053] In this embodiment, the material of the first gate mask structure 230 includes silicon nitride.

[0054] The process of forming the first gate material layer 222 includes a chemical vapor deposition process or a physical vapor deposition process.

[0055] Please refer to Figure 6 The first gate material layer 222 is etched using the first gate mask structure 230 as a mask until the surface of the first dielectric layer 210 is exposed, thereby forming an initial first gate structure 220.

[0056] In this embodiment, the process of etching the first gate material layer 222 includes a dry etching process.

[0057] In the process of etching the first gate material layer 222 using the first gate mask structure 230 as a mask, the top of the initial first gate structure 220 is protected by the mask structure 230. At the same time, in order to etch to the bottom of the first gate material layer 222 to form the initial first gate structure 220, high-energy ions in the dry etching process are likely to hit back and forth on the sidewall of the middle part of the initial first gate structure 220. Therefore, the sidewall of the formed initial first gate structure 220 is recessed (as shown in the area A in Figure 6 , forming a structure with a wide top and a thin middle.

[0058] Please refer to Figure 7 After the initial first gate structure 220 is formed, a second dielectric layer 240 is formed on the surface of the first dielectric layer 210 and part of the sidewall of the initial first gate structure 220.

[0059] Specifically, the method of forming the second dielectric layer 240 includes: after forming the initial first gate structure 220, forming a second dielectric material layer (not shown) on the surface of the first dielectric layer 210 and the surface of the initial first gate structure 220, the surface of the second dielectric material layer being higher than the top surface of the initial first gate structure 220; planarizing or etching back the second dielectric material layer until the top surface of the initial first gate structure 220 is exposed, forming an initial second dielectric layer (not shown); after forming the initial second dielectric layer, etching the initial second dielectric layer until the second dielectric layer 240 is formed.

[0060] The second dielectric layer 240 exposes the sidewall of the initial first gate structure 220, and the top surface of the second dielectric layer 240 is lower than the sidewall.

[0061] In the embodiment, the process of forming the second dielectric material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process or a physical vapor deposition process.

[0062] In the embodiment, in the process of planarizing or etching back the second dielectric material layer, the planarization process includes a chemical mechanical polishing process, and the etching back process includes a dry etching process or a wet etching process.

[0063] In the embodiment, the first gate mask structure 230 is also removed in the process of planarizing or etching back the second dielectric material layer.

[0064] In the embodiment, the material of the second dielectric layer 240 includes an oxide.

[0065] Please refer to Figure 8 The initial first gate structure 220 is etched so that the top of the initial first gate structure 220 is rounded.

[0066] The purpose of etching the initial first gate structure 220 is to reduce the height of the initial first gate structure 220 by a small amount so that the height of the initial first gate structure 220 meets the design requirement, and to round the top of the initial first gate structure 220.

[0067] In the embodiment, the process of etching the initial first gate structure 220 includes a dry etching process.

[0068] Please refer to Figure 9 After etching the initial first gate structure 220, an ion implantation process is used to perform surface treatment on the top of the initial first gate structure 220 and the sidewall connected to the top, forming the first gate structure 224, and in the direction perpendicular to the surface of the substrate 200, the line width of the first gate structure 224 continuously increases from the top to the bottom of the first gate structure 224.

[0069] Since the ion implantation process can cause material loss to the initial first gate structure 220 while the loss amount generated by the loss is small, the control accuracy of the surface treatment is high, so that through the surface treatment, the morphology of the initial first gate structure 220 can be fine-tuned, thereby not only reducing the line width size of the top region of the initial first gate structure 220, but also accurately controlling the amount of reduced line width size to reduce the impact of reduced line width size on the performance of the first gate structure 224. On this basis, since the morphology of the initial first gate structure 220 is fine-tuned and the line width size of the top region of the initial first gate structure 220 is accurately reduced, the first gate structure 224 with continuously increasing line width from the top to the bottom of the first gate structure 224 is formed, therefore, the spacing between adjacent first gate structures 224 continuously increases from the top to the bottom of the first gate structure 224, thereby the material of the subsequent second gate structure is more easily filled between adjacent first gate structures 224, reducing the risk of forming a hole defect in the second gate structure around the middle or bottom of the first gate structure 224, thereby improving the performance and reliability of the semiconductor device.

[0070] In the embodiment, the initial first gate structure 220 is doped with first ions, the ion implantation process implants second ions into the initial first gate structure 220, and the first ions and the second ions are opposite in conductivity type.

[0071] Since the ion implantation process implants second ions into the initial first gate structure 220, and the first ions and the second ions are opposite in conductivity type, by implanting the second ions, the depletion layer width in the substrate 200 can be increased, so that the electrical thickness of the semiconductor structure is increased, to reduce the capacitance between the first gate structure 224 and the subsequently formed dielectric film and the second gate structure, thereby reducing the pressure difference between the first gate structure 224 and the substrate 220, to increase the switching times of the semiconductor device, that is, to increase the service life of the semiconductor device.

[0072] In the embodiment, the first ions are N-type ions, and the second ions are P-type ions.

[0073] In other embodiments, the first ions are P-type ions, and the second ions are N-type ions.

[0074] In the embodiment, the concentration range of the second ions in the first gate structure 224 is 2E15 atoms / cm 3 ~ 5E15 atoms / cm 3 .

[0075] The concentration of the second ions is too large, which causes the depletion layer to disappear, resulting in the failure of the device. The concentration of the second ions is too small, which causes the increased width of the depletion layer to be small, thereby the number of switching times of the semiconductor device is limited to increase, which is not conducive to better growth of the service life of the semiconductor device. Therefore, the appropriate concentration range of the second ions, i.e., the concentration range of the second ions is 2E15 atoms / cm 3 ~ 5E15 atoms / cm 3 , can increase the width of the depletion layer while avoiding the disappearance of the depletion layer, thereby better increasing the number of switching times of the semiconductor device to better growth of the service life of the semiconductor device.

[0076] In this embodiment, the material of the first gate structure 224 includes polycrystalline silicon or amorphous silicon.

[0077] In this embodiment, the process parameters of the ion implantation process include: an implantation energy of 1 KeV ~ 3 KeV; an implantation dose of 2E15 atoms / cm 3 ~ 5E15 atoms / cm 3 ; and an implantation angle of 35 degrees to 55 degrees. The implantation angle is the angle between the normal direction perpendicular to the surface of the substrate and the direction of the implantation.

[0078] On the one hand, by controlling the implantation energy, the implantation dose and the implantation angle, i.e., within the range of the implantation energy, the implantation dose and the implantation angle, the topography adjustment of the initial first gate structure 220 can be better controlled to improve the topography of the first gate structure 224. On the other hand, the control of the implantation dose range, i.e., the selection of the implantation dose range, helps to realize the control of the concentration of the second ions in the first gate structure 224, thereby better growth of the service life of the semiconductor device.

[0079] Please refer to Figure 10 , after forming the first gate structure, a dielectric film 250 (not shown) is formed on the surface of the first gate structure; and a plurality of second gate structures 260 are formed on the surface of the dielectric film 250, the extension direction of the second gate structures 260 being perpendicular to the extension direction of the first gate structure 224.

[0080] In this embodiment, the dielectric film 250 includes a lower dielectric film (not shown), a middle dielectric film (not shown) on the surface of the lower dielectric film, and an upper dielectric film (not shown) on the surface of the middle dielectric film.

[0081] Specifically, the material of the lower dielectric film is oxide, the material of the middle dielectric film is nitride, and the material of the upper dielectric film is oxide.

[0082] Specifically, the dielectric film 250 is also located on the surface of the second dielectric layer 240.

[0083] In the embodiment, the method for forming the second gate structure 260 comprises: forming a second gate material layer (not shown) on the surface of the dielectric film 250; patterning the second gate material layer to form a plurality of second gate structures 260.

[0084] In the embodiment, the material of the second gate structure 260 comprises polycrystalline silicon or amorphous silicon.

[0085] Correspondingly, the embodiment of the present application further provides a semiconductor structure formed by the above method, which will be described in detail with reference to Figure 10 , comprising: a substrate 200, wherein a plurality of mutually separated fin structures 201 are arranged on the substrate 200 and extend along a first direction; and a first gate structure 224 arranged on each fin structure 201 and extending along the first direction, wherein the top of the first gate structure 224 is rounded, the line width of the first gate structure 224 continuously increases from the top to the bottom of the first gate structure 224 in the direction perpendicular to the surface of the substrate 200, the first gate structure 224 is doped with a first ion and a second ion, and the conductive types of the first ion and the second ion are opposite.

[0086] In the embodiment, the first ion is an N-type ion and the second ion is a P-type ion.

[0087] In other embodiments, the first ion is a P-type ion and the second ion is an N-type ion.

[0088] In the embodiment, the concentration of the second ion in the first gate structure 224 ranges from 2E15 atoms / cm 3 to 5E15 atoms / cm 3 .

[0089] The material of the substrate 200 comprises a semiconductor material.

[0090] In the embodiment, the material of the substrate 200 is silicon.

[0091] In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0092] In the embodiment, the material of the first gate structure 224 comprises polycrystalline silicon or amorphous silicon.

[0093] In this embodiment, the semiconductor structure further comprises an oxide layer 221 between the top surface of the fin structure 201 and the first gate structure 224.

[0094] The material of the oxide layer 221 comprises silicon oxide.

[0095] In this embodiment, the semiconductor structure further comprises a first dielectric layer 210 between the surface of the substrate 200 and the sidewall of the fin structure 201.

[0096] The first dielectric layer 210 is an isolation structure for isolating adjacent fin structures 201 and the substrate 200 from other devices.

[0097] In this embodiment, the material of the first dielectric layer 210 comprises oxide.

[0098] In this embodiment, the semiconductor structure further comprises a dielectric film 250 on the surface of the first gate structure 224, and a plurality of second gate structures 260 on the surface of the dielectric film 250, the extension direction of the second gate structures 260 being perpendicular to the extension direction of the first gate structure 224.

[0099] In this embodiment, the dielectric film 250 comprises a lower dielectric film (not shown), a middle dielectric film (not shown) on the surface of the lower dielectric film, and an upper dielectric film (not shown) on the surface of the middle dielectric film.

[0100] Specifically, the material of the lower dielectric film is oxide, the material of the middle dielectric film is nitride, and the material of the upper dielectric film is oxide.

[0101] In this embodiment, the material of the second gate structure 260 comprises polysilicon or amorphous silicon.

[0102] In this embodiment, the semiconductor structure further comprises a second dielectric layer 240 on the surface of the first dielectric layer 210 and part of the sidewall of the first gate structure 224.

[0103] In this embodiment, the material of the second dielectric layer 240 comprises oxide.

[0104] Specifically, the dielectric film 250 is also on the surface of the second dielectric layer 240.

[0105] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the scope of protection of the present application should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate having a plurality of mutually discrete fin structures extending along a first direction; A first gate structure located on each fin structure and extending along a first direction, the top of the first gate structure having rounded corners, and the linewidth of the first gate structure continuously increasing from the top to the bottom in a direction perpendicular to the substrate surface, the first gate structure being doped with a first ion and a second ion, and the first ion and the second ion having opposite conductivity types; A dielectric film located on the surface of the first gate structure; a plurality of second gate structures located on the surface of the dielectric film, wherein the extending direction of the second gate structures is perpendicular to the extending direction of the first gate structure; The morphology of the first gate structure is formed by implanting second ions into the top of the initial first gate structure doped with first ions and the sidewall connected to the top, thereby fine-tuning the morphology of the initial first gate structure; the top of the initial first gate structure has rounded corners and the sidewall has a recess.

2. The semiconductor structure as described in claim 1, characterized in that, The first ion is an N-type ion, and the second ion is a P-type ion.

3. The semiconductor structure as described in claim 2, characterized in that, The concentration range of the second ion in the first gate structure is 2E15 atoms / cm³. 3 ~5E15atoms / cm 3 .

4. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided having a plurality of mutually discrete fin structures extending along a first direction; An initial first gate structure extending along a first direction is formed on each fin structure; the initial first gate structure is doped with a first ion; The initial first gate structure is etched so that the top of the initial first gate structure has rounded corners and the sidewalls have recesses. After etching the initial first gate structure, the top of the initial first gate structure and the sidewall connected to the top are surface treated by ion implantation to form the first gate structure. In addition, the linewidth of the first gate structure increases continuously from the top to the bottom of the first gate structure in the direction perpendicular to the substrate surface. After forming the first gate structure, a dielectric film is formed on the surface of the first gate structure; a plurality of second gate structures are formed on the surface of the dielectric film, wherein the extending direction of the second gate structures is perpendicular to the extending direction of the first gate structure. The ion implantation process is used to implant second ions into the top of the initial first gate structure and the sidewall connected to the top, so as to fine-tune the morphology of the initial first gate structure; the conductivity type of the second ion is opposite to that of the first ion.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The parameters of the ion implantation process include: implantation energy of 1 keV to 3 keV; implantation dose of 2E15 atoms / cm. 3 ~5E15atoms / cm 3 The injection angle is 35 to 55 degrees.

6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The first ion is an N-type ion, and the second ion is a P-type ion.

7. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: Before forming the initial first gate structure, a first dielectric layer is formed on the substrate surface and the sidewalls of the fin structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the initial first gate structure includes: forming a first gate material layer on the top surface of the fin structure and the top surface of the first dielectric layer; forming a plurality of mutually discrete first gate mask structures on the first gate material layer; using the first gate mask structures as masks, etching the first gate material layer until the surface of the first dielectric layer is exposed, thereby forming the initial first gate structure.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, Also includes: After the initial first gate structure is formed, and before the first gate structure is formed, a second dielectric layer is formed on the surface of the first dielectric layer and on a portion of the sidewalls of the initial first gate structure.

10. The method for forming a semiconductor structure as described in claim 4, characterized in that, The dielectric membrane includes a lower dielectric membrane, a middle dielectric membrane located on the surface of the lower dielectric membrane, and an upper dielectric membrane located on the surface of the middle dielectric membrane.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The lower dielectric film is made of oxide, the middle dielectric film is made of nitride, and the upper dielectric film is made of oxide.

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