Metal oxide thin film transistor device, manufacturing method thereof, and display panel

Abstract

The present application provides a metal oxide thin film transistor device, a method for manufacturing the same, and a display panel, relating to the field of semiconductor technology. The present application sequentially prepares a silicon nitride layer, a gate, a gate dielectric layer covering the gate, and a metal oxide layer covering at least the gate dielectric layer on one side of a substrate, so that the portion of the metal oxide layer in contact with the silicon nitride layer is conductively doped with hydrogen or fluorine contained in the silicon nitride layer to form a source region and a drain region. The portion of the metal oxide layer in contact with the gate dielectric layer and not conductively doped is a semiconductor region connecting the source region and the drain region, and the gate, source region, and drain region are located on the same surface of the silicon nitride layer. Therefore, the thin film transistor device can achieve low parasitic capacitance and a high upper limit of operating frequency through an extremely simple self-aligned bottom gate structure, and has the characteristics of a simple manufacturing process, and can be used to manufacture a display panel with high image display quality at low cost.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a metal oxide thin film transistor device, a manufacturing method thereof, and a display panel. Background Art

[0002] With the continuous development of science and technology, metal oxide thin film transistors (TFTs) using metal oxides (for example, amorphous indium gallium zinc oxide (a-IGZO), indium tin zinc oxide (ITZO) or rare earth-doped indium zinc oxide (Ln-IZO)) as channel materials have been widely used in display panels due to their high mobility, extremely small off-state current, large-area uniform preparation, good stability and compatibility with low-temperature processes. They are used to construct switching elements of the display panel's driving pixel units.

[0003] For metal oxide thin film transistors, the overlapping area between the source / drain and the gate is positively correlated with the parasitic capacitance of the metal oxide thin film transistor. The larger the parasitic capacitance of the metal oxide thin film transistor, the more likely it is to affect the image display quality of large-size display panels that use this metal oxide thin film transistor on a large area.

[0004] At present, the metal oxide thin film transistors circulating on the market usually cannot effectively maintain a balance in terms of the size of parasitic capacitance and the complexity of transistor preparation. The preparation of metal oxide thin film transistors with small parasitic capacitance often requires a more complex process, resulting in a higher preparation cost of the display panel using the metal oxide thin film transistor backplane. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a metal oxide thin film transistor device, a manufacturing method and a display panel, which can effectively reduce the parasitic capacitance of the transistor, increase the upper limit of the operating frequency of the transistor, and have the characteristics of a simple preparation process, thereby reducing the preparation cost required for preparing a display panel with high image display quality.

[0006] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0007] In a first aspect, the present application provides a metal oxide thin film transistor device, the thin film transistor device comprising:

[0008] substrate;

[0009] a silicon nitride layer disposed on the substrate;

[0010] a gate disposed on a side of the silicon nitride layer away from the substrate;

[0011] a gate dielectric layer covering an outer surface of the gate that is not in contact with the silicon nitride layer;

[0012] A metal oxide layer at least covering the outer surface of the gate dielectric layer that is not in contact with the silicon nitride layer; the metal oxide layer includes a source region, a semiconductor region and a drain region, the source region and the drain region are respectively located on both sides of the semiconductor region and are interconnected with the semiconductor region, wherein the source region and the drain region are both formed by diffused doping of hydrogen or fluorine contained in the silicon nitride layer in contact with the metal oxide layer.

[0013] In an optional embodiment, the thin film transistor device further includes:

[0014] A first routing layer and a second routing layer are arranged on a side of the silicon nitride layer away from the substrate, wherein the first routing layer and the second routing layer are respectively located on both sides of the semiconductor region, the source region is electrically connected to the first routing layer, and the drain region is electrically connected to the second routing layer.

[0015] In an optional embodiment, the thin film transistor device further includes:

[0016] A passivation layer is provided on a side of the metal oxide layer away from the substrate, wherein the passivation layer covers an outer surface of the semiconductor region away from the gate.

[0017] In an optional embodiment, the first wiring layer partially covers the source region, and the second wiring layer partially covers the drain region;

[0018] The passivation layer further covers the first routing layer, an outer surface of the source region not covered by the first routing layer, the second routing layer, and an outer surface of the drain region not covered by the second routing layer.

[0019] In an optional embodiment, the passivation layer also covers the source region and the drain region;

[0020] A first via hole is formed in a first region of the passivation layer that overlaps with a projection position of the source region, and the first wiring layer is connected to the source region through the first via hole;

[0021] A second via hole is formed in a second region of the passivation layer that overlaps with a projection position of the drain region, and the second wiring layer is overlapped with the drain region through the second via hole.

[0022] In a second aspect, the present application provides a method for manufacturing a metal oxide thin film transistor device, the manufacturing method comprising:

[0023] providing a substrate;

[0024] Depositing a silicon nitrogen layer containing hydrogen or fluorine on one side of the substrate;

[0025] forming a gate on a side of the silicon nitride layer away from the substrate;

[0026] forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate, wherein the gate dielectric layer covers an outer surface of the gate that is not in contact with the silicon nitride layer;

[0027] Depositing a metal oxide semiconductor layer on a side of the silicon nitride layer away from the substrate, wherein the metal oxide semiconductor layer covers an outer surface of the gate dielectric layer not in contact with the silicon nitride layer and an outer surface of the silicon nitride layer away from the substrate;

[0028] The metal oxide semiconductor layer is annealed to make a portion of the metal oxide semiconductor layer in direct contact with the silicon nitride layer conductive by diffusion doping of hydrogen or fluorine contained in the silicon nitride layer, thereby obtaining a metal oxide layer including a source region, a semiconductor region, and a drain region, wherein the source region and the drain region are respectively located on both sides of the semiconductor region and are interconnected with the semiconductor region, the source region and the drain region both belong to the conductive portion of the metal oxide semiconductor layer, and the semiconductor region is the non-conductive portion of the metal oxide semiconductor layer.

[0029] In an optional embodiment, the step of forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate includes:

[0030] forming the gate dielectric layer by growing it on the outer surface of the gate that is not in contact with the silicon nitride layer based on an anodic oxidation method;

[0031] Alternatively, the step of forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate includes:

[0032] preparing a gate dielectric precursor film on a side of the silicon nitride layer away from the substrate, wherein the gate dielectric precursor film covers an outer surface of the gate that is not in contact with the silicon nitride layer and an outer surface of the silicon nitride layer away from the substrate;

[0033] Dehydrating and curing the gate dielectric precursor film region directly in contact with the gate electrode based on an anodic oxidation induction method;

[0034] The undehydrated and uncured film region of the gate dielectric precursor film is removed by etching to form the gate dielectric layer.

[0035] In an optional embodiment, the manufacturing method further includes:

[0036] Depositing a wiring precursor layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is prepared, wherein the wiring precursor layer covers the metal oxide layer;

[0037] Etching and removing the routing region in the routing precursor layer that is in direct contact with the semiconductor region of the metal oxide layer to obtain a first routing layer and a second routing layer, wherein the first routing layer and the second routing layer are respectively located on both sides of the semiconductor region, the first routing layer covers a portion of the source region, and the second routing layer covers a portion of the drain region;

[0038] A passivation layer is deposited on the outer surface of the thin film transistor device away from the substrate after the first wiring layer and the second wiring layer are prepared.

[0039] In an optional embodiment, the manufacturing method further includes:

[0040] Depositing a passivation layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is formed, wherein the passivation layer covers the metal oxide layer;

[0041] A hole is opened in a first region of the passivation layer that overlaps with a projected position of the source region to obtain a first via hole connected to the source region, and a hole is opened in a second region of the passivation layer that overlaps with a projected position of the drain region to obtain a second via hole connected to the drain region;

[0042] A first wiring layer overlapping the source region through the first via hole and a second wiring layer overlapping the drain region through the second via hole are formed on the outer surface of the passivation layer away from the substrate.

[0043] In a third aspect, the present application provides a display panel, which includes a pixel unit array and a plurality of metal oxide thin film transistor devices described in any one of the aforementioned embodiments, wherein the plurality of metal oxide thin film transistor devices cooperate with each other to form a switch array for driving the pixel unit array.

[0044] In this case, the beneficial effects of the embodiments of the present application include the following:

[0045] The present application sequentially prepares a silicon nitride layer, a gate, a gate dielectric layer covering the gate, and a metal oxide layer covering at least the gate dielectric layer on one side of a substrate, and conducts the portion of the metal oxide layer in contact with the silicon nitride layer through diffusion doping with hydrogen or fluorine contained in the silicon nitride layer to form a source region and a drain region of the metal oxide layer. At this time, the portion of the metal oxide layer in contact with the gate dielectric layer and not conducted is the semiconductor region of the metal oxide layer connecting the source region and the drain region. The overlapping area of ​​the gate and the source / drain region on the same surface of the silicon nitride layer is significantly small, thereby effectively reducing the parasitic capacitance of the transistor and improving the upper limit of the operating frequency of the thin film transistor through an extremely simple self-aligned bottom gate structure. The metal oxide thin film transistor device has the characteristics of a simple preparation process and can be used to prepare a display panel with high image display quality at low cost.

[0046] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic diagram of the composition of a metal oxide thin film transistor provided by the prior art;

[0049] Figure 2 This is a schematic diagram of the composition of a metal oxide thin film transistor device provided in an embodiment of the present application;

[0050] Figure 3 The second schematic diagram of the composition of the metal oxide thin film transistor device provided in an embodiment of the present application;

[0051] Figure 4 The third schematic diagram of the composition of the metal oxide thin film transistor device provided in an embodiment of the present application;

[0052] Figure 5 The fourth schematic diagram of the composition of the metal oxide thin film transistor device provided in an embodiment of the present application;

[0053] Figure 6 The fifth schematic diagram of the composition of the metal oxide thin film transistor device provided in an embodiment of the present application;

[0054] Figure 7The sixth schematic diagram of the composition of the metal oxide thin film transistor device provided in an embodiment of the present application;

[0055] Figure 8 This is a schematic diagram of a process for manufacturing a metal oxide thin film transistor device according to an embodiment of the present application;

[0056] Figure 9 One of the manufacturing flow charts of the metal oxide thin film transistor device provided in the embodiment of the present application;

[0057] Figure 10 The second flowchart of the manufacturing process of the metal oxide thin film transistor device provided in the embodiment of the present application;

[0058] Figure 11 The second flowchart of the method for manufacturing a metal oxide thin film transistor device provided in an embodiment of the present application;

[0059] Figure 12 The third flowchart of the manufacturing process of the metal oxide thin film transistor device provided in the embodiment of the present application;

[0060] Figure 13 The third flow chart of the method for manufacturing a metal oxide thin film transistor device provided in an embodiment of the present application;

[0061] Figure 14 This is the fourth flowchart of the manufacturing process of the metal oxide thin film transistor device provided in the embodiment of the present application.

[0062] Icon: 10-metal oxide thin film transistor device; 11-substrate; 12-silicon nitride layer; 13-gate; 14-gate dielectric layer; 15-metal oxide layer; 151-semiconductor region; 152-source region; 153-drain region; 16-first routing layer; 17-second routing layer; 18-passivation layer; 191-first via; 192-second via; 21-metal oxide semiconductor layer; 22-routing precursor layer. DETAILED DESCRIPTION

[0063] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0064] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0065] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not require further definition or explanation in subsequent drawings.

[0066] In the description of this application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the application is usually placed when in use, or are the orientation or position relationship commonly understood by those skilled in the art. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0067] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "setting", "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be a connection between the internal parts of two elements.

[0068] In addition, relational terms such as the terms "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment comprising a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment comprising the elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0069] The applicant has found through research that the existing metal oxide thin film transistors are usually Figure 1The preparation was carried out according to the composition diagram shown:

[0070] Figure 1 The metal oxide thin film transistor shown in (a) is a bottom-gate non-self-aligned etch stop (ESL) TFT. An etch stop layer deposited on the active layer defines an effective active layer (i.e., the region of the active layer that overlaps with the projected position of the etch stop layer) in the active layer, which acts as a semiconductor channel. This prevents damage to the effective active layer during source / drain electrode deposition and patterning.

[0071] Figure 1 The metal oxide thin film transistor shown in (b) is a bottom-gate non-self-aligned back channel etched (BCE) TFT, which is deposited and patterned after the active layer is deposited and patterned, and then the source / drain electrode layer is deposited and patterned. At this time, since the back channel of the active layer is not protected by a barrier layer during the source / drain electrode deposition and patterning process, the back channel will produce some defects due to damage. Therefore, the electrical characteristics and stability of BCE TFT are generally inferior to those of ESL TFT. However, the preparation of BCE TFT does not require a mask for patterning the etching barrier layer in ESLTFT, which means that BCE TFT has lower preparation cost and preparation complexity. It is worth noting that the above-mentioned non-self-aligned ESL TFT and non-self-aligned BCE TFT often use metal as the gate. Therefore, when backlight enters from the bottom of the gate, the metal gate can block the light and protect the effective channel layer from light exposure, which is beneficial to the stability of the device. However, the source / drain of these two TFT structures have a large area overlap with the gate, resulting in ESL TFT and BCE The parasitic capacitance of TFT is large, which is not conducive to the improvement of TFT operating frequency. At the same time, large-size display panels will also experience mura due to the difference in parasitic capacitance between TFTs on the large-size TFT backplane.

[0072] Figure 1 The metal oxide thin film transistor shown in (c) is a self-aligned metal oxide TFT with a top-gate structure. By introducing a metal shielding layer below the active layer (i.e., the film layer where the conductor region and the semiconductor region are located), when backlight is irradiated from the glass surface toward the gate, the metal shielding layer blocks the backlight from reaching the active layer, thereby improving the stability of the device. However, it is worth noting that to avoid electrostatic breakdown between the metal shielding layer and the active layer, and to prevent the metal shielding layer from being in a floating state and affecting the TFT characteristics, it is usually necessary to electrically connect the metal shielding layer to the source electrode. This results in a certain degree of overlap between the source and the gate electrode, which significantly increases the parasitic capacitance of the TFT and is not conducive to increasing the operating frequency of the TFT. At the same time, this TFT structure requires a mask for patterning the metal shielding layer, and the manufacturing cost and complexity of the specific TFT manufacturing process are significantly high.

[0073] Figure 1 The metal oxide thin film transistor shown in (d) is a self-aligned metal oxide TFT with a bottom gate structure. After the passivation layer is deposited, a shielding layer needs to be deposited and patterned using the shielding effect of the gate electrode. An opening with the same width as the gate is formed on the shielding layer. The opening provides a channel for oxygen to diffuse into the metal conductor layer below the opening during the subsequent thermal annealing process, thereby converting the metal conductor area directly below the opening from a conductor to a semiconductor. At this time, the area of ​​overlap between the source / drain and the gate is small, and the corresponding parasitic capacitance is small. However, it is worth noting that this self-aligned TFT is relatively Figure 1 The conventional TFT shown in (a) significantly increases process complexity, requires a higher annealing temperature (≥400°C), and requires a specialized gas, oxygen, for semiconductorization, resulting in higher device fabrication costs and overall fabrication complexity.

[0074] Figure 1 The metal oxide thin film transistor shown in (e) is a self-aligned ESL TFT with a bottom-gate structure. It requires the use of a self-aligned etch barrier layer to define a metal oxide film with the same width as the gate as a semiconductor channel region. The area of ​​the metal oxide film that is in direct contact with the nitrogen silicon layer rich in hydrogen or fluorine elements will become a conductor under the action of hydrogen / fluorine diffusion doping. As the source / drain electrode of the TFT, the overlapping area between the source / drain electrode and the gate at the self-aligned ESL TFT is small, and has a higher upper limit on the operating frequency, but the TFT has a high preparation complexity and preparation cost.

[0075] Therefore, in essence, the current preparation of metal oxide thin film transistors with smaller parasitic capacitance often requires more complex process steps, resulting in higher preparation costs for the corresponding thin film transistor backplanes.

[0076] In this case, the applicant provides a metal oxide thin film transistor device, a manufacturing method thereof and a display panel through the embodiments of the present application, which effectively reduces the parasitic capacitance of the transistor and increases the upper limit of the operating frequency of the transistor, while effectively reducing the complexity of thin film transistor preparation, thereby reducing the cost of thin film transistor backplane preparation while meeting the high display quality requirements of the display panel.

[0077] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0078] Please refer to the combination Figure 2 and Figure 3 ,in Figure 2 This is one of the schematic diagrams of the composition of the metal oxide thin film transistor device 10 provided in an embodiment of the present application. Figure 3This is the second schematic diagram of the composition of the metal oxide thin film transistor device 10 provided in an embodiment of the present application. In this embodiment of the present application, the overlapping area between the source / drain and gate electrodes of the metal oxide thin film transistor device 10 is small, thereby ensuring that the metal oxide thin film transistor device 10 has extremely small parasitic capacitance and a high upper limit of operating frequency. At the same time, the metal oxide thin film transistor device 10 has a simple structure and a simple manufacturing process. When the metal oxide thin film transistor device 10 is manufactured over a large area, there is no problem of significant differences in transistor parasitic capacitance. Therefore, a thin film transistor backplane using the metal oxide thin film transistor device 10 can be manufactured at low cost, ensuring that large-scale display panels using the thin film transistor backplane have high image display quality.

[0079] In this embodiment, the metal oxide thin film transistor device 10 may include a substrate 11 and a silicon nitride layer 12, a gate 13, a gate dielectric layer 14 covering the gate 13, and a metal oxide layer 15 covering at least the gate dielectric layer 14, which are sequentially prepared on one side of the substrate 11. The metal oxide layer 15 is in contact with the outer surface portion of the silicon nitride layer 12 away from the substrate 11. The portion of the metal oxide layer 15 in contact with the silicon nitride layer 12 is conductively doped by the diffusion of hydrogen or fluorine contained in the silicon nitride layer 12 to form a source region 152 and a drain region 153 included in the metal oxide layer 15. At this time, the portion of the metal oxide layer 15 that is in direct contact with the gate dielectric layer 14 and is not conductively doped by the silicon nitride layer 12 is the semiconductor region 151 included in the metal oxide layer 15 that connects the source region 152 and the drain region 153.

[0080] In this case, the source region 152 and the drain region 153 are respectively located on both sides of the semiconductor region 151 , and the gate 13 is within the projection coverage of the semiconductor region 151 . The semiconductor region 151 represents the channel region of the gate 13 .

[0081] The gate 13, the source region 152, and the drain region 153 are located on the same outer surface of the silicon nitride layer 12. The gate dielectric layer 14 covering the gate 13 separates the gate 13, the source region 152, and the drain region 153, thereby ensuring a small overlap area between the source / drain and the gate. Therefore, the metal oxide thin film transistor device 10 has a small parasitic capacitance and a high upper limit on the operating frequency.

[0082] Therefore, the above-mentioned metal oxide thin film transistor device 10 can effectively reduce the device parasitic capacitance through an extremely simple self-aligned bottom gate structure, effectively reduce the complexity of thin film transistor preparation, improve the problem of obvious parasitic capacitance differences when transistors are prepared over a large area, and improve the image display quality of large-size display panels using thin film transistor backplanes using the metal oxide thin film transistor device 10.

[0083] In this embodiment, the substrate 11 can be a rigid substrate such as glass or silicon, or a flexible polymer substrate such as polyimide or polyethylene naphthalate. It is understood that substrates for metal oxide thin film transistor devices include but are not limited to the aforementioned examples, and any material that can serve as a substrate for a metal oxide thin film transistor device falls within the scope of protection of this application.

[0084] In this embodiment, the silicon nitride layer 12 is provided on one side surface of the substrate 11, and can be formed by depositing on one side surface of the substrate 11 by adopting PECVD (Plasma Enhanced Chemical Vapor Deposition) method. The material of the silicon nitride layer 12 is a silicon nitride substance rich in hydrogen or fluorine, and the thickness of the silicon nitride layer 12 is in the range of 10nm to 1000nm. The silicon nitride layer 12 can isolate water and oxygen when the substrate 11 is prepared by organic materials, and can also provide a flattened surface for the gate 13 prepared subsequently, the gate dielectric layer 14 covering the gate 13, and the metal oxide layer 15 covering at least the gate dielectric layer 14. In addition, the silicon nitride layer 12 is used to conduct the semiconductor material in contact with itself.

[0085] In this embodiment, the gate 13 is disposed on a surface of the silicon nitride layer 12 away from the substrate 11. A gate electrode film layer can be deposited on the outer surface of the silicon nitride layer 12 away from the substrate 11 by sputtering, and then the deposited gate electrode film layer is patterned by photolithography to form the gate 13. The gate 13 is made of metal, which can be, but is not limited to, any one or more combinations of metal materials such as aluminum (Al), copper (Cu), molybdenum (Mo), tantalum (Ta), hafnium (Hf), and chromium (Cr).

[0086] In this embodiment, the gate dielectric layer 14 is disposed on a side of the gate 13 away from the silicon nitride layer 12 and covers the outer surface of the gate 13 that is not in contact with the silicon nitride layer 12 to prevent the gate 13 from directly contacting the subsequently fabricated source region 152 and drain region 153 and causing a short circuit. The gate dielectric layer 14 can be formed of an insulating oxide material such as silicon oxide, aluminum oxide, hafnium oxide, or zirconium oxide.

[0087] In one implementation of this embodiment, the gate dielectric layer 14 can be directly grown on the outer surface of the gate 13 that is not in contact with the silicon nitride layer 12 by an anodic oxidation method. In this case, the gate dielectric layer 14 can have a film thickness ranging from 5 nm to 500 nm.

[0088] In another implementation of this embodiment, the gate dielectric layer 14 can also be prepared by spin coating, scraping or spraying to form a gate dielectric precursor film on the side surface of the silicon nitride layer 12 away from the substrate 11, so that the gate dielectric precursor film covers the outer surface of the gate 13 that is not in contact with the silicon nitride layer 12 and the outer surface of the silicon nitride layer 12 away from the substrate 11 and not blocked by the gate 13, and then the film area of ​​the gate dielectric precursor film that is in direct contact with the gate 13 (that is, the film area covering the gate 13) is dehydrated and solidified based on the anodic oxidation induction method, and the film area of ​​the gate dielectric precursor film that is not dehydrated and solidified is etched away by a wet etching process to form the gate dielectric layer 14. At this time, the film thickness of the gate dielectric layer 14 can range from 10nm to 1000nm.

[0089] Among them, the gate 13 can be connected to the positive pole of the power supply as an anode, and the Pt, Fe or other metal electrode can be connected to the negative pole of the power supply as a cathode, and then the gate 13 and the cathode covered by the gate dielectric precursor film are immersed in an electrolyte solution (ammonium tartrate solution can be used) and energized to perform anodization-induced dehydration and curing on the film area of ​​the gate dielectric precursor film covering the gate 13.

[0090] In this embodiment, the metal oxide layer 15 covers the outer surface of the gate dielectric layer 14 that is not in contact with the silicon nitride layer 12, and at least partially covers the outer surface of the silicon nitride layer 12 that is not blocked by the gate 13 and the gate dielectric layer 14. The source region 152 and the drain region 153 included in the metal oxide layer 15 are the portions of the metal oxide layer 15 that are in direct contact with the silicon nitride layer 12, and the semiconductor region 151 included in the metal oxide layer 15 is the portion of the metal oxide layer 15 that is in contact only with the gate dielectric layer 14.

[0091] A metal oxide semiconductor layer can be deposited on the surface of the silicon nitride layer 12 away from the substrate 11. The metal oxide semiconductor layer covers the outer surface of the gate dielectric layer 14 not in contact with the silicon nitride layer 12 and the outer surface of the silicon nitride layer 12 away from the substrate 11. The metal oxide semiconductor layer can then be annealed at 100° C. to 500° C. to allow the local area of ​​the metal oxide semiconductor layer in direct contact with the silicon nitride layer 12 to become conductive due to the diffusion doping of hydrogen or fluorine contained in the silicon nitride layer 12, thereby forming conductive regions that can serve as the source region 152 and the drain region 153. The non-conductive regions of the metal oxide semiconductor layer can directly serve as the semiconductor region 151 of the metal oxide layer 15. The semiconductor region 151 directly separates the conductive region into two parts, and the semiconductor region 151 connects the two separated conductive regions together to form the metal oxide layer 15.

[0092] The metal oxide semiconductor material used to prepare the metal oxide layer 15 may be, but is not limited to, amorphous indium gallium zinc oxide (a-IGZO), indium tin zinc oxide (ITZO) or rare earth doped indium zinc oxide (Ln-IZO); the thickness of the metal oxide semiconductor layer is in the range of 10 nm to 1000 nm.

[0093] In one implementation of this embodiment, the metal oxide layer 15 partially covers the outer surface of the silicon nitride layer 12 that is not blocked by the gate 13 and the gate dielectric layer 14. At this time, the specific structure of the metal oxide thin film transistor device 10 is as follows: Figure 2 As shown, it is necessary to perform photolithographic patterning on the basis of obtaining the conductive region of the metal oxide semiconductor layer to form Figure 2 The source region 152 and the drain region 153 shown cover a portion of the outer surface of the silicon nitride layer 12 away from the substrate 11 .

[0094] In another embodiment of the present invention, the metal oxide layer 15 completely covers the outer surface of the silicon nitride layer 12 that is not blocked by the gate 13 and the gate dielectric layer 14. In this case, the specific structure of the metal oxide thin film transistor device 10 is as follows: Figure 3 As shown, the two conductive regions separated by the semiconductor region 151 can be used as the source region 152 and the drain region 153 respectively, thereby Figure 2 The metal oxide thin film transistor device 10 shown can effectively reduce one photolithography patterning operation, thereby further reducing the complexity and cost of transistor manufacturing.

[0095] In the embodiment of the present application, the metal oxide thin film transistor device 10 may further include a first wiring layer 16, a second wiring layer 17, and a passivation layer 18. The first wiring layer 16 and the second wiring layer 17 are respectively located on either side of the semiconductor region 151. The source region 152 is electrically connected to the first wiring layer 16, allowing the source region 152 to be connected to other external electronic devices through the first wiring layer 16. The drain region 153 is electrically connected to the second wiring layer 17, allowing the drain region 153 to be connected to other external electronic components through the second wiring layer 17. The passivation layer 18 is used to prevent the channel region of the metal oxide thin film transistor device 10 from being affected by water and oxygen, which may cause electrical instability.

[0096] In the embodiment of the present application, the first routing layer 16 and the second routing layer 17 are both disposed on the side of the silicon nitride layer 12 away from the substrate 11, and the passivation layer 18 is disposed on the side of the metal oxide layer 15 away from the substrate 11. The first routing layer 16 and the second routing layer 17 can be disposed side by side between the passivation layer 18 and the silicon nitride layer 12, and the first routing layer 16 and the second routing layer 17 can also be electrically connected to the metal oxide layer 15 with the passivation layer 18 interposed therebetween. The first routing layer 16 and the second routing layer 17 can be made of metal or transparent conductive metal oxide materials; the passivation layer 18 can be made of an oxide insulating material such as silicon oxide or aluminum oxide, or can be made of a silicon oxide / silicon nitride stacked material.

[0097] Optionally, please refer to Figure 4 and Figure 5 ,in Figure 4 This is the third schematic diagram of the composition of the metal oxide thin film transistor device 10 provided in an embodiment of the present application. Figure 5 This is the fourth schematic diagram of the composition of the metal oxide thin film transistor device 10 provided in the embodiment of the present application. In the embodiment of the present application, Figure 4 The metal oxide thin film transistor device 10 is shown in FIG. Figure 2 The transistor structure is obtained by first forming a first wiring layer 16 and a second wiring layer 17 on the outer surface away from the substrate 11 of the metal oxide thin film transistor device 10, and then forming a passivation layer 18. Figure 5 The metal oxide thin film transistor device 10 is shown in FIG. Figure 3 The transistor structure is obtained by first forming the first wiring layer 16 and the second wiring layer 17 on the outer surface away from the substrate 11 of the metal oxide thin film transistor device 10, and then forming the passivation layer 18. Figure 4 and Figure 5In the metal oxide thin film transistor device 10 shown, the first wiring layer 16 and the second wiring layer 17 are arranged side by side between the passivation layer 18 and the silicon nitride layer 12 .

[0098] At this time, you can Figure 2 or Figure 3 A wiring precursor layer is deposited on the outer surface of the metal oxide thin film transistor device 10 shown, away from the substrate 11, and the wiring precursor layer covers the metal oxide layer 15. The wiring area in the wiring precursor layer that is in direct contact with the semiconductor region 151 of the metal oxide layer 15 is then etched away to obtain a first wiring layer 16 and a second wiring layer 17 located on both sides of the semiconductor region 151. At this time, the first wiring layer 16 covers a portion of the source region 152, and the second wiring layer 17 covers a portion of the drain region 153, so as to realize the electrical connection between the source region 152 and the first wiring layer 16, and the electrical connection between the drain region 153 and the second wiring layer 17.

[0099] Then, a passivation layer 18 covering the first wiring layer 16, the second wiring layer 17 and the semiconductor region 151 can be deposited on the side of the metal oxide layer 15 away from the substrate 11, so as to obtain Figure 4 or Figure 5 The metal oxide thin film transistor device 10 shown. Figure 5 For the metal oxide thin film transistor device 10 shown in FIG, after depositing the wiring precursor layer, the metal oxide layer 15 and the wiring precursor layer can be directly patterned using a set of half-tone masks to form a pattern. Figure 5 The metal oxide thin film transistor device 10 is shown.

[0100] Optionally, please refer to Figure 6 and Figure 7 ,in Figure 6 This is the fifth schematic diagram of the composition of the metal oxide thin film transistor device 10 provided in the embodiment of the present application. Figure 7 This is the sixth schematic diagram of the composition of the metal oxide thin film transistor device 10 provided in the embodiment of the present application. In the embodiment of the present application, Figure 6 The metal oxide thin film transistor device 10 is shown in FIG. Figure 2 The transistor structure is obtained by first forming a passivation layer 18 on the outer surface of the metal oxide thin film transistor device 10 away from the substrate 11 and then forming a first wiring layer 16 and a second wiring layer 17. Figure 7 The metal oxide thin film transistor device 10 is shown in FIG. Figure 3The transistor structure is obtained by first forming a passivation layer 18 on the outer surface of the metal oxide thin film transistor device 10 away from the substrate 11, and then forming the first wiring layer 16 and the second wiring layer 17. Figure 6 and Figure 7 In the metal oxide thin film transistor device 10 shown, the first wiring layer 16 and the second wiring layer 17 are electrically connected to the metal oxide layer 15 via the passivation layer 18 .

[0101] At this time, you can Figure 2 or Figure 3 A passivation layer 18 is deposited on the outer surface of the metal oxide thin film transistor device 10 shown in the figure away from the substrate 11, and then a hole is opened in a first area of ​​the passivation layer 18 overlapping with the projection position of the source region 152 by dry etching to obtain a first via 191 connecting to the source region 152, and a hole is opened in a second area of ​​the passivation layer 18 overlapping with the projection position of the drain region 153 to obtain a second via 192 connecting to the drain region 153.

[0102] Next, a wiring precursor layer is deposited on the outer surface of the passivation layer 18 away from the substrate 11, and the wiring precursor layer is patterned by photolithography to obtain a first wiring layer 16 overlapping the source region 152 through the first via hole 191, and a second wiring layer 17 overlapping the drain region 153 through the second via hole 192, that is, Figure 6 or Figure 7 The metal oxide thin film transistor device 10 is shown.

[0103] Therefore, the above-mentioned various metal oxide thin film transistor devices 10 provided in the present application can reduce the overlapping area of ​​the source / drain and the gate through an extremely simple self-aligned bottom gate structure, thereby effectively reducing the parasitic capacitance of the transistor and increasing the upper limit of the operating frequency of the transistor. At the same time, it effectively reduces the complexity of transistor preparation, improves the problem of obvious parasitic capacitance differences when transistors are prepared over a large area, and improves the image display quality of the corresponding display panel.

[0104] In this application, to ensure that the metal oxide thin film transistor device 10 can be quickly and orderly manufactured and to improve the problem of significant parasitic capacitance differences that occur when transistors are manufactured over large areas, the embodiments of this application provide a method for manufacturing a metal oxide thin film transistor device to achieve the aforementioned functions. The method for manufacturing the metal oxide thin film transistor device provided in this application is described in detail below.

[0105] Please refer to Figure 8 、 Figure 9 and Figure 10 ,in Figure 8 This is one of the flow charts of the method for manufacturing a metal oxide thin film transistor device provided in an embodiment of the present application. Figure 9 is with Figure 8 One of the manufacturing flow charts of the metal oxide thin film transistor device matching the manufacturing method shown, Figure 10 is with Figure 8 The manufacturing method of the metal oxide thin film transistor device shown in the second manufacturing flow chart is matched with the manufacturing method shown in the second flow chart. In the embodiment of the present application, the manufacturing method of the metal oxide thin film transistor device may include steps S310 to S360 to prepare Figure 2 or Figure 3 The metal oxide thin film transistor device 10 is shown.

[0106] Step S310: providing a substrate.

[0107] In this embodiment, Figure 9 (a) with Figure 10 (a) are schematic diagrams of the substrate 11. The substrate 11 can be a rigid substrate such as glass, silicon, etc., or a flexible polymer substrate such as polyimide, polyethylene naphthalate, etc.

[0108] In step S320 , a silicon nitrogen layer containing hydrogen or fluorine is deposited on one side of the substrate.

[0109] In this embodiment, Figure 9 (b) with Figure 10 (b) are schematic diagrams of devices for preparing and forming the silicon nitride layer 12 on the substrate 11. The silicon nitride layer 12 can be formed by depositing it using the PECVD method. The material of the silicon nitride layer 12 is a silicon nitride material rich in hydrogen or fluorine. The thickness of the silicon nitride layer 12 ranges from 10 nm to 1000 nm.

[0110] In step S330 , a gate is formed on a side of the silicon nitride layer away from the substrate.

[0111] In this embodiment, Figure 9 (c) with Figure 10 (c) are schematic diagrams of devices for forming the gate 13 on the silicon nitride layer 12. The gate 13 can be obtained by depositing a gate electrode film layer on the silicon nitride layer 12 and then performing photolithographic patterning. The material of the gate 13 is metal, which can be but is not limited to any one or more combinations of metal materials such as aluminum (Al), copper (Cu), molybdenum (Mo), tantalum (Ta), hafnium (Hf), and chromium (Cr).

[0112] Step S340 , forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate, wherein the gate dielectric layer covers an outer surface of the gate that is not in contact with the silicon nitride layer.

[0113] In this embodiment, Figure 9 (d) with Figure 10 (d) are schematic diagrams of devices in which a gate dielectric layer 14 for covering the gate 13 is formed on the silicon nitride layer 12. The gate dielectric layer 14 can be formed using an insulating oxide material such as silicon oxide, aluminum oxide, hafnium oxide, and zirconium oxide. The gate dielectric layer 14 can be formed by growing directly on the outer surface of the gate 13 that is not in contact with the silicon nitride layer 12 by anodization. In this case, the gate dielectric layer 14 can have a film thickness ranging from 5 nm to 500 nm. The gate dielectric layer 14 can also be formed by depositing a gate dielectric precursor film on the silicon nitride layer 12, performing anodization-induced dehydration and curing, and etching away the undehydrated and cured area. In this case, the gate dielectric layer 14 can have a film thickness ranging from 10 nm to 1000 nm.

[0114] The step of forming the gate dielectric layer 14 on the side of the silicon nitride layer 12 away from the substrate 11 by using a dehydration and curing method may include:

[0115] forming a gate dielectric precursor film on a side of the silicon nitride layer 12 away from the substrate 11, wherein the gate dielectric precursor film covers an outer surface of the gate 13 not in contact with the silicon nitride layer 12 and an outer surface of the silicon nitride layer 12 away from the substrate 11;

[0116] Dehydrating and curing the gate dielectric precursor film region directly in contact with the gate electrode 13 based on an anodic oxidation induction method;

[0117] The undehydrated and uncured film region of the gate dielectric precursor film is removed by etching to form the gate dielectric layer 14 .

[0118] Step S350 , depositing a metal oxide semiconductor layer on the side of the silicon nitride layer away from the substrate, wherein the metal oxide semiconductor layer covers the outer surface of the gate dielectric layer not in contact with the silicon nitride layer and the outer surface of the silicon nitride layer away from the substrate.

[0119] In this embodiment, Figure 9 (e) with Figure 10 (e) are schematic diagrams of devices in which a metal oxide semiconductor layer 21 is formed on the silicon nitride layer 12 to cover the gate dielectric layer 14 and the outer surface of the silicon nitride layer 12 not blocked by the gate dielectric layer 14. The metal oxide semiconductor layer 21 may be made of, but is not limited to, amorphous indium gallium zinc oxide (a-IGZO), indium tin zinc oxide (ITZO), or rare earth-doped indium zinc oxide (Ln-IZO). The thickness of the metal oxide semiconductor layer 21 is in the range of 10 nm to 1000 nm.

[0120] In step S360 , the metal oxide semiconductor layer is annealed to make the portion of the metal oxide semiconductor layer directly in contact with the silicon nitride layer conductive by diffusion doping with hydrogen or fluorine contained in the silicon nitride layer, thereby obtaining a metal oxide layer including a source region, a semiconductor region, and a drain region.

[0121] In this embodiment, Figure 9 (f) and Figure 10 (f) are schematic diagrams of devices formed when the metal oxide semiconductor layer 21 is annealed in an environment of 100° C. to 500° C. due to the diffusion doping of hydrogen or fluorine elements in the silicon nitride layer 12. At this time, the portion of the metal oxide semiconductor layer 21 that is in direct contact with the silicon nitride layer 12 is conductively doped by the hydrogen or fluorine contained in the silicon nitride layer 12, forming conductive regions that can serve as the source region 152 and the drain region 153. The portion of the metal oxide semiconductor layer 21 that is not conductively doped can directly serve as the semiconductor region 151 included in the metal oxide layer 15. At this time, the semiconductor region 151 directly separates the conductive region into two parts, and the semiconductor region 151 connects the two separated conductive regions together.

[0122] In one implementation of this embodiment, the source region 152 and the drain region 153 may completely cover the outer surface of the silicon nitride layer 12 that is not blocked by the gate 13 and the gate dielectric layer 14. In this case, there is no need to perform photolithography patterning on the aforementioned conductive region. After the subsequent wiring precursor layer is successfully deposited, the wiring precursor layer and the wiring precursor layer can be photolithographically patterned using a shared half-tone mask. Figure 9 The semiconductor device shown in (f) is Figure 3 The metal oxide thin film transistor device 10 is shown.

[0123] In another embodiment of the present invention, the source region 152 and the drain region 153 can only partially cover the outer surface of the silicon nitride layer 12 that is not blocked by the gate 13 and the gate dielectric layer 14, and the conductive region and the semiconductor region 151 need to be patterned by photolithography. Figure 10 The semiconductor device shown in (g) is Figure 2 The metal oxide thin film transistor device 10 is shown.

[0124] Optionally, please refer to Figure 11 and Figure 12 ,in Figure 11 This is the second flow chart of the method for manufacturing a metal oxide thin film transistor device provided in an embodiment of the present application. Figure 12 is with Figure 11The third flow chart of the manufacturing process of the matched metal oxide thin film transistor device. Figure 8 Compared with the method for manufacturing the metal oxide thin film transistor device shown in FIG. Figure 11 The method for manufacturing the metal oxide thin film transistor device shown in the figure may further include steps S370 to S390 for preparing Figure 4 or Figure 5 The metal oxide thin film transistor device 10 is shown.

[0125] Step S370 , depositing a wiring precursor layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is formed, wherein the wiring precursor layer covers the metal oxide layer.

[0126] In this embodiment, the thin film transistor device after the metal oxide layer 15 is prepared can be Figure 2 or Figure 3 The metal oxide thin film transistor device 10 shown, Figure 12 (a) Figure 2 The metal oxide thin film transistor device 10 shown is a schematic diagram of an exemplary thin film transistor device. Figure 12 (b) is in Figure 12 (a) is a schematic diagram of a thin film transistor device in which a wiring precursor layer 22 is deposited on the outer surface away from the substrate 11. The preparation material of the wiring precursor layer 22 can be but is not limited to metal or transparent conductive metal oxide material.

[0127] Step S380 , etching and removing the wiring region in the wiring precursor layer that is in direct contact with the semiconductor region of the metal oxide layer, to obtain a first wiring layer and a second wiring layer.

[0128] In this embodiment, Figure 12 (c) is a schematic diagram of a device in which the deposited routing precursor layer 22 is etched to form a first routing layer 16 and a second routing layer 17. The first routing layer 16 and the second routing layer 17 are respectively located on both sides of the semiconductor region 151. The first routing layer 16 covers a portion of the source region 152, and the second routing layer 17 covers a portion of the drain region 153.

[0129] Among them, if Figure 3To prepare the first wiring layer 16 and the second wiring layer 17 based on the metal oxide thin film transistor device 10 shown, it is necessary to use the same set of half-tone masks to etch and remove the wiring area in the wiring precursor layer that is in direct contact with the semiconductor area 151 of the metal oxide layer 15, and it is also necessary to etch and pattern the semiconductor area 151 and the conductive area (including the source area 152 and the drain area 153) of the metal oxide layer 15.

[0130] Step S390 , depositing a passivation layer on the outer surface of the thin film transistor device away from the substrate after the first wiring layer and the second wiring layer are formed.

[0131] In this embodiment, the thin film transistor device after the first wiring layer 16 and the second wiring layer 17 are prepared can be Figure 4 or Figure 5 The metal oxide thin film transistor device 10 shown is a device structure with the passivation layer 18 removed. Figure 12 (d) is a schematic diagram of a device in which a passivation layer 18 is deposited on a side of the metal oxide layer 15 away from the substrate 11 to cover the first wiring layer 16, the second wiring layer 17, and the semiconductor region 151. The passivation layer 18 can be formed of an oxide insulating material such as silicon oxide or aluminum oxide, or can be formed of a silicon oxide / silicon nitride stacked material.

[0132] Optionally, please refer to Figure 13 and Figure 14 ,in Figure 13 This is the third flow chart of the method for manufacturing a metal oxide thin film transistor device provided in an embodiment of the present application. Figure 14 is with Figure 13 Flowchart 4 of the manufacturing process of the matched metal oxide thin film transistor device. In the embodiment of the present application, Figure 8 Compared with the method for manufacturing the metal oxide thin film transistor device shown in FIG. Figure 13 The method for manufacturing the metal oxide thin film transistor device shown may further include steps S400 to S420 for preparing Figure 6 or Figure 7 The metal oxide thin film transistor device 10 is shown.

[0133] Step S400 , depositing a passivation layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is formed, wherein the passivation layer covers the metal oxide layer.

[0134] In this embodiment, the thin film transistor device after the metal oxide layer 15 is prepared can be Figure 2 or Figure 3 The metal oxide thin film transistor device 10 shown, Figure 14 (a) Figure 2 The metal oxide thin film transistor device 10 shown is a schematic diagram of an exemplary thin film transistor device. Figure 14 (b) is in Figure 14 (a) is a schematic diagram of a thin film transistor device in which a passivation layer 18 is deposited on the outer surface away from the substrate 11. The passivation layer 18 can be prepared by using an oxide insulating material such as silicon oxide and aluminum oxide, or by using a silicon oxide / silicon nitride stacked material.

[0135] In step S410, a hole is opened in a first area of ​​the passivation layer that overlaps with the projection position of the source region to obtain a first via hole connected to the source region, and a hole is opened in a second area of ​​the passivation layer that overlaps with the projection position of the drain region to obtain a second via hole connected to the drain region.

[0136] In this embodiment, Figure 14 (c) is a schematic diagram of a device in which the deposited passivation layer 18 is opened to form a first via hole 191 and a second via hole 192 .

[0137] Step S420 , forming a first wiring layer overlapping the source region through the first via hole and a second wiring layer overlapping the drain region through the second via hole on the outer surface of the passivation layer away from the substrate.

[0138] In this embodiment, Figure 14 (d) is a schematic diagram of a device for preparing the first routing layer 16 and the second routing layer 17 on the passivation layer 18. The first routing layer 16 and the second routing layer 17 can be obtained by depositing a routing precursor layer on the passivation layer 18 and then performing photolithographic patterning.

[0139] Therefore, the present application can ensure that the prepared metal oxide thin film transistor device 10 can be based on an extremely simple self-aligned bottom gate structure and have a smaller overlapping area between the source / drain and the gate by executing any of the above-mentioned methods for manufacturing metal oxide thin film transistor devices, thereby effectively reducing the parasitic capacitance of the transistor and increasing the upper limit of the operating frequency of the transistor, while effectively reducing the complexity of transistor preparation, improving the problem of obvious parasitic capacitance differences when transistors are prepared over a large area, and improving the image display quality of the corresponding display panel.

[0140] In the present application, embodiments of the present application may further provide a display panel, comprising a pixel unit array and a plurality of any of the aforementioned metal oxide thin film transistor devices 10, wherein the plurality of metal oxide thin film transistor devices 10 cooperate with each other to form a switch array for driving the pixel unit array, thereby ensuring that the display panel can adjust the pixel display status of the pixel unit array by controlling the on / off state of the switch array. The display panel may be, but is not limited to, an AMLCD (active matrix liquid crystal display) display panel, an AMOLED (active matrix organic light emitting diode display) display panel, a Mini-LED (mini light emitting diode) display panel, a Micro-LED (micro light emitting diode) display panel, and the like.

[0141] In summary, in the metal oxide thin film transistor device, its manufacturing method and display panel provided in the embodiments of the present application, the present application sequentially prepares a silicon nitride layer, a gate, a gate dielectric layer covering the gate and a metal oxide layer covering at least the gate dielectric layer on one side of the substrate, so that the partial area of ​​the metal oxide layer in contact with the silicon nitride layer is diffusely doped with hydrogen or fluorine contained in the silicon nitride layer to be conductive, thereby forming the source region and drain region of the metal oxide layer. At this time, the partial area of ​​the metal oxide layer in contact with the gate dielectric layer and not conductive is the semiconductor region connecting the source region and the drain region of the metal oxide layer. The overlapping area of ​​the gate and the source region / drain region on the same silicon nitride layer surface is significantly small, thereby effectively reducing the parasitic capacitance of the transistor through an extremely simple self-aligned bottom gate structure, and improving the upper limit of the operating frequency of the thin film transistor. The metal oxide thin film transistor device has the characteristics of a simple preparation process, and can be used to prepare a display panel with high image display quality at low cost.

[0142] The above are merely various embodiments of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A metal oxide thin film transistor device, characterized in that: The thin film transistor device comprises: substrate; a silicon nitride layer disposed on the substrate; a gate disposed on a side of the silicon nitride layer away from the substrate; a gate dielectric layer covering an outer surface of the gate that is not in contact with the silicon nitride layer; A metal oxide layer at least covering the outer surface of the gate dielectric layer that is not in contact with the silicon nitride layer; the metal oxide layer includes a source region, a semiconductor region, and a drain region, the source region and the drain region are respectively located on both sides of the semiconductor region and are interconnected with the semiconductor region, wherein the source region and the drain region are both formed by diffuse doping of hydrogen or fluorine contained in the silicon nitride layer in contact with the metal oxide layer; wherein the gate, the source region, and the drain region are located on the same outer surface of the silicon nitride layer, separated by the gate dielectric layer, and the gate is within the projected coverage of the semiconductor region; the silicon nitride layer is used to isolate water and oxygen and to conduct the semiconductor material in contact with it.

2. The thin film transistor device according to claim 1, wherein: The thin film transistor device further includes: A first routing layer and a second routing layer are arranged on a side of the silicon nitride layer away from the substrate, wherein the first routing layer and the second routing layer are respectively located on both sides of the semiconductor region, the source region is electrically connected to the first routing layer, and the drain region is electrically connected to the second routing layer.

3. The thin film transistor device according to claim 2, wherein: The thin film transistor device further includes: A passivation layer is provided on a side of the metal oxide layer away from the substrate, wherein the passivation layer covers an outer surface of the semiconductor region away from the gate.

4. The thin film transistor device according to claim 3, wherein: The first wiring layer partially covers the source region, and the second wiring layer partially covers the drain region; The passivation layer further covers the first routing layer, an outer surface of the source region not covered by the first routing layer, the second routing layer, and an outer surface of the drain region not covered by the second routing layer.

5. The thin film transistor device according to claim 3, wherein: The passivation layer also covers the source region and the drain region; A first via hole is formed in a first region of the passivation layer that overlaps with a projection position of the source region, and the first wiring layer is connected to the source region through the first via hole; A second via hole is formed in a second region of the passivation layer that overlaps with a projection position of the drain region, and the second wiring layer is overlapped with the drain region through the second via hole.

6. A method for manufacturing a metal oxide thin film transistor device, characterized in that: The production method comprises: providing a substrate; Depositing a silicon nitrogen layer containing hydrogen or fluorine on one side of the substrate; forming a gate on a side of the silicon nitride layer away from the substrate; forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate, wherein the gate dielectric layer covers an outer surface of the gate that is not in contact with the silicon nitride layer; Depositing a metal oxide semiconductor layer on a side of the silicon nitride layer away from the substrate, wherein the metal oxide semiconductor layer covers an outer surface of the gate dielectric layer not in contact with the silicon nitride layer and an outer surface of the silicon nitride layer away from the substrate; The metal oxide semiconductor layer is annealed to make a portion of the metal oxide semiconductor layer directly in contact with the silicon nitride layer conductive by diffusion doping with hydrogen or fluorine contained in the silicon nitride layer, thereby obtaining a metal oxide layer including a source region, a semiconductor region, and a drain region, wherein the source region and the drain region are respectively located on either side of the semiconductor region and are interconnected with the semiconductor region, the source region and the drain region both being conductive portions of the metal oxide semiconductor layer, and the semiconductor region being non-conductive portions of the metal oxide semiconductor layer; wherein the gate electrode, the source region, and the drain region are located on the same outer surface of the silicon nitride layer and separated from each other by the gate dielectric layer, and the gate electrode is within the projection coverage of the semiconductor region; the silicon nitride layer is used to isolate water and oxygen and to conductively connect the semiconductor material in contact with it.

7. The production method according to claim 6, characterized in that: The step of forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate comprises: forming the gate dielectric layer by growing it on the outer surface of the gate that is not in contact with the silicon nitride layer based on an anodic oxidation method; Alternatively, the step of forming a gate dielectric layer on a side of the silicon nitride layer away from the substrate includes: preparing a gate dielectric precursor film on a side of the silicon nitride layer away from the substrate, wherein the gate dielectric precursor film covers an outer surface of the gate that is not in contact with the silicon nitride layer and an outer surface of the silicon nitride layer away from the substrate; Dehydrating and curing the gate dielectric precursor film region directly in contact with the gate electrode based on an anodic oxidation induction method; The undehydrated and uncured film region of the gate dielectric precursor film is removed by etching to form the gate dielectric layer.

8. The production method according to claim 6 or 7, characterized in that: The production method further comprises: Depositing a wiring precursor layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is prepared, wherein the wiring precursor layer covers the metal oxide layer; Etching and removing the routing region in the routing precursor layer that is in direct contact with the semiconductor region of the metal oxide layer to obtain a first routing layer and a second routing layer, wherein the first routing layer and the second routing layer are respectively located on both sides of the semiconductor region, the first routing layer covers a portion of the source region, and the second routing layer covers a portion of the drain region; A passivation layer is deposited on the outer surface of the thin film transistor device away from the substrate after the first wiring layer and the second wiring layer are prepared.

9. The production method according to claim 6 or 7, characterized in that: The production method further comprises: Depositing a passivation layer on the outer surface of the thin film transistor device away from the substrate after the metal oxide layer is formed, wherein the passivation layer covers the metal oxide layer; A hole is opened in a first region of the passivation layer that overlaps with a projected position of the source region to obtain a first via hole connected to the source region, and a hole is opened in a second region of the passivation layer that overlaps with a projected position of the drain region to obtain a second via hole connected to the drain region; A first wiring layer overlapping the source region through the first via hole and a second wiring layer overlapping the drain region through the second via hole are formed on the outer surface of the passivation layer away from the substrate.

10. A display panel, characterized in that: The display panel includes a pixel unit array and a plurality of metal oxide thin film transistor devices according to any one of claims 1 to 5, wherein the plurality of metal oxide thin film transistor devices cooperate with each other to form a switch array for driving the pixel unit array.

Images