LED epitaxial wafer and method of manufacturing the same
By employing an alternating N_SL and N_Bulk layer structure in the LED epitaxial wafer, the problems of large lattice mismatch and poor antistatic capability are solved, resulting in higher luminous brightness and lower production costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FOCUS LIGHTINGS SCI & TECH
- Filing Date
- 2022-04-29
- Publication Date
- 2026-05-12
AI Technical Summary
Traditional LED epitaxial wafers suffer from problems such as large lattice mismatch, high production costs, and poor antistatic properties.
An N-type GaN layer structure with alternating N_SL and N_Bulk layers is used. By designing different silicon doping concentrations and thicknesses, multiple capacitor structures are formed, which enhances current diffusion, reduces lattice mismatch, improves antistatic capability, and reduces the switching frequency of SiH4 valve group in MOCVD equipment to extend its service life.
This improves the luminous brightness and lattice quality of LED epitaxial wafers, reduces production costs, and enhances antistatic capabilities.
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Figure CN114824016B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of LED technology, and in particular to an LED epitaxial wafer and its manufacturing method. Background Technology
[0002] An LED (Light-Emitting Diode) is a semiconductor light-emitting device that converts electrical energy into light energy. An LED epitaxial wafer refers to a specific single-crystal thin film grown on a substrate heated to a suitable temperature. See also... Figure 1 LED epitaxial wafers typically consist of a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, and a P-type GaN layer, arranged sequentially from bottom to top. The growth of LED epitaxial wafers is primarily achieved using MOCVD (Metal-organic Chemical Vapor Deposition) equipment.
[0003] The N-type GaN layer structure of LED epitaxial wafers grown in MOCVD equipment includes two types: N-Bulk and N-SL. The N-Bulk structure can provide a higher electron concentration, but it suffers from significant lattice mismatch with the underlying U-type GaN layer and the upper quantum well light-emitting layer, affecting the crystal quality of the quantum well light-emitting layer. Compared to the N-Bulk structure, the N-SL structure can effectively reduce the lattice mismatch between the N-type GaN layer and the underlying U-type GaN layer; however, the N-SL structure experiences larger fluctuations in emission voltage due to differences in N-electrode etching. Furthermore, during growth, the SiH4 valve group in the MOCVD equipment requires a high switching frequency, reducing the lifespan of the SiH4 valve group and increasing production costs.
[0004] Furthermore, during the manufacturing, installation, and use of LEDs, they are inevitably affected by static electricity, generating induced charges. If these induced charges are not released in time, a high voltage will form across the PN junction. Traditional LED epitaxial wafers have poor anti-static capabilities. When the voltage exceeds the maximum withstand value of the LED epitaxial wafer, the static charge will discharge across the PN junction in a very short instant, causing the PN junction to break down and the LED to fail. Summary of the Invention
[0005] This application provides an LED epitaxial wafer and its manufacturing method to solve the problems of large lattice mismatch, high production cost and poor antistatic capability of traditional LED epitaxial wafers.
[0006] On one hand, this application provides an LED epitaxial wafer, comprising a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer, and a P-type GaN layer stacked sequentially. The N-type GaN layer includes an N_SL layer and an N_Bulk layer disposed on the N_SL layer, wherein the thickness of the N_SL layer is less than the thickness of the N_Bulk layer.
[0007] The N_SL layer includes several first N_SL layers and several second N_SL layers. The N_Bulk layer includes a first N_Bulk layer and a second N_Bulk layer disposed on the first N_Bulk layer.
[0008] The silicon doping concentration of the first N_SL layer is lower than that of the second N_SL layer. The silicon doping concentration of the first N_Bulk layer is higher than that of the second N_Bulk layer. The silicon doping concentration of the first N_SL layer is lower than that of the second N_Bulk layer.
[0009] The N_SL layer and the N_Bulk layer effectively form multiple capacitor structures. Different silicon doping concentrations enhance current diffusion and improve the anti-static capability of the LED epitaxial wafer. The N_SL layer and N_Bulk layer structure reduces the dislocation density of the grown quantum well light-emitting layer and improves the lattice quality of the quantum well light-emitting layer.
[0010] Optionally, the first N_SL layer and the second N_SL layer are set sequentially from bottom to top in a cyclical manner, with the number of cycles ranging from 10 to 20.
[0011] Optionally, the silicon doping concentration of the first N_SL layer is 1×10⁻⁶. 18 ~5×10 18 / cm -3 Between; the silicon doping concentration of the second N_SL layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the first N_Bulk layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the second N-Bulk layer is 5×10. 18 ~1×10 19 / cm -3 between.
[0012] Optionally, the thickness of the first N_SL layer is between 15 and 20 nm; the thickness of the second N_SL layer is between 30 and 35 nm; and the thickness of the N_SL layer is between 450 and 550 nm.
[0013] Optionally, the thickness of the first N_Bulk layer is between 500 and 600 nm; the thickness of the second N_Bulk layer is between 500 and 600 nm; and the thickness of the N_Bulk layer is between 1000 and 1200 nm.
[0014] Optionally, the quantum well light-emitting layer includes periodically arranged GaN layers and In layers. x Ga 1-x The N-layer has an x-value between 0.2 and 0.3 and a period number between 7 and 12; the GaN layer has a thickness between 8 and 12 nm; the In-layer has an In-value between 8 and 12 nm. x Ga 1-x The thickness of the N layer is between 2 and 5 nm.
[0015] On the other hand, this application also provides a method for manufacturing an LED epitaxial wafer, for manufacturing the above-mentioned LED epitaxial wafer, comprising:
[0016] A substrate is prepared, and a buffer layer is grown on the substrate; the growth temperature of the buffer layer is between 800 and 1100°C.
[0017] A U-shaped GaN layer is grown on the buffer layer; the growth temperature of the U-shaped GaN layer is between 1000 and 1400°C.
[0018] A first N_SL layer and a second N_SL layer are sequentially grown on the U-shaped GaN layer to obtain an N_SL layer; the number of cycles is between 10 and 20; the growth temperature of the first N_SL layer is between 1000 and 1200°C; the growth thickness of the first N_SL layer is between 15 and 20 nm; the growth temperature of the second N_SL layer is between 1000 and 1200°C; the growth thickness of the second N_SL layer is between 30 and 35 nm.
[0019] A first N_Bulk layer is grown on the N_SL layer; the growth temperature of the first N_Bulk layer is between 1000 and 1200°C; the growth thickness of the first N_Bulk layer is between 500 and 600 nm.
[0020] A second N_Bulk layer is grown on the first N_Bulk layer; the growth temperature of the second N_Bulk layer is between 900 and 1100°C; the growth thickness of the second N_Bulk layer is between 500 and 600 nm.
[0021] A quantum well light-emitting layer is grown on the second N-Bulk layer; the growth temperature of the quantum well light-emitting layer is between 700 and 800°C.
[0022] A P-type electron blocking layer is grown on the quantum well light-emitting layer; the growth temperature of the P-type electron blocking layer is between 800 and 1000°C.
[0023] A P-type GaN layer is grown on the P-type electron blocking layer; the growth temperature of the P-type GaN layer is between 900 and 1100 °C.
[0024] Optionally, the silicon doping concentration of the first N_SL layer is 1×10⁻⁶. 18 ~5×10 18 / cm -3 Between; the silicon doping concentration of the second N_SL layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the first N_Bulk layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the second N-Bulk layer is 5×10. 18 ~1×10 19 / cm -3 between.
[0025] This application provides an LED epitaxial wafer and its manufacturing method. The LED epitaxial wafer includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer, and a P-type GaN layer stacked sequentially. The N-type GaN layer includes an N-SL layer and an N-Bulk layer disposed on the N-SL layer. The N-SL layer includes a plurality of first N-SL layers and a plurality of second N-SL layers, which are cyclically arranged from bottom to top. The N-Bulk layer includes a first N-Bulk layer and a second N-Bulk layer. The silicon doping concentration of the first N-SL layer is lower than that of the second N-SL layer, the silicon doping concentration of the first N-Bulk layer is greater than that of the second N-Bulk layer, and the silicon doping concentration of the first N-SL layer is lower than that of the second N-Bulk layer. The N-SL layer and the N-Bulk layer effectively form multiple capacitor structures. Simultaneously, the different silicon doping concentrations enhance current diffusion and improve the anti-static capability of the LED epitaxial wafer. The N_SL layer and the N_Bulk layer structure reduces the dislocation density during the growth of the quantum well light-emitting layer, thereby improving the lattice quality of the quantum well light-emitting layer. In the manufacturing process of the LED epitaxial wafer provided in this application, the SiH4 valve group of the MOCVD equipment does not require a high switching frequency, thus increasing the service life of the SiH4 valve group and reducing production costs. Attached Figure Description
[0026] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0027] Figure 1 A schematic diagram of a conventional LED epitaxial wafer provided in this application;
[0028] Figure 2 This is a schematic diagram of an LED epitaxial wafer provided in an embodiment of this application;
[0029] Figure 3 A schematic diagram of the N-type GaN layer structure of the LED epitaxial wafer provided in this application embodiment;
[0030] Figure 4 This is a schematic diagram of the equivalent capacitance of the N-type GaN layer of the LED epitaxial wafer provided in an embodiment of this application. Detailed Implementation
[0031] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims.
[0032] LED epitaxial wafers refer to specific single-crystal thin films grown on a substrate heated to an appropriate temperature. See also Figure 1Traditional LED epitaxial wafers typically consist of a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, and a P-type GaN layer, arranged sequentially from bottom to top. N-type GaN layer structures generally include two types: N-Bulk and N-SL. The conventional N-SL structure consists of multiple alternating layers of undoped and doped GaN layers, while the N-Bulk structure consists of two stacked silicon-doped GaN layers. The N-Bulk structure can provide a higher electron concentration, but it suffers from a significant lattice mismatch with the underlying U-type GaN layer. This mismatch leads to dislocations extending into the quantum well light-emitting layer, affecting its lattice quality and reducing luminous efficiency. The N-SL structure effectively reduces the lattice mismatch between the N-type GaN layer and the underlying U-type GaN layer, decreasing dislocations extending into the quantum well light-emitting layer and improving lattice quality. However, the N-SL structure experiences significant voltage fluctuations due to variations in the N-electrode etching depth. Furthermore, the N_SL structure requires a high switching frequency for the SiH4 valve assembly in the MOCVD (Metal-organic Chemical Vapor Deposition) equipment during manufacturing, which reduces the lifespan of the SiH4 valve assembly and increases production costs. In addition, traditional LED epitaxial wafers have poor anti-static properties; if the PN junction is broken down, it will lead to LED failure.
[0033] To address the aforementioned issues, this application provides an LED epitaxial wafer and its manufacturing method, which reduces lattice mismatch, lowers production costs, and improves antistatic properties.
[0034] On one hand, embodiments of this application provide an LED epitaxial wafer. See also... Figure 2 The LED epitaxial wafer provided in this application includes, from bottom to top, a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer, and a P-type GaN layer. The N-type GaN layer includes an N_SL layer and an N_Bulk layer, with the N_Bulk layer disposed above the N_SL layer. See also... Figure 3 The N_SL layer includes several first N_SL layers and several second N_SL layers, which are arranged cyclically from bottom to top, with a cycle number between 10 and 20. The N_Bulk layer includes a first N_Bulk layer and a second N_Bulk layer, with the second N_Bulk layer positioned above the first N_Bulk layer.
[0035] See Figure 4The N-type GaN layer structure of the LED epitaxial wafer provided in this application embodiment effectively forms multiple capacitor structures. The potential difference across the capacitors accelerates the electron transport rate, which can increase the electron concentration of the quantum well light-emitting layer, thereby improving the LED brightness. Through the multilayer structure design of the N_SL layer and the N_Bulk layer, the lattice mismatch with the U-type GaN layer can be gradually reduced, the dislocation density of the grown quantum well light-emitting layer can be decreased, and the lattice quality of the quantum well light-emitting layer can be improved, thereby improving the luminous efficiency.
[0036] The thickness of the N_SL layer is less than the thickness of the N_Bulk layer. The thickness of each layer can be set according to production requirements. In one embodiment, the thickness of the first N_SL layer is between 15 and 20 nm, and the thickness of the second N_SL layer is between 30 and 35 nm. The thickness of the N_SL layer, formed by multiple cycles of the first and second N_SL layers, is between 450 and 550 nm. The thickness of the first N_Bulk layer is between 500 and 600 nm, and the thickness of the second N_Bulk layer is between 500 and 600 nm. The thickness of the N_Bulk layer is between 1000 and 1200 nm.
[0037] Based on the LED epitaxial wafer structure provided in this application embodiment, the operating parameters of the N_SL layer thickness and the N_Bulk layer thickness within different value ranges are compared in Table 2. Referring to Table 1, Sample 11 represents an LED epitaxial wafer with the following thicknesses: the first N_SL layer thickness is 18 nm, the second N_SL layer thickness is 32 nm, the N_SL layer thickness is 500 nm, the first N_Bulk layer thickness is 550 nm, the second N_Bulk layer thickness is 550 nm, and the N_Bulk layer thickness is 1100 nm. Sample 12 represents an LED epitaxial wafer with the following thicknesses: the first N_SL layer thickness is 15 nm, the second N_SL layer thickness is 30 nm, the N_SL layer thickness is 450 nm, the first N_Bulk layer thickness is 500 nm, the second N_Bulk layer thickness is 500 nm, and the N_Bulk layer thickness is 1000 nm. Sample 13 represents an LED epitaxial wafer with a first N_SL layer thickness of 20 nm, a second N_SL layer thickness of 35 nm, an N_SL layer thickness of 550 nm, a first N_Bulk layer thickness of 600 nm, a second N_Bulk layer thickness of 600 nm, and an N_Bulk layer thickness of 1200 nm. Sample 21 represents an LED epitaxial wafer where the thicknesses of both the N_SL and N_Bulk layers are slightly smaller than the minimum values of the corresponding ranges provided in the embodiments of this application (i.e., the thickness of the N_SL layer is slightly less than 450 nm, and the thickness of the N_Bulk layer is slightly less than 1000 nm). Sample 22 represents an LED epitaxial wafer where the thicknesses of both the N_SL and N_Bulk layers are slightly larger than the maximum values of the corresponding ranges provided in the embodiments of this application (i.e., the thickness of the N_SL layer is slightly greater than 550 nm, and the thickness of the N_Bulk layer is slightly greater than 1200 nm).
[0038] In this application embodiment, the range of "slightly less than" and / or "slightly greater than" is within 10% of the length of the value range provided in this application embodiment. For example, the thickness of the N_SL layer provided in this application embodiment is between 450 and 550 nm, and the length of the value range is 550 nm - 450 nm = 100 nm. The thickness of the N_SL layer in sample 21 is slightly less than 450 nm, that is, the thickness of the N_SL layer is between 440 and 450 nm (440 nm = 450 nm - (550 nm - 450 nm) × 10%). The thickness of the N_SL layer in sample 22 is slightly greater than 550 nm, that is, the thickness of the N_SL layer is between 550 and 560 nm (560 nm = 550 nm + (550 nm - 450 nm) × 10%).
[0039] In the embodiments of this application, the operating parameters are as follows: Lop is used to characterize the sample brightness, and a larger value indicates better performance. VF1 is the sample operating voltage, and a smaller value indicates less energy consumption. IR is the reverse breakdown current, used to characterize crystal quality, and a smaller value indicates better crystal quality. ESD is the antistatic capability, representing the probability that the sample passes the antistatic test, and a larger value indicates better antistatic capability. WLD is the sample emission wavelength.
[0040] Table 1
[0041]
[0042] Table 2
[0043]
[0044] As can be seen from Table 2, the LED epitaxial wafers with the thicknesses of the N_SL layer and the N_Bulk layer within the range provided in this application have higher brightness, lower operating costs, better crystal quality, and stronger antistatic capabilities.
[0045] The silicon doping concentration of the first N_SL layer is lower than that of the second N_SL layer, the silicon doping concentration of the first N_Bulk layer is greater than that of the second N_Bulk layer, and the silicon doping concentration of the first N_SL layer is lower than that of the second N_Bulk layer. In one embodiment, the silicon doping concentration of the first N_SL layer is 1×10⁻⁶. 18 ~5×10 18 / cm -3 The growth temperature of the first N-SL layer is between 1000 and 1200°C. The silicon doping concentration of the second N-SL layer is 1 × 10⁻⁶. 19 ~3×10 19 / cm -3 The growth temperature of the second N_SL layer is between 1000 and 1200°C. The silicon doping concentration of the first N_Bulk layer is 1 × 10⁻⁶. 19 ~3×10 19 / cm -3 The growth temperature of the first N-Bulk layer is between 1000 and 1200°C. The silicon doping concentration of the second N-Bulk layer is 5 × 10⁻⁶. 18 ~1×10 19 / cm -3 The growth temperature of the second N_Bulk layer is between 900 and 1100°C.
[0046] Based on the LED epitaxial wafer structure provided in this application embodiment, the comparison of operating parameters for the silicon doping concentrations of the N_SL layer and the N_Bulk layer within different value ranges is shown in Table 4. Referring to Table 3, sample 14 indicates that the silicon doping concentration of the first N_SL layer is 3 × 10⁻⁶. 18 / cm -3 The silicon doping concentration of the second N_SL layer is 2×10⁻⁶. 19 / cm -3 The silicon doping concentration of the first N-Bulk layer is 2×10⁻⁶. 19 / cm -3 The silicon doping concentration of the second N-Bulk layer is 8 × 10⁻⁶. 18 / cm -3 LED epitaxial wafers. Sample 15 indicates that the silicon doping concentration of the first N_SL layer is 1×10⁻⁶. 18 / cm -3 The silicon doping concentration of the second N_SL layer is 1×10⁻⁶. 19 / cm -3 The silicon doping concentration of the first N-Bulk layer is 1×10⁻⁶. 19 / cm -3 The silicon doping concentration of the second N-Bulk layer is 5 × 10⁻⁶. 18 / cm -3 LED epitaxial wafers. Sample 16 indicates that the silicon doping concentration of the first N_SL layer is 5 × 10⁻⁶. 18 / cm -3 The silicon doping concentration of the second N_SL layer is 3×10⁻⁶. 19 / cm -3 The silicon doping concentration of the first N-Bulk layer is 3×10⁻⁶. 19 / cm -3 The silicon doping concentration of the second N-Bulk layer is 1×10⁻⁶. 19 / cm -3 The LED epitaxial wafers are shown. Sample 31 represents an LED epitaxial wafer in which the silicon doping concentrations of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly less than the minimum value of the corresponding range provided in the embodiments of this application. Sample 32 represents an LED epitaxial wafer in which the silicon doping concentrations of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly greater than the maximum value of the corresponding range provided in the embodiments of this application.
[0047] Table 3
[0048]
[0049] Table 4
[0050]
[0051] As can be seen from Table 4, for LED epitaxial wafers with silicon doping concentrations of the N_SL layer and the N_Bulk layer within the range provided in this application, the brightness is higher, the operating temperature is lower, the crystal quality is better, and the antistatic capability is stronger.
[0052] Based on the LED epitaxial wafer structure provided in this application embodiment, the comparison of operating parameters for the growth temperatures of the N_SL layer and the N_Bulk layer within different value ranges is shown in Table 6. Referring to Table 5, Sample 17 represents an LED epitaxial wafer with the first N_SL layer growing at 1100℃, the second N_SL layer growing at 1100℃, the first N_Bulk layer growing at 1100℃, and the second N_Bulk layer growing at 1000℃. Sample 18 represents an LED epitaxial wafer with the first N_SL layer growing at 1000℃, the second N_SL layer growing at 1000℃, the first N_Bulk layer growing at 1000℃, and the second N_Bulk layer growing at 900℃. Sample 19 represents an LED epitaxial wafer with the first N_SL layer growing at 1200℃, the second N_SL layer growing at 1200℃, the first N_Bulk layer growing at 1200℃, and the second N_Bulk layer growing at 1100℃. Sample 41 represents an LED epitaxial wafer in which the growth temperatures of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly lower than the minimum values of the corresponding ranges provided in the embodiments of this application. Sample 42 represents an LED epitaxial wafer in which the growth temperatures of the first N_SL layer, the second N_SL layer, the first N_Bulk layer, and the second N_Bulk layer are all slightly higher than the maximum values of the corresponding ranges provided in the embodiments of this application.
[0053] Table 5
[0054]
[0055] Table 6
[0056]
[0057] As can be seen from Table 6, the LED epitaxial wafers with growth temperatures of the N_SL layer and the N_Bulk layer within the range provided in this application have higher brightness, lower operating temperature, better crystal quality, and stronger antistatic capability.
[0058] In this embodiment, different silicon doping concentrations, growth thicknesses, and growth temperatures are set for the N_SL layer and the N_Bulk layer. High and low silicon doping can enhance current diffusion. High and low silicon doping includes high silicon doping and low silicon doping. The low silicon doping portion has a certain ability to confine electrons, which can increase the concentration of the two-dimensional electron gas, thereby enhancing the antistatic capability of the LED epitaxial wafer. At the same time, it can improve electron mobility, reduce the luminous voltage, and improve the stability of the luminous voltage. The combination of high and low silicon doping and high and low temperature growth can further release stress, thereby improving the overall growth quality of the epitaxial structure. Furthermore, in the LED epitaxial wafer provided in this embodiment, since silicon doping is required throughout the entire N-type GaN layer growth stage, the SiH4 valve group of the MOCVD equipment remains in a normally open state. Only the degree of opening of the SiH4 valve group needs to be adjusted according to different silicon doping concentrations, avoiding high-frequency switching of the SiH4 valve group's on / off state, thereby extending the service life of the SiH4 valve group and reducing production costs.
[0059] The quantum well light-emitting layer provided in this application embodiment is a multi-period GaN / In. x Ga 1-x N-structure, where the GaN layer is the barrier layer, In x Ga 1-x The N layer is a potential well layer. In one embodiment, the number of periods is between 7 and 12, x is between 0.2 and 0.3, the thickness of the barrier layer is between 8 and 12 nm, and the thickness of the potential well layer is between 2 and 5 nm.
[0060] Table 4 compares the operating parameters of the LED epitaxial wafer provided in this application embodiment with those of a conventional LED epitaxial wafer. Sample 0 represents a conventional LED epitaxial wafer, and Sample 1 represents the LED epitaxial wafer provided in this application embodiment.
[0061] Table 7
[0062]
[0063] As can be seen from Table 7, compared with conventional LED epitaxial wafers, the LED epitaxial wafers provided in this application embodiment include a multi-layer structure in the N_Sl layer and the N_Bulk layer. By limiting the thickness, growth temperature and silicon doping concentration of different layer structures, the luminous brightness is improved, the operating voltage is reduced, the crystal quality is improved, and the antistatic ability is good.
[0064] On the other hand, this application also provides a method for manufacturing an LED epitaxial wafer, used to manufacture the LED epitaxial wafer provided in this application. The method includes the following steps:
[0065] A substrate is prepared, and a buffer layer is grown on the substrate. The growth temperature of the buffer layer is between 800 and 1100°C. The growth thickness of the buffer layer is between 15 and 30 nm. The substrate can be a sapphire (Al₂O₃) substrate.
[0066] A U-shaped GaN layer is grown on the buffer layer. The growth temperature of the U-shaped GaN layer is between 1000 and 1400°C. The thickness of the U-shaped GaN layer is between 2 and 4 μm.
[0067] A first N_SL layer and a second N_SL layer are sequentially grown on the U-shaped GaN layer to obtain the N_SL layer. The number of cycles is between 10 and 20, depending on production requirements. The silicon doping concentration of the first N_SL layer is 1 × 10⁻⁶. 18 ~5×10 18 / cm -3 The growth temperature of the first N-SL layer is between 1000 and 1200°C, and the growth thickness of the first N-SL layer is between 15 and 20 nm. The silicon doping concentration of the second N-SL layer is 1 × 10⁻⁶. 19 ~3×10 19 / cm -3 The growth temperature of the second N_SL layer is between 1000 and 1200°C, and the growth thickness of the second N_SL layer is between 30 and 35 nm.
[0068] A first N_Bulk layer is grown on the N_SL layer. The silicon doping concentration of the first N_Bulk layer is 1×10⁻⁶. 19 ~3×10 19 / cm -3 The growth temperature of the first N_Bulk layer is between 1000 and 1200°C, and the growth thickness of the first N_Bulk layer is between 500 and 600 nm.
[0069] A second N_Bulk layer is grown on the first N_Bulk layer. The silicon doping concentration of the second N_Bulk layer is 5 × 10⁻⁶. 18 ~1×10 19 / cm -3 The growth temperature of the second N-Bulk layer is between 900 and 1100°C, and the growth thickness of the second N-Bulk layer is between 500 and 600 nm.
[0070] The growth rate of the first N-Bulk layer and the second N-Bulk layer is between 6 and 9 μm / h.
[0071] A quantum well light-emitting layer is grown on the second N-Bulk layer. The growth temperature of the quantum well light-emitting layer is between 700℃ and 800℃.
[0072] A P-type electron blocking layer is grown on the quantum well light-emitting layer. The growth temperature of the P-type electron blocking layer is between 800℃ and 1000℃.
[0073] A P-type GaN layer is grown on the P-type electron blocking layer. The growth temperature of the P-type GaN layer is between 900 and 1100 °C.
[0074] This application provides an LED epitaxial wafer and its manufacturing method. The LED epitaxial wafer includes a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron blocking layer, and a P-type GaN layer stacked sequentially. The N-type GaN layer includes an N-SL layer and an N-Bulk layer disposed on the N-SL layer. The N-SL layer includes a plurality of first N-SL layers and a plurality of second N-SL layers, which are cyclically arranged from bottom to top. The N-Bulk layer includes a first N-Bulk layer and a second N-Bulk layer. The silicon doping concentration of the first N-SL layer is lower than that of the second N-SL layer, the silicon doping concentration of the first N-Bulk layer is greater than that of the second N-Bulk layer, and the silicon doping concentration of the first N-SL layer is lower than that of the second N-Bulk layer. The N-SL layer and the N-Bulk layer effectively form multiple capacitor structures. Simultaneously, the different silicon doping concentrations enhance current diffusion and improve the anti-static capability of the LED epitaxial wafer. The N_SL layer and the N_Bulk layer structure reduces the dislocation density during the growth of the quantum well light-emitting layer, thereby improving the lattice quality of the quantum well light-emitting layer. In the manufacturing process of the LED epitaxial wafer provided in this application, the SiH4 valve group of the MOCVD equipment does not require a high switching frequency, thus increasing the service life of the SiH4 valve group and reducing production costs.
[0075] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.
Claims
1. An LED epitaxial wafer, comprising a substrate, a buffer layer, a U-type GaN layer, an N-type GaN layer, a quantum well light-emitting layer, a P-type electron-blocking layer, and a P-type GaN layer stacked sequentially, characterized in that, The N-type GaN layer includes an N_SL layer and an N_Bulk layer disposed on the N_SL layer. The N_SL layer and the N_Bulk layer effectively form multiple capacitor structures. The potential difference across the capacitors accelerates the electron transport rate, thereby increasing the electron concentration of the quantum well light-emitting layer and gradually reducing the lattice mismatch with the U-type GaN layer, thus reducing the dislocation density of the quantum well light-emitting layer. The thickness of the N_SL layer is smaller than the thickness of the N_Bulk layer. The N_SL layer includes several first N_SL layers and several second N_SL layers; the N_Bulk layer includes a first N_Bulk layer and a second N_Bulk layer disposed on the first N_Bulk layer; The silicon doping concentration of the first N_SL layer is less than that of the second N_SL layer; the silicon doping concentration of the first N_Bulk layer is greater than that of the second N_Bulk layer; the silicon doping concentration of the first N_SL layer is less than that of the second N_Bulk layer; The first N_SL layer and the second N_SL layer are set sequentially from bottom to top, with the number of cycles ranging from 10 to 20.
2. The LED epitaxial wafer according to claim 1, characterized in that, The silicon doping concentration of the first N_SL layer is 1×10 18 ~5×10 18 / cm -3 Between; the silicon doping concentration of the second N_SL layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the first N_Bulk layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the second N-Bulk layer is 5×10. 18 ~1×10 19 / cm -3 between.
3. The LED epitaxial wafer according to claim 2, characterized in that, The thickness of the first N_SL layer is between 15 and 20 nm; the thickness of the second N_SL layer is between 30 and 35 nm; and the thickness of the N_SL layer is between 450 and 550 nm.
4. The LED epitaxial wafer according to claim 2, characterized in that, The thickness of the first N-Bulk layer is between 500 and 600 nm; the thickness of the second N-Bulk layer is between 500 and 600 nm; and the thickness of the N-Bulk layer is between 1000 and 1200 nm.
5. The LED epitaxial wafer according to claim 1, characterized in that, The quantum well light-emitting layer includes periodically arranged GaN layers and In layers. x Ga 1-x The N-layer has an x-value between 0.2 and 0.3 and a period number between 7 and 12; the GaN layer has a thickness between 8 and 12 nm; the In-layer has an In-value between 8 and 12 nm. x Ga 1-x The thickness of the N layer is between 2 and 5 nm.
6. A method for manufacturing an LED epitaxial wafer, used to manufacture the LED epitaxial wafer according to any one of claims 1-5, characterized in that, include: A substrate is prepared, and a buffer layer is grown on the substrate; the growth temperature of the buffer layer is between 800 and 1100°C. A U-shaped GaN layer is grown on the buffer layer; the growth temperature of the U-shaped GaN layer is between 1000 and 1400°C. A first N_SL layer and a second N_SL layer are sequentially grown on the U-shaped GaN layer to obtain an N_SL layer; the number of cycles is between 10 and 20; the growth temperature of the first N_SL layer is between 1000 and 1200°C; the growth thickness of the first N_SL layer is between 15 and 20 nm; the growth temperature of the second N_SL layer is between 1000 and 1200°C; the growth thickness of the second N_SL layer is between 30 and 35 nm. A first N_Bulk layer is grown on the N_SL layer; the growth temperature of the first N_Bulk layer is between 1000 and 1200°C; the growth thickness of the first N_Bulk layer is between 500 and 600 nm. A second N_Bulk layer is grown on the first N_Bulk layer; the growth temperature of the second N_Bulk layer is between 900 and 1100°C; the growth thickness of the second N_Bulk layer is between 500 and 600 nm. A quantum well light-emitting layer is grown on the second N-Bulk layer; the growth temperature of the quantum well light-emitting layer is between 700 and 800°C. A P-type electron blocking layer is grown on the quantum well light-emitting layer; the growth temperature of the P-type electron blocking layer is between 800 and 1000°C. A P-type GaN layer is grown on the P-type electron blocking layer; the growth temperature of the P-type GaN layer is between 900 and 1100 °C.
7. The method for manufacturing an LED epitaxial wafer according to claim 6, characterized in that, The silicon doping concentration of the first N_SL layer is 1×10 18 ~5×10 18 / cm -3 Between; the silicon doping concentration of the second N_SL layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the first N_Bulk layer is 1×10 19 ~3×10 19 / cm -3 Between; the silicon doping concentration of the second N-Bulk layer is 5×10. 18 ~1×10 19 / cm -3 between.