A relay protection device and method for preventing single-event upset

Abstract

The present invention discloses a relay protection device and method for preventing single-particle upsets. The relay protection device includes at least four cores, including a transceiver core and at least three logic cores, and the main frequency of each core is greater than or equal to 1.2GHz. The method includes the following steps: the transceiver core receives external data and performs preprocessing; the preprocessing includes performing basic parsing on the data and adding a CRC check code at the end of the data; each logic core performs a CRC check on the preprocessed data, and if the check is correct, performs export data calculation; the data after the export calculation is completed is subjected to export preprocessing; the export preprocessing includes adding a CRC check code to the data; the transceiver core first performs a CRC check on the data after the export preprocessing, and if the check is qualified, performs export logic judgment on the data, and if the judgment is qualified, exports the data. The present invention sets data verification in multiple links of the relay protection device, which can effectively eliminate data changed due to single-particle upsets, thereby reducing the operation risk of the backbone power grid.

Description

Technical Field

[0001] The present invention relates to a relay protection device and method for preventing single particle upset, belonging to the technical field of power system relay protection. Background Art

[0002] Particle radiation from high-energy particles (protons, electrons, heavy ions, etc.) in the atmosphere can severely impact electronic devices. When bombarded by these high-energy particles, the integrated circuit components in relay protection devices can experience a state flip, an effect known as a single-event upset. If a component's state flips erroneously, it can cause unstable operation or even fatal errors, leading to data acquisition errors. This is particularly serious in the field of relay protection. Therefore, designing and implementing integrated circuit components to mitigate the impact of single-event upsets is becoming increasingly important.

[0003] At the same time, relay protection devices are the first line of defense in the power system. They have four basic requirements: selectivity, speed, sensitivity, and reliability. They safeguard the safe and stable operation of the power grid. In particular, medium and high voltage relay protection devices directly guarantee the safe operation of the main power grid. Therefore, reliable software and hardware design is particularly important in medium and high voltage relay protection devices to avoid the impact of false operation caused by single particle upsets. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of the existing technology and provide a relay protection device and method for preventing single-particle upsets. By setting data verification in multiple links of the relay protection device, data changed due to single-particle upsets can be effectively eliminated to reduce the operation risk of the main power grid.

[0005] To achieve the above objectives, in a first aspect, the present invention provides a relay protection device for preventing single event upsets, wherein the relay protection device has at least four cores, and the cores of the relay protection device include:

[0006] The transceiver core is used to receive and send data, add CRC check code to the received data, and perform CRC check on the data to be exported;

[0007] and a logic core, for performing logic operations, adding a CRC check code to the data after the logic operations, and performing a CRC check on the received data, wherein at least three logic cores are provided;

[0008] Each of the logic cores is communicatively connected to the transceiver core.

[0009] Furthermore, the number of the core processors is 4.

[0010] Furthermore, the main frequency of each core processor is greater than or equal to 1.2 GHz.

[0011] In a second aspect, the present invention provides a method for preventing a single event upset based on the relay protection device described in the first aspect, comprising the following steps:

[0012] The transceiver core receives external data and performs preprocessing; preprocessing includes basic parsing of the data and adding a CRC checksum to the end of the data;

[0013] Each logic core performs CRC check on the pre-processed data, and if the check is correct, the export data calculation is performed;

[0014] Each logic check performs pre-export processing on the data after the export calculation is completed; wherein, the pre-export processing includes adding a CRC check code to the data;

[0015] The data processed before export is first subjected to CRC check by the sender and receiver. If the check is qualified, the data is subjected to export logic judgment. If the judgment is qualified, the data is exported.

[0016] Furthermore, the data received by the transceiver core includes: switch value data and analog value data.

[0017] Furthermore, the data is subjected to export logic judgment, and if the judgment is qualified, the data is exported, including:

[0018] The data in the three logical cores are compared in groups of two. If the comparison results are consistent, the consistent results are exported. If the comparison results are not consistent after all comparisons are completed, they are not exported.

[0019] The beneficial effects achieved by the present invention are:

[0020] (1) Through multi-core (quad-core and above) operation, the system is divided into the receiving and transmitting core and the logic core to operate independently, thus achieving independent operation of multiple relay protection logics without mutual interference.

[0021] (2) The correctness of the device input data is ensured by adding a CRC check code to the original received data. The check is added at the source, so that whether the data is correct can be identified in subsequent transmissions, thereby avoiding the situation where a single particle upset destroys the data without perception.

[0022] (3) By transmitting data between the transceiver core and the logic core with CRC checksum, the reliability of data transmission between multiple cores is guaranteed, thereby avoiding the possibility of data tampering and calculation logic errors caused by single-particle flips in components within the device.

[0023] (4) Through the "software three out of two" logical judgment of the export data, the impact of single-particle upset on a certain core logic is avoided, and the probability of two single-particle upsets occurring simultaneously in the same device is basically zero, ensuring the reliability of the relay protection device export and meeting the four requirements of relay protection. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a block diagram of the architecture of a multi-core processor in a relay protection device and method for preventing single event upsets provided by an embodiment of the present invention;

[0025] Figure 2 This is a flow chart of data transmission between cores of a multi-core processor with CRC check in a relay protection device and method for preventing single event upset provided by an embodiment of the present invention;

[0026] Figure 3 This is a schematic diagram of a relay protection device and method for preventing single-particle upsets provided by an embodiment of the present invention for verifying data processed before receiving and sending a check. DETAILED DESCRIPTION

[0027] The present invention will be further described below in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solutions of the present invention and are not intended to limit the scope of protection of the present invention.

[0028] Glossary of prior art: CRC: Cyclic Redundancy Check (CRC).

[0029] Example 1:

[0030] The first embodiment of the present invention provides a relay protection device for preventing single event upset, such as Figure 1 and Figure 2As shown, the relay protection device includes at least four core processors, and the core processor includes a transceiver core and a logic core. The transceiver core and the logic core are communicatively connected. The transceiver core is used to receive and send data, and add a CRC check code to the data when receiving data. The CRC check is performed before the data is exported. The CRC check code is added at the source of data processing, which helps to identify whether the data is correct in subsequent transmission, and can avoid the situation where a single particle upset destroys the data without perception. The logic core is used to perform logical operations on the data and perform CRC checks on the received data. The logic core performs logical operations after receiving the data from the transceiver core, and performs CRC checks on the received data. After the calculation is completed, a CRC check code is added to the data, and then it is sent to the transceiver core for sending operation. Since the probability of two single-particle upsets occurring at the same time in the same device is 0, in order to ensure the reliability of the export data of the relay protection device and facilitate the "software three out of two" logical judgment of the export data, at least three logic cores are set, which perform logical operations independently without interfering with each other. In the embodiment of the present invention, on the basis of ensuring the implementation of the operation, cost savings are achieved at the same time. This device uses a relay protection device with 4 core processors, and the main frequency of each core processor is not less than 1.2GHz, of which 3 core processors are logic cores and 1 core processor is a transceiver core.

[0031] Example 2:

[0032] Based on the relay protection device for preventing single-particle upset provided in the first embodiment, the second embodiment of the present invention provides a method for preventing single-particle upset, such as Figures 1 to 3 As shown, the present invention uses a relay protection device with at least four core processors. In the relay protection device, one core is used as a transceiver core for receiving and sending data, while the remaining cores are used as logic cores, each communicating with the transceiver core for performing logical calculations and processing. This enables multiple relay protection logics to operate independently without interfering with each other. The present invention adds a CRC checksum to the original received data to effectively ensure the correctness of the input data. This method of adding checksums at the source can also ensure the correctness of the data during subsequent transmission, avoiding the loss of detection when a single-particle upset occurs. The present invention also adds a CRC checksum when data is transferred between the transceiver core and the logic core, effectively ensuring the reliability of data transmission between multiple cores, preventing data tampering caused by single-particle upsets in components during transmission within the device, and avoiding calculation logic errors. The present invention performs a "software three-out-of-two" logical judgment on the output data before export. Since the probability of two single-particle upsets occurring simultaneously in the same device is essentially zero, the "software three-out-of-two" judgment can effectively ensure the reliability of the relay protection device export and meet the requirements of the four properties of relay protection.

[0033] The second embodiment of the present invention provides a method for preventing single event upset, such as Figure 1 As shown, as described in Example 1, in order to ensure the completion of the "software three out of two" logical judgment, a relay protection device with at least four core processors should be selected. In the embodiment of the present invention, under the premise of ensuring the function is realized, in order to save industrial costs, a relay protection device with four cores is selected; among them, one core is used as a transceiver core for receiving and sending data, and the remaining three cores are used as logic cores for performing logical operations of relay protection. Each logic core is communicated with the transceiver core, and each logic core independently runs the logical operation of relay protection without interfering with each other.

[0034] like Figure 2 As shown, on the basis of the above, after the external switch quantity data and analog quantity data enter the relay protection device, the transceiver core in the relay protection device receives these external data, and after receiving the data, performs basic analysis on the received data, and then adds a CRC check code at the end of the data after the basic analysis is completed, and then puts the data with the CRC check code into the inter-core shared memory for use by the three logic cores. The above operation can effectively ensure the correctness of the device input data, and add verification at the source, so that the data can be identified whether it is correct in subsequent transmissions, thereby avoiding the single particle flip phenomenon of the components in the relay protection device, which destroys the data without perception.

[0035] When each logic core is operating, it first takes out the data it needs to use from the inter-core shared memory, and then performs a CRC code check on the data. If the check passes, the data is prepared for export, and the export data is calculated for the data to be exported. If the check fails, the data is not exported. Through the above design, the present invention can effectively avoid the miscalculation phenomenon that occurs in the calculation logic when the data is incorrect due to a single-particle upset.

[0036] After each logic core completes the calculation of the export data, it adds a CRC check code to the end of the export data, and then stores the export data with the CRC check code into the inter-core shared memory again so that the sending and receiving cores can read it;

[0037] like Figure 3 As shown, after the transceiver core reads the data, it first performs a CRC check on the data. After the CRC check passes, the data is subjected to an export logic judgment. If the judgment passes, the data is exported. The specific steps include the following:

[0038] The data of the three logical cores are compared in groups of two. If the comparison results are consistent, the consistent results are exported. If the comparison results are still not consistent after all comparisons are completed, no export is made this time. In the specific implementation, three logical cores are first arbitrarily designated as logical core 1, logical core 2 and logical core 3. The naming of the logical cores is mainly for the convenience of verification description and there is no special requirement. Then the data of logical core 1 and logical core 2 are compared. If the two data are consistent, the data are directly exported as export data; otherwise, the data of logical core 1 and logical core 3 are compared. If they are consistent, they are exported; otherwise, the data of logical core 2 and logical core 3 are compared. If they are consistent, they are exported. If they are inconsistent, no export is made this time. In the present invention, the above-mentioned "software three out of two" logical judgment can avoid malfunction of the export, because a single particle can affect the component data of one core processor at most, and will not affect multiple core processors at the same time. With the above-mentioned method, the influence of single particle flip on the export data can be effectively avoided.

[0039] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for preventing a relay protection device from a single event upset, characterized in that: The relay protection device has at least four cores, and the cores of the relay protection device include: The transceiver core is used to receive and send data, add CRC check code to the received data, and perform CRC check on the data to be exported; and a logic core, for performing logic operations, adding a CRC check code to the data after the logic operations, and performing a CRC check on the received data, wherein at least three logic cores are provided; Each of the logic cores is communicatively connected to the transceiver core; The method for preventing a relay protection device from a single event upset comprises the following steps: The transceiver core receives external data and performs preprocessing, wherein the preprocessing includes parsing the data and adding a CRC checksum to the end of the data. Each logic core performs CRC check on the pre-processed data, and if the check is correct, the export data calculation is performed; Each logic check performs pre-export processing on the data after the export calculation is completed; wherein, the pre-export processing includes adding a CRC check code to the data; The sender and receiver perform CRC check on the data processed before export. If the check is qualified, the data will be subjected to export logic judgment. If the judgment is qualified, the data will be exported; The data received by the transceiver core includes: switch data and analog data; Perform export logic judgment on the data. If the judgment is qualified, the data will be exported, including: The data in the three logical cores are compared in groups of two. If the comparison results are consistent, the consistent results are exported. If the comparison results are not consistent after all comparisons are completed, they are not exported.

2. The method for preventing a relay protection device from a single event upset according to claim 1, characterized in that: The number of cores is 4.

3. The method for preventing a relay protection device from a single event upset according to claim 1, characterized in that: The main frequency of each core is greater than or equal to 1.2GHz.

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