Pulse width modulation controller for hybrid converter
By using the PWM controller of the hybrid converter, and combining threshold generation and regulation circuits with comparators, the efficiency and stability problems caused by power stage mismatch are solved, achieving efficient and stable voltage conversion and reducing switching losses and the risk of circuit damage.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ANALOG DEVICES INC
- Filing Date
- 2021-12-24
- Publication Date
- 2026-06-02
AI Technical Summary
The efficiency of existing low dropout (LDO) series regulators is limited by the ratio of output voltage to supply voltage. Switching regulators are difficult to guarantee stability and efficiency when power stage mismatch occurs, resulting in unstable current supply and excessive power loss.
The pulse width modulation (PWM) controller using a hybrid converter achieves stable control of the switch through a combination of threshold generation circuit, threshold adjustment circuit and comparator, compensates for power stage mismatch and asymmetry, and ensures current matching between the inductor and the flying capacitor.
It improves the stability and efficiency of the hybrid converter, reduces the switching losses of power transistors, supports high-frequency operation and efficient voltage conversion, and avoids circuit damage and reliability issues.
Smart Images
Figure CN114825926B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to electronic systems, and more specifically, to electronic power conversion. Background Technology
[0002] Voltage regulators are used to produce a substantially constant output voltage from a specified poor and / or fluctuating supply voltage or other input voltage source. Series regulators and switching regulators are two common types of voltage regulators. Low dropout (LDO) series regulators offer good regulation with extremely low noise; however, the current supply from the regulated output comes directly from the supply voltage. Therefore, the efficiency of an LDO series regulator is limited by the ratio of the output voltage to the supply voltage, and thus the efficiency of an LDO series regulator decreases rapidly as the supply voltage increases relative to the output voltage.
[0003] Switching regulators are generally more efficient than series regulators. A switching regulator employs one or more switches (e.g., power transistors) coupled in series and / or parallel to an output terminal that supplies the output voltage to the load. Furthermore, the controller turns the switches on and off to control the delivery of current pulses to the output terminal. One or more energy storage elements, such as inductors and / or capacitors, can be used to convert the switched current pulses into a stable load current. Summary of the Invention
[0004] This document provides a pulse width modulation (PWM) controller for a hybrid converter. In some embodiments, a PWM controller for a hybrid converter includes: a threshold generation circuit for generating a threshold signal based on the output voltage of the hybrid converter; a threshold adjustment circuit for generating an adjusted threshold signal based on sensing the voltage of a flying capacitor of the hybrid converter; and a comparator for generating a comparison signal based on comparing the adjusted threshold signal with an indication of inductor current of the hybrid converter. The output of the comparator is used to generate PWM control signals for turning on and off switches (e.g., power transistors) of the hybrid converter. By implementing the PWM controller in this way, stable operation of the hybrid converter is achieved even when power stage mismatch exists and / or the PWM controller has asymmetry in the circuitry used to generate the PWM control signals for the power stage of the hybrid converter.
[0005] In one aspect, a power conversion system includes a power converter and a PWM controller. The power converter is configured to generate a regulated output voltage based on an input voltage and includes a first inductor, a first capacitor, and a first set of switches configured to control the electrical connection between the first inductor and the first capacitor. The PWM controller includes: a threshold generation circuit configured to generate a threshold signal based on the regulated output voltage; a first threshold adjustment circuit configured to generate a first regulated threshold signal by adjusting the threshold signal based on the input voltage and the voltage of the first capacitor; a first comparator configured to compare a current through the first inductor with the first regulated threshold signal; and a switch control circuit configured to generate at least one control signal for controlling the first set of switches based on the output of the first comparator.
[0006] In another aspect, a power conversion method includes: generating an regulated output voltage using a power converter based on an input voltage, the power converter including a first inductor, a first capacitor, and a first set of switches for controlling the electrical connection between the first inductor and the first capacitor; generating a threshold signal using a threshold generation circuit based on the regulated output voltage; generating a first regulated threshold signal using a first threshold adjustment circuit by adjusting the threshold signal based on the input voltage and the voltage of the first capacitor; comparing the current through the first inductor with the first regulated threshold signal using a first comparator; and controlling the first set of switches based on the output of the first comparator.
[0007] In another aspect, a PWM controller includes: a threshold generation circuit configured to generate a threshold signal based on an regulated output voltage of a power converter; a first threshold adjustment circuit configured to generate a first regulated threshold signal by adjusting the threshold signal based on an input voltage of the power converter and a first capacitor voltage of the power converter; a first comparator configured to compare a first inductor current of the power converter with the first regulated threshold signal; and a switch control circuit configured to generate at least one switch control signal for the power converter based on the output of the first comparator. Attached Figure Description
[0008] Figure 1A This is a schematic diagram of an example of a buck converter.
[0009] Figure 1B Is for display Figure 1A A graph showing an example of the control signal and inductor current waveform of a buck converter.
[0010] Figure 1C Is for display Figure 1AA graph showing an example of transistor current, transistor voltage, and transistor power loss in a buck converter.
[0011] Figure 2A This is a schematic diagram of an example of a hybrid converter.
[0012] Figure 2B It is used for Figure 2A A schematic diagram of an embodiment of the control logic circuit system of a hybrid converter.
[0013] Figure 2C It is used for Figure 2A A schematic diagram of an example of low duty cycle regulation of a hybrid converter.
[0014] Figure 2D It is used for Figure 2A A schematic diagram of an example of a high duty cycle regulation of a hybrid converter.
[0015] Figure 3A This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the first operating stage of the hybrid converter.
[0016] Figure 3B This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the second and fourth operating stages of the hybrid converter.
[0017] Figure 3C This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the third operating stage of the hybrid converter.
[0018] Figure 4A This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the first operating stage of the hybrid converter.
[0019] Figure 4B This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the second and fourth operating stages of the hybrid converter.
[0020] Figure 4C This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the third operating stage of the hybrid converter.
[0021] Figure 5 This is a schematic diagram of a hybrid power conversion system according to one embodiment.
[0022] Figure 6A It is used for Figure 5An example of instantaneous performance simulation of a hybrid power conversion system without power stage mismatch.
[0023] Figure 6B yes Figure 6A The extended part of the instantaneous performance simulation.
[0024] Figure 7A It is used for Figure 5 An example of instantaneous performance simulation of a hybrid power conversion system with power stage mismatch.
[0025] Figure 7B yes Figure 7A The extended part of the instantaneous performance simulation.
[0026] Figure 8 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0027] Figure 9 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0028] Figure 10A It is used for Figure 9 An example of instantaneous performance simulation of a hybrid power conversion system with flight capacitor mismatch.
[0029] Figure 10B It is used for Figure 9 An example of instantaneous performance simulation of a hybrid power conversion system with comparator mismatch.
[0030] Figure 11 It is used for Figure 9 An example of instantaneous performance simulation of a hybrid power conversion system with inductor mismatch.
[0031] Figure 12 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0032] Figure 13 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0033] Figure 14 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0034] Figure 15 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0035] Figure 16 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0036] Figure 17 This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0037] Figure 18 It is used for Figure 17 An example of instantaneous performance simulation of a hybrid power conversion system with inductor mismatch, flying capacitor mismatch, comparator mismatch, and current sensing gain mismatch.
[0038] Figure 19A This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0039] Figure 19B This is a schematic diagram of a hybrid power conversion system according to another embodiment.
[0040] Figure 19C This is a schematic diagram of a hybrid power conversion system according to another embodiment. Detailed Implementation
[0041] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention can be implemented in many different ways. In this description, reference is made to the accompanying drawings, wherein like reference numerals may indicate the same or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. Furthermore, it will be understood that some embodiments may include more elements than shown in the drawings and / or a subset of the elements shown in the drawings. Additionally, some embodiments may combine any suitable combination of features from two or more drawings.
[0042] Figure 1A This is a schematic diagram of an example of a buck converter 10. Figure 1B Is for display Figure 1A A graph illustrating an example of the control signal and inductor current waveform of the buck converter 10. Figure 1C Is for display Figure 1A A graph illustrating an example of transistor drain current, transistor drain-source voltage, and transistor power loss in a buck converter 10.
[0043] The buck converter 10 includes a top power transistor M1, a bottom power transistor M2, an inductor L, and an output capacitor C. OUT The buck converter receives the input voltage V. IN And generate a voltage less than the input voltage V IN Output voltage V O In this example, the output voltage V O It is supplied to an external load. The top power transistor M1 is connected to the input voltage V. IN Between the switching node SW and ground, the bottom power transistor M2 is connected between the switching node SW and ground, and the inductor L is connected between the switching node SW and the output voltage V. O Between, and the output capacitor COUT Connected to the output voltage V O Between and ground.
[0044] exist Figure 1A In this example, the top power transistor M1 is controlled by the top control signal T, and the bottom power transistor M2 is controlled by the bottom control signal B. By adjusting or modulating the widths of the top control signal T and the bottom control signal B, the output voltage V is obtained. O The adjustment.
[0045] For example, when the top control signal T is high, the top power transistor M1 is turned on, and when the complementary bottom control signal B is high, the bottom power transistor M2 is turned on. When the top power transistor M1 is turned on, the input voltage V... IN The current i is applied to the switching node SW and flows through the inductor L. L Ramp-up. When the bottom power transistor M2 is turned on, a ground potential is applied to the switching node SW, and the inductor current i L Slope.
[0046] This operation is repeated periodically, and the switching period is T. SW The on-time of the top power transistor M1 and the switching period T SW The ratio of [the percentage of work cycles] is called the work cycle.
[0047] Due to the inductor current i L The ramp-up slope is determined by the switching node SW and the output voltage V. O The voltage difference between the two current sources determines the current ripple amplitude, resulting in a larger current ripple amplitude at lower switching frequencies. Therefore, to support a given DC output load current, a larger inductor L is selected to avoid inductor saturation under peak current.
[0048] The on / off transition of power transistors used in power converters cannot be completed in zero time. During the transition time, both the drain-to-source voltage and the current through the power transistor are not zero. This results in switching losses for each transition of the power transistor from on to off or from off to on. The higher the drain-to-source voltage at which the power transistor blocks, the higher the switching losses during each switching operation.
[0049] For example, in Figure 1C In one example, for a typical state transition, waveforms of the voltage, current, and power loss of the top power transistor M1 are shown.
[0050] Switching losses limit the practical maximum switching frequency. However, small power supplies require high switching frequencies.
[0051] Figure 2AThis is a schematic diagram of one embodiment of the hybrid converter 111. Figure 2B It is used for Figure 2A A schematic diagram of an embodiment of the control logic circuit system of the hybrid converter 111. Figure 2C It is used for Figure 2A A schematic diagram of an example of low duty cycle regulation of the hybrid converter 111. Figure 2D It is used for Figure 2A A schematic diagram of an example of the high duty cycle regulation of the hybrid converter 111.
[0052] The hybrid converter 111 includes a first half-power stage P1, which includes a first power transistor Q1, a second power transistor Q2, a third power transistor Q3, a fourth power transistor Q4, a first inductor L1, and a first switched capacitor C. fly1 (Also referred to herein as a flying capacitor). The hybrid converter 111 further includes a second half-power stage P2, which includes a fifth power transistor Q5, a sixth power transistor Q6, a seventh power transistor Q7, an eighth power transistor Q8, a second inductor L2, and a second flying capacitor C. fly2 The hybrid converter 111 uses at least one inductor and at least one switched capacitor for regulation, and is therefore a hybrid converter.
[0053] like Figure 2A As shown, the hybrid converter 111 receives the input voltage V from the input terminal. IN and connected to the output capacitor C OUT The output terminal provides the output voltage V O Despite Figure 2A Not shown, however, the output terminals of the hybrid converter 111 can be coupled to any desired load. In this embodiment, the hybrid converter 111 operates with a duty cycle d, which is relative to 2V. O / V IN The ratio varies.
[0054] like Figure 2A As shown, the first power transistor Q1 and the second power transistor Q2 are connected in series at the input voltage V. IN Between the intermediate node MID and the first flying capacitor C fly1 A fourth power transistor Q4 is connected between the source of the first power transistor Q1 and the first switching node SW1. The fourth power transistor Q4 is connected between the first switching node SW1 and ground, while the first inductor L1 is connected between the first switching node SW1 and the output voltage V. O Between. The fifth power transistor Q5 and the sixth power transistor Q6 are connected in series at the input voltage V. IN Between the intermediate node MID and the second flying capacitor C fly5The fifth power transistor Q5 is connected between its source and the second switching node SW2. The eighth power transistor Q8 is connected between the second switching node SW2 and ground, while the second inductor L2 is connected between the second switching node SW2 and the output voltage V. O The third power transistor Q3 is connected between the first switching node SW1 and the intermediate node MID, while the seventh power transistor Q7 is connected between the second switching node SW2 and the intermediate node MID.
[0055] Compared to Figure 1A The step-down converter 10, Figure 2A The hybrid converter 111 operates with reduced switching losses in the power transistors, thereby allowing operation at higher frequencies. Furthermore, even when V... O It is from V IN When the voltage drop is large (e.g., when the voltage drop is at a ratio of 4:1 or greater, for example, from 48V to 12V), the hybrid converter 111 also operates with high efficiency.
[0056] like Figures 2A-2D As shown, the first to eighth power transistors Q1-Q8 are controlled by control signals A, A', B, B', C, and D, where A' is the complementary signal of A, and B' is the complementary signal of B. Since this example uses an n-type field-effect transistor (NFET) to implement the power transistors, the corresponding power transistor is turned on when the given control signal is high. However, p-type transistors, n-type and p-type transistors, and / or other types of switches can also be used. Figure 2B As shown in the example, D is produced by (B and A') using the first AND gate, while C is produced by (A and B') using the second AND gate.
[0057] When operating in a steady state and when the hybrid converter 111 stabilizes, the flying capacitor remains approximately equal to V. IN 1 / 2 of the DC voltage.
[0058] Figure 3A This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the first operating stage of the hybrid converter 111.
[0059] like Figure 3A As shown, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Therefore, the second flying capacitor C... fly2 and the first flight capacitor C fly1 Connected in series with input voltage V IN Between and ground. In addition, the current through inductor L1 slopes down, while the current through inductor L2 slopes up.
[0060] Figure 3B This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the second and fourth operating stages of the hybrid converter 111.
[0061] like Figure 3B As shown, power transistors Q4 and Q8 are turned on, while the remaining power transistors are turned off. Therefore, the current through inductor L1 and the current through inductor L2 both decrease at a steeper angle.
[0062] Figure 3C This is according to one embodiment for low duty cycle adjustment. Figure 2A A schematic diagram of the third operating stage of the hybrid converter 111.
[0063] like Figure 3C As shown, power transistors Q1, Q3, Q6, and Q8 are turned on, while the remaining power transistors are turned off. Therefore, the first flying capacitor C... fly1 and the second flight capacitor C fly2 Connected in series with input voltage V IN Between and ground. In addition, the current through inductor L1 ramps up, while the current through inductor L2 ramps down.
[0064] refer to Figures 3A-3C The hybrid converter 111 can be cyclically passed through the first operation phase by making the hybrid converter 111 ( Figure 3A ), second operation stage ( Figure 3B ), third operation stage ( Figure 3C ) and the fourth operational phase ( Figure 3B Regulation can be provided through the fourth operating stage. Figure 3B Return to the first operation phase ( Figure 3A This is repeated to adjust the cycle. This operation can correspond to low duty cycle (d) operation, for example, d is less than fifty percent.
[0065] Figure 4A This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the first operating stage of the hybrid converter 111.
[0066] like Figure 4A As shown, power transistors Q2, Q4, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Therefore, the second flying capacitor C... fly2 and the first flight capacitor C fly1 Connected in series with input voltage V IN Between and ground. In addition, the current through inductor L1 slopes down, while the current through inductor L2 slopes up.
[0067] Figure 4B This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the second and fourth operating stages of the hybrid converter 111.
[0068] like Figure 4B As shown, power transistors Q1, Q3, Q5, and Q7 are turned on, while the remaining power transistors are turned off. Therefore, the current through inductor L1 and the current through inductor L2 both increase at a ramp rate. Furthermore, paths are provided through power transistors Q3 and Q7 to allow the first flying capacitor C to... fly1 The second end is connected to the second flight capacitor C fly2 The second end.
[0069] Figure 4C This is according to one embodiment for high duty cycle adjustment. Figure 2A A schematic diagram of the third operating stage of the hybrid converter 111.
[0070] like Figure 4C As shown, power transistors Q1, Q3, Q6, and Q8 are turned on, while the remaining power transistors are turned off. Therefore, the first flying capacitor C... fly1 and the second flight capacitor C fly2 Connected in series with input voltage V IN Between and ground. In addition, the current through inductor L1 ramps up, while the current through inductor L2 ramps down.
[0071] refer to Figures 4A-4C The hybrid converter 111 can be cyclically passed through the first operation phase by making the hybrid converter 111 ( Figure 4A ), second operation stage ( Figure 4B ), third operation stage ( Figure 4C ) and the fourth operational phase ( Figure 4B Regulation can be provided through the fourth operating stage. Figure 4B Return to the first operation phase ( Figure 4A This is used to repeatedly adjust the cycle. This operation can correspond to a high duty cycle (d) operation, for example, d greater than or equal to 50%.
[0072] Figure 5 This is a schematic diagram of a hybrid power conversion system 110 according to one embodiment. The hybrid power conversion system 110 includes a hybrid converter 111 and a PWM controller 102. Figure 5 As shown, the output voltage V of the hybrid converter 111 O It is supplied to the load and is also sensed by the PWM controller 102 to help generate control signals for the power transistors of the hybrid converter.
[0073] In the illustrated embodiment, the PWM controller 102 includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a third capacitor C3, an error amplifier EA, a first comparator PWMCMP1, and a second comparator PWMCMP2.
[0074] The PWM controller 102 provides closed-loop feedback to the hybrid converter 111. For example, the first resistor R1 and the second resistor R2 are used as a voltage divider to output a voltage V based on the divided output voltage. O This generates a feedback voltage FB. The error amplifier EA amplifies the error between the feedback voltage FB and the DC reference voltage REF to generate the comparison threshold signal COMP.
[0075] The first comparator PWMCMP1 generates a first PWM control signal A by comparing the comparison threshold signal COMP with the first sawtooth ramp signal RAMP1, while the second comparator PWMCMP2 generates a second PWM control signal B by comparing the comparison threshold signal COMP with the second sawtooth ramp signal RAMP2. The third PWM control signal C and the fourth PWM control signal D can be used... Figure 2B The configuration generates the signal, while the inverter can be used to generate a logically inverted version of any PWM control signal.
[0076] Continue to refer to Figure 5 The first sawtooth ramp signal RAMP1 and the second sawtooth ramp signal RAMP2 can be generated in various ways and can have a phase difference of about 180 degrees, respectively corresponding to the sensed current flowing through the first inductor L1 and the second inductor L2.
[0077] When the feedback voltage FB is lower than the DC reference voltage REF, the comparison threshold signal COMP rises, and the duty cycle d increases. Conversely, when the feedback voltage FB is higher than the DC reference voltage REF, the comparison threshold signal COMP falls, and the duty cycle d decreases. Therefore, the output voltage V is provided. O The PWM controller 102 includes a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a third capacitor C3 to provide stability compensation.
[0078] Figure 6A It is used for Figure 5 An example of instantaneous performance simulation of a hybrid power conversion system 110 without power stage mismatch. Figure 6B yes Figure 6A The extended part of the instantaneous performance simulation.
[0079] Simulation observation of step changes in load current (I) LOADThe instantaneous response of the hybrid converter 111 under a current step, wherein the first flying capacitor C fly1 and the second flight capacitor C fly2 The capacitances are equal, and the inductances of the first inductor L1 and the second inductor L2 are equal, and the comparators in the PWM controller 102 have the same delay and input offset.
[0080] like Figure 6A and Figure 6B As shown, the output voltage V O After a brief and momentary deviation, the voltage stabilizes and returns to oscillation-free regulation. Therefore, the stability compensation operates normally under analog conditions.
[0081] Figure 7A It is used for Figure 5 An example of instantaneous performance simulation of a hybrid power conversion system 110 with power stage mismatch. Figure 7B yes Figure 7A The extended part of the instantaneous performance simulation.
[0082] In reality, the hardware circuitry components of a hybrid converter will never be exactly the same. Therefore, Figure 2A and Figure 5 The first half-power stage P1 and the second half-power stage P2 of the hybrid converter 111 may suffer from many mismatches, including but not limited to comparator delay imbalance and first flying capacitor C. fly1 and the second flight capacitor C fly2 The capacitance difference and / or the inductance difference between the first inductor L1 and the second inductor L2.
[0083] Figure 7A and Figure 7B simulation and Figure 6A and Figure 6B The simulation is the same, except in Figure 7A and Figure 7B In the simulation, the inductance of the first inductor L1 is less than the inductance of the second inductor L2.
[0084] like Figure 7A and Figure 7B As shown, inductor mismatch causes the first flying capacitor C of the hybrid converter 111 to... fly1 and the second flight capacitor C fly2 The voltage across the terminals becomes uncontrolled, and the currents through the first inductor L1 and the second inductor L2 are unequal. This, in turn, leads to excessive power loss on the hybrid converter 111, causing reliability issues, and / or immediate circuit damage (e.g., circuit explosion) due to electrical overload on the capacitors and / or power transistors.
[0085] This document provides a PWM controller for a hybrid converter. In some embodiments, a PWM controller for a hybrid converter includes: a threshold generation circuit for generating a threshold signal based on the output voltage of the hybrid converter; a threshold adjustment circuit for generating an adjusted threshold signal based on sensing the voltage of a flying capacitor of the hybrid converter; and a comparator for generating a comparison signal based on comparing the adjusted threshold signal with an indication of inductor current of the hybrid converter. The output of the comparator is used to generate PWM control signals for turning on and off a switch (e.g., a power transistor) of the hybrid converter.
[0086] By implementing the PWM controller in this way, stable operation of the hybrid converter can still be achieved even when power stage mismatch exists and / or the PWM controller has asymmetry in the circuitry used to generate the PWM control signal for the power stage of the hybrid converter.
[0087] Figure 8 This is a schematic diagram of a hybrid power conversion system 120 according to another embodiment. The hybrid power conversion system 120 includes a hybrid converter 111 and a PWM controller 112.
[0088] In the illustrated embodiment, the PWM controller 112 includes a threshold generation circuit 113, a threshold adjustment circuit 114, a first comparator 115, a second comparator 116, and a switch control circuit 117.
[0089] Threshold generation circuit 113 is based on output voltage V O Generate a threshold signal THRESH. The threshold signal THRESH can be generated in various ways, including but not limited to using the output voltage V... O A portion of the error amplifier is compared with a reference signal. In this example, the threshold signal THRESH is provided to the first comparator 115 and the second comparator 116.
[0090] like Figure 8 As shown, the PWM controller 112 includes a threshold adjustment circuit 114, which is used to adjust the threshold based on the first flying capacitor voltage V. Cfly1 and input voltage V IN Adjust the comparison threshold of the first comparator 115. This adjustment can be based on the voltage V of the first flying capacitor. Cfly1 With input voltage V IN A comparison of some parts.
[0091] Although an example of adjusting the threshold of the first comparator 114 is shown, the teachings herein also apply to configurations for adjusting the threshold of the second comparator 116, as well as configurations for adjusting the thresholds of the first comparator 115 and the second comparator 116 separately. For example, the adjusted threshold of the second comparator 116 may be based on the voltage V of the second flying capacitor. Cfly2 With input voltage V IN A comparison of some parts.
[0092] The first comparator 115 compares the adjusted threshold with the sensed current through the first inductor L1. Furthermore, the second comparator 116 compares the threshold signal THRESH with the sensed current through the second inductor L2.
[0093] The current through the first inductor L1 and the current through the second inductor L2 can be sensed in any suitable manner. In a first example, a small resistor is included in series with the inductor, and the detected voltage across the small resistor is used to sense the current through the inductor. In a second example, a DC resistance (DCR) sensor of the inductor is used to sense the current through the inductor. The DCR sensor may include connecting a resistor-capacitor (RC) network in parallel with the inductor, and designing the product of the resistance and capacitance of the RC network to be approximately equal to the ratio of the inductor's inductance to its parasitic resistance. When configured in this way, the voltage across the capacitor of the RC network is proportional to the current through the inductor.
[0094] Although two examples of inductor current sensing are provided, any suitable technique for measuring inductor current can be used.
[0095] The switch control circuit 117 generates various control signals (A, A', B, B', C, and D in this example) to turn the power transistors of the hybrid converter 111 on or off. The pulse width of the control signals is controlled based on the comparison results generated from the first comparator 115 and the second comparator 116.
[0096] By implementing a PWM controller 112 with threshold regulation, compensation is provided for the asymmetry between the first half-power stage and the second half-power stage. This asymmetry may include C fly1 / C fly2 The mismatch between L1 and L2, the mismatch between L1 and L2, and / or the mismatch of the delays of the first comparator 115 and the second comparator 116.
[0097] In some embodiments herein, the PWM controller (e.g., Figure 8 The PWM controller 112 is implemented on the semiconductor die. Furthermore, the hybrid converter (e.g., Figure 8The hybrid converter 111 can be implemented in part using off-chip components such as discrete power transistors for enhanced power handling and / or heat dissipation capabilities.
[0098] Figure 9 This is a schematic diagram of a hybrid power conversion system 150 according to another embodiment. The hybrid power conversion system 150 includes a hybrid converter 121 and a PWM controller 122.
[0099] Figure 9 The hybrid converter 121 is similar to Figure 2A The hybrid converter 111, in addition to the hybrid converter 121, further includes a first current sensing circuit 123 for sensing the current through the first inductor L1 and a second current sensing circuit 124 for sensing the current through the inductor L2. The first current sensing circuit 123 and the second current sensing circuit 124 can provide current sensing in a variety of ways, including but not limited to DCR sensing and / or sensing the voltage across a series resistor.
[0100] In the illustrated embodiment, the PWM controller 122 includes a first resistor R1, a second resistor R2, an error amplifier EA, a first half-range limiter 125, a second half-range limiter 126, a first controlled voltage source 127, a second controlled voltage source 128, an amplifier stability network 129, a first comparator CMP1, a second comparator CMP2, a first set / reset (S / R) latch RS1, a second S / R latch RS2, a top voltage divider resistor R5, a bottom voltage divider resistor R6, a first sampling switch 131, a second sampling switch 132, a first sampling capacitor C1, a second sampling capacitor C2, a first gain circuit GAIN1, and a second gain circuit GAIN2. Although one embodiment of the implemented PWM controller 122 has been described, the teachings herein apply to PWM controllers implemented in various ways. Therefore, other implementations are possible.
[0101] like Figure 9 As shown, the top voltage divider resistor R5 and the bottom voltage divider resistor R6 are connected as a resistive voltage divider, which generates a voltage divider approximately equal to the input voltage V. IN Approximately half of the voltage signal is HALFVIN. Therefore, R5 and R6 can have nominally equal resistance values.
[0102] In the illustrated embodiment, the first sampling switch 131 and the second sampling switch 132 are respectively connected between the intermediate node MID and the first sampling capacitor C1 and the second sampling capacitor C2.
[0103] When power transistor Q2 is turned on by control signal C (e.g.) Figure 2C and Figure 2DAs shown, when C is active, power transistor Q4 is also turned on by A', and the first sampling switch 131 is also turned on to turn on the first flying capacitor C. fly1 The voltage is stored in the first sampling capacitor C1. Furthermore, the difference between the sampled voltage of the first sampling capacitor C1 and the voltage signal HALFVIN is amplified by the first gain circuit GAIN1. A first half-limiter 125 is used to limit the output of the first gain circuit GAIN1. Specifically, when the output of the first gain circuit GAIN1 is negative, the output of the first half-limiter 125 is zero. However, when the output of the first gain circuit GAIN1 is positive, the output of the first half-limiter 125 tracks the input of the first half-limiter 125 until the maximum permissible output value is reached. The output of the first half-limiter 125 controls the first controlled voltage source 127 to adjust the threshold ITH generated by the error amplifier EA. Therefore, the first controlled voltage source 127 generates a first adjusted threshold ITH1 that is approximately equal to ITH minus the first adjusted voltage set by the first half-limiter 125.
[0104] Symmetrically, when power transistor Q6 is turned on by control signal D (e.g.) Figure 2C and Figure 2D As shown, when D is active, power transistor Q8 is also turned on by B', and the second sampling switch 132 is also turned on to turn on the second flying capacitor C. fly2 The voltage is stored in the second sampling capacitor C2. Furthermore, the difference between the sampled voltage of the second sampling capacitor C2 and the voltage signal HALFVIN is amplified by the second gain circuit GAIN2. The second half-limiter 126 limits the output of the second gain circuit GAIN2 in such a way that it outputs zero when the output of the second gain circuit GAIN2 is negative, and tracks the output of the second gain circuit GAIN2 until the maximum permissible output value when the output of the second gain circuit GAIN2 is positive. The second controlled voltage source 128 generates a second regulated threshold ITH2 that is approximately equal to ITH minus the second regulated voltage set by the second half-limiter 126.
[0105] Continue to refer to Figure 9 Using a resistor divider formed by the first resistor R1 and the second resistor R2, the output voltage V O The voltage is divided to generate a feedback signal FB. The feedback signal FB is coupled to the inverting input of the error amplifier EA, which can be implemented as a transconductance amplifier. A reference DC voltage REF is coupled to the non-inverting input of the error amplifier EA, and the error between FB and REF is converted into a current output used to set the threshold ITH. The amplifier stability network 129 can be implemented in various ways, such as using a resistor-capacitor (RC) compensation network to provide stability compensation.
[0106] The first comparator CMP1 compares the indication of the current of the first inductor L1 (provided by the first current sensing circuit 123) with a first adjusted threshold ITH1, while the second comparator CMP2 compares the indication of the current of the second inductor L2 (provided by the second current sensing circuit 124) with a second adjusted threshold ITH2.
[0107] The first SR latch RS1 outputs a first PWM control signal A, which is set when the first clock signal CLK1 is applied. When the current signal of the first sensing inductor is higher than ITH1, the output of the first comparator CMP1 resets the first PWM control signal A, which is the control signal for the first power transistor Q1 and the third power transistor Q3. In addition, the first PWM control signal A can be logically inverted to control the fourth power transistor Q4.
[0108] Continue to refer to Figure 9 The second SR latch RS2 outputs a second PWM control signal B, which is set when the second clock signal CLK2 is applied. In some embodiments, the second clock signal CLK2 has a phase shift of approximately 180 degrees from the first clock signal CLK1. When the current signal of the second sensing inductor is higher than ITH2, the output of the second comparator CMP2 resets the second PWM control signal B, which is the control signal for the fifth power transistor Q5 and the seventh power transistor Q7. Furthermore, the second PWM control signal B can be logically inverted to control the eighth power transistor Q8. Additionally, digital logic operations (e.g., see configuration) Figure 2B It can be used to generate a third PWM control signal C for controlling the second power transistor Q2 and a fourth PWM control signal D for controlling the sixth power transistor Q6.
[0109] Figure 10A It is used for Figure 9 An example of the instantaneous performance simulation of a hybrid power conversion system 150 with flying capacitor mismatch.
[0110] Simulation results for C FLY1 ≠C FLY2 The simulation is described. For example... Figure 10A As shown, even when a dynamic load is applied to the output of the hybrid converter 121, the flying capacitor voltage is well locked at 1 / 2V. IN Furthermore, the inductor current will also be closely matched.
[0111] Figure 10B It is used for Figure 9 An example of instantaneous performance simulation of a hybrid power conversion system 150 with comparator mismatch.
[0112] The simulation results are described for a current comparator with a mismatched input offset. For example... Figure 10B As shown, the PWM controller 122 is used to regulate ITH1 and ITH2 to ensure V cfly1 =V cfly2 =1 / 2V IN , and i L1 =i L2 .
[0113] Figure 11 It is used for Figure 9 An example of a transient performance simulation of a hybrid power conversion system 150 with inductor mismatch.
[0114] The simulation results are described for simulations where L1 ≠ L2. For example... Figure 11 As shown, even when a dynamic load is applied, the flying capacitor voltage is well locked at 1 / 2V. IN Furthermore, the inductor current will also be closely matched.
[0115] Figure 12 This is a schematic diagram of a hybrid power conversion system 160 according to another embodiment. The hybrid power conversion system 160 includes a hybrid converter 121 and a PWM controller 152.
[0116] Figure 12 The PWM controller 152 is similar to Figure 9 The PWM controller 122, in addition to Figure 12 The embodiments illustrate different implementations of the first sampling switch 131 and the second sampling switch 132. Specifically, the first sampling switch 131 is directly connected to the first flying capacitor C. fly1 The first terminal is connected between the first sampling capacitor C1 and the second sampling switch 132, and is controlled by the control signal A'. The second sampling switch 132 is directly connected to the second sampling capacitor C1. fly2 The first terminal is connected to the second sampling capacitor C2 and is controlled by the control signal B'. Relative to Figure 9 The PWM controller 122 is implemented in this way. Figure 12 The PWM controller 152 provides a longer sampling time (see, for example, see...). Figure 2C and Figure 2D (Timing diagram).
[0117] Figure 13 This is a schematic diagram of a hybrid power conversion system 170 according to another embodiment. The hybrid power conversion system 170 includes a hybrid converter 121 and a PWM controller 162.
[0118] Figure 13 The PWM controller 162 is similar to Figure 9 The PWM controller 122, in addition to Figure 13The PWM controller 162 omits sampling switches 131 and 132 and sampling capacitors C1 and C2, and includes a first differential amplifier DIFF1 and a second differential amplifier DIFF2. For example... Figure 13 As shown, the first differential amplifier DIFF1 has coupling with the first flying capacitor C. fly1 The differential inputs at both ends and the output coupled to the non-inverting input of the first gain circuit GAIN1. Furthermore, the second differential amplifier DIFF2 has a coupling to the second flying capacitor C. fly2 The differential inputs at both ends and the output coupled to the non-inverting input of the second gain circuit GAIN2. The first gain circuit GAIN1 and the second gain circuit GAIN2 each include an inverting input that receives HALFVIN.
[0119] By implementing the PWM controller 162 in this manner, enhanced tracking of the flight capacitor voltage is achieved at the cost of increased complexity. For example, the first differential amplifier DIFF1 and the second differential amplifier DIFF2 respectively provide voltage to the first flight capacitor C. fly1 and the second flight capacitor C fly2 Continuous indication of voltage across both ends, but operates with a wide input voltage range.
[0120] Figure 14 This is a schematic diagram of a hybrid power conversion system 180 according to another embodiment. The hybrid power conversion system 180 includes a hybrid converter 121 and a PWM controller 172.
[0121] Figure 14 The PWM controller 172 is similar to Figure 13 The PWM controller 162, except for the PWM controller 172, omits the second differential amplifier DIFF2, the second gain circuit GAIN2, the second half limiter 126, and the second controlled voltage source 128. Furthermore, the PWM controller 172 omits the first half limiter 125 and includes a full limiter 173.
[0122] By using the full limiter 173 to control the first controlled voltage source 127, regulation of the threshold voltage ITH1 is provided to maintain the first flying capacitor C. fly1 The voltage across the terminals is approximately 1 / 2V. IN .
[0123] Figure 15 This is a schematic diagram of a hybrid power conversion system 190 according to another embodiment. The hybrid power conversion system 190 includes a hybrid converter 121 and a PWM controller 182.
[0124] Figure 15 The PWM controller 182 is similar to Figure 14The PWM controller 172, except that the resistors R5 and R6 are omitted from the PWM controller 182, includes a second differential amplifier DIFF2. For example... Figure 15 As shown, the first gain circuit GAIN1 compares the output of the first differential amplifier DIFF1 with the output of the second differential amplifier DIFF2.
[0125] Figure 16 This is a schematic diagram of a hybrid power conversion system 200 according to another embodiment. The hybrid power conversion system 200 includes a hybrid converter 121 and a PWM controller 192.
[0126] Figure 16 The PWM controller 192 is similar to Figure 13 The PWM controller 162, except that the PWM controller 192 is implemented such that the first half limiter 125 controls the second controlled voltage source 128 and the second half limiter 126 controls the first controlled voltage source 127.
[0127] Figure 17 This is a schematic diagram of a hybrid power conversion system 310 according to another embodiment. The hybrid power conversion system 310 includes a hybrid converter 300, a first PWM controller 301, a second PWM controller 302, a first resistor R1, and a second resistor R2. Figure 17 The PWM controller can be implemented according to any of the embodiments described herein.
[0128] In the illustrated embodiment, the hybrid converter 300 includes a first half-power stage P1 and a second half-power stage P2, which are similar to... Figure 2A The hybrid converter 111 is implemented in such a way that the first half-power stage P1 and the second half-power stage P2 form the first power stage. These half-stages also contain nodes SW1, SW2, and MID1, as well as the first output capacitor C. OUT1 The first PWM controller 301 generates PWM control signals A, A', B, B', C, and D for the first half-power stage P1 and the second half-power stage P2. Although Figure 17 Not shown, but may include current sensing circuitry for the first inductor L1 and the second inductor L2.
[0129] The hybrid converter 310 further includes a third half-power stage P3 and a fourth half-power stage P4. In this embodiment, the third half-power stage P3 and the fourth power stage P4 form a second power stage, and therefore the hybrid converter 310 is implemented using two stages.
[0130] The third half-power stage P3 includes the ninth power transistor Q9 and the tenth power transistor Q. 10 Eleventh power transistor Q 11 The twelfth power transistor Q 12Third inductor L3 and third flying capacitor C fly3 Furthermore, the fourth half-power stage P4 includes the thirteenth power transistor Q. 13 Fourteenth power transistor Q 14 The fifteenth power transistor Q 15 The sixteenth power transistor Q 16 Fourth inductor L4 and fourth flying capacitor C fly4 These semistages also contain nodes SW3, SW4, and MID2, as well as the second output capacitor C. OUT2 The second PWM controller 302 generates PWM control signals E, E', F, F', G, and H for the third half-power stage P3 and the fourth half-power stage P4. Although Figure 17 Not shown, but may include current sensing circuitry for the third inductor L3 and the fourth inductor L4. In this embodiment, all four half-power stages P1-P4 share a common V0. IN and shared V O operate.
[0131] The teachings of this paper apply to more than two power stages (e.g., Figure 17 The embodiment includes two power stages, and also includes a number of other power stages in the hybrid converter.
[0132] The first PWM controller 301 and the second PWM controller 302 operate by sharing ITH (before regulation by the threshold adjustment circuit), a shared soft-start (SS) signal, and a shared feedback signal FB generated by the output voltage divider formed by resistors R1 and R2. The first PWM controller 301 also provides a clock signal from its output CLKOUT to the input CLKIN of the second PWM controller 302 to help coordinate the timing of the PWM signals and match the regulator switching frequency. The SS signal can be used to provide soft-start. For example, a current source may be included in each PWM controller and may be connected to an off-chip capacitor to allow the SS signal voltage to ramp up smoothly. Furthermore, the voltage regulation loop regulates the feedback FB to either SS or an internal reference REF, whichever is lower, so that the output voltage ramps up linearly. Although one example of soft-start has been described, other implementations exist. Any embodiment described herein can operate with soft-start capability.
[0133] Figure 18 It is used for Figure 17 An example of the instantaneous performance simulation of the hybrid power conversion system 310 with inductor mismatch, flying capacitor mismatch, comparator mismatch, and current sensing gain mismatch.
[0134] like Figure 18 As shown, the hybrid power conversion system 310 provides stable regulation in the presence of load current steps.
[0135] Figure 19A This is a schematic diagram of a hybrid power conversion system 420 according to another embodiment. The hybrid power conversion system 420 includes a hybrid converter 411 and a PWM controller 112.
[0136] Figure 19A The hybrid power conversion system 420 is similar to Figure 8 The hybrid power conversion system 420 illustrates different implementations of the hybrid converter. Specifically, compared to... Figure 8 The hybrid converter 111 shown, Figure 19A The hybrid converter 411 further includes a capacitor C connected between the intermediate node MID and ground. OPT .
[0137] The PWM control scheme presented in this paper is applicable to hybrid converters implemented in various ways.
[0138] Figure 19B This is a schematic diagram of a hybrid power conversion system 430 according to another embodiment. The hybrid power conversion system 430 includes a hybrid converter 421 and a PWM controller 112.
[0139] Compared to Figure 8 The hybrid converter 111, Figure 19B The hybrid converter 421 includes a first conductor MID1 connecting the source of power transistor Q2 to the drain of power transistor Q7, and a second conductor MID2 connecting the source of power transistor Q6 to the drain of power transistor Q3. Implementing the hybrid converter 421 in this manner enhances the converter balance between half-stages.
[0140] Figure 19C This is a schematic diagram of a hybrid power conversion system 440 according to another embodiment. The hybrid power conversion system 440 includes a hybrid converter 431 and a PWM controller 112.
[0141] Compared to Figure 19B The hybrid converter 421, Figure 19C The hybrid converter 431 includes a first capacitor C connected between MID1 and ground. OPT1 And the second capacitor C connected between MID2 and ground. OPT2 .
[0142] application
[0143] The device employing the above-described solution can be implemented in a wide range of electronic devices, including but not limited to bus converters, high-current distributed power systems, telecommunications systems, data communication systems, storage systems, and automotive systems. Therefore, examples of electronic devices that can be implemented using the hybrid power conversion system described herein include, but are not limited to, communication systems, consumer electronics, electronic test equipment, communication infrastructure, servers, and automobiles.
[0144] in conclusion
[0145] The preceding description may refer to elements or features as “connected” or “coupled” together. As used herein, unless explicitly stated otherwise, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically connected. Similarly, unless explicitly stated otherwise, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically connected. Therefore, although the various schematic diagrams shown in the figures depict exemplary arrangements of elements and assemblies, additional intermediate elements, devices, features, or assemblies may be present in actual embodiments (assuming that the function of the depicted circuit will not be adversely affected).
[0146] Although certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel devices, methods, and systems described herein can be implemented in various other forms; furthermore, various omissions, substitutions, and changes can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although the disclosed embodiments are presented with a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements can be implemented in various different ways. Any suitable combination of elements and actions of the various embodiments described above can be combined to provide further embodiments. Therefore, the scope of the invention is defined only by reference to the appended claims.
[0147] Although the claims presented herein are submitted to the USPTO in a single dependent form, it should be understood that any claim may depend on any prior claim of the same type unless it is clearly impractical in the technical sense.
Claims
1. A power conversion system comprising: A power converter configured to generate a regulated output voltage based on an input voltage, wherein the power converter comprises: The first half-power stage includes a first inductor, a first capacitor, and a first set of switches configured to control the electrical connection between the first inductor and the first capacitor. The first set of switches includes a first switch, a second switch, a third switch, and a fourth switch, wherein: The first switch, the second switch, and the third switch are connected in series between the input voltage and the first switch node; The fourth switch is connected between the first switch node and the ground voltage; The first capacitor is connected in parallel with the second switch and the third switch; as well as The first inductor is connected between the first switching node and the regulated output voltage; The second half-power stage includes a second inductor, a second capacitor, and a second set of switches, wherein the second set of switches includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch, wherein: The fifth switch, the sixth switch, and the seventh switch are connected in series between the input voltage and the second switch node; The eighth switch is connected between the second switch node and the ground voltage; The second capacitor is connected in parallel with the sixth switch and the seventh switch; and The second inductor is connected between the second switching node and the regulated output voltage; and A pulse width modulation (PWM) controller includes: A threshold generation circuit is configured to generate a threshold signal based on the regulated output voltage; A first threshold adjustment circuit is configured to adjust the threshold signal based on a comparison of a portion of the input voltage with the voltage of the first capacitor to compensate for the mismatch between the first half-power stage and the second half-power stage by generating a first adjusted threshold signal. A first comparator is configured to compare the current through the first inductor with the first adjusted threshold signal; A second comparator is configured to compare the current through the second inductor with the threshold signal; and A switch control circuit is configured to generate at least one control signal for controlling the first group of switches based on the output of the first comparator and to generate at least one control signal for controlling the second group of switches based on the output of the second comparator.
2. The power conversion system according to claim 1, wherein, The first threshold adjustment circuit is operable to compensate for the mismatch between the first comparator and the second comparator.
3. The power conversion system of claim 1, further comprising a second threshold adjustment circuit configured to generate a second adjusted threshold signal by adjusting the threshold signal based on the input voltage and the voltage of the second capacitor, wherein the second comparator is configured to compare the current through the second inductor with the second adjusted threshold signal.
4. The power conversion system according to claim 3, wherein, The first threshold adjustment circuit includes a first gain circuit configured to amplify the difference between the voltage of the first capacitor and the portion of the input voltage, and the second threshold adjustment circuit includes a second gain circuit configured to amplify the difference between the voltage of the second capacitor and the portion of the input voltage.
5. The power conversion system according to claim 4, wherein, The portion of the input voltage corresponds to approximately half of the input voltage.
6. The power conversion system according to claim 1, wherein, The first threshold adjustment circuit includes: a first gain circuit configured to amplify the difference between the voltage of the first capacitor and a portion of the input voltage; and a first limiter configured to adjust the threshold signal based on the output of the first gain circuit.
7. The power conversion system according to claim 6, wherein, The first threshold adjustment circuit further includes a first sampling capacitor and a first sampling switch, the first sampling switch being configured to provide the voltage of the first capacitor to the sampling capacitor during the sampling phase.
8. The power conversion system according to claim 6, wherein, The first threshold adjustment circuit further includes a first differential amplifier, which includes a differential input coupled to both ends of the first capacitor and an output coupled to a first input of the first gain circuit.
9. The power conversion system according to claim 8, wherein, The first threshold adjustment circuit further includes a voltage divider connected between the input voltage and the ground voltage, and configured to provide a divided input voltage to the second input of the first gain circuit.
10. The power conversion system according to claim 1, wherein, The threshold generation circuit includes: a voltage divider configured to generate a feedback voltage based on the regulated output voltage; and a transconductance amplifier configured to generate the threshold signal based on the difference between the feedback voltage and a reference voltage.
11. The power conversion system according to claim 1, wherein, The first switch includes a first power transistor, the second switch includes a second power transistor, the third switch includes a third power transistor, the fourth switch includes a fourth power transistor, the fifth switch includes a fifth power transistor, the sixth switch includes a sixth power transistor, the seventh switch includes a seventh power transistor, and the eighth switch includes an eighth power transistor.
12. A power conversion method, comprising: A power converter generates a regulated output voltage based on an input voltage. The power converter includes a first half-power stage and a second half-power stage. The first half-power stage includes a first inductor, a first capacitor, and a first set of switches for controlling the electrical connection between the first inductor and the first capacitor. The second half-power stage includes a second inductor, a second capacitor, and a second set of switches for controlling the electrical connection between the second inductor and the second capacitor. The first set of switches includes a first switch, a second switch, a third switch, and a fourth switch; The first switch, the second switch, and the third switch are connected in series between the input voltage and the first switch node; The fourth switch is connected between the first switch node and the ground voltage; The first capacitor is connected in parallel with the second switch and the third switch; as well as The first inductor is connected between the first switching node and the regulated output voltage; The second group of switches includes the fifth switch, the sixth switch, the seventh switch, and the eighth switch; The fifth switch, the sixth switch, and the seventh switch are connected in series between the input voltage and the second switch node; The eighth switch is connected between the second switch node and the ground voltage; The second capacitor is connected in parallel with the sixth switch and the seventh switch; as well as The second inductor is connected between the second switching node and the regulated output voltage; A threshold signal is generated based on the regulated output voltage using a threshold generation circuit; A first regulated threshold signal is generated by adjusting the threshold signal based on a comparison between a portion of the input voltage and the voltage of the first capacitor using a first threshold adjustment circuit. A second adjusted threshold signal is generated by adjusting the threshold signal based on a comparison of a portion of the input voltage with the voltage of the second capacitor of the power converter; The first comparator is used to compare the current through the first inductor with the first adjusted threshold signal; The second comparator is used to compare the current through the second inductor of the power converter with the second regulated threshold signal; The first group of switches is controlled based on the output of the first comparator; as well as The output of the second comparator controls the second set of switches of the power converter.
13. The method according to claim 12, wherein, Generating the first regulated threshold signal includes amplifying the difference between the voltage of the first capacitor and a portion of the input voltage, and limiting the amplified difference using a limiter.