A circuit module and Delta-Sigma modulator for implementing low-harmonic data weighted averaging algorithm

Abstract

The present invention discloses a circuit module and a Delta-Sigma modulator for implementing a low-harmonic data weighted averaging algorithm. The circuit module includes: a thermometer decoder for converting an input 3-bit binary code into an 8-bit thermometer code; a periodic random signal generator for generating a random signal every M clocks; a three-input modulo adder for adding the input binary code of the current clock, the output of the periodic random signal generator, and the address pointer of the previous clock, and then calculating the remainder by 8 to generate a new address pointer to control the shift operation of a barrel shift register; a D flip-flop; and a barrel shift register for performing a corresponding shift operation on the input thermometer code according to the address pointer ptr[2:0] of the current clock, and outputting the shifted data to a 1-bit DAC unit. The present invention has a simple structure and can effectively suppress the output harmonics of a traditional data weighted averaging circuit module without significantly increasing the noise floor, thereby improving the linearity of the system.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a circuit module and a Delta-Sigma modulator for realizing a low-harmonic data weighted averaging algorithm. Background Art

[0002] Data converters are crucial building blocks in modern signal processing systems, yet they also represent the bottleneck that limits the overall system's signal processing capabilities. Due to the matching accuracy of the analog components used in the converter circuit implementation, traditional Nyquist converters achieve only a moderate effective number of bits (ENOB), typically less than 14 bits. Careful layout, improved process technology, and calibration techniques can improve the performance of these converters to near-perfect levels, but this also significantly increases their cost. In this context, the oversampled Delta-Sigma converter architecture is often favored due to its high resolution, insensitivity to circuit non-idealities, and low cost.

[0003] While single-bit delta-sigma modulators were once the primary choice for early data converters, multi-bit delta-sigma modulators are now becoming the dominant choice. Given a small input signal, such as -60dBFS, the output of a multi-bit modulator is primarily concentrated near the zero code level, with few adjacent levels. In contrast, the output of a single-bit modulator fluctuates between maximum and minimum values. This fluctuation results in greater quantization noise in the single-bit modulator. In addition to lower noise, multi-bit modulators exhibit better stability than single-bit modulators of the same order. Therefore, despite the inherently superior linearity of single-bit modulators, multi-bit modulators are preferred in high-end data converters.

[0004] Although multi-bit quantization improves the stability and signal-to-noise ratio of Delta-Sigma converters, in actual circuit implementation, due to manufacturing process limitations, the DAC units composed of analog components cannot be perfectly matched. Consequently, DAC unit mismatch is transferred to the modulation loop in the form of nonlinear errors, affecting the modulator's signal-to-noise ratio and other performance characteristics. Therefore, to ensure high modulator accuracy, dynamic element matching (DEM) techniques are generally used to suppress or compensate for nonlinear errors. Among the various DEM techniques, data-weighted averaging (DWA) is widely used due to its simple implementation.

[0005] Figure 1This diagram illustrates a traditional DWA algorithm using three-bit quantization (8 DAC units) as an example. The eight quantization units are numbered 1 through 8. The Input column represents the input signal, and the Pointer column represents the address pointer position (initial value 1). The pointer position in the current clock cycle equals the pointer position in the previous clock cycle modulo 8, summed with the input signal. When the first output signal is 3, the DWA selects units 1 through 3, and the address pointer changes to 4. When the second input signal is 2, the DWA selects units 4 through 5, and the address pointer changes to 6. When the next input signal is 6, the DWA selects units 6 through 8 and loops back to the first of the eight DAC units, reselecting units 1 through 3 and changing the address pointer to 4. This cycle of feedback unit selection continues, and the DAC unit selected for each input signal is shaded in the diagram.

[0006] When the frequency of the input signal is too small and close to DC, the limitations of traditional DWA technology become apparent. Figure 2 Taking the above three-bit quantization as an example, when the input signal is continuously 2, the DAC unit will have the following regular selection: (1,2), (3,4), (5,6), (7,8)... and so on. When considering the mismatch error of the DAC unit, due to the regularity of the selection unit, the mismatch error also appears regularly in the output signal of the DWA unit. This regularity affects the accuracy of the modulator in the form of harmonics in the spectrum.

[0007] Therefore, in order to suppress the harmonics introduced by the regular selection of feedback units, the traditional DWA technology needs to be improved. Summary of the Invention

[0008] The present invention aims to provide a circuit module for implementing a low-harmonic data weighted averaging algorithm to solve the above-mentioned problem. To this end, the technical solution for sampling of the present invention is as follows:

[0009] According to one aspect of the present invention, a circuit module for implementing a low harmonic data weighted averaging algorithm is provided, the circuit module comprising:

[0010] Thermometer decoder, used to convert the input 3-bit binary code into 8-bit thermometer code;

[0011] A periodic random signal generator, wherein the periodic random signal generator has a period of M and is used to generate a random signal every M clocks;

[0012] A three-input modular adder, configured to add the input binary code of the current clock, the output of the periodic random signal generator, and the address pointer of the previous clock, and then calculate the modulo 8 to generate a new address pointer;

[0013] a D flip-flop, an input end of which is connected to the output end of the three-input modular adder, and an output end of which is connected to one of the input ends of the three-input modular adder and the barrel shift register;

[0014] The barrel shift register is used to perform corresponding shift operations on the input thermometer code according to the address pointer ptr[2:0] of the current clock and output the shifted data to the 1-bit DAC unit.

[0015] In a preferred embodiment, the periodic random signal generator includes a constant 0, a random number generator, a counter and a two-choice selector; wherein the random number generator is used to generate a random integer in the interval [0,7]; the counter is used to count the number of clock cycles and return to zero when the counting result is M; the input of the two-choice selector is coupled with the output of the random number generator, the constant 0, and the output of the counter. When the output of the counter is 0, the output of the two-choice selector is equal to the output of the random number generator, and when the output of the counter is not 0, the output of the two-choice selector is the constant 0.

[0016] In a preferred embodiment, the three-input modular adder is a full adder with three data inputs; wherein the carry input of the full adder is set to 0 and the carry output is not used.

[0017] In a preferred embodiment, the barrel shift register includes 24 two-way selectors, wherein the 24 two-way selectors are divided into three groups, each group having eight two-way selectors. Specifically, the two-way selectors in the first group are controlled by the address pointer ptr[0] to perform a 1-bit shift operation on the input thermometer code tem0[7:0] and output the shifted data tem1[7:0] to the second group of two-way selectors; the two-way selectors in the second group are controlled by the address pointer ptr[1] to perform a 2-bit shift operation on the input thermometer code tem1[7:0] and output the shifted data tem2[7:0] to the third group of two-way selectors; the two-way selectors in the third group are controlled by the address pointer ptr[2] to perform a 4-bit shift operation on the input thermometer code tem2[7:0] to obtain the final data output d0 to d7, and output it to the 1-bit DAC unit.

[0018] In a preferred embodiment, the circuit module further includes a superposition module for superimposing the individual 1-bit DAC units into a total output.

[0019] According to another aspect of the present invention, a Delta-Sigma modulator is provided. The Delta-Sigma modulator includes the circuit module for implementing the low-harmonic data weighted averaging algorithm as described above.

[0020] The circuit module implemented in this invention for implementing a low-harmonic data weighted averaging algorithm adds only a periodic random number generator to the architecture of traditional DWA technology, resulting in a simple structure and low circuit overhead. This periodic random number generator disrupts the regular selection of DAC units in traditional DWA every M clock cycles. By adjusting M, this circuit module effectively suppresses harmonics without affecting the first-order shaping effect of traditional DWA, thereby significantly improving system linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To further illustrate various embodiments, the present invention is provided with accompanying drawings. These drawings form part of the present disclosure and are primarily used to illustrate the embodiments and, in conjunction with the relevant description in the specification, to explain the operating principles of the embodiments. By referring to these drawings, one of ordinary skill in the art will understand other possible embodiments and the advantages of the present invention. The components in the figures are not drawn to scale, and similar reference numerals are generally used to represent similar components.

[0022] Figure 1 It is a schematic diagram of the traditional DWA algorithm;

[0023] Figure 2 It is a schematic diagram of the limitations of the traditional DWA algorithm;

[0024] Figure 3 is a schematic diagram of implementing a low harmonic DWA algorithm according to an embodiment of the present invention;

[0025] Figure 4 2 is a schematic structural diagram of a circuit module for implementing a low harmonic data weighted averaging algorithm according to an embodiment of the present invention;

[0026] Figure 5 yes Figure 4 The structural diagram of the periodic random signal generator shown in FIG.

[0027] Figure 6 yes Figure 4 The schematic diagram of the structure of the three-input modular adder shown in FIG.

[0028] Figure 7 yes Figure 4 The structural diagram of the barrel shift register shown in FIG.

[0029] Figure 8 1 is a schematic structural diagram of a Delta-Sigma modulator for testing according to an embodiment of the present invention;

[0030] Figure 9 1 is a power spectrum density diagram of an output signal of the DAC feedback module when the DAC feedback module in the embodiment of the present invention adopts a no-mismatch mode;

[0031] Figure 10 1 is a power spectrum density diagram of the output signal of the DAC feedback module when the DAC feedback module adopts the mismatch mode and the DWA module adopts the DWA algorithm off mode according to an embodiment of the present invention;

[0032] Figure 11 1 is a power spectrum density diagram of the output signal of the DAC feedback module when the DAC feedback module of the embodiment of the present invention adopts the mismatch mode and the DWA module adopts the traditional DWA algorithm start mode;

[0033] Figure 12 This is a power spectrum density diagram of the output signal of the DAC feedback module when the DAC feedback module of the embodiment of the present invention adopts the mismatch mode and the DWA module adopts the low harmonic DWA algorithm on mode. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings so that the objects, features and advantages of the present invention can be more clearly understood. It should be understood that the embodiments shown in the accompanying drawings are not intended to limit the scope of the present invention, but are only intended to illustrate the essential spirit of the technical solutions of the present invention.

[0035] In the following description, for the purpose of illustrating the various disclosed embodiments, certain specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details. In other cases, well-known devices, structures, and techniques associated with this application may not be shown or described in detail to avoid unnecessarily obscuring the description of the embodiments.

[0036] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any manner in one or more embodiments.

[0037] In the following description, in order to clearly show the structure and working mode of the present invention, many directional words will be used for description, but words such as "front", "back", "left", "right", "outside", "inside", "outward", "inward", "up", and "down" should be understood as convenient terms and should not be understood as restrictive terms.

[0038] See Figure 3 , Figure 3This diagram illustrates a low-harmonic DWA algorithm using three-bit quantization (8 DAC units) as an example. This algorithm is similar to the traditional DWA algorithm, except that the additional column, "Random Data," contains the output signal from a periodic random signal generator with a period M of 1. This column disrupts the address pointer's behavior in the traditional DWA algorithm, so that the pointer position in the current clock cycle equals the pointer position in the previous clock cycle, and the input signal and the random input signal are summed modulo 8. When the first output signal is 3 and the random input signal is 1, the DWA selects units 1 through 3, and the address pointer changes to 5. When the second input signal is 2 and the random input signal is 2, the DWA selects units 5 through 6, and the address pointer changes to 1. When the next input signal is 6 and the random input signal is 3, the DWA selects units 1 through 6, and the address pointer changes to 2. This cycle of feedback unit selection continues, and the DAC unit selected for each input signal is also shaded in the diagram.

[0039] See also Figure 4 , Figure 4 This is a schematic diagram of the structure of a circuit module for implementing a low-harmonic data weighted averaging algorithm according to an embodiment of the present invention. The circuit module comprises five major components: a thermometer decoder 1, a periodic random signal generator 2, a three-input analog adder 3, a D flip-flop 4, and a barrel shift register 5. The thermometer decoder 1 is used to convert a 3-bit binary code input into an 8-bit thermometer code. The structure of the thermometer decoder 1 is well known and will not be described in detail here. The periodic random signal generator 2 has a period of M and is used to generate a random signal every M clock cycles. The three-input analog adder 3 is used to add the current clock's input binary code, the output of the periodic random signal generator 2, and the address pointer of the previous clock, and then calculate the modulo 8 to generate a new address pointer to control the shift operation of the barrel shift register 5. The D terminal of the D flip-flop 4 is connected to the output of the three-input analog adder 3, and the Q terminal is connected to the input of the three-input analog adder 3 and the address pointer input of the barrel shift register 5, thereby accumulating data with the three-input analog adder 3. The barrel shift register 5 performs a corresponding shift operation on the input thermometer code according to the address pointer ptr[2:0] of the current clock, and outputs the shifted data to the 1-bit DAC unit 6. Furthermore, this circuit module includes an addition module 7 for adding the output signals of each DAC unit 6 to form a total output. The structure of the addition module 7 is well known and will not be described in detail here.

[0040] See also Figure 5 , Figure 52 is a schematic diagram of the structure of a periodic random signal generator 2, which includes a constant 0, a random number generator 21, a counter 22, and a two-choice selector 23. The random number generator 21 is used to generate a random integer in the interval [0, 7]. The counter 22 is used to count the number of clock cycles and return to zero when the count result is M. The input of the two-choice selector 23 is coupled with the output of the random number generator 21, the constant 0, and the output of the counter 22. When the output of the counter 22 is 0, the output of the two-choice selector 23 is equal to the output of the random number generator 21. When the output of the counter 22 is not 0, the output of the two-choice selector 23 is the constant 0.

[0041] See also Figure 6 , Figure 6 1 is a schematic diagram of a three-input modular adder according to an embodiment of the present invention, which is a three-input full adder. The carry input of the full adder is set to 0, and the carry output is not used.

[0042] See also Figure 7 , Figure 7 This is a schematic diagram of the structure of a barrel shift register according to an embodiment of the present invention, comprising 24 two-way selectors. The 24 two-way selectors are divided into three groups, each with eight two-way selectors. The two-way selectors in the first group perform a 1-bit shift operation on the input thermometer code tem0[7:0] according to the control of the address pointer ptr[0], and output the shifted data tem1[7:0] to the second group of two-way selectors; the two-way selectors in the second group perform a 2-bit shift operation on the input thermometer code tem1[7:0] according to the control of the address pointer ptr[1], and output the shifted data tem2[7:0] to the third group of two-way selectors; the two-way selectors in the third group perform a 4-bit shift operation on the input thermometer code tem2[7:0] according to the control of the address pointer ptr[2], and obtain the final data output d0 to d7, which is then output to the 1-bit DAC unit.

[0043] See also Figure 8 , Figure 8The structure of a Delta-Sigma modulator for testing according to an embodiment of the present invention is schematically illustrated. The Delta-Sigma modulator includes a loop filter, a quantizer, a DWA module, a DAC feedback module, and an adder. The quantizer has a 3-bit bit count, and its input is coupled to the output of the loop filter, quantizing the output of the loop filter into a 3-bit digital output signal Y. The DWA module is used to implement a low-harmonic data weighted averaging algorithm, and its structure has been described above. The DWA module has three operating modes: DWA algorithm off mode, traditional DWA algorithm on mode, and low-harmonic DWA algorithm on mode. Its input is coupled to the output of the quantizer. The DAC feedback module has two operating modes: no mismatch mode and mismatch mode. In no mismatch mode, all DAC units are fully matched. In mismatch mode, all DAC units have a mismatch deviation of 5‰. The input of this module is coupled to the output of the DWA module. The adder receives the analog input signal X and the output signal Z of the DAC feedback module, sums them, and then inputs them into the input of the loop filter.

[0044] See also Figures 9 to 12 , where the amplitude of the input signal is 0.01, Figure 9 This is the power spectrum density diagram of the output signal Z of the DAC feedback module when the DAC feedback module of the Sigma-Delta modulator adopts the no-mismatch mode; Figure 10 This is the power spectral density diagram of the DAC feedback module output signal Z when the DAC feedback module of the Delta-Sigma modulator adopts the mismatch mode and the DWA module adopts the traditional DWA algorithm off mode; Figure 11 The power spectral density diagram of the DAC feedback module output signal Z when the DAC feedback module of the Delta-Sigma modulator adopts the mismatch mode and the DWA module adopts the traditional DWA algorithm mode; Figure 12 Figure 1 shows the power spectral density of the DAC feedback module output signal Z when the DAC feedback module of the Delta-Sigma modulator adopts the mismatch mode and the DWA module adopts the low harmonic DWA algorithm on mode (M=10000).

[0045] from Figure 9 and Figure 10 It can be seen from the comparison that when the DWA algorithm is turned off, the signal-to-noise ratio in the output signal spectrum when there is a DAC unit mismatch is much lower than when there is no DAC unit mismatch; Figure 9 、 Figure 10 and Figure 11 By comparison, we can see that the traditional DWA algorithm reduces the mismatch noise in the signal band and effectively improves the signal-to-noise ratio in the output signal spectrum. However, it also introduces harmonics in the signal band, which seriously affects the linearity. Figure 11 and Figure 12 From the comparison, it can be seen that the low harmonic DWA algorithm not only reduces the mismatch noise in the signal band, but also suppresses the harmonics introduced by the traditional DWA algorithm, effectively improving the linearity of the system.

[0046] In summary, the present invention has the following technical features: (1) A low harmonic data weighted averaging algorithm circuit module for high-precision multi-bit quantized Sigma-Delta modulator is proposed. On the basis of the architecture of traditional data weighted averaging technology, only a periodic random number generator is added, which has a simple structure and low circuit overhead; (2) Under the action of the periodic random number generator, the regular selection of DAC units by traditional DWA is disrupted every M clock cycles. By adjusting M, the circuit module achieves effective suppression of harmonics without significantly increasing the noise floor, thereby effectively improving the linearity of the system; (3) The circuits used in the present invention are all 3-bit structures. To change the number of bits of the output signal, it is only necessary to change the number of input and output ports of the thermometer encoder, full adder, periodic random signal generator, and barrel shift register accordingly to achieve different output bit numbers, which has good scalability.

[0047] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A circuit module for implementing a low harmonic data weighted averaging algorithm, characterized in that: The circuit module includes: Thermometer decoder, used to convert the input 3-bit binary code into 8-bit thermometer code; A periodic random signal generator, wherein the periodic random signal generator has a period of M and is used to generate a random signal every M clocks; a three-input modular adder for adding the input binary code of the current clock, the output of the periodic random signal generator, and the address pointer of the previous clock, and then calculating the modulo 8 to generate a new address pointer to control the shift operation of the barrel shift register; a D flip-flop, wherein an input terminal of the D flip-flop is connected to an output terminal of the three-input modular adder, and an output terminal of the D flip-flop is connected to one input terminal of the three-input modular adder and the barrel shift register; The barrel shift register is used to perform corresponding shift operations on the input thermometer code according to the address pointer ptr[2:0] of the current clock and output the shifted data to the 1-bit DAC unit.

2. The circuit module for implementing the low harmonic data weighted averaging algorithm according to claim 1, characterized in that: The periodic random signal generator includes a constant 0, a random number generator, a counter and a two-choice selector; wherein the random number generator is used to generate a random integer in the interval [0,7]; the counter is used to count the number of clock cycles and return to zero when the counting result is M; the input of the two-choice selector is coupled with the output of the random number generator, the constant 0, and the output of the counter; when the output of the counter is 0, the output of the two-choice selector is equal to the output of the random number generator, and when the output of the counter is not 0, the output of the two-choice selector is the constant 0.

3. The circuit module for implementing the low harmonic data weighted averaging algorithm according to claim 1, characterized in that: The modular adder is a full adder with three data inputs; wherein the carry input of the full adder is set to 0, and the carry output is not used.

4. The circuit module for implementing the low harmonic data weighted averaging algorithm according to claim 1, characterized in that: The barrel shift register includes 24 two-way selectors; wherein the 24 two-way selectors are divided into 3 groups, each group includes 8 two-way selectors.

5. The circuit module for implementing the low harmonic data weighted averaging algorithm according to claim 4, characterized in that: The first group of two-way selectors is controlled by the address pointer ptr[0], performs a 1-bit shift operation on the input thermometer code tem0[7:0], and outputs the shifted data tem1[7:0] to the second group of two-way selectors; the second group of two-way selectors is controlled by the address pointer ptr[1], performs a 2-bit shift operation on the input thermometer code tem1[7:0], and outputs the shifted data tem2[7:0] to the third group of two-way selectors; the third group of two-way selectors is controlled by the address pointer ptr[2], performs a 4-bit shift operation on the input thermometer code tem2[7:0], obtains the final data output d0~d7, and outputs it to the 1-bit DAC unit.

6. The circuit module for implementing the low harmonic data weighted averaging algorithm according to claim 1, characterized in that: The circuit module also includes a superposition module for superimposing the individual 1-bit DAC units into a total output.

7. A Delta-Sigma modulator, characterized in that The Delta-Sigma modulator includes a circuit module for implementing a low harmonic data weighted averaging algorithm according to any one of claims 1 to 6.

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