Detection device

Abstract

A detection device comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, and arranged corresponding to the plurality of photoelectric conversion elements respectively; and a first electrode and a second electrode, which are arranged between the substrate and the photoelectric conversion elements in a direction perpendicular to the substrate and are opposite to each other with an insulating film therebetween, the first electrode having a plurality of main parts respectively overlapping with the photoelectric conversion elements and a connecting part connecting adjacent main parts, the second electrode being formed in an island shape on each of the plurality of photoelectric conversion elements, the first electrode being in the same layer as the gate electrode, and the second electrode being in the same layer as the semiconductor layer.

Description

Technical Field

[0001] The invention relates to a detection device. Background Art

[0002] Patent document 1 describes a detection device (referred to as a photoelectric conversion device in Patent document 1) in which a plurality of photoelectric conversion elements such as PIN photodiodes are arranged on a substrate. The photoelectric conversion element of Patent document 1 is driven by a driving circuit including three transistors and a capacitor. The signal (charge) generated by the photoelectric conversion device is accumulated in the capacitor. A voltage signal corresponding to the signal accumulated in the capacitor is output from the output transistor.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-12696 Summary of the invention

[0006] Technical problem to be solved by the invention

[0007] The detection device is required to suppress the variation of the signal output from the transistor.

[0008] An object of the present invention is to provide a detection device capable of suppressing the variation of an output signal.

[0009] Solutions for solving technical problems

[0010] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, and arranged corresponding to the plurality of photoelectric conversion elements respectively; and a first electrode and a second electrode, arranged between the substrate and the photoelectric conversion elements in a direction perpendicular to the substrate and opposite to each other with an insulating film therebetween, the first electrode having a plurality of main portions respectively overlapping with the photoelectric conversion elements and a connecting portion connecting adjacent main portions, the second electrode being formed in an island shape on each of the plurality of photoelectric conversion elements, the first electrode being on the same layer as the gate electrode, and the second electrode being on the same layer as the semiconductor layer.

[0011] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors, including a semiconductor layer, a gate electrode opposite to the semiconductor layer, and a source electrode connected to the semiconductor layer, which are respectively arranged corresponding to the plurality of photoelectric conversion elements; and a first electrode and a second electrode, which are arranged between the substrate and the photoelectric conversion elements in a direction perpendicular to the substrate and are opposite to each other with an insulating film therebetween, the first electrode having a plurality of main portions respectively overlapping with the photoelectric conversion elements and a connecting portion connecting adjacent main portions, the second electrode being formed in an island shape on each of the plurality of photoelectric conversion elements, the first electrode being on the same layer as the gate electrode, and the second electrode being on the same layer as the source electrode.

[0012] A detection device according to one embodiment of the present invention comprises: a substrate; a plurality of photoelectric conversion elements arranged on the substrate; a plurality of transistors arranged corresponding to the plurality of photoelectric conversion elements, respectively; and a first electrode and a second electrode, which, when viewed from above, are arranged in a region overlapping with the photoelectric conversion elements and the plurality of transistors, and are opposed to each other via an insulating film in a direction perpendicular to the substrate, the first electrode being arranged above the photoelectric conversion elements, and the second electrode being arranged above the first electrode via the insulating film. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device including the detection device according to the first embodiment.

[0014] Figure 2 It is a plan view showing the detection device according to the first embodiment.

[0015] Figure 3 This is a block diagram showing a configuration example of a detection device according to the first embodiment.

[0016] Figure 4 is a circuit diagram showing a detection element.

[0017] Figure 5 is a top view showing a detection element.

[0018] Figure 6 It is a top view of the array substrate constituting the detection element.

[0019] Figure 7 yes Figure 6 VII-VII' cross-sectional view.

[0020] Figure 8 It is a plan view of an array substrate constituting the detection element according to the second embodiment.

[0021] Fig. 9 yes Figure 8 IX-IX' cross-section diagram.

[0022] Fig.10 It is a plan view showing a detection element according to a third embodiment.

[0023] Fig.11 It is a plan view of an array substrate constituting a detection element according to a third embodiment.

[0024] Fig.12 yes Fig.11 XII-XII' cross-section. DETAILED DESCRIPTION

[0025] The method (implementation method) for implementing the invention is described in detail with reference to the accompanying drawings. The present invention is not limited to the contents described in the following implementation methods. In addition, the constituent elements described below include elements that can be easily thought of by a person skilled in the art and substantially the same elements. Furthermore, the constituent elements described below can be appropriately combined. It should be noted that the disclosure is only an example, and appropriate changes that can be easily thought of by a person skilled in the art to maintain the gist of the invention are certainly included in the scope of the present invention. In addition, in order to make the description clearer, the accompanying drawings sometimes schematically indicate the width, thickness, shape, etc. of each part compared to the actual method, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, for the elements that are the same as the elements described in the figures that have appeared, the same figure marks are marked, and the detailed description is sometimes appropriately omitted.

[0026] In the present specification and claims, when expressing the manner of configuring another structure on a certain structure, when simply expressed as "on", unless otherwise specified, it includes both the case where the other structure is configured directly above the certain structure in a manner of contacting the certain structure and the case where the other structure is configured above the certain structure with another structure further between them.

[0027] (First Embodiment)

[0028] Figure 1 2 is a cross-sectional view showing a schematic cross-sectional structure of a detection device with an illumination device having a detection device according to the first embodiment. Figure 1 As shown, the detection device 120 with lighting device has a detection device 1, a lighting device 121, an adhesive layer 125 and a cover member 122. In a direction perpendicular to the surface of the detection device 1, the lighting device 121, the detection device 1, the adhesive layer 125 and the cover member 122 are stacked in this order.

[0029] The lighting device 121 has a light irradiation surface 121a for irradiating light, and irradiates light L1 from the light irradiation surface 121a toward the detection device 1. The lighting device 121 is a backlight. The lighting device 121 may be, for example, a so-called side-light type backlight having a light guide plate disposed at a position corresponding to the detection area AA and a plurality of light sources arranged at one end or both ends of the light guide plate. As the light source, for example, a light emitting diode (LED: Light Emitting Diode) emitting light of a prescribed color is used. In addition, the lighting device 121 may be a so-called directly below type backlight having a light source (for example, LED) disposed directly below the detection area AA. In addition, the lighting device 121 is not limited to a backlight, and may be disposed on the side or above the detection device 1, and may irradiate the light L1 from the side or above the finger Fg.

[0030] The detection device 1 is arranged to be opposite to the light irradiation surface 121a of the lighting device 121. The light L1 irradiated from the lighting device 121 passes through the detection device 1 and the cover part 122. The detection device 1 can detect the unevenness of the surface of the finger Fg (for example, a fingerprint) by detecting the light L2 reflected by the finger Fg. Alternatively, in addition to detecting fingerprints, the detection device 1 can also detect information related to a living body by detecting the light L2 reflected inside the finger Fg. The information related to a living body is, for example, a blood vessel image such as a vein, a pulse, a pulse wave, etc. The color of the light L1 from the lighting device 121 may also be different depending on the detection object.

[0031] The cover member 122 is a member for protecting the detection device 1 and the lighting device 121, and covers the detection device 1 and the lighting device 121. The cover member 122 is, for example, a glass substrate. In addition, the cover member 122 is not limited to a glass substrate, and may be a resin substrate or the like. In addition, the cover member 122 may not be provided. In this case, a protective layer such as an insulating film is provided on the surface of the detection device 1, and the finger Fg is in contact with the protective layer of the detection device 1.

[0032] The detection device 120 with a lighting device may also be provided with a display panel instead of the lighting device 121. The display panel may be, for example, an organic EL display panel (OLED: Organic Light Emitting Diode) or an inorganic EL display (micro LED, mini LED). Alternatively, the display panel may be a liquid crystal display panel (LCD: Liquid Crystal Display) using a liquid crystal element as a display element or an electrophoretic display panel (EPD: Electrophoretic Display) using an electrophoretic element as a display element. Even in this case, the display light (light L1) irradiated from the display panel passes through the detection device 1, and based on the light L2 reflected by the finger Fg, the fingerprint of the finger Fg and information related to the biological body can be detected. In addition, the stacking order of the display panel and the detection device 1 may also be reversed. That is, the display panel may also be stacked on the detection device 1.

[0033] Figure 2 FIG. 2 is a top view showing the detection device involved in the first embodiment. Figure 2 As shown, the detection device 1 includes an array substrate 2 (substrate 21 ), a sensor unit 10 , a scanning line driving circuit 15 , a signal line selecting circuit 16 , a detection circuit 48 , a control circuit 102 , and a power supply circuit 103 .

[0034] The control substrate 101 is electrically connected to the substrate 21 via the wiring substrate 110. The wiring substrate 110 is, for example, a flexible printed substrate or a rigid substrate. A detection circuit 48 is provided on the wiring substrate 110. A control circuit 102 and a power supply circuit 103 are provided on the control substrate 101. The control circuit 102 is, for example, an FPGA (Field Programmable Gate Array). The control circuit 102 supplies control signals to the sensor unit 10, the scan line driving circuit 15, and the signal line selecting circuit 16 to control the detection operation of the sensor unit 10. The power supply circuit 103 generates a power supply potential VDD and a reference potential VCOM (reference potential VCOM). Figure 4 ) and other voltage signals are supplied to the sensor unit 10, the scanning line driving circuit 15, and the signal line selecting circuit 16. In addition, although in the present embodiment, the detection circuit 48 is illustrated as being arranged on the wiring substrate 110, it is not limited thereto. The detection circuit 48 may also be arranged on the substrate 21.

[0035] The substrate 21 has a detection area AA and a peripheral area GA. The detection area AA is an area where a plurality of detection elements 3 of the sensor unit 10 are provided. The peripheral area GA is an area outside the detection area AA, and is an area where no detection element 3 is provided. That is, the peripheral area GA is an area between the periphery of the detection area AA and the outer edge of the substrate 21. The scan line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA.

[0036] The plurality of detection elements 3 of the sensor unit 10 are light sensors each having a photoelectric conversion element 30 as a sensor element. The photoelectric conversion element 30 is a photodiode that outputs an electrical signal corresponding to the light irradiated respectively. More specifically, the photoelectric conversion element 30 is a PIN (Positive Intrinsic Negative) photodiode. In addition, the photoelectric conversion element 30 may also be renamed as an OPD (Organic Photo Diode). The detection elements 3 are arranged in a matrix in the detection area AA. The photoelectric conversion elements 30 of the plurality of detection elements 3 perform detection according to a gate drive signal (for example, a reset control signal RST, a readout control signal RD) supplied from the scanning line drive circuit 15. The plurality of photoelectric conversion elements 30 outputs an electrical signal corresponding to the light irradiated respectively as a detection signal Vdet to the signal line selection circuit 16. The detection device 1 detects information related to the biological body based on the detection signal Vdet from the plurality of photoelectric conversion elements 30.

[0037] The scan line drive circuit 15 and the signal line selection circuit 16 are provided in the peripheral area GA. Specifically, the scan line drive circuit 15 is provided in a region extending along the second direction Dy in the peripheral area GA. The signal line selection circuit 16 is provided in a region extending along the first direction Dx in the peripheral area GA, and is provided between the sensor unit 10 and the detection circuit 48.

[0038] In addition, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21, and is a direction orthogonal to the first direction Dx. In addition, the second direction Dy may not intersect the first direction Dx orthogonally. In addition, the third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy, and is a normal direction of the substrate 21.

[0039] Figure 3 1 is a block diagram showing an example of the configuration of a detection device according to the first embodiment. Figure 3 As shown, the detection device 1 further includes a detection control circuit 11 and a detection unit 40. A part or all of the functions of the detection control circuit 11 are included in the control circuit 102. In addition, a part or all of the functions of the detection unit 40 other than the detection circuit 48 are included in the control circuit 102.

[0040] The detection control circuit 11 is a circuit that supplies control signals to the scan line drive circuit 15, the signal line selection circuit 16, and the detection unit 40, and controls their operations. The detection control circuit 11 supplies various control signals such as a start signal STV and a clock signal CK to the scan line drive circuit 15. In addition, the detection control circuit 11 supplies various control signals such as a selection signal ASW to the signal line selection circuit 16.

[0041] The scanning line driving circuit 15 drives a plurality of scanning lines (a readout control scanning line GLrd, a reset control scanning line GLrst (see Figure 4 The scanning line driving circuit 15 selects a plurality of scanning lines sequentially or simultaneously, and supplies a gate driving signal (for example, a reset control signal RST, a readout control signal RD) to the selected scanning lines. Thus, the scanning line driving circuit 15 selects a plurality of photoelectric conversion elements 30 connected to the scanning lines.

[0042] The signal line selection circuit 16 selects a plurality of output signal lines SL in sequence or simultaneously (see Figure 4 ). The signal line selection circuit 16 is, for example, a multiplexer. The signal line selection circuit 16 connects the selected output signal line SL to the detection circuit 48 based on the selection signal ASW supplied from the detection control circuit 11. Thus, the signal line selection circuit 16 outputs the detection signal Vdet of the photoelectric conversion element 30 to the detection unit 40.

[0043] The detection unit 40 includes a detection circuit 48, a signal processing circuit 44, a coordinate extraction circuit 45, a storage circuit 46, and a detection timing control circuit 47. The detection timing control circuit 47 controls the detection circuit 48, the signal processing circuit 44, and the coordinate extraction circuit 45 based on a control signal supplied from the detection control circuit 11 so as to operate synchronously.

[0044] The detection circuit 48 is, for example, an analog front end circuit (AFE). The detection circuit 48 is a signal processing circuit having at least the functions of the detection signal amplifier circuit 42 and the A / D converter circuit 43. The detection signal amplifier circuit 42 is a circuit for amplifying the detection signal Vdet, for example, an integration circuit. The A / D converter circuit 43 converts the analog signal output from the detection signal amplifier circuit 42 into a digital signal.

[0045] The signal processing circuit 44 is a logic circuit that detects a predetermined physical quantity input to the sensor unit 10 based on the output signal of the detection circuit 48. When the finger Fg contacts or approaches the detection surface, the signal processing circuit 44 can detect the concavity and convexity of the surface of the finger Fg or the palm based on the signal from the detection circuit 48. In addition, the signal processing circuit 44 can also detect information related to the living body based on the signal from the detection circuit 48. The information related to the living body is, for example, a blood vessel image, a pulse wave, a pulse, and a blood oxygen saturation of the finger Fg or the palm.

[0046] The storage circuit 46 temporarily stores the signal calculated by the signal processing circuit 44. The storage circuit 46 may be, for example, a RAM (Random Access Memory) or a register circuit.

[0047] The coordinate extraction circuit 45 is a logic circuit that obtains the detection coordinates of the concavo-convex surface of the finger Fg or the like when the contact or approach of the finger Fg is detected in the signal processing circuit 44. In addition, the coordinate extraction circuit 45 is a logic circuit that obtains the detection coordinates of the blood vessels of the finger Fg or the palm. The coordinate extraction circuit 45 combines the detection signals Vdet output from the detection elements 3 of the sensor unit 10 to generate two-dimensional information indicating the shape of the concavo-convex surface of the finger Fg or the like. In addition, the coordinate extraction circuit 45 may output the detection signal Vdet as the sensor output Vo without calculating the detection coordinates.

[0048] Next, a circuit configuration example of the detection device 1 will be described. Figure 4 is a circuit diagram showing a detection element. Figure 4 As shown, the detection element 3 has a photoelectric conversion element 30, a reset transistor Mrst, a readout transistor Mrd, and a source follower transistor Msf. In addition, in the detection element 3, a reset control scan line GLrst and a readout control scan line GLrd are provided as detection drive lines (scan lines), and an output signal line SL is provided as a wiring for signal readout.

[0049] In addition, Figure 4 , one detection element 3 is shown, but the reset control scanning line GLrst, the readout control scanning line GLrd, and the output signal line SL are connected to a plurality of detection elements 3. Specifically, the reset control scanning line GLrst and the readout control scanning line GLrd are connected in the first direction Dx (refer to Figure 2 ) and is connected to a plurality of detection elements 3 arranged in the first direction Dx. In addition, the output signal line SL extends in the second direction Dy and is connected to a plurality of detection elements 3 arranged in the second direction Dy.

[0050] The reset transistor Mrst, the read transistor Mrd, and the source follower transistor Msf are provided corresponding to one photoelectric conversion element 30. The plurality of transistors included in the detection element 3 are each formed of an n-type TFT (Thin Film Transistor), but this is not limiting, and each transistor may also be formed of a p-type TFT.

[0051] A reference potential VCOM is applied to the anode of the photoelectric conversion element 30. The cathode of the photoelectric conversion element 30 is connected to the node N1. The node N1 is connected to the capacitor Cs, the capacitor Cad, one of the source and the drain of the reset transistor Mrst, and the gate of the source follower transistor Msf. In addition, there is a parasitic capacitor Cp in the node N1. One end of the capacitor Cs and the capacitor Cad is connected to the node N1, and the other end is connected to the reference potential VCOM. When the photoelectric conversion element 30 is irradiated with light, the signal (charge) output from the photoelectric conversion element 30 is accumulated in the capacitor Cs and the capacitor Cad. Here, the capacitor Cs is, for example, an upper electrode 34 and a lower electrode 35 (see Figure 7 ) is formed between the first electrode 81 and the second electrode 82 (see Figure 7 ) forms a capacitance between them.

[0052] The gate of the reset transistor Mrst is connected to the reset control scanning line GLrst. The reset potential Vrst is supplied to the other of the source and drain of the reset transistor Mrst. When the reset transistor Mrst is turned on (conducting state) in response to the reset control signal RST, the potential of the node N1 is reset to the reset potential Vrst. The reference potential VCOM has a potential lower than the reset potential Vrst, and the photoelectric conversion element 30 is reverse biased and driven.

[0053] The source follower transistor Msf is connected between a terminal supplied with a power supply potential VDD and the read transistor Mrd (node ​​N2). The gate of the source follower transistor Msf is connected to the node N1. The gate of the source follower transistor Msf is supplied with a signal (charge) generated by the photoelectric conversion element 30. Thus, the source follower transistor Msf outputs a signal (voltage) corresponding to the signal (charge) generated in the photoelectric conversion element 30 to the read transistor Mrd.

[0054] The read transistor Mrd is connected between the source (node ​​N2) of the source follower transistor Msf and the output signal line SL (node ​​N3). The gate of the read transistor Mrd is connected to the read control scanning line GLrd. When the read transistor Mrd is turned on in response to the read control signal RD, the signal output from the source follower transistor Msf, that is, the signal voltage corresponding to the signal (charge) generated in the photoelectric conversion element 30, is output to the output signal line SL as the detection signal Vdet.

[0055] In this embodiment, by adding a capacitor Cad in addition to the capacitor Cs, it is possible to suppress a decrease in the potential of the node N1 during the exposure period between the reset period (a period during which the potential of the node N1 is reset to the reset potential Vrst) and the read period (a period during which the read transistor Mrd is turned on). As a result, a deviation in the potential of the node N1 is suppressed, and as a result, a deviation in the signal (voltage) output from the source follower transistor Msf is suppressed.

[0056] In addition, Figure 4 In the example shown, the reset transistor Mrst and the read transistor Mrd are respectively a so-called dual-gate structure formed by connecting two transistors in series. However, it is not limited to this, and the reset transistor Mrst and the read transistor Mrd can be a single-gate structure, or three or more transistors can be connected in series. In addition, the circuit of a detection element 3 is not limited to a structure having three transistors: the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd. The detection element 3 can have two transistors or four or more transistors.

[0057] Next, the planar structure and cross-sectional structure of the detection element 3 will be described. Figure 5 FIG. 1 is a top view showing the detection element. Figure 5 As shown, one detection element 3 is formed in a region surrounded by two reset control scanning lines GLrst and two output signal lines SL.

[0058] The plurality of reset control scanning lines GLrst extend in the first direction Dx and are arranged in parallel in the second direction Dy. The plurality of output signal lines SL extend in the second direction Dy and are arranged in parallel in the first direction Dx.

[0059] The photoelectric conversion element 30 is provided in a region surrounded by two reset control scanning lines GLrst adjacent to each other in the second direction Dy and two output signal lines SL adjacent to each other in the first direction Dx. The upper electrode 34 and the lower electrode 35 are opposed to each other in the third direction Dz with the photoelectric conversion element 30 interposed therebetween. Specifically, the photoelectric conversion element 30 is arranged with the lower electrode 35 interposed therebetween on the array substrate 2 provided with various wirings and various transistors.

[0060] The lower electrode 35 has a larger area than the photoelectric conversion element 30 and the upper electrode 34. The lower electrode 35 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the contact hole H2 in the portion that does not overlap with the photoelectric conversion element 30 and the upper electrode 34. The upper electrode 34 is provided to cover the photoelectric conversion element 30 and is electrically connected to the photoelectric conversion element 30 via the contact hole H1. The upper electrode 34 is connected to the reference potential supply line via the connection wiring 36 to supply the reference potential VCOM to the photoelectric conversion element 30. In addition, although not shown in the figure, the reference potential supply line is extended in the second direction Dy so as to overlap with the output signal line SL, for example.

[0061] In addition, a first electrode 81 and a second electrode 82 are provided in a region overlapping the photoelectric conversion element 30. A capacitor Cad is formed between the first electrode 81 and the second electrode 82. The detailed configuration of the photoelectric conversion element 30, the first electrode 81, and the second electrode 82 will be described later.

[0062] Figure 6 It is a top view of the array substrate constituting the detection element. Figure 6 It is a plan view schematically showing a part of the detection element 3 , that is, a member above the photoelectric conversion element 30 , without the part.

[0063] like Figure 6 As shown, the detection element 3 also includes a readout control scan line GLrd and two signal lines (a power signal line SLsf and a reset signal line SLrst). The readout control scan line GLrd extends in the first direction Dx and is arranged in a second direction Dy with the reset control scan line GLrst. In one detection element 3, a photoelectric conversion element 30, a plurality of transistors, and a capacitor Cad are provided between the reset control scan line GLrst and the readout control scan line GLrd adjacent to each other in the second direction Dy. In addition, the power signal line SLsf and the reset signal line SLrst extend in the second direction Dy, respectively, and are arranged in a first direction Dx with the output signal line SL.

[0064] Figure 5 The photoelectric conversion element 30 shown is arranged on an array substrate 2 provided with various wirings and various transistors, and is arranged to overlap with at least a portion of the various transistors. In addition, it is arranged in an area overlapping with at least a portion of the power signal line SLsf, the reset signal line SLrst and the readout control scan line GLrd.

[0065] like Figure 6As shown, the reset transistor Mrst includes a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. One end of the semiconductor layer 61 is connected to the reset signal line SLrst. The other end of the semiconductor layer 61 is connected to the connection wiring SLcn. The portion of the reset signal line SLrst connected to the semiconductor layer 61 functions as the source electrode 62, and the portion of the connection wiring SLcn connected to the semiconductor layer 61 functions as the drain electrode 63. The gate electrode 64 is opposite to the semiconductor layer 61. More specifically, two branches branching in the second direction Dy are provided in the reset control scanning line GLrst, and the semiconductor layer 61 intersects the two branches of the reset control scanning line GLrst. The two branches are adjacently provided in the first direction Dx. The portions of the two branches of the reset control scanning line GLrst that overlap with the semiconductor layer 61 function as the gate electrode 64. A channel region is formed in the portion of the semiconductor layer 61 that overlaps with the two branches of the reset control scanning line GLrst.

[0066] The connection wiring SLcn is formed in an inverted L shape and includes a portion extending in the first direction Dx and a portion extending in the second direction Dy. The end of the portion of the connection wiring SLcn extending in the first direction Dx is connected to the connection wiring SLcn via the contact hole H2 (see Figure 5 ) is connected to the cathode (n-type semiconductor layer 33) of the photoelectric conversion element 30. In addition, the reset transistor Mrst is connected to the gate of the source follower transistor Msf via the portion of the connection wiring SLcn extending in the second direction Dy. That is, the connection wiring SLcn is connected to Figure 4 Corresponding to node N1.

[0067] The source follower transistor Msf has a semiconductor layer 65, a source electrode 67, a drain electrode 66, and a gate electrode 68. One end of the semiconductor layer 65 is connected to the power signal line SLsf. The other end of the semiconductor layer 65 is connected to the read transistor Mrd via the connection wiring SLcna. The portion of the power signal line SLsf connected to the semiconductor layer 65 functions as the drain electrode 66, and the portion of the connection wiring SLcna connected to the semiconductor layer 65 functions as the source electrode 67.

[0068] One end of the gate electrode 68 is connected to the connection wiring SLcn via a contact hole. The semiconductor layer 65 intersects with the gate electrode 68. A channel region is formed in a portion of the semiconductor layer 65 intersecting with the gate electrode 68.

[0069] With such a configuration, the cathode (n-type semiconductor layer 33 ) of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the connection wiring SLcn.

[0070] The read transistor Mrd has a semiconductor layer 71, a source electrode 73, a drain electrode 72, and a gate electrode 74. One end of the semiconductor layer 71 is connected to the source follower transistor Msf via the connection wiring SLcna. The other end of the semiconductor layer 71 is connected to the output signal line SL. The portion of the output signal line SL connected to the semiconductor layer 71 functions as the source electrode 73. The portion of the connection wiring SLcna connected to the semiconductor layer 71 functions as the drain electrode 72. Two branches extending in the second direction Dy are connected to the read control scan line GLrd. The two branches are arranged adjacent to each other in the first direction Dx. The semiconductor layer 71 intersects with the two branches branched from the read control scan line GLrd. The two branches of the read control scan line GLrd function as the gate electrode 74. In such a configuration, the source follower transistor Msf and the read transistor Mrd are connected to the output signal line SL.

[0071] In a plan view, the first electrode 81 and the second electrode 82 are arranged in an area overlapping with the photoelectric conversion element 30 and not overlapping with the reset transistor Mrst, the source follower transistor Msf, and the read transistor Mrd. The first electrode 81 includes a main portion 81a, a connecting portion 81b, a secondary portion 81c, and a connecting portion 81d. The second electrode 82 includes a main portion 82a, a connecting portion 82b, and a secondary portion 82c. The main portion 81a is arranged to overlap with the main portion 82a, the connecting portion 81b is arranged to overlap with the connecting portion 82b, and the secondary portion 81c is arranged to overlap with the secondary portion 82c.

[0072] The main portion 81a and the main portion 82a are formed to have the largest area among the portions constituting the first electrode 81 and the second electrode 82, and are arranged in a region surrounded by the output signal line SL, the connection wiring SLcn, the source follower transistor Msf, and the read transistor Mrd. The end of the second electrode 82 on the second direction Dy side of the main portion 82a is connected to the portion of the connection wiring SLcn extending in the first direction Dx via four contact holes H3. Thus, the second electrode 82 is electrically connected to the cathode of the photoelectric conversion element 30, the reset transistor Mrst, and the gate of the source follower transistor Msf via the connection wiring SLcn (node ​​N1).

[0073] The connection portion 81b and the connection portion 82b are arranged to intersect the portion of the connection wiring SLcn extending in the second direction Dy. The connection portion 81b connects the main portion 81a and the auxiliary portion 81c adjacent to each other in the first direction Dx. The connection portion 82b connects the main portion 82a and the auxiliary portion 82c adjacent to each other in the first direction Dx. The width of the connection portion 81b and the connection portion 82b in the second direction Dy is smaller than the width of the main portion 81a and the main portion 82a in the second direction Dy.

[0074] The auxiliary portions 81c and 82c are provided between the reset signal line SLrst and the power signal line SLsf. The widths of the auxiliary portions 81c and 82c in the second direction Dy are larger than the widths of the connecting portions 81b and 82b in the second direction Dy.

[0075] The connecting portion 81d connects the main portion 81a and the auxiliary portion 81c of the detection element 3 adjacent to each other in the first direction Dx. In other words, the first electrode 81 overlaps with the plurality of detection elements 3 arranged in the first direction Dx and extends in the first direction Dx. The first electrode 81 is connected to the reference potential VCOM at an arbitrary position. In addition, the second electrode 82 is separately provided in units of the detection element 3. That is, when viewed from above, the first electrode 81 and the second electrode 82 overlap with the photoelectric conversion element 30. The first electrode 81 has a plurality of main portions 81a respectively overlapping with the photoelectric conversion element 30 and a connecting portion 81d connecting the adjacent main portions 81a. In addition, the second electrode 82 is formed in an island shape on each of the plurality of photoelectric conversion elements 30.

[0076] With such a configuration, the first electrode 81 and the second electrode 82 form capacitance between the opposing main portions 81a and 82a, respectively, and further, capacitance is formed between the opposing connecting portions 81b and 82b, and between the opposing auxiliary portions 81c and 82c, and a large capacitance Cad is formed as a whole. However, this is not limited to this, and the first electrode 81 and the second electrode 82 may not have the connecting portions 81b, 82b, and the auxiliary portions 81c, 82c.

[0077] In addition, the first electrode 81 and the second electrode 82 have chamfered corners 81e and 82e. That is, no sharp portion is formed at the ends of the first electrode 81 and the second electrode 82. Therefore, compared with the case where the corners of the first electrode 81 and the second electrode 82 are formed at right angles, it is possible to suppress the concentration of the electric field at the ends of the first electrode 81 and the second electrode 82. Therefore, the detection device 1 can suppress the generation of ESD (Electro-Static Discharge) in the manufacturing process of the array substrate 2.

[0078] also, Figure 5 as well as Figure 6 The planar structure of the photoelectric conversion element 30, capacitor Cad, and each transistor shown is only an example and can be changed appropriately. For example, the configuration of multiple transistors can also be different. For example, in this embodiment, the semiconductor layer 65 and the semiconductor layer 71 are separately configured, but it is not limited to this. The source follower transistor Msf and the read transistor Mrd can also be formed by a common semiconductor layer.

[0079] In addition, the configuration of the first electrode 81 and the second electrode 82 may be appropriately changed according to the configuration of each transistor. Figure 5 and Figure 6 In the embodiment, the area of ​​the second electrode 82 is larger than that of the first electrode 81, and the periphery of the second electrode 82 is arranged to surround the periphery of the first electrode 81. However, this is not limited to this, and the area relationship between the second electrode 82 and the first electrode 81 may be opposite or the same area.

[0080] Figure 7 yes Figure 6 VII-VII' cross-sectional view. In addition, Figure 7 , the cross-sectional structure of the reset transistor Mrst among the three transistors included in the detection element 3 is shown, but the cross-sectional structures of the source follower transistor Msf and the read transistor Mrd are also the same as that of the reset transistor Mrst.

[0081] The substrate 21 is an insulating substrate, for example, a glass substrate such as quartz or alkali-free glass is used. The substrate 21 has a first main surface S1 and a second main surface S2 opposite to the first main surface S1. Various transistors including a reset transistor Mrst, various wirings (scanning lines and signal lines), a first electrode 81, a second electrode 82, and an insulating film are provided on the first main surface S1 of the substrate 21 to form an array substrate 2. The photoelectric conversion element 30 is arranged on the array substrate 2, that is, on the first main surface S1 side of the substrate 21.

[0082] The primer film 22 is provided on the first main surface S1 of the substrate 21. The primer film 22, the insulating films 23, 24, 25, and the insulating films 27, 28 are inorganic insulating films, such as silicon oxide (SiO2), silicon nitride (SiN), and the like.

[0083] In the cross-sectional structure of the reset transistor Mrst, the semiconductor layer 61 is provided on the primer film 22. The semiconductor layer 61 uses polysilicon, for example. However, the semiconductor layer 61 is not limited thereto, and may also be microcrystalline oxide semiconductor, amorphous oxide semiconductor, low temperature polysilicon (LTPS) or the like.

[0084] The insulating film 23 covers the semiconductor layer 61 and is disposed on the primer film 22. The gate electrode 64 is disposed on the insulating film 23. In addition, the gate electrode 68 of the source follower transistor Msf is also disposed on the insulating film 23 in the same layer as the gate electrode 64. The insulating film 23 is a gate insulating film, and TEOS (Tetra Ethyl Ortho Silicate) can be used as a material of the insulating film 23. The reset control scanning line GLrst and the readout control scanning line GLrd (see Figure 6) is also provided in the same layer as the gate electrode 64. The insulating film 24 is provided on the insulating film 23 to cover the gate electrodes 64 and 68.

[0085] The reset transistor Mrst has a top gate structure in which the gate electrode 64 is arranged on the upper side of the semiconductor layer 61 , but can also be a bottom gate structure in which the gate electrode 64 is arranged on the lower side of the semiconductor layer 61 , or can also be a double gate structure in which the gate electrodes 64 are arranged on the upper and lower sides of the semiconductor layer 61 .

[0086] The insulating film 24 and the insulating film 25 cover the gate electrode 64 and are provided on the insulating film 23. The source electrode 62 and the drain electrode 63 are provided on the insulating film 25. The source electrode 62 and the drain electrode 63 are connected to the semiconductor layer 61 via contact holes penetrating the insulating films 23, 24, and 25, respectively. The source electrode 62 and the drain electrode 63 are composed of, for example, a stacked film of TiAlTi or TiAl, which is a stacked structure of titanium and aluminum.

[0087] In addition, various signal lines (output signal line SL (refer to Figure 5 ), power signal line SLsf and reset signal line SLrst) and connection wiring SLcn are provided in the same layer as source electrode 62 and drain electrode 63. Connection wiring SLcn is connected to gate electrode 68 of source follower transistor Msf via a contact hole penetrating insulating films 24 and 25.

[0088] The first electrode 81 and the second electrode 82 forming the capacitor Cad are arranged using two layers of each layer constituting a transistor (for example, a reset transistor Mrst). In the present embodiment, the first electrode 81 and the second electrode 82 are arranged between the substrate 21 and the photoelectric conversion element 30 in the third direction Dz. The second electrode 82 is arranged on the primer film 22, and is opposite to the first electrode 81 across the insulating film 23 in the third direction Dz. The first electrode 81 is in the same layer as the gate electrode 64 and is formed of the same material as the gate electrode 64. The second electrode 82 is in the same layer as the semiconductor layer 61 and is formed of the same material as the semiconductor layer 61. The second electrode 82 has an area larger than the first electrode 81 and extends to a region overlapping with the connection wiring SLcn. The second electrode 82 is connected to the connection wiring SLcn via four contact holes H3 that penetrate the insulating films 23, 24, and 25.

[0089] Since the first electrode 81 and the second electrode 82 are provided in the same layer as the reset transistor Mrst, the manufacturing process is simpler than a configuration in which the capacitor Cad is formed in a layer different from the reset transistor Mrst, and the detection device 1 (array substrate 2) can be made thinner.

[0090] The insulating film 26 covers various transistors such as the reset transistor Mrst and the capacitor Cad and is provided on the insulating film 25. The insulating film 26 is an organic insulating film made of an organic material such as photosensitive acrylic. The insulating film 26 is thicker than the insulating film 25. Compared with inorganic insulating materials, the insulating film 26 has good coverage of height differences and can flatten the height differences formed by various transistors and various wirings.

[0091] Next, the cross-sectional structure of the photoelectric conversion element 30 is described. The photoelectric conversion element 30 is disposed on the insulating film 26. Specifically, the lower electrode 35 is disposed on the insulating film 26 and is electrically connected to the connection wiring SLcn via the contact hole H2. The photoelectric conversion element 30 is connected to the lower electrode 35. The lower electrode 35 can adopt a stacked structure of titanium (Ti) and titanium nitride (TiN), for example. The lower electrode 35 is disposed between the substrate 21 and the photoelectric conversion element 30, so the lower electrode 35 functions as a light shielding layer, which can suppress the intrusion of light from the second main surface S2 side of the substrate 21 into the photoelectric conversion element 30.

[0092] The photoelectric conversion element 30 is configured to include a semiconductor layer having a photoelectromotive force effect. Specifically, the semiconductor layer of the photoelectric conversion element 30 includes an i-type semiconductor layer 31, a p-type semiconductor layer 32, and an n-type semiconductor layer 33. The i-type semiconductor layer 31, the p-type semiconductor layer 32, and the n-type semiconductor layer 33 are, for example, amorphous silicon (a-Si). In addition, the material of the semiconductor layer is not limited thereto, and may also be polycrystalline silicon, microcrystalline silicon, etc.

[0093] The p-type semiconductor layer 32 is formed by doping impurities in a-Si to form a p+ region. The n-type semiconductor layer 33 is formed by doping impurities in a-Si to form an n+ region. The i-type semiconductor layer 31 is, for example, an undoped intrinsic semiconductor and has lower conductivity than the p-type semiconductor layer 32 and the n-type semiconductor layer 33.

[0094] In the direction (third direction Dz) perpendicular to the surface of substrate 21, i-type semiconductor layer 31 is provided between n-type semiconductor layer 33 and p-type semiconductor layer 32. In the present embodiment, n-type semiconductor layer 33, i-type semiconductor layer 31, and p-type semiconductor layer 32 are stacked on lower electrode 35 in this order.

[0095] Thus, the n-type semiconductor layer 33 of the photoelectric conversion element 30 is electrically connected to the reset transistor Mrst and the source follower transistor Msf via the lower electrode 35 and the connection wiring SLcn.

[0096] The upper electrode 34 is provided on the p-type semiconductor layer 32. The upper electrode 34 is, for example, a light-transmitting conductive material such as ITO (Indium Tin Oxide). The insulating film 27 covers the photoelectric conversion element 30 and the upper electrode 34 and is provided on the insulating film 26. A contact hole H1 is provided in a region of the insulating film 27 that overlaps with the upper electrode 34.

[0097] The connection wiring 36 is provided on the insulating film 27 and is electrically connected to the upper electrode 34 via the contact hole H1. The reference potential VCOM (see Figure 4 ).

[0098] The photoelectric conversion element 30 is disposed on the insulating film 26, that is, disposed on the upper side of the plurality of transistors and the capacitor Cad. In other words, the first electrode 81 and the second electrode 82 constituting the capacitor Cad are less restricted by the configuration and shape of the photoelectric conversion element 30, and thus can be formed in a large area using an area that does not overlap with the plurality of transistors. Thus, the capacitance value of the capacitor Cad can be increased.

[0099] The insulating film 28 covers the upper electrode 34 and the connection wiring 36 and is provided on the insulating film 27. The insulating film 28 is provided as a protective layer to suppress the intrusion of moisture into the photoelectric conversion element 30. Furthermore, the insulating film 29 covers the plurality of photoelectric conversion elements 30 and is provided on the insulating film 28. The insulating film 29 is a hard coating film formed of an organic material. The insulating film 29 flattens the height difference of the surface of the insulating film 28 formed by the photoelectric conversion element 30 and the connection wiring 36.

[0100] The cover member 122 is provided so as to cover various transistors and the photoelectric conversion element 30 via an adhesive layer 125. The adhesive layer 125 bonds the insulating film 29 to the cover member 122. The adhesive layer 125 is, for example, a light-transmitting optical adhesive sheet (OCA: Optical Clear Adhesive).

[0101] As described above, the detection device 1 of the present embodiment includes: a substrate 21; a plurality of photoelectric conversion elements 30 arranged on the substrate 21; a plurality of transistors (source follower transistor Msf, reset transistor Mrst, and read transistor Mrd) including a semiconductor layer 61 and a gate electrode 64 opposite to the semiconductor layer 61, and arranged corresponding to the plurality of photoelectric conversion elements 30, respectively; and a first electrode 81 and a second electrode 82, which are arranged between the substrate 21 and the photoelectric conversion element 30 in a direction perpendicular to the substrate 21, and are opposite to each other via the insulating film 23. The first electrode 81 is in the same layer as the gate electrode 64, and the second electrode 82 is in the same layer as the semiconductor layer 61.

[0102] Thus, a capacitor Cad is formed between the first electrode 81 and the second electrode 82, thereby suppressing the decrease in the potential of the node N1 (the cathode of the photoelectric conversion element 30, the gate of the source follower transistor Msf, and the source or drain of the reset transistor Mrst) during the exposure period. As a result, the detection device 1 can suppress the deviation of the signal output from the source follower transistor Msf. In addition, the first electrode 81 and the second electrode 82 are formed on the same layer as the transistor, so compared with a structure set on a layer different from the transistor, the detection device 1 (array substrate 2) can be thinned.

[0103] (Second Embodiment)

[0104] Figure 8 It is a top view of an array substrate constituting a detection element according to the second embodiment. In the following description, the same reference numerals are given to the same components as those described in the above embodiment, and duplicate descriptions are omitted.

[0105] like Figure 8 As shown, in the detection element 3A of the second embodiment, the configuration of the first electrode 81A and the second electrode 82A constituting the capacitor Cad is different from that of the first embodiment described above. Specifically, the first electrode 81A has a main portion 81Aa and a connecting portion 81Ab. The main portion 81Aa is provided in an area surrounded by the output signal line SL, the power signal line SLsf, the reset control scanning line GLrst, the source follower transistor Msf, and the read transistor Mrd. The connecting portion 81Ab extends in the first direction Dx in a manner intersecting each signal line, and connects the main portions 81Aa adjacent to each other in the first direction Dx.

[0106] The second electrode 82A is provided overlapping the main portion 81Aa of the first electrode 81A. The second electrode 82A also serves as the connection wiring SLcn. That is, one end side of the second electrode 82A in the second direction Dy is connected to the semiconductor layer 61 of the reset transistor Mrst. In addition, one end side of the second electrode 82A in the second direction Dy is connected to the semiconductor layer 61 of the reset transistor Mrst via the contact hole H2 (see Figure 5 ) is electrically connected to the cathode of the photoelectric conversion element 30. Furthermore, the other end side of the second electrode 82A in the second direction Dy is electrically connected to the gate electrode 68 of the source follower transistor Msf.

[0107] In the second embodiment, the first electrode 81A is also connected to the reference potential VCOM. The second electrode 82A functions as the node N1. In addition, the first electrode 81A is provided with a chamfered portion 81Ae. In addition, the second electrode 82A may also be formed with a chamfered portion.

[0108] Fig. 9 yes Figure 8 IX-IX' cross-section diagram. Fig. 9 As shown, in the detection device 1A of the second embodiment, the first electrode 81A and the second electrode 82A are opposed to each other via the insulating films 24 and 25. The first electrode 81A is in the same layer as the gate electrode 64 and is formed of the same material as the gate electrode 64. The second electrode 82A is in the same layer as the source electrode 62 and the drain electrode 63 and is formed of the same material as the source electrode 62 and the drain electrode 63.

[0109] In this embodiment, the first electrode 81A and the second electrode 82A are also provided between the substrate 21 and the photoelectric conversion element 30 in the third direction Dz. In addition, the first electrode 81A and the second electrode 82A are provided in a region that does not overlap with the plurality of transistors in a plan view.

[0110] Furthermore, the second embodiment may be combined with the configuration of the first embodiment. Fig. 9 In the embodiment, the primer film 22 and the insulating film 23 are stacked between the first electrode 81A and the substrate 21, and no electrode is provided. However, as in the first embodiment, the first electrode 81 opposite to the first electrode 81A may be provided on the same layer as the semiconductor layer 61. In this case, in the capacitor Cad, the capacitor formed between the first electrode 81A and the second electrode 82A and the capacitor formed between the first electrode 81A and the first electrode 81 are connected in parallel. Thus, even when the area of ​​the detection element 3A is small, the capacitor Cad can be ensured.

[0111] (Third Embodiment)

[0112] Fig.10 FIG. 2 is a top view showing a detection element according to a third embodiment. Fig.10 As shown in FIG. 1 , the detection element 3B of the third embodiment has a second electrode 82B. Fig.10 In the figure, the second electrode 82B is indicated by a two-dot chain line for easy viewing of the drawing.

[0113] The second electrode 82B is arranged to overlap with the upper electrode 34, and the capacitor Cad is formed by the opposing second electrode 82B and the upper electrode 34. That is, the upper electrode 34 corresponds to the first electrodes 81 and 81A in the above-mentioned first embodiment and the second embodiment. The upper electrode 34 is connected to the reference potential VCOM in the same way as the first electrodes 81 and 81A. In addition, the second electrode 82B is formed in a rectangular shape in a manner that occupies most of the area surrounded by two adjacent output signal lines SL and two adjacent reset control scanning lines GLrst. In addition, when viewed from above, the second electrode 82B is formed with an area larger than that of the photoelectric conversion element 30, and is connected to the connection wiring SLcn (refer to Fig.11 )connect.

[0114] Fig.11 FIG. 1 is a top view of an array substrate constituting a detection element according to the third embodiment. Fig.11 In FIG. 8 , the positional relationship between the second electrode 82B and the upper electrode 34 is indicated by a double-dashed line. Fig.11 As shown, the second electrode 82B and the upper electrode 34 are arranged in the region overlapping with the source follower transistor Msf, the read transistor Mrd and the reset transistor Mrst. In other words, the electrode forming the capacitor Cad is arranged in a layer different from the plurality of transistors and is not arranged on the side of the array substrate 2. The second electrode 82B and the upper electrode 34 are arranged separately from each other in each region surrounded by the output signal line SL and the reset control scanning line GLrst.

[0115] Fig.12 yes Fig.11 XII-XII' section diagram. Fig.12 As shown, the upper electrode 34 is provided on the photoelectric conversion element 30, and the second electrode 82B is provided on the upper electrode 34 via the insulating film 28. The second electrode 82B extends to a region that does not overlap with the photoelectric conversion element 30, and is connected to the connection wiring SLcn via a contact hole H2A that penetrates the insulating films 27 and 28. The second electrode 82B is formed of a light-transmitting conductive material such as ITO, similarly to the upper electrode 34.

[0116] The second electrode 82B is disposed in a region overlapping with multiple transistors such as the reset transistor Mrst, and there are fewer restrictions caused by multiple transistors and various wirings. Therefore, in this embodiment, the area of ​​the second electrode 82B can be increased compared to the first and second embodiments described above. That is, a larger capacitor Cad can be formed.

[0117] This embodiment can be combined with at least one of the first and second embodiments described above. That is, a first electrode and a second electrode facing each other with an insulating film interposed therebetween may be provided in a region between the photoelectric conversion element 30 and the substrate 21 and not overlapping with the plurality of transistors.

[0118] The preferred embodiments of the present invention have been described above, but the present invention is not limited to such embodiments. The contents disclosed in the embodiments are only examples, and various changes can be made without departing from the scope of the gist of the present invention. The appropriate changes made without departing from the scope of the gist of the present invention certainly also belong to the technical scope of the present invention.

[0119] Description of Reference Numerals

[0120] 1, 1A: detection device; 2: array substrate; 3, 3A, 3B: detection element; 10: sensing part; 15: scanning line driving circuit; 16: signal line selection circuit; 21: substrate; 22: primer film; 23, 24, 25, 26, 27, 28, 29: insulating film; 30: photoelectric conversion element; 81: first electrode; 82: second electrode; AA: detection area; Cs, Cad: capacitance; Cp: parasitic capacitance; GA: peripheral area; GLrst: reset control scanning line; GLrd: readout control scanning line; SL: output signal line; SLsf: power supply signal line; SLrst: reset signal line; Mrst: reset transistor; Msf: source follower transistor; Mrd: readout transistor.

Claims

1. A detection device, comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, are respectively provided corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the semiconductor layer, At least one of the first electrode and the second electrode has a chamfered portion having a chamfered corner in a plan view.

2. A detection device, comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer, a gate electrode opposite to the semiconductor layer, and a source electrode connected to the semiconductor layer, and arranged corresponding to the plurality of photoelectric conversion elements respectively; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the source electrode, At least one of the first electrode and the second electrode has a chamfered portion having a chamfered corner in a plan view.

3. The detection device according to claim 1 or 2, wherein: In a plan view, the first electrode and the second electrode are provided in a region that does not overlap with the plurality of transistors. The first electrode and the second electrode overlap with the photoelectric conversion element in a plan view.

4. The detection device according to claim 1 or 2, wherein: The plurality of photoelectric conversion elements are arranged side by side in a first direction, The connecting portion of the first electrode electrically connects the main portions adjacent to each other in the first direction.

5. A detection device comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors are respectively arranged corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided in a region overlapping the photoelectric conversion element and the plurality of transistors in a plan view, and are opposed to each other via an insulating film in a direction perpendicular to the substrate. The first electrode is disposed on the photoelectric conversion element. The second electrode is provided on the first electrode via the insulating film.

6. The detection device according to claim 5, wherein: The detection device comprises: an organic insulating film covering the plurality of transistors; and a lower electrode disposed between the organic insulating film and the photoelectric conversion element in a direction perpendicular to the substrate and electrically connected to the photoelectric conversion element, The second electrode extends in a region not overlapping with the photoelectric conversion element, and is electrically connected to the lower electrode via a contact hole penetrating the insulating film.

7. The detection device according to claim 5 or 6, wherein: The detection device includes a plurality of signal lines and a plurality of scanning lines connected to the plurality of transistors. The photoelectric conversion element, the first electrode, and the second electrode are provided in each region surrounded by the plurality of the signal lines and the plurality of the scanning lines.

8. The detection device according to any one of claims 1, 2 and 5, wherein: The first electrode is connected to a reference potential, The second electrode is electrically connected to the transistor and the photoelectric conversion element.

9. The detection device according to any one of claims 1, 2 and 5, wherein: The plurality of transistors include a source follower transistor, a reset transistor, and a readout transistor, The second electrode is electrically connected to one of a source and a drain of the reset transistor and a gate of the source follower transistor.

10. The detection device according to any one of claims 1, 2 and 5, wherein: The photoelectric conversion element includes an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer stacked on the substrate.

11. A detection device comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, are respectively provided corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the semiconductor layer, The plurality of photoelectric conversion elements are arranged side by side in a first direction, The connecting portion of the first electrode electrically connects the main portions adjacent to each other in the first direction.

12. A detection device comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, are respectively provided corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the semiconductor layer, The first electrode is connected to a reference potential, The second electrode is electrically connected to the transistor and the photoelectric conversion element.

13. A detection device comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, are respectively provided corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the semiconductor layer, The plurality of transistors include a source follower transistor, a reset transistor, and a readout transistor, The second electrode is electrically connected to one of a source and a drain of the reset transistor and a gate of the source follower transistor.

14. A detection device comprising: substrate; A plurality of photoelectric conversion elements are arranged on the substrate; A plurality of transistors, including a semiconductor layer and a gate electrode opposite to the semiconductor layer, are respectively provided corresponding to the plurality of the photoelectric conversion elements; as well as The first electrode and the second electrode are provided between the substrate and the photoelectric conversion element in a direction perpendicular to the substrate and face each other with an insulating film interposed therebetween. The first electrode comprises: a plurality of main portions overlapping the photoelectric conversion elements respectively; and a connecting portion connecting adjacent main portions. The second electrode is formed in an island shape on each of the plurality of photoelectric conversion elements. The first electrode is in the same layer as the gate electrode, The second electrode is in the same layer as the semiconductor layer, The photoelectric conversion element includes an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer stacked on the substrate.

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