Ranging method and apparatus, receiving device, and storage medium

Abstract

Embodiments of the present application disclose a ranging method and device, a receiving device and a storage medium. The method comprises: in the process of receiving a ranging frame, switching the clock phase of an ADC at a plurality of preset sampling clock switching points, so that the ADC samples to obtain a plurality of phase corresponding sampling signals based on a plurality of clock phases; obtaining a channel estimation value corresponding to each phase according to the sampling signal of each phase; obtaining positioning information for ranging according to all channel estimation values; and sampling signals by switching clock phases, which is conducive to the baseband processing unit obtaining more channel estimation values by time-sharing processing, achieving equivalent high clock sampling rate positioning information by sampling at a lower clock sampling rate, effectively reducing the area and power consumption of the baseband processor, and improving the ranging accuracy without changing the data processing complexity of the baseband processing unit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of wireless communication, and particularly relates to a ranging method and device, a receiving device and a storage medium. BACKGROUND

[0002] At present, the application of time of flight (TOF) ranging is more and more common. A receiving device samples a signal through a high-speed analog-to-digital converter (ADC), and then a baseband processor obtains positioning information according to the sampled signal to obtain a time of flight, and performs positioning according to the time of flight.

[0003] The accuracy of the positioning information obtained by the baseband processor completely depends on the sampling of the ADC. A higher ADC clock sampling rate usually enables higher-accuracy positioning information, and higher positioning accuracy. However, the higher the ADC clock sampling rate, the greater the amount of data that needs to be processed by the baseband processor, and the higher the processing complexity and power consumption of the baseband processor. SUMMARY

[0004] Embodiments of the present application disclose a ranging method, device, receiving device and storage medium, which can improve ranging accuracy without changing the processing complexity of the baseband processor.

[0005] In a first aspect, a ranging method is disclosed, which can include:

[0006] In the process of receiving a ranging frame, the clock phase of the ADC is switched at a plurality of preset sampling clock switching points, so that the ADC samples a plurality of phase corresponding sampling signals based on a plurality of clock phases;

[0007] According to the sampling signal corresponding to each phase, a channel estimation value corresponding to the phase is obtained;

[0008] According to all the channel estimation values, positioning information for ranging is obtained.

[0009] As an optional implementation, in the first aspect of the embodiments of the present application, the process of receiving a ranging frame, the clock phase of the ADC is switched at a plurality of preset sampling clock switching points, so that the ADC samples a plurality of phase corresponding sampling signals based on a plurality of clock phases, including:

[0010] During the process of receiving the ranging frame, a plurality of preset sampling clock switching points are detected by the baseband processor, and the phase of the clock switched by a phase-locked loop (PLL) is controlled to the ADC at the plurality of sampling clock switching points respectively, so that the ADC samples to obtain a plurality of sampling signals at a corresponding phase after each switching of the clock phase. The clock phase switched by the plurality of sampling clock switching points includes a plurality of different phases.

[0011] As an optional implementation, in the first aspect of the embodiment of the present application, the channel estimation value corresponding to each phase is obtained according to the sampling signal corresponding to the phase, and the method comprises:

[0012] The plurality of sampling signals obtained by each switching are processed to obtain a plurality of channel estimation values.

[0013] The channel estimation value corresponding to each phase is obtained in combination with a plurality of phase switchings.

[0014] The positioning information used for ranging is obtained according to all the channel estimation values, and the method comprises:

[0015] The channel estimation values of all phases are arranged.

[0016] The best synchronization position is obtained by interpolation processing according to the arranged channel estimation values.

[0017] The time of flight (TOF) is calculated according to the best synchronization position.

[0018] The positioning information is obtained according to the TOF.

[0019] As an optional implementation, in the first aspect of the embodiment of the present application, the clock phase switched by any one of the sampling clock switching points has a phase difference from the clock phase switched by the immediately next sampling clock switching point.

[0020] As an optional implementation, in the first aspect of the embodiment of the present application, the sampling clock switching point is arranged at any time point of the idle gap (GAP) of the ranging frame.

[0021] The second aspect of the embodiment of the present application discloses a ranging device, which can comprise:

[0022] A sampling module is configured to switch the clock phase of the ADC at a plurality of preset sampling clock switching points respectively during the process of receiving the ranging frame, so that the ADC samples to obtain a plurality of sampling signals corresponding to a plurality of phases respectively based on a plurality of clock phases.

[0023] A channel estimation module is configured to obtain a channel estimation value corresponding to each phase according to the sampling signal corresponding to the phase.

[0024] The channel estimation module is further configured to obtain positioning information for ranging according to all the channel estimation values.

[0025] As an optional implementation, in the second aspect of the embodiment of the present application, the clock phase of the ADC is switched at the preset plurality of sampling clock switching points during the process of receiving the ranging frame, so that the ADC samples to obtain a plurality of sampling signals corresponding to a plurality of phases based on a plurality of clock phases.

[0026] During the process of receiving the ranging frame, the plurality of sampling clock switching points are detected by the baseband processor, and the phase-locked loop (PLL) is controlled to switch the clock phase to the ADC at the plurality of sampling clock switching points, so that the ADC samples to obtain a plurality of sampling signals at the corresponding phase after each time the clock phase is switched. The clock phase switched by the plurality of sampling clock switching points includes a plurality of different phases.

[0027] As an optional implementation, in the second aspect of the embodiment of the present application, the channel estimation module is configured to obtain a channel estimation value corresponding to each phase according to the sampling signal corresponding to the phase in the following manner:

[0028] The plurality of sampling signals obtained by each time switching are processed to obtain a plurality of channel estimation values.

[0029] The channel estimation value corresponding to each phase is obtained in combination with the plurality of times of phase switching.

[0030] As an optional implementation, in the second aspect of the embodiment of the present application, the channel estimation module is configured to obtain positioning information for ranging according to all the channel estimation values in the following manner:

[0031] The channel estimation values of all the phases are arranged.

[0032] The best synchronization position is obtained by interpolation processing according to all the arranged channel estimation values.

[0033] The time of flight (TOF) is calculated according to the best synchronization position.

[0034] The positioning information is obtained according to the TOF.

[0035] The third aspect of the embodiment of the present application discloses a receiving device, which can include:

[0036] A memory in which an executable program code is stored;

[0037] A processor coupled to the memory;

[0038] The processor invokes the executable program code stored in the memory to execute the ranging method disclosed in the first aspect of the embodiment of the present application.

[0039] The fourth aspect of the embodiment of the present application discloses a computer readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of any one of the ranging methods disclosed in the first aspect of the embodiment of the present application are implemented.

[0040] The fifth aspect of the embodiment of the present application discloses a computer program product. When the computer program product is run on a computer, the computer is caused to execute part or all of the steps of any one of the methods of the first aspect.

[0041] The sixth aspect of the embodiment of the present application discloses an application publishing platform. The application publishing platform is used to publish a computer program product. When the computer program product is run on a computer, the computer is caused to execute part or all of the steps of any one of the methods of the first aspect.

[0042] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0043] In the embodiment of the present application, in the process of receiving the ranging frame, the clock phase of the ADC is switched at a plurality of preset sampling clock switching points, so that the ADC can sample based on a plurality of clock phases, obtain a plurality of sampling signals corresponding to the plurality of phases respectively, obtain a channel estimation value corresponding to each phase according to the sampling signal corresponding to the phase, and further obtain positioning information of the ranging according to the channel estimation values of all the phases. It can be seen that, by switching the clock phase of the ADC in the process of receiving the ranging frame, the embodiment of the present application obtains a plurality of received signals corresponding to a plurality of clock phases, further obtains channel estimation values under a plurality of clock phases, obtains a plurality of channel estimation values by time division processing, and obtains more accurate positioning information. The positioning information with an equivalent high clock sampling rate is obtained by sampling at a low clock sampling rate, which effectively reduces the area and power consumption of the baseband processor, and improves the accuracy of the ranging without changing the data processing complexity of the baseband processing unit. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0045] Figure 1 An application diagram of the ranging system disclosed in the embodiment of the present application is shown in the figure.

[0046] Figure 2 Structure diagram of receiving device disclosed by embodiment one of the present application;

[0047] Figure 3 Flow diagram of ranging method disclosed by embodiment one of the present application;

[0048] Figure 4 Structure diagram of UWB frame disclosed by embodiment of the present application;

[0049] Figure 5 Setting diagram of sampling clock switching point in UWB ranging frame disclosed by embodiment of the present application;

[0050] Figure 6 Flow diagram of ranging method disclosed by embodiment two of the present application;

[0051] Figure 7 Waveform diagram of four clock phases provided by PLL disclosed by embodiment of the present application;

[0052] Figure 8 Arrangement diagram of channel estimation values of four clock phases disclosed by embodiment of the present application;

[0053] Figure 9 Waveform diagram of channel estimation values under four clock phases disclosed by embodiment of the present application;

[0054] Figure 10 Structure diagram of ranging device disclosed by embodiment of the present application;

[0055] Figure 11 Structure diagram of receiving device disclosed by embodiment of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those of ordinary skill in the art without creative work, belong to the scope of protection of the present application.

[0057] It should be noted that the terms "first", "second", "third", and "fourth" in the specification and claims of the present application are used to distinguish different objects, and are not used to describe a specific order. The terms "include" and "have" and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or units need not be limited to those steps or units clearly listed, but can include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0058] First, refer to Figure 1 , Figure 1 The application diagram of the ranging system disclosed by the embodiments of the present application is shown in Figure 1 , which includes a transmitting device (transmitter) and a receiving device (receiver), the transmitting device includes a transmitting antenna, the receiving device includes a receiving antenna, the transmitting device transmits signals through the transmitting antenna, the receiving device receives signals through the receiving antenna, the receiving device performs channel estimation through the received signals, obtains positioning information, and realizes ranging.

[0059] Further, refer to Figure 2 , Figure 2 The structure diagram of the receiving device disclosed by the embodiments of the present application is shown in Figure 2 , which includes one or more receiving antennas (only one receiving antenna is shown in Figure 2 ), a radio frequency front-end (RF front-end), an analog-to-digital converter (ADC), a baseband processor, a digital signal processor (DSP), and a timing information module (not shown in the figure), etc., wherein the receiving antenna and the radio frequency front-end convert the radio signals in the air into electrical signals (analog signals), the baseband processor controls the phase-locked loop PLL to output the clock phase to the ADC, the ADC samples the electrical signals based on the clock phase provided by the phase-locked loop PLL to obtain the sampling signals (digital signals) corresponding to the clock phase, the baseband processor processes the sampling signals to obtain timing information, the DSP calculates the TOF according to the timing information, and thus obtains the positioning information. Figure 2In the embodiment, the phase-locked loop (PLL) can provide four clock phases, which are clock0, clock1, clock2 and clock3, the phases of the four clock phases are different, and the phase difference between any adjacent two clock phases is equal, during receiving the ranging frame by the ADC, the baseband processor outputs a control signal to control the phase-locked loop (PLL) to sequentially provide one of the four clock phases to the ADC at the preset four sampling clock switching points, so that the ADC samples the sampling signals corresponding to the four clock phases respectively at different time periods, the channel estimation is performed according to the sampling signals of the four clock phases, the positioning information is obtained, the ranging is realized, the signal is sampled at a lower clock sampling rate without changing the data processing complexity of the baseband processor, then the timing information equivalent to a higher clock sampling rate can be obtained, the ranging is realized, and the ranging accuracy is improved.

[0060] The ranging frame is a data frame transmitted by the transmitting device and received by the receiving device to perform channel estimation and calculate TOF, so as to realize distance measurement between the two devices.

[0061] Therefore, the embodiment of the present application discloses a ranging method, device, receiving device and storage medium, which can sample high-bandwidth signals at a lower ADC clock sampling rate to obtain equivalent high-clock sampling rate positioning information, effectively improve the ranging accuracy without increasing the data processing complexity of the baseband processor. The technical solutions of the present application will be described in detail below through specific embodiments.

[0062] Please refer to Figure 3 , Figure 3 The embodiment one of the present application discloses a flowchart of the ranging method; as shown in Figure 3 The ranging method can include:

[0063] 301, during receiving the ranging frame, switching the clock phase of the ADC at the preset multiple sampling clock switching points, so that the ADC samples multiple clock phases to obtain sampling signals corresponding to multiple phases respectively.

[0064] The execution subject of the embodiment of the present application can be a receiving device or a ranging device, wherein the embodiment of the present application is implemented during receiving the ranging frame. Figure 1 As shown in

[0065] Optionally, the preset plurality of sampling clock switching points can include 2 or more, and correspondingly, the clock phases can also include 2 or more. Further, there can be one sampling clock switching point corresponding to one clock phase, and the phase difference between the clock phase switched by a certain sampling clock switching point and the clock phase switched by the immediately next sampling clock switching point is a preset value, which can be set according to actual conditions, and is preferably set according to the number of sampling clock switching points and the data processing capability of the baseband processor; or, the clock phases are 2 or more, but the total number is less than the total number of sampling clock switching points, so that one clock phase can correspond to one or more sampling clock switching points, and the clock phase switched by any sampling clock switching point has a phase difference with the clock phase switched by the immediately next sampling clock switching point, and preferably, the plurality of clock phases are switched in a cyclic sequence.

[0066] Further, the setting of the sampling clock switching points can be combined with the characteristics of the ranging frame, and a suitable time point can be arbitrarily selected as the sampling clock switching point in combination with the process of the ranging frame. Since the switching of the clock phase is controlled by the baseband processor outputting a control signal to the PLL, the baseband processor can determine whether the clock phase is switched, so as to switch the clock phase, so that the ADC performs signal sampling based on the switched clock phase in different time periods, and obtains sampling signals corresponding to a plurality of clock phases, and further obtains channel estimation values corresponding to a plurality of clock phases, and combines a plurality of channel estimation values to obtain timing information equivalent to a high clock sampling rate.

[0067] As shown in FIG. 4, four sampling clock switching points and four clock phases are set in advance, and one sampling clock switching point corresponds to one clock phase. Figure 2

[0068] Optionally, the above ranging frame can be an UltraWide Band (UWB) signal, and the UWB transmitting device transmits the UWB signal through a transmitting antenna, and the UWB receiving device receives the UWB signal through a receiving antenna. For reference, see Figure 4 , Figure 4 The UWB frame structure disclosed in the embodiment of the present application is shown in FIG. 5, and the UWB frame structure includes a preamble, an SFD, a GAP, a STS segment, a PHR (PHY header), and a Payload. The preamble part includes the preamble and the SFD, the SFD is a frame start delimiter field, and the data part includes the PHR (PHY header) and the Payload.

[0069] ​The UWB ranging frame comprises several positioning time slots, each of which comprises a GAP and a known ranging sequence (STS segment). In the GAP time period, the transmitting device does not transmit signals, and the time period is idle. In the known ranging sequence (STS segment) time period, the time period is effective, and the known ranging sequence (STS segment) is a known signal waveform. According to the signal waveform in the time period, channel estimation and timing information can be obtained. Therefore, further optionally, please refer to Figure 5 , Figure 5 The setting diagram of the sampling clock switching point set in the UWB ranging frame is disclosed in the embodiment of the present application, Figure 5 The sampling clock switching point diagram set for the UWB ranging frame shown in Figure 4 In Figure 5 , the sampling clock switching points are set in each GAP time period according to the frame structure characteristics of the UWB ranging frame, and the sampling clock switching points are sampling clock switching point 0, sampling clock switching point 1, sampling clock switching point 2 and sampling clock switching point 3. Of course, the sampling clock switching points can also be set at a time point in the known ranging sequence (STS segment) time period, and channel estimation is performed by sampling the STS segment.

[0070] Further, in combination with Figure 2 , Figure 4 and Figure 5 , at the sampling clock switching point 0, the clock phase of the ADC is switched to clock 0; at the sampling clock switching point 1, the clock phase of the ADC is switched to clock 1; at the sampling clock switching point 2, the clock phase of the ADC is switched to clock 2; and at the sampling clock switching point 3, the clock phase of the ADC is switched to clock 3.

[0071] The above Figure 4 and Figure 5 illustrate the process of receiving a frame of ranging frames, and the sampling clock switching points and the clock phases are in one-to-one correspondence in the frame of ranging frames.

[0072] If multiple frames of ranging frames are received in succession, optionally, in the first frame of ranging frames, in combination with Figure 4 and Figure 5 , the first GAP is switched to clock 0, the second GAP is switched to clock 1, the third GAP is switched to clock 2, and the fourth GAP is switched to clock 3; in the second frame of ranging frames, the same switching operation as in the first frame is performed, the first GAP is switched to clock 0, the second GAP is switched to clock 1, and the third GAP is switched to clock 2; similarly, the same switching operation is performed on the nth frame, and n is a positive integer greater than or equal to 3.

[0073] Alternatively, only two clock phases are set, and one sampling clock phase is set in each GAP in each frame. Figure 4 In the first ranging frame, clock 0 is switched in the first GAP, clock 1 is switched in the second GAP, clock 0 is switched in the third GAP, and clock 1 is switched in the fourth GAP; in the second ranging frame, clock 0 is switched in the first GAP, clock 1 is switched in the second GAP, clock 0 is switched in the third GAP, and clock 1 is switched in the fourth GAP; similarly, the same switching operation is performed in the nth frame.

[0074] The above embodiments only show several possibilities of the correspondence between the clock phase and the sampling clock switching point, and more possible correspondences obtained by optimization or deformation and capable of achieving the technical effects of the embodiments of the present application are within the protection scope of the present application, which will not be listed one by one.

[0075] 302. Obtain a channel estimation value corresponding to each phase according to the sampling signal corresponding to the phase.

[0076] The ADC samples the corresponding sampling signal based on each clock phase and transmits the sampling signal to the baseband processor, and the baseband processor processes the sampling signal output by the ADC to obtain a channel estimation value. Specifically, each sampling signal is processed to obtain a corresponding channel estimation value.

[0077] 303. Obtain positioning information for ranging according to all channel estimation values.

[0078] Optionally, the above obtaining positioning information for ranging according to all channel estimation values can include:

[0079] Obtaining timing information according to all channel estimation values;

[0080] Calculating the time of flight (TOF) according to the timing information;

[0081] Obtaining positioning information according to the time of flight (TOF).

[0082] In the above embodiments, the baseband processor first obtains timing information according to the channel estimation value, the timing information is sent to the DSP, the DSP calculates the TOF according to the timing information, and thus obtains the positioning information, and the detailed calculation process will not be described here.

[0083] It can be seen that, by implementing the above embodiment, in the process of receiving the ranging frame, the clock phase of the ADC is switched at the preset plurality of sampling clock switching points, so that the ADC can sample based on a plurality of clock phases, a plurality of phase sampling signals are obtained, the channel estimation value is obtained according to the plurality of phase sampling signals, and the positioning information of the ranging is further obtained according to the channel estimation value. It can be seen that, by implementing the embodiment of the application, the clock phase of the ADC is switched in the process of receiving the ranging frame, the received signals corresponding to a plurality of clock phases are obtained, the channel estimation value under a plurality of clock phases is further obtained, the positioning information of the equivalent high clock sampling rate is obtained by sampling at a low clock sampling rate, and the accuracy of the ranging can be improved without changing the data processing complexity of the baseband processing unit.

[0084] Please refer to Figure 6 , Figure 6 The flowchart of the ranging method disclosed in Embodiment Two of the application is shown in FIG. 2. As shown in FIG. 2, the ranging method can include the following steps. Figure 6

[0085] 601、In the process of receiving the ranging frame, the baseband processor detects a plurality of sampling clock switching points, controls the phase-locked loop (PLL) to switch the clock phase to the ADC at the plurality of sampling clock switching points, so that the ADC samples at the corresponding phase after each switching of the clock phase to obtain a plurality of sampling signals, and the clock phase switched by the plurality of sampling clock switching points includes a plurality of different phases.

[0086] In this way, at least two or more clock phases corresponding to the sampling signals can be sampled by switching the clock phase at the plurality of sampling clock switching points.

[0087] Optionally, in the process of receiving the ranging frame, the baseband processor detects the sampling clock switching point, the baseband processor sends a clock control signal to the phase-locked loop (PLL) connected thereto, and the phase-locked loop (PLL) sequentially provides the corresponding clock phase to the ADC when receiving the clock control signal; wherein the clock control signal can carry the identification of the sampling clock switching point, the phase-locked loop (PLL) obtains the matched clock phase according to the identification of the sampling clock switching point, and provides the matched clock phase to the ADC, so that the ADC samples the signal based on the clock phase to obtain the sampling signal corresponding to the clock phase; for example, as shown in FIG. 3 and FIG. 4, the sampling clock switching point 0, the sampling clock switching point 1, the sampling clock switching point 2 and the sampling clock switching point 3 can be used as the identification of the sampling clock switching point, the sampling clock switching point 0 corresponds to clock 0, the sampling clock switching point 1 corresponds to clock 1, the sampling clock switching point 2 corresponds to clock 2, and the sampling clock switching point 3 corresponds to clock 3. Figure 2 Figure 5 Further, in combination with

[0088] ​​​Figure 2 and Figure 5 , the preset sampling clock switching points include sampling clock switching point 0, sampling clock switching point 1, sampling clock switching point 2 and sampling clock switching point 3 respectively, and the 4 clock phases preset by the phase-locked loop PLL are clock0, clock1, clock2 and clock3 respectively. When the baseband processor detects the sampling clock switching point 0, it sends a clock control signal carrying the sampling clock switching point 0 to the phase-locked loop PLL, and the phase-locked loop PLL provides the clock phase clock0 to the ADC according to the identification carried by the clock control signal, so that the ADC samples the signal based on the clock phase clock0 in the time period between the sampling clock switching point 0 and the sampling clock switching point 1, thereby obtaining the sampling signal corresponding to the clock phase clock0; when the baseband processor detects the sampling clock switching point 1, it sends a clock control signal carrying the sampling clock switching point 1 to the phase-locked loop PLL, and the phase-locked loop PLL provides the clock phase clock1 to the ADC according to the identification carried by the clock control signal, so that the ADC samples the signal based on the clock phase clock1 in the time period between the sampling clock switching point 1 and the sampling clock switching point 2, thereby obtaining the sampling signal corresponding to the clock phase clock1; when the baseband processor detects the sampling clock switching point 2, it sends a clock control signal carrying the sampling clock switching point 2 to the phase-locked loop PLL, and the phase-locked loop PLL provides the clock phase clock2 to the ADC according to the identification carried by the clock control signal, so that the ADC samples the signal based on the clock phase clock2 in the time period between the sampling clock switching point 2 and the sampling clock switching point 3, thereby obtaining the sampling signal corresponding to the clock phase clock2; when the baseband processor detects the sampling clock switching point 3, it sends a clock control signal carrying the sampling clock switching point 3 to the phase-locked loop PLL, and the phase-locked loop PLL provides the clock phase clock3 to the ADC according to the identification carried by the clock control signal, so that the ADC samples the signal based on the clock phase clock3 in the time period between the sampling clock switching point 3 and the reception of the payload, thereby obtaining the sampling signal corresponding to the clock phase clock3.

[0089] Further, the ADC samples based on the clock phase clock0 in the time period between the sampling clock switching point 0 and the sampling clock switching point 1, to obtain a plurality of sampling signals; the ADC samples based on the clock phase clock1 in the time period between the sampling clock switching point 1 and the sampling clock switching point 2, to obtain a plurality of sampling signals; the ADC samples based on the clock phase clock2 in the time period between the sampling clock switching point 2 and the sampling clock switching point 3, to obtain a plurality of sampling signals; and the ADC samples based on the clock phase clock3 in the time period between the sampling clock switching point 3 and the reception of the payload, to obtain a plurality of sampling signals.

[0090] Further refer to Figure 7 , Figure 7 Waveform diagram of 4 clock phases provided by the PLL disclosed in the embodiment of the present application; in combination with Figure 7 , the data processing capability of the baseband processor of the receiving device can only process the data of clock0, which is 1GHz clock, clock1 lags behind clock0 by 0.250ns, clock2 lags behind clock1 by 0.250ns, clock3 lags behind clock2 by 0.250ns, and the ADC obtains the corresponding sampling signals by time-division sampling through clock0, clock1, clock2 and clock3, so as to be able to time-division process the data of 4 1GHz clocks, such as the clock data shown in the uppermost waveform diagram in Figure 7 , wherein 0, 1, 2 and 3 in the waveform diagram correspond to clock0, clock1, clock2 and clock3 respectively. Therefore, the baseband processor with the data processing capability of 1GHz clock in the embodiment of the present application realizes the data processing capability of 4GHz clock through time-division processing, so as to be able to improve the data processing capability of the baseband processor without changing the data processing complexity of the baseband processor, and effectively improve the accuracy of ranging.

[0091] 602, process the multiple sampling signals obtained in each switching to obtain multiple channel estimation values, and obtain the channel estimation value corresponding to each phase in combination with multiple phase switching.

[0092] For example, at the sampling clock switching point 0 of the UWB frame, the clock phase of the ADC is switched to clock 0, the ADC samples based on clock 0 with an interval of 1 ns to obtain a plurality of sampling signals, and after the sampling signals are processed by the baseband processor, a plurality of channel estimation values are obtained, which are Cir0_0, Cir0_1, Cir0_2, …, Cir0_n respectively; at the sampling clock switching point 1, the clock phase of the ADC is switched to clock 1, the ADC also samples based on clock 1 with an interval of 1 ns to obtain a plurality of sampling signals, and after the sampling signals are processed by the baseband processor, a plurality of channel estimation values are obtained, which are Cir1_0, Cir1_1, Cir1_2, …, Cir1_n respectively; at the sampling clock switching point 2, the clock phase of the ADC is switched to clock 2, the ADC also samples based on clock 2 with an interval of 1 ns to obtain a plurality of sampling signals, and after the sampling signals are processed by the baseband processor, a plurality of channel estimation values are obtained, which are Cir2_0, Cir2_1, Cir2_2, …, Cir2_n respectively; at the sampling clock switching point 3, the clock phase of the ADC is switched to clock 3, the ADC also samples based on clock 3 with an interval of 1 ns to obtain a plurality of sampling signals, and after the sampling signals are processed by the baseband processor, a plurality of channel estimation values are obtained, which are Cir3_0, Cir3_1, Cir3_2, …, Cir3_n respectively, but clock 1 lags behind clock 0 by 0.25 ns, clock 2 lags behind clock 1 by 0.25 ns, and clock 3 lags behind clock 2 by 0.25 ns.

[0093] 603, arrange the channel estimation values of all phases.

[0094] 604, perform interpolation processing according to the arranged channel estimation values of all phases to obtain the best synchronization position.

[0095] In combination with the description of step 602, according to the sampling interval of 1 ns of each clock phase and the sampling interval of 0.25 ns between clock phases, the channel estimation values of clock 0, the channel estimation values of clock 1, the channel estimation values of clock 2 and the channel estimation values of clock 3 are arranged as shown in Figure 8 .

[0096] Further, please refer to Figure 9 , Figure 9 the waveform schematic diagram of the channel estimation values under the 4 clock phases disclosed in the embodiment of the present application. After steps 601 and 602, the baseband processor obtains a plurality of channel estimation values under each phase, and in Figure 9 , the arrows represent the channel estimation values, and different arrows represent the channel estimation values under different clock phases, Figure 9In this context, Cir0_0, Cir0_1, Cir0_2, and Cir0_3 represent the channel estimates for a sampling interval of 1 ns corresponding to clock 0; Cir1_0, Cir1_1, Cir1_2, and Cir1_3 represent the channel estimates for a sampling interval of 1 ns corresponding to clock 1; Cir2_0, Cir2_1, Cir2_2, and Cir2_3 represent the channel estimates for a sampling interval of 1 ns corresponding to clock 2; and Cir3_0, Cir3_1, and Cir3_2 represent the channel estimates for a sampling interval of 1 ns corresponding to clock 3. Then, the DSP... Figure 8 All channel estimates arranged as shown are interpolated according to the sampling interval of each clock phase and the phase difference between two clock phases. That is, interpolation filtering is performed on multiple channel estimates Cir0_0, Cir0_1, Cir0_2, ..., Cir0_n for clock0, and on multiple channel estimates Cir1_0, Cir1_1, Cir1_2, ..., Cir1_n for clock1, and on multiple channel estimates Cir2_0, Cir2_1, Cir2_2, ..., Cir2_n for clock2, and on multiple channel estimates Cir3_0, Cir3_1, Cir3_2, ..., Cir3_n for clock3, thereby recovering the optimal synchronization position (optimalsync pos). Therefore, positioning information can be obtained based on the optimal synchronization position. The more sampling signals sampled by switching clock phases, the more refined the channel estimation value can be obtained, thus obtaining a more refined optimal synchronization position and more accurate timing information. That is, more channel estimation values ​​can be obtained by time-division processing, achieving timing information equivalent to a high clock sampling rate by using a low clock sampling rate through switching clock phases, thus achieving high-precision positioning.

[0097] 605. Calculate the Time of Flight (TOF) based on the optimal synchronization position, and obtain the positioning information based on the TOF.

[0098] Optionally, the optimal synchronization position can be recovered by interpolating all channel estimates, and timing information can be obtained based on the optimal synchronization position to obtain TOF and achieve ranging.

[0099] In this embodiment of the invention, the ADC samples the signal based on multiple clock phases to obtain channel estimation values ​​corresponding to each clock phase, and then performs interpolation recovery to obtain the optimal synchronization position, thereby obtaining timing information and achieving high-precision positioning.

[0100] The embodiment of the present application is implemented by switching the clock phase of the ADC in the process of receiving the ranging frame, obtaining sampling signals corresponding to multiple clock phases respectively, further obtaining channel estimation values corresponding to multiple clock phases respectively, achieving the positioning information of equivalent high clock sampling rate by sampling at a lower clock sampling rate, and improving the ranging accuracy without changing the data processing complexity of the baseband processing unit.

[0101] Please refer to Figure 10 , Figure 10 The structure diagram of the ranging device disclosed by the embodiment of the present application is shown in FIG. 1. Figure 10 As shown in the figure, the ranging device can include:

[0102] The sampling module 1010 is configured to switch the clock phase of the ADC at a plurality of preset sampling clock switching points respectively in the process of receiving the ranging frame, so that the ADC samples based on multiple clock phases to obtain sampling signals corresponding to multiple phases respectively.

[0103] The channel estimation module 1020 is configured to obtain a channel estimation value corresponding to each phase according to the sampling signal corresponding to the phase.

[0104] The channel estimation module 1020 is further configured to obtain positioning information for ranging according to all channel estimation values.

[0105] It can be seen that by implementing the above device, the clock phase of the ADC is switched in the process of receiving the ranging frame, the received signals corresponding to multiple clock phases are obtained, further channel estimation values under multiple clock phases are obtained, the positioning information of equivalent high clock sampling rate is achieved by sampling at a lower clock sampling rate, and the ranging accuracy can be improved without changing the data processing complexity of the baseband processing unit.

[0106] Optionally, the sampling module 1010 is configured to switch the clock phase of the ADC at a plurality of preset sampling clock switching points respectively in the process of receiving the ranging frame, so that the ADC samples based on multiple clock phases to obtain sampling signals corresponding to multiple phases respectively.

[0107] In the process of receiving the ranging frame, the baseband processor detects a plurality of preset sampling clock switching points, controls the phase-locked loop (PLL) to switch the clock phase to the ADC at the plurality of sampling clock switching points respectively, so that the ADC samples at the corresponding phase to obtain a plurality of sampling signals after each time the clock phase is switched, and the clock phases switched by the plurality of sampling clock switching points include multiple different phases.

[0108] Further, the sampling module 1010 detects the sampling clock switching point through the baseband processor during receiving the ranging frame, sends a clock control signal from the baseband processor to the phase-locked loop (PLL) connected electrically, and the phase-locked loop (PLL) sequentially provides a corresponding clock phase to the ADC upon receiving the clock control signal; wherein the clock control signal can carry the identification of the sampling clock switching point, the phase-locked loop (PLL) acquires the matched clock phase according to the identification of the sampling clock switching point, and provides the matched clock phase to the ADC, so that the ADC samples the signal based on the clock phase to obtain the sampling signal corresponding to the clock phase; for example, as shown in Figure 2 and Figure 5 the sampling clock switching point 0, the sampling clock switching point 1, the sampling clock switching point 2 and the sampling clock switching point 3 can be used as the identification of the sampling clock switching point, the sampling clock switching point 0 corresponds to clock 0, the sampling clock switching point 1 corresponds to clock 1, the sampling clock switching point 2 corresponds to clock 2, and the sampling clock switching point 3 corresponds to clock 3, the phase-locked loop (PLL) is controlled by the baseband processor to switch the clock phase to the ADC at different sampling clock switching points, so as to sample the sampling signal at multiple clock phases, obtain the channel estimation value of different clock phases, combine the channel estimation values of multiple clock phases to obtain the timing information equivalent to the higher clock sampling rate, and improve the accuracy of ranging.

[0109] Optionally, the channel estimation module 1020 is configured to obtain the channel estimation value corresponding to each phase according to the sampling signal corresponding to each phase, and the manner is specifically as follows:

[0110] processing the multiple sampling signals obtained by each switching to obtain multiple channel estimation values;

[0111] combining multiple phase switching to obtain the channel estimation value corresponding to each phase.

[0112] The channel estimation module 1020 is configured to obtain the positioning information for ranging according to all channel estimation values, and the manner is specifically as follows:

[0113] arranging the channel estimation values of all phases;

[0114] performing interpolation processing on the arranged all channel estimation values to obtain the best synchronization position;

[0115] calculating the time of flight (TOF) according to the best synchronization position;

[0116] obtaining the positioning information according to the TOF.

[0117] Please refer to Figure 11 , Figure 11 the structure schematic diagram of the receiving device disclosed by the embodiment of the application; Figure 11The shown receiving device can include:

[0118] The memory 1101 stores executable program codes.

[0119] The processor 1102 is coupled with the memory 1101.

[0120] The processor 1102 invokes the executable program codes stored in the memory 1101 to perform Figure 3 and Figure 6 part or all of the steps of any one of the disclosed ranging methods.

[0121] The embodiments of the present application also disclose a computer readable storage medium storing a computer program, wherein the computer program causes a computer to perform Figure 3 and Figure 6 any one of the disclosed ranging methods.

[0122] The embodiments of the present application also disclose a computer program product, which causes a computer to perform Figure 3 and Figure 6 part or all of the steps of any one of the disclosed methods when the computer program product runs on the computer.

[0123] The embodiments of the present application also disclose an application publishing platform, which is used to publish a computer program product, wherein the computer program product causes a computer to perform Figure 3 and Figure 6 part or all of the steps of any one of the disclosed methods when the computer program product runs on the computer.

[0124] Those skilled in the art can understand that all or part of the steps of various methods in the above embodiments can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer readable storage medium, including Read-Only Memory (ROM), Random Access Memory (RAM), Programmable Read-only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), One-time Programmable Read-Only Memory (OTPROM), Electrically-Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk memories, magnetic disk memories, magnetic tape memories, or any other computer readable medium capable of carrying or storing data.

[0125] The above describes in detail a ranging method, device, receiving device and storage medium disclosed by the embodiments of the present application. The principles and implementation manners of the present application are described by applying specific examples in this paper. The above embodiment description is only used to help understand the method of the present application and its core idea. Meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manners and application ranges will be changed. In summary, the content of the specification should not be understood as a limitation of the present application.

Claims

1. A method of distance measurement, characterized by, The method comprises the following steps: During receiving the ranging frame, a plurality of preset sampling clock switching points are detected by a baseband processor, and a phase-locked loop (PLL) is controlled to switch a clock phase to an ADC at the plurality of sampling clock switching points respectively, so that the ADC samples a plurality of sampling signals at a corresponding phase after each switching of the clock phase, and the clock phase switched by the plurality of sampling clock switching points comprises a plurality of different phases; Channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase; Positioning information for ranging is obtained according to all the channel estimation values.

2. The method of claim 1, wherein, The step of obtaining the channel estimation values corresponding to each phase according to the sampling signals corresponding to each phase comprises the following steps: The plurality of sampling signals obtained by each switching are processed to obtain a plurality of channel estimation values; The channel estimation value corresponding to each phase is obtained by combining a plurality of phase switchings.

3. The method of claim 2, wherein, The step of obtaining the positioning information for ranging according to all the channel estimation values comprises the following steps: The channel estimation values of all the phases are arranged; An optimal synchronization position is obtained by interpolation processing on the arranged channel estimation values; A time of flight (TOF) is calculated according to the optimal synchronization position; Positioning information is obtained according to the TOF.

4. The method according to any one of claims 1 to 3, characterized in that, The clock phase switched by any one of the plurality of sampling clock switching points has a phase difference from the clock phase switched by an immediately subsequent sampling clock switching point.

5. A ranging device, characterized by The method comprises the following steps: During receiving the ranging frame, a plurality of preset sampling clock switching points are detected by a baseband processor, and a phase-locked loop (PLL) is controlled to switch a clock phase to an ADC at the plurality of sampling clock switching points respectively, so that the ADC samples a plurality of sampling signals at a corresponding phase after each switching of the clock phase, and the clock phase switched by the plurality of sampling clock switching points comprises a plurality of different phases; Channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase; The channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase. The channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase.

6. The apparatus of claim 5, wherein, The channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase. The channel estimation values corresponding to each phase are obtained according to the sampling signals corresponding to each phase. The method comprises the following steps:

7. A receiving device, characterized by A memory storing executable program codes; A processor coupled with the memory; The processor invokes the executable program codes stored in the memory to execute the ranging method according to any one of claims 1-4. The program is executed by the processor to implement the steps of the method according to any one of claims 1-4.

8. A computer-readable storage medium having stored thereon a computer program, characterized in that, ​

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