Memory access method and device

Abstract

A memory access method and device, applied to a CPU core, the method comprising: in response to a memory access request, searching in a TLB for a physical address corresponding to a virtual address carried in the memory access request; in the case where the physical address corresponding to the virtual address is not found, sending an address detection request, the address detection request carrying the virtual address, so that the CPU core that receives the address detection request searches in its TLB for the physical address corresponding to the virtual address, and in the case where the corresponding physical address is found, returning an address detection response, the address detection response carrying the found physical address; in response to the received address detection response, storing the mapping relationship between the physical address carried in the address detection response and the virtual address in the TLB, and performing memory access based on the physical address.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory access method and device. Background Art

[0002] The CPU (Central Processing Unit) is the computing and control core of the computer system and the final execution unit for information processing and program execution. The CPU may include one or more CPU cores. The CPU core usually includes a TLB (Translation Look-aside Buffer), which is a high-speed hardware cache used to cache the mapping relationship between virtual addresses and physical addresses, which can increase the address conversion rate.

[0003] For multi-core CPUs, different threads of the same process may run on different CPU cores; processes or threads may also be scheduled to run on other CPU cores. In this scenario of running across CPU cores, how to improve the address translation rate has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] In view of this, the present specification provides a memory access method and device.

[0005] Specifically, this specification is implemented through the following technical solutions:

[0006] A memory access method is used for memory access of a computer system, wherein the computer system includes a central processing unit (CPU), the CPU includes multiple CPU cores, the CPU core includes a translation bypass cache (TLB), and the TLB is used to cache a mapping relationship between a virtual address and a physical address. The method is applied to the CPU core and includes:

[0007] In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request;

[0008] In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address;

[0009] In response to the received address detection response, the mapping relationship between the physical address and the virtual address carried in the address detection response is stored in the TLB, and memory access is performed based on the physical address.

[0010] Optionally, sending an address detection request includes:

[0011] Broadcast address detection request.

[0012] Optionally, sending an address detection request includes:

[0013] Read the target core ID of the target CPU core from the register;

[0014] An address detection request is sent to the target CPU core based on the target core identifier.

[0015] Optionally, the target CPU core is a CPU core where other threads in the process to which the thread initiating the memory access request belongs are located.

[0016] Optionally, the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

[0017] Optionally, the target core identifier is written by a scheduler.

[0018] Optionally, also include:

[0019] receiving a TLB invalidation instruction, wherein the TLB invalidation instruction is sent after the thread initiating the memory access request is scheduled to another CPU core;

[0020] In response to the TLB invalidation instruction, marking a mapping relationship between a virtual address and a physical address specified by the TLB invalidation instruction in the TLB as an invalid state;

[0021] The method further comprises:

[0022] After receiving the address detection request sent by other CPU cores, the physical address corresponding to the virtual address in the valid state and the invalid state is searched in the TLB.

[0023] Optionally, also include:

[0024] In the case where the address detection response is not received, the physical address corresponding to the virtual address is searched based on the process page table of the memory.

[0025] A memory access device is used for memory access of a computer system. The computer system includes a central processing unit (CPU), the CPU includes multiple CPU cores, the CPU core includes a translation bypass cache (TLB), and the TLB is used to cache the mapping relationship between a virtual address and a physical address. The device is applied to the CPU core and includes:

[0026] An address search unit, in response to a memory access request, searches the TLB for a physical address corresponding to a virtual address carried in the memory access request;

[0027] The address detection unit sends an address detection request when the physical address corresponding to the virtual address is not found, and the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and returns an address detection response when the corresponding physical address is found, and the address detection response carries the found physical address;

[0028] The memory access unit, in response to the received address detection response, stores the mapping relationship between the physical address and the virtual address carried in the address detection response into the TLB, and performs memory access based on the physical address.

[0029] Optionally, the address detection unit reads a target core identifier of a target CPU core from a register; and sends an address detection request to the target CPU core based on the target core identifier.

[0030] A central processing unit (CPU), the CPU includes a plurality of CPU cores, the CPU core includes a translation bypass cache (TLB), the TLB is used to cache a mapping relationship between a virtual address and a physical address, and the CPU core is configured as follows:

[0031] In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request;

[0032] In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address;

[0033] In response to the received address detection response, the mapping relationship between the physical address and the virtual address carried in the address detection response is stored in the TLB, and memory access is performed based on the physical address.

[0034] With the above implementation, when the CPU core does not store the physical address corresponding to the virtual address in the TLB, it sends an address detection request to other CPU cores, and other CPU cores check whether the physical address corresponding to the virtual address is stored in their respective TLBs, and can add the queried physical address to the address detection response and return it. The CPU core can then store the mapping relationship between the physical address and the virtual address in its TLB and perform memory access.

[0035] By adopting the above implementation, TLB cache sharing between CPU cores can be realized, which greatly reduces the repeated process page table queries performed by the CPU core in the scenario of cross-CPU core operation, reduces the waste of CPU core processing resources, and effectively shortens the time consumption of address conversion in the case of TLB Miss, thereby improving IO performance. On the other hand, the above technical solution provided in this specification can be implemented based on existing hardware and cache detection protocols, without the need for new hardware, with low cost and high feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a flowchart of a memory access method shown in an exemplary embodiment of this specification.

[0037] Figure 2 It is a CPU block diagram shown in an exemplary embodiment of this specification.

[0038] Figure 3 It is a flowchart of another memory access method shown in an exemplary embodiment of this specification.

[0039] Figure 4 It is a flowchart of another memory access method shown in an exemplary embodiment of this specification.

[0040] Figure 5 It is a block diagram of a memory access device shown in an exemplary embodiment of this specification. DETAILED DESCRIPTION

[0041] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with this specification. Instead, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0042] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. The singular forms "a", "the" and "the" used in this specification and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0043] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0044] The CPU core may generally include an MMU (Memory Management Unit), which may convert a virtual address into a physical address required for memory access, and may store a mapping relationship between the virtual address and the physical address in a TLB of the CPU core.

[0045] When an application running on the CPU core accesses memory, the MMU can first query the physical address corresponding to the virtual address in the TLB, and then access the memory based on the queried physical address. If the physical address corresponding to the virtual address is not stored in the TLB, the MMU needs to find the physical address corresponding to the virtual address based on the process page table in the memory.

[0046] In order to isolate the virtual addresses used by different applications, ASID (Address Space ID) is introduced. After the application is initialized, the operating system can generate an ASID for the application and bind the ASID to the application process identifier (PID). Different applications have different ASIDs, so that the same virtual address can be used for different applications. The mapping relationship between ASID, virtual address and physical address is stored in TLB.

[0047] Among them, a process is the carrier of application running, and the running of an application usually corresponds to a process. A thread is the smallest unit for executing operations in a process. It is contained in the process and is the actual operation unit in the process. A process can usually include multiple threads, which share the memory space of the application. When a process or thread accesses memory, it uses the ASID corresponding to the process. The MMU can search for the physical address corresponding to the two in the TLB based on the ASID and virtual address.

[0048] For multi-core CPUs, there are often many scenarios that run across CPU cores.

[0049] For example, a process of a certain application is scheduled from CPU core 1 to CPU core 2 by the scheduler.

[0050] For another example, multiple threads of a process run in different CPU cores.

[0051] In these cross-CPU core running scenarios, since they are all processes or threads of the same application, they can share the same memory space. However, currently, the TLBs of different CPU cores cannot be shared. In the above cross-CPU core running scenarios, the MMU of each CPU core needs to look up the physical address corresponding to the virtual address based on the process page table in the memory, and then store the mapping relationship in the TLB, resulting in repeated process page table queries, wasting CPU core processing resources, and also affecting IO performance.

[0052] This specification provides a memory access solution for a computer system, which can improve IO performance in cross-CPU core operation scenarios and save CPU core processing resources.

[0053] Figure 1 It is a flowchart of a memory access method shown in an exemplary embodiment of this specification.

[0054] Please refer to Figure 1 The memory access method can be used for memory access of a computer system, the computer system includes a CPU, the CPU includes multiple CPU cores, the CPU core includes a TLB, the method is applied to the CPU core, for example, can be applied to the MMU of the CPU core, and includes the following steps:

[0055] Step 102: In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request.

[0056] In this specification, a process or thread running on a CPU core can initiate a memory access request (since a thread is the actual operating unit in a process, it is described as a thread initiating a memory access request in the following), and the memory access request usually carries the virtual address to be accessed. In a CPU that supports ASID, the memory access request also carries the ASID of the application, and this specification will be described later using the payment ASID as an example.

[0057] In response to the memory access request, the MMU of the CPU core may first query the TLB of the CPU core to check whether the physical address corresponding to the virtual address is cached in the TLB. For example, query the physical address corresponding to the ASID and virtual address specified in the memory access request in the TLB.

[0058] If the corresponding physical address is found in the TLB (TLB Hit), memory access can be performed based on the found physical address.

[0059] If the corresponding physical address is not found in the TLB (TLB Miss), the following step 104 may be executed.

[0060] It is worth noting that in the related art, if the corresponding physical address is not found in the TLB, the physical address can be queried based on the process page table of the memory. Using the memory access scheme provided in this specification, if the corresponding physical address is not found in the TLB, the following step 104 can be directly executed without first querying the physical address based on the process page table of the memory; or the physical address can be queried based on the process page table of the memory in parallel when executing the following step 104, and this specification does not impose any special restrictions on this.

[0061] Step 104, if the physical address corresponding to the virtual address is not found, an address detection request is sent, and the address detection request carries the virtual address, so that the CPU core that receives the address detection request can search for the physical address corresponding to the virtual address in its TLB, and if the corresponding physical address is found, an address detection response is returned, and the address detection response carries the found physical address.

[0062] Based on the search result of the aforementioned step 102 , when the physical address corresponding to the ASID and the virtual address is not cached in the TLB, the CPU core may construct an address detection request and add the ASID and the virtual address to the address detection request.

[0063] The address detection request may be constructed based on the cache detection Snoop Protocol, which is a strategy for solving the cache consistency of multi-core processors in a hardware manner. Of course, in other examples of the specification, the address detection request may also be constructed based on other protocols, and this specification does not impose any special restrictions on this.

[0064] In one example, the CPU core may broadcast the constructed address probe request to all CPU cores.

[0065] In another example, the CPU core may also send the constructed address detection request to the specified CPU core. For example, the CPU core may first read the target core identifier of the target CPU core from the specified register, and then send the address detection request to the target CPU core based on the target core identifier.

[0066] The target CPU core may be a CPU core where other threads in the process to which the thread initiating the memory access request belongs are located; the target CPU core may also be a CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core. The target core identifier of the target CPU core may be written into the designated register by the scheduler.

[0067] In the case where the address detection request is sent to a designated CPU core, after the target core identifier is read from a register, the target core identifier may be added as a parameter to the address detection request.

[0068] In this specification, after receiving an address detection request sent by another CPU core, a CPU core may query in its TLB whether a physical address corresponding to the ASID and virtual address carried in the address detection request is cached.

[0069] In the case where the physical address corresponding to the ASID and the virtual address is cached in its TLB, the physical address may be added to the address detection response and returned to the CPU core that sent the address detection request.

[0070] In the case that the ASIM and the physical address corresponding to the virtual address are not cached in its TLB, an address detection response may also be returned to the CPU core that sent the address detection request, and the address detection response does not carry the physical address.

[0071] Please refer to Figure 2 In the CPU block diagram shown, each CPU core is connected via a bus, such as a ring bus (RingBus), a MESH network bus, etc. The address detection request and the address detection response can be transmitted between each CPU core via the bus.

[0072] It is worth noting that Figure 2 The transmission direction of the address detection request / address detection response shown is only for exemplary purposes, representing that the address detection request and the address detection response are transmitted between CPU cores, and does not represent an actual transmission path.

[0073] Step 106: In response to the received address detection response, store the mapping relationship between the physical address and the virtual address carried in the address detection response in the TLB, and perform memory access based on the physical address.

[0074] In this specification, after receiving the address detection response to the address detection request sent by the CPU core, the CPU core can, on the one hand, extract the physical address from the address detection response, and then store the mapping relationship between the physical address, the virtual address and the ASID in the TLB. On the other hand, memory access can be performed based on the physical address.

[0075] When the CPU core does not receive an address detection response to the address detection request sent by the CPU core, the CPU core may search for a physical address corresponding to the virtual address based on a process page table in the memory.

[0076] From the above description, it can be seen that when the CPU core of this specification does not store the physical address corresponding to the virtual address in the TLB, it sends an address detection request to other CPU cores, and other CPU cores check whether the physical address corresponding to the virtual address is stored in their respective TLBs, and can add the queried physical address to the address detection response and return it. The CPU core can then store the mapping relationship between the physical address and the virtual address in its TLB and perform memory access.

[0077] By adopting the above technical solution provided in this specification, TLB cache sharing between CPU cores can be realized, which greatly reduces the repeated process page table queries performed by the CPU core in the scenario of running across CPU cores, reduces the waste of CPU core processing resources, and effectively shortens the time of address conversion in the case of TLB Miss, thereby improving IO performance.

[0078] On the other hand, the above technical solution provided in this specification can be implemented based on existing hardware and cache detection protocol, without the need for new hardware, with low cost and high feasibility.

[0079] The specific implementation process of this specification is described in detail below based on the two scenarios of running across CPU cores mentioned above.

[0080] 1. Multiple threads of the same process run on different CPU cores

[0081] In this specification, multiple threads of the same process share memory space and use the same ASID, that is, they all use the ASID bound to the process to which they belong.

[0082]

[0083] Table 1

[0084] Please refer to the example in Table 1. Assume that a process includes four threads, namely thread 1 to thread 4. Thread 1 and thread 2 run in CPU core 8, thread 3 and thread 4 run in CPU core 12, and ASIDs used by thread 1 to thread 4 are all ASID 7.

[0085] Assume that thread 1 first performs memory access, and the virtual address it accesses is 0x800000. The MMU of CPU core 8 searches TLB 8, but TLB 8 does not store the physical address corresponding to the virtual address 0x800000 and ASID 7. Then, the corresponding physical address is queried based on the process page table of the memory, and the queried physical address and the mapping relationship between the virtual address and ASID are stored in TLB 8. Then, CPU core 8 can perform memory access based on the queried physical address.

[0086] ASID 7 Virtual Address 0x800000 Physical Address 0x2000

[0087] Table 2

[0088] Assuming that the queried physical address is 0x2000, the TLB entry shown in Table 2 above may be stored in TLB 8. It should be noted that Table 2 is only an exemplary description, and in actual implementation, the TLB entry may also include other fields such as access rights (read or write) and page type.

[0089] If thread 3 also needs to access memory, the virtual address it accesses is also 0x800000, and the MMU of CPU core 12 searches TLB 12, but TLB 12 does not store the physical address corresponding to the virtual address 0x800000 and ASID 7. In the related art, CPU core 12 will query the physical address based on the process page table of the memory. To avoid such repeated queries, the technical solution provided in this specification is adopted, and CPU core 12 can construct an address detection request and add the virtual address 0x800000 and ASID 7 to the address detection request.

[0090] In one example, the CPU core 12 may broadcast the address detection request to all CPU cores via the bus. In a multi-core CPU architecture, a MESH network may be used to implement bus design, which results in lower latency.

[0091] In another example, see Figure 3 , the CPU core 12 may send the address detection request to the CPU core 8 where the thread 1-2 belonging to the same process as the thread 3 is located.

[0092] In this example, the CPU core 12 may first read the core identifier 8 of the CPU core 8 from the specified register, and then add the core identifier 8 as a parameter to the address detection request. Taking the Snoop protocol as an example, the address detection request is sent to the Snoop Agent, and the Snoop Agent may send the address detection request to the CPU core 8 according to the core identifier 8 carried in the address detection request.

[0093] The core identifier 8 in the register can be written by the scheduler. The scheduler knows all threads under the same process and the CPU core on which each thread runs. The scheduler can write the core identifier of the CPU core on which each thread runs under the process into the designated registers of these CPU cores.

[0094] Still taking the situation shown in Table 1 as an example, the threads under the process run in two CPU cores, namely CPU core 8 and CPU core 12, and the scheduler can write core identifier 8 into the specified register of CPU core 12, and can write core identifier 12 into the specified register of CPU core 8. Of course, the current CPU core may not be excluded, and core identifier 8 and core identifier 12 may be written into the specified registers of CPU core 8 and CPU core 12 respectively. It is worth noting that in the example of Table 1, the process runs in two CPU cores, and in other examples, it can also run in three or even more CPU cores, and this specification does not impose any special restrictions on this.

[0095] Throughout this manual, please continue to refer to Figure 3 After receiving the address detection message sent by the CPU core 12, the CPU core 8 finds the physical address 0x2000 corresponding to the virtual address 0x800000 and ASID 7 in the TLB 8, and then adds the physical address 0x2000, the virtual address 0x800000 and ASID 7 to the address detection response and returns it to the CPU core 12. The CPU core 12 can store the mapping relationship between the physical address 0x2000, the virtual address 0x800000 and ASID 7 in the TLB 12, that is, also form the TLB table entry shown in Table 2. The CPU core 12 can also perform memory access based on the physical address 0x2000.

[0096] In this specification, the CPU core 8 may also only add the physical address 0x2000 to the address detection response, and this specification does not impose any special restrictions on this.

[0097] It should be noted that in the process of implementing physical address detection based on the Snoop protocol, the forwarding of address detection requests and address detection responses is usually implemented by SnoopAgent. For example, after receiving address detection responses returned by different CPU cores, Snoop Agent filters out address detection responses that do not carry physical addresses, and can also deduplicate address detection responses carrying the same search results returned by different CPU cores. For example, an address detection response carrying the aforementioned physical address is returned to the CPU core that sent the address detection request.

[0098] From the above description, it can be seen that in the scenario where multiple threads of the same process run on different CPU cores, if the CPU core does not store the physical address corresponding to the virtual address in the TLB, it can send an address detection request to other CPU cores. Other CPU cores check whether the physical address corresponding to the virtual address is stored in their respective TLBs, and can add the queried physical address to the address detection response and return it. The CPU core can then store the mapping relationship between the physical address and the virtual address in its TLB and perform memory access.

[0099] By adopting the above technical solution provided in this specification, TLB cache sharing between CPU cores can be realized, which greatly reduces the repeated process page table queries performed by the CPU core when multiple threads of the same process run on different CPU cores, reduces the waste of CPU core processing resources, and effectively shortens the time of address conversion in the case of TLB Miss, thereby improving IO performance.

[0100] On the other hand, the above technical solution provided in this specification can be implemented based on existing hardware and cache detection protocol, without the need for new hardware, with low cost and high feasibility.

[0101] 2. Process Migration

[0102] In the related art, a TLB entry may have three states: Valid, Stale, and Invalid.

[0103] Valid means the corresponding TLB entry is valid;

[0104] Stale means that the corresponding TLB entry is temporarily invalid and can be reactivated to the Valid state;

[0105] Invalid means that when the memory corresponding to the TLB entry is released, for example, when the process is destroyed, the corresponding TLB entry is destroyed and the destroyed TLB entry cannot be activated again.

[0106] Among them, after the TLB table entry is generated, its status is valid. During the process switching process, if the process is swapped out, the TLB table entry corresponding to the ASID bound to the swapped out process is set to an invalid Stale state. For example, the operating system sends a TLB invalidation instruction after the process is swapped out. The TLB invalidation instruction specifies the ASID bound to the swapped out process. Based on the TLB invalidation instruction, the TLB table entry corresponding to the specified ASID is set from a valid Valid state to an invalid Stale state. After the process is switched back, when accessing memory, the MMU queries the TLB table entry that hits the Stale state, and then the state of the hit TLB table entry can be set from invalid Stale to valid Valid.

[0107] After the process is destroyed, the operating system may send a TLB shootdown instruction (TLB Shootdown), in which the ASID bound to the destroyed process is specified. Based on the TLB shootdown instruction, the TLB table entries corresponding to the specified ASID (including TLB table entries in the valid state and TLB table entries in the invalid state) may be completely destroyed, for example, the TLB table entries may be deleted to be in the Invalid state.

[0108] In this specification, the scheduler can schedule processes based on the load of each CPU core, for example, if a process is running in the first CPU core, the process is scheduled to run in the second CPU core, etc. Scheduling a process generally refers to scheduling all threads under the process.

[0109] In the related art, when a process is scheduled, the operating system will send a TLB destroy instruction to the first CPU core, thereby completely destroying the TLB entry corresponding to the ASID bound to the process in the TLB of the first CPU core. After the process is scheduled to the second CPU core, when accessing memory, the second CPU core still needs to perform address translation based on the process page table in the memory.

[0110] To avoid such repeated queries, the technical solution provided in this specification is adopted. In the case of process scheduling, on the one hand, the operating system sends a TLB invalidation instruction to replace the TLB destruction instruction to avoid the relevant TLB table entries being completely destroyed. On the other hand, in the case of TLB Miss, the second CPU core can construct an address detection request to request other CPU cores to assist in querying the physical address.

[0111] Please refer to Figure 4 In the process scheduling scenario, the memory access method provided in this specification may include the following steps:

[0112] Step 402: The first CPU core receives a TLB invalidation instruction and sets the TLB entry in the first TLB to which the called-out process is bound to to an invalid state.

[0113] In this embodiment, after the process is scheduled out of the first CPU core, unlike related technologies, the operating system does not send a TLB destroy instruction to the first CPU core, but sends a TLB invalidate instruction to the first CPU core, in which the ASID bound to the called out process is specified.

[0114] In response to the TLB invalidation instruction, the first CPU core sets the TLB entry corresponding to the ASID in the first TLB (ie, the TLB of the first CPU core) from a valid Valid state to an invalid Stale state.

[0115] In other words, by adopting the technical solution provided in this specification, when a process is scheduled, the TLB entries in the CPU core where the process originally resides will not be completely destroyed, but these TLB entries will be set to a temporarily invalid Stale state.

[0116] Step 404: The second CPU core searches the second TLB for a physical address corresponding to the virtual address in response to the memory access request of the called process.

[0117] In this embodiment, the above process or the thread under the process scheduled to run on the second CPU core initiates a memory access request to the second CPU core when performing memory access. The second CPU core then first searches the second TLB (i.e., the TLB of the second CPU core) for the physical address corresponding to the ASID and the virtual address. If the corresponding physical address is found (TLB Hit), memory access can be performed based on the physical address. If the corresponding physical address is not found (TLB Miss), the following step 406 can be executed.

[0118] Step 406: If the second CPU core fails to find the physical address, the second CPU core sends an address detection request to the first CPU core.

[0119] Based on the query result of the aforementioned step 404, if the second CPU core fails to find the physical address, it may construct an address detection request and add the virtual address to be accessed and the process-bound ASID to the address detection request.

[0120] The second CPU core sends the address detection request. For example, the address detection request may be broadcasted, or the address detection request may be sent to the CPU core where the process is located before being scheduled, that is, the first CPU core.

[0121] In this embodiment, the construction and sending of the address detection request may refer to the specific implementation process of the above-mentioned embodiment, and this embodiment will not be described in detail here.

[0122] It should be noted that, when the second CPU core sends an address detection request to the first CPU core based on the first core identifier of the first CPU core in the register, the first core identifier in the designated register may be written by the scheduler after the process is scheduled.

[0123] Step 408: The first CPU core searches the first TLB for a physical address corresponding to the virtual address in response to the address detection request.

[0124] In this embodiment, the first CPU core searches for TLB entries in a valid state and an invalid state in the first TLB in response to the address detection request to query the physical address.

[0125] Among them, if the query hits a TLB table entry in a valid state, it can be explained that it is likely that different threads of the same process are running on different CPU cores, that is, the thread that initiates the memory access request in the second CPU core and some threads running in the first CPU core belong to the same process.

[0126] If the query hits an invalid TLB entry, it may indicate a scenario of process scheduling migration, that is, the process originally runs in the first CPU core and is then migrated to the second CPU core by the scheduler.

[0127] In other words, for the CPU core that receives the address detection request, when querying the TLB table entries, it is necessary to query both the TLB table entries in the valid state and the TLB table entries in the invalid state. After the query hits, the found physical address can be returned, and the CPU core does not need to pay attention to the specific application scenario.

[0128] Step 410: The first CPU core adds the found physical address to the address detection response and returns it to the second CPU core.

[0129] Step 412: After receiving the address detection response, the second CPU core stores the mapping relationship between the physical address and the virtual address in the second TLB, and performs memory access based on the physical address.

[0130] In this embodiment, the implementation process of steps 410 - 412 may refer to the description in the above-mentioned embodiment.

[0131] In this embodiment, if the second CPU core does not receive an address detection response carrying a physical address, for example, if no address detection response carrying a physical address is received within a preset time period, the second CPU core can query the physical address based on the process page table of the memory.

[0132] From the above description, it can be seen that in the process migration scenario, if the CPU core does not store the physical address corresponding to the virtual address in the TLB, it can send an address detection request to other CPU cores. Other CPU cores check whether the physical address corresponding to the virtual address is stored in their respective TLBs, and can add the queried physical address to the address detection response and return it. The CPU core can then store the mapping relationship between the physical address and the virtual address in its TLB and perform memory access.

[0133] By adopting the above technical solution provided in this specification, TLB cache sharing between CPU cores can be realized, which greatly reduces the repeated process page table queries performed by the CPU core in the process migration scenario, reduces the waste of CPU core processing resources, and effectively shortens the time of address conversion in the case of TLB Miss, thereby improving IO performance.

[0134] On the other hand, the above technical solution provided in this specification can be implemented based on existing hardware and cache detection protocol, without the need for new hardware, with low cost and high feasibility.

[0135] Corresponding to the above-mentioned embodiment of the memory access method, this specification also provides an embodiment of a memory access device.

[0136] The memory access device of the present specification can be applied to the CPU core of a computer system, wherein the CPU core includes a TLB, and the TLB is used to cache the mapping relationship between the virtual address and the physical address. Figure 5 The memory access device 500 includes: an address search unit 501, an address detection unit 502, a memory access unit 503 and a status marking unit 504.

[0137] The address search unit 501 searches the TLB for a physical address corresponding to a virtual address carried in the memory access request in response to the memory access request;

[0138] The address detection unit 502 sends an address detection request when the physical address corresponding to the virtual address is not found, and the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and returns an address detection response when the corresponding physical address is found, and the address detection response carries the found physical address;

[0139] The memory access unit 503, in response to the received address detection response, stores the mapping relationship between the physical address and the virtual address carried in the address detection response into the TLB, and performs memory access based on the physical address.

[0140] Optionally, the address detection unit 502 reads a target core identifier of a target CPU core from a register; and sends an address detection request to the target CPU core based on the target core identifier.

[0141] Optionally, the address detection unit 502 broadcasts an address detection request.

[0142] Optionally, the target CPU core is a CPU core where other threads in the process to which the thread initiating the memory access request belongs are located.

[0143] Optionally, the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

[0144] Optionally, the target core identifier is written by a scheduler.

[0145] Optionally, also include:

[0146] A status marking unit 504 receives a TLB invalidation instruction, wherein the TLB invalidation instruction is sent after the thread initiating the memory access request is scheduled to another CPU core;

[0147] In response to the TLB invalidation instruction, marking a mapping relationship between a virtual address and a physical address specified by the TLB invalidation instruction in the TLB as an invalid state;

[0148] The method further comprises:

[0149] The address search unit 501 searches the TLB for physical addresses corresponding to virtual addresses in valid and invalid states after receiving address detection requests sent by other CPU cores.

[0150] Optionally, the address search unit 501 searches for a physical address corresponding to the virtual address based on a process page table in a memory when the address detection response is not received.

[0151] The implementation process of the functions and effects of each unit in the above-mentioned device is specifically described in the implementation process of the corresponding steps in the above-mentioned method, and will not be repeated here.

[0152] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can refer to the partial description of the method embodiments. The device embodiments described above are only schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this specification. Ordinary technicians in this field can understand and implement it without paying creative work.

[0153] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer, which may be in the form of a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email transceiver, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0154] Corresponding to the embodiment of the aforementioned memory access method, the present specification further provides a CPU core, the CPU core includes a translation bypass cache TLB, the TLB is used to cache the mapping relationship between the virtual address and the physical address, and the CPU core is configured as follows:

[0155] In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request;

[0156] In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address;

[0157] In response to the received address detection response, the mapping relationship between the physical address and the virtual address carried in the address detection response is stored in the TLB, and memory access is performed based on the physical address.

[0158] Optionally, sending an address detection request includes:

[0159] Broadcast address detection request.

[0160] Optionally, sending an address detection request includes:

[0161] Read the target core ID of the target CPU core from the register;

[0162] An address detection request is sent to the target CPU core based on the target core identifier.

[0163] Optionally, the target CPU core is a CPU core where other threads in the process to which the thread initiating the memory access request belongs are located.

[0164] Optionally, the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

[0165] Optionally, the target core identifier is written by a scheduler.

[0166] Optionally, also include:

[0167] receiving a TLB invalidation instruction, wherein the TLB invalidation instruction is sent after the thread initiating the memory access request is scheduled to another CPU core;

[0168] In response to the TLB invalidation instruction, marking a mapping relationship between a virtual address and a physical address specified by the TLB invalidation instruction in the TLB as an invalid state;

[0169] The CPU core is also configured as:

[0170] After receiving the address detection request sent by other CPU cores, the physical address corresponding to the virtual address in the valid state and the invalid state is searched in the TLB.

[0171] Optionally, also include:

[0172] In the case where the address detection response is not received, the physical address corresponding to the virtual address is searched based on the process page table of the memory.

[0173] Corresponding to the embodiment of the aforementioned memory access method, this specification also provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a CPU core, the following steps are implemented:

[0174] In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request;

[0175] In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address;

[0176] In response to the received address detection response, the mapping relationship between the physical address and the virtual address carried in the address detection response is stored in the TLB, and memory access is performed based on the physical address.

[0177] Optionally, sending an address detection request includes:

[0178] Broadcast address detection request.

[0179] Optionally, sending an address detection request includes:

[0180] Read the target core ID of the target CPU core from the register;

[0181] An address detection request is sent to the target CPU core based on the target core identifier.

[0182] Optionally, the target CPU core is a CPU core where other threads in the process to which the thread initiating the memory access request belongs are located.

[0183] Optionally, the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

[0184] Optionally, the target core identifier is written by a scheduler.

[0185] Optionally, also include:

[0186] receiving a TLB invalidation instruction, wherein the TLB invalidation instruction is sent after the thread initiating the memory access request is scheduled to another CPU core;

[0187] In response to the TLB invalidation instruction, marking a mapping relationship between a virtual address and a physical address specified by the TLB invalidation instruction in the TLB as an invalid state;

[0188] The method further comprises:

[0189] After receiving the address detection request sent by other CPU cores, the physical address corresponding to the virtual address in the valid state and the invalid state is searched in the TLB.

[0190] Optionally, also include:

[0191] In the case where the address detection response is not received, the physical address corresponding to the virtual address is searched based on the process page table of the memory.

[0192] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0193] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A memory access method for memory access of a computer system, wherein the computer system comprises a central processing unit (CPU), the CPU comprises a plurality of CPU cores, the CPU core comprises a translation bypass cache (TLB), the TLB is used to cache a mapping relationship between a virtual address and a physical address, and the method is applied to the CPU core, comprising: In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request; In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address; In response to the received address detection response, store the mapping relationship between the physical address and the virtual address carried in the address detection response in the TLB, and perform memory access based on the physical address; The sending of the address detection request comprises: Read the target core ID of the target CPU core from the register; Sending an address detection request to the target CPU core based on the target core identifier; The target CPU core is the CPU core where other threads in the process to which the thread initiating the memory access request belongs are located, or the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

2. The method according to claim 1, wherein sending an address detection request comprises: Broadcast address detection request. 3 . The method according to claim 1 , wherein the target core identifier is written by a scheduler.

4. The method according to claim 1, further comprising: receiving a TLB invalidation instruction, wherein the TLB invalidation instruction is sent after the thread initiating the memory access request is scheduled to another CPU core; In response to the TLB invalidation instruction, marking a mapping relationship between a virtual address and a physical address specified by the TLB invalidation instruction in the TLB as an invalid state; The method further comprises: After receiving the address detection request sent by other CPU cores, the physical address corresponding to the virtual address in the valid state and the invalid state is searched in the TLB.

5. The method according to claim 1, further comprising: In the case where the address detection response is not received, the physical address corresponding to the virtual address is searched based on the process page table of the memory.

6. A memory access device for memory access of a computer system, wherein the computer system comprises a central processing unit (CPU), the CPU comprises a plurality of CPU cores, the CPU core comprises a translation bypass buffer (TLB), the TLB is used to cache a mapping relationship between a virtual address and a physical address, and the device is applied to the CPU core, comprising: An address search unit, in response to a memory access request, searches the TLB for a physical address corresponding to a virtual address carried in the memory access request; The address detection unit sends an address detection request when the physical address corresponding to the virtual address is not found, and the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and returns an address detection response when the corresponding physical address is found, and the address detection response carries the found physical address; A memory access unit, in response to a received address detection response, stores a mapping relationship between the physical address and the virtual address carried in the address detection response into the TLB, and performs memory access based on the physical address; The address detection unit sending the address detection request includes: reading a target core identifier of a target CPU core from a register; and sending the address detection request to the target CPU core based on the target core identifier; The target CPU core is the CPU core where other threads in the process to which the thread initiating the memory access request belongs are located, or the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

7. A central processing unit (CPU), the CPU comprising a plurality of CPU cores, the CPU core comprising a translation bypass buffer (TLB), the TLB being used to cache a mapping relationship between a virtual address and a physical address, the CPU core being configured as follows: In response to a memory access request, searching the TLB for a physical address corresponding to a virtual address carried in the memory access request; In the case where the physical address corresponding to the virtual address is not found, an address detection request is sent, the address detection request carries the virtual address, so that the CPU core that receives the address detection request searches for the physical address corresponding to the virtual address in its TLB, and in the case where the corresponding physical address is found, an address detection response is returned, the address detection response carries the found physical address; In response to the received address detection response, store the mapping relationship between the physical address and the virtual address carried in the address detection response in the TLB, and perform memory access based on the physical address; The sending of the address detection request comprises: reading a target core identifier of a target CPU core from a register; and sending the address detection request to the target CPU core based on the target core identifier; The target CPU core is the CPU core where other threads in the process to which the thread initiating the memory access request belongs are located, or the target CPU core is the CPU core where the thread initiating the memory access request was located before being scheduled to the current CPU core.

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