A control component

Abstract

The present application discloses a control component, including a processor, a cache write unit and a cache query unit; the processor provides a write command to the cache write unit; the cache write unit obtains a logical address from the write command and provides the logical address to the cache query unit; the cache query unit is coupled with each entry of a cache queue, and queries whether the logical address provided by the cache write unit hits an entry of the cache queue; in response to the cache query unit indicating that the logical address hits a first entry of the cache queue, the cache write unit writes the data to be written by the write command into the cache unit corresponding to the first entry.

Description

Technical Field

[0001] The present application relates to storage technology, and in particular, to write cache hardware in a storage controller. Background Art

[0002] Figure 1 The block diagram of the solid-state storage device is shown. The solid-state storage device 102 is coupled to the host to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in a variety of ways, including but not limited to connecting the host and the solid-state storage device 102 through, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIe), NVMe (NVM Express), Ethernet, Fiber Channel, wireless communication network, etc. The host can be an information processing device that can communicate with the solid-state storage device in the above manner, such as a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, etc. The solid-state storage device 102 includes an interface 103 , a control component 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory) 110 .

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), RRAM (Resistive Random Access Memory), XPoint memory, etc. are common NVMs.

[0004] The interface 103 may be adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fibre Channel, etc.

[0005] The control component 104 is used to control data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, mapping of host logical addresses to flash physical addresses, erase leveling, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof. For example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control component 104 can also include a processor or a controller, in which software is executed to manipulate the hardware of the control component 104 to process IO (Input / Output) commands. The control component 104 can also be coupled to the DRAM 110 and can access the data of the DRAM 110. The data of the FTL table and / or cached IO commands can be stored in the DRAM.

[0006] The control component 104 includes a flash memory interface controller (or medium interface controller, flash memory channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner that complies with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

[0007] In a solid-state storage device, a Flash Translation Layer (FTL) is used to maintain mapping information from logical addresses to physical addresses. The logical address constitutes the storage space of the solid-state storage device perceived by upper-layer software such as the operating system. The physical address is the address used to access the physical storage unit of the solid-state storage device. In the related art, address mapping can also be implemented using an intermediate address form. For example, the logical address is mapped to an intermediate address, and then the intermediate address is further mapped to a physical address. In these cases, the read / write command received by the storage device indicates the logical address.

[0008] The table structure that stores the mapping information from logical addresses to physical addresses is called an FTL table. The FTL table is an important metadata in a solid-state storage device. Usually, the entries in the FTL table record the address mapping relationship in units of data pages in the solid-state storage device.

[0009] Some storage devices' FTLs are provided by the host to which the storage device is coupled, with the host's memory storing the FTL table and the host's CPU executing software to provide the FTL. Other storage management devices provided by some storage management devices between the host and the storage device provide the FTL. In these cases, the read / write commands received by the storage device indicate physical addresses.

[0010] The command provided by the host to the storage device may access the logical address space corresponding to one or more entries of the FTL table. And the control component may change the form of the command received from the interface 103 (for example, split the command according to the size of the logical address space corresponding to the FTL entry) and process the changed form of the command.

[0011] For the purpose of clarity, in this document, it is described as an example that a read / write command received by a storage device accesses a single FTL entry.

[0012] The control unit 104 of the storage device provides a write cache managed by software running in the processor of the control unit 104. For a write command, the data to be written is temporarily stored in the write cache to reduce the processing delay of the write command. If the write command hits the write cache, the data corresponding to the write command is stored in the hit write cache. For a read command, if the read command hits the write cache, the data in the write cache is used to respond to the read command. The write cache is also used to process "lower writes". A write command that accesses part (but not all) of the address space corresponding to a single FTL entry is called a lower write command. The data corresponding to the lower write command is stored in the write cache, and the part of the address space of the FTL entry accessed by the lower write command that may not be accessed by the lower write command is also read from the NVM chip of the storage device, and the read part is also stored in the write cache. This operation is called a merge of the address space corresponding to the FTL entry. Summary of the invention

[0013] The write cache implemented by software puts a heavy load on the processor of the control unit and its performance needs to be improved.

[0014] According to an embodiment of the present application, a hardware-implemented write cache is provided to share the load of the processor and improve performance.

[0015] According to the first aspect of the present application, a method for processing a first command according to the first aspect of the present application is provided, which includes the following steps: obtaining a write command; in response to the write command hitting an entry in the cache queue, writing the data to be written by the write command into the cache unit corresponding to the entry.

[0016] According to the processing method of the first command of the first aspect of the present application, a processing method of the second command of the first aspect of the present application is provided, wherein the logical address accessed by the write command is compared with the logical addresses of one or more entries of the cache queue to determine whether the write command hits the entry of the cache queue.

[0017] According to the method for processing commands of any one of the first to second items of the first aspect of the present application, a method for processing the third command of the first aspect of the present application is provided, wherein the entry of the cache queue records the logical address, tag and cache unit index of the write command.

[0018] According to the processing method of the third command of the first aspect of the present application, a processing method of the fourth command of the first aspect of the present application is provided, wherein the cache unit index indicates a logical address or number of the cache unit.

[0019] According to the processing method of the third or fourth command of the first aspect of the present application, a processing method of the fifth command of the first aspect of the present application is provided, wherein each entry in the cache queue has a designated cache unit, and the index of the cache unit is obtained according to the number of the entry in the cache queue.

[0020] According to the command processing method of any one of the third to fifth items of the first aspect of the present application, a command processing method of the sixth aspect of the present application is provided, wherein a mark indicates whether the logical address accessed by the write command covers the logical address space corresponding to the cache queue entry.

[0021] According to the processing method of the fifth command of the first aspect of the present application, a processing method of the seventh command of the first aspect of the present application is provided, wherein the entries in the cache queue are queried according to the logical address, and the entries indicate that the write command hits the cache unit to be merged, and the cache units are merged.

[0022] According to the processing method of the seventh command of the first aspect of the present application, a processing method of the eighth command of the first aspect of the present application is provided, wherein, in response to merging cache units, the mark state of the entry is set to not require merging, and the value of the merge counter is reduced by 1.

[0023] According to the command processing method of any one of items 1 to 8 of the first aspect of the present application, a command processing method of the ninth aspect of the present application is provided, wherein, in response to receiving a write command, it is determined whether the write command writes data to the complete logical address space corresponding to the entry of the cache queue.

[0024] According to the processing method of the seventh command of the first aspect of the present application, a processing method of the tenth command of the first aspect of the present application is provided, wherein, if the write command does not write data to the complete logical address space corresponding to the entry of the cache queue, the mark of the entry is set to indicate to be merged, and the value of the merge counter is increased by 1.

[0025] According to the processing method of the tenth command of the first aspect of the present application, a processing method of the eleventh command of the first aspect of the present application is provided, wherein, if the write command indicates to write data to part of the complete logical address space corresponding to the first entry of the cache queue, the data to be written by the write command is written to the allocated first cache unit, and the remaining data in the logical address space corresponding to the first entry is read from the non-volatile memory.

[0026] According to the processing method of the eleventh command of the first aspect of the present application, a processing method of the twelfth command of the first aspect of the present application is provided, wherein, in response to reading the remaining data of the logical address space corresponding to the first entry, the mark of the first entry is set to indicate that merging is not required, and the value of the merge counter is decremented by 1.

[0027] According to the processing method of the eleventh command of the first aspect of the present application, a processing method of the thirteenth command of the first aspect of the present application is provided, wherein, if the write command indicates to write data to the part of the complete logical address space corresponding to the first entry of the cache queue, the data corresponding to the write command is written to the first cache unit, and if the first cache unit still has not recorded the data of the complete logical address space corresponding to the first entry, the mark state of the first entry does not change and the merge counter is not updated.

[0028] According to the processing method of any one of the first to thirteenth commands of the first aspect of the present application, a processing method of the fourteenth command of the first aspect of the present application is provided, wherein if the write command does not hit an entry in the cache queue, an entry is added to the cache queue.

[0029] According to the processing method of any one of the first to fourteenth commands of the first aspect of the present application, a processing method of the fifteenth command of the first aspect of the present application is provided, wherein, if the number of filled entries in the cache queue is greater than a threshold, data stored in the cache units corresponding to one or more entries of the cache queue are written to a non-volatile memory.

[0030] According to the processing method of the fifteenth command of the first aspect of the present application, a processing method of the sixteenth command of the first aspect of the present application is provided, which further includes checking whether there are cache units to be merged in the cache queue.

[0031] According to the processing method of the sixteenth command of the first aspect of the present application, a processing method of the seventeenth command of the first aspect of the present application is provided, wherein whether the cache queue has cache units to be merged is determined according to the value of the merge counter.

[0032] According to the processing method of the seventeenth command of the first aspect of the present application, a processing method of the eighteenth command of the first aspect of the present application is provided, wherein, if it is checked that the cache queue has cache units to be merged, the cache units are merged and then the data stored in the cache units are written to the non-volatile memory.

[0033] According to a method for processing commands of any one of items 1 to 18 of the first aspect of the present application, a method for processing the 19th command of the first aspect of the present application is provided, which includes the following steps: obtaining a read command; in response to the read command hitting an entry in the cache queue, accessing the cache unit corresponding to the entry, and obtaining data accessed by the read command.

[0034] According to the second aspect of the present application, a first control component according to the second aspect of the present application is provided, which includes a processor, a cache write unit and a cache query unit; the processor provides a write command to the cache write unit; the cache write unit obtains a logical address from the write command and provides the logical address to the cache query unit; the cache query unit queries whether the logical address provided by the cache write unit hits an entry in the cache queue; in response to the cache query unit indicating that the logical address hits a first entry in the cache queue, the cache write unit writes the data to be written by the write command into the cache unit corresponding to the first entry.

[0035] According to the first control component of the second aspect of the present application, a second control component of the second aspect of the present application is provided, wherein the cache query unit is coupled to each entry of the cache queue, compares the logical address of the write command with the logical address of each entry of the cache queue, and determines whether the write command hits one of the entries of the cache queue.

[0036] According to the first or second control component of the second aspect of the present application, a third control component of the second aspect of the present application is provided, which also includes a cache management unit. In response to the cache query unit indicating that the logical address does not hit any entry in the cache queue, the cache write unit adds the logical address and tag of the write command to the entry at the end of the cache queue through the cache management unit.

[0037] According to the first control component of the second aspect of the present application, a fourth control component of the second aspect of the present application is provided, wherein, in response to the cache query unit indicating that the logical address hits the first entry of the cache queue, the cache write unit writes the data to be written by the write command into the cache unit corresponding to the first entry through the cache management unit.

[0038] According to the control component of any one of the third to fourth items of the second aspect of the present application, a fifth control component of the second aspect of the present application is provided, wherein the cache management unit generates a cache unit index through the number of the entry to be written in the cache queue, or the cache management unit allocates an available cache unit to the entry to be written and records the index of the allocated cache unit in the entry.

[0039] According to the control component of any one of the third to fifth items of the second aspect of the present application, a sixth control component of the second aspect of the present application is provided, wherein the cache write unit generates a mark according to whether the logical address accessed by the write command covers the logical address space corresponding to the entry of the cache queue.

[0040] According to the control component of any one of items 3 to 6 of the second aspect of the present application, a seventh control component of the second aspect of the present application is provided, wherein the cache management unit also includes a merge counter, and the value of the merge counter indicates the number of entries stored in the cache queue that do not accommodate complete data of the logical address space.

[0041] According to the control component of any one of the third to seventh items of the second aspect of the present application, an eighth control component of the second aspect of the present application is provided, wherein if the cache write unit determines that the write command does not write data to the complete logical address space corresponding to the entry of the cache queue, the cache write unit provides a signal to the processor.

[0042] According to the control component of any one of the third to seventh items of the second aspect of the present application, a ninth control component of the second aspect of the present application is provided, wherein if the cache write unit determines that the write command does not write data to the complete logical address space corresponding to the first entry of the cache queue, the cache write unit provides a signal to the processor.

[0043] According to the ninth control component of the second aspect of the present application, a tenth control component of the second aspect of the present application is provided, wherein, in response to receiving a signal provided by the cache write unit to the processor, the processor reads data of the unwritten portion of the logical address space corresponding to the first entry from the non-volatile memory.

[0044] According to the tenth control component of the second aspect of the present application, an eleventh control component of the second aspect of the present application is provided, wherein, in response to the logical address space corresponding to the first entry being completed, the flag of the second entry of the cache write unit is set to not require merging, and the cache write unit instructs the cache management unit to decrement the value of the merge counter.

[0045] According to the tenth control component of the second aspect of the present application, a twelfth control component of the second aspect of the present application is provided, wherein, in response to the cache write unit writing the data to be written by the write command into the first cache unit, if the cache write unit determines that the second write command does not write data to the complete logical address space corresponding to the first entry of the cache queue, the cache write unit does not provide a signal to the processor, so that the mark state of the first entry does not change, and the merge counter is not updated.

[0046] According to the eleventh or twelfth control component of the second aspect of the present application, a thirteenth control component of the second aspect of the present application is provided, wherein, in response to the cache query unit indicating that the logical address of the second write command hits the first entry of the cache queue, the cache write unit writes the data to be written by the second write command into the cache unit corresponding to the first entry; in response to the cache write unit writing the data to be written by the second write command into the first cache unit, if the first cache unit still has not recorded the data of the complete logical address space corresponding to the first entry, the mark state of the first entry does not change and the merge counter is not updated.

[0047] According to the first to thirteenth control components of the second aspect of the present application, a fourteenth control component of the second aspect of the present application is provided, wherein, in response to the cache query unit querying that the logical address of the write command does not hit the entry of the cache queue, the cache query unit instructs the cache write unit to add an entry to the cache queue.

[0048] According to the first to fourteenth control components of the second aspect of the present application, a fifteenth control component of the second aspect of the present application is provided, wherein if there are cache units to be merged, the processor merges the cache units to be merged, and then writes the data stored in the cache units into the non-volatile memory.

[0049] According to the first to fifteenth control components of the second aspect of the present application, a sixteenth control component of the second aspect of the present application is provided, which also includes a cache read unit, which is coupled to the processor, the cache query unit and the cache management unit, receives the read command and its logical address sent by the processor, and provides the logical address to the cache query unit.

[0050] According to the sixteenth control component of the second aspect of the present application, a seventeenth control component of the second aspect of the present application is provided, wherein the cache query unit queries whether the logical address provided by the cache read unit hits an entry in the cache queue.

[0051] According to the seventeenth control component of the second aspect of the present application, an eighteenth control component of the second aspect of the present application is provided, wherein, if the cache query unit indicates that the logical address hits the first entry of the cache queue, the cache read unit accesses the cache unit corresponding to the first entry.

[0052] According to the first to eighteenth control components of the second aspect of the present application, a nineteenth control component of the second aspect of the present application is provided, wherein, in response to the number of entries filled in the cache queue being greater than a first threshold or the number of unfilled entries being less than a second threshold, the cache management unit provides a second signal to the processor; and the processor performs a flush operation on the cache queue in response to receiving the second signal.

[0053] According to the nineteenth control component of the second aspect of the present application, a twentieth control component of the second aspect of the present application is provided, wherein, during a flush operation, the processor writes data of a cache unit corresponding to each filled entry of the cache queue into a non-volatile memory, and releases the corresponding queue entry.

[0054] According to the control component of any one of items 18 to 19 of the second aspect of the present application, there is provided a twenty-first control component of the second aspect of the present application, wherein, if the complete logical address space corresponding to one or more entries being flushed has not been written with complete data, the processor merges the cache units corresponding to one or more entries in its complete logical address space in which complete data has not been written, and then writes the data stored in the cache units corresponding to these entries into the non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0056] Figure 1 A block diagram of a storage device in the prior art;

[0057] Figure 2 A block diagram of a cache system according to an embodiment of the present application is shown;

[0058] Figure 3 A flow chart showing a method implemented by a cache system according to an embodiment of the present application;

[0059] Figure 4A and 4B A schematic diagram of using a cache system according to an embodiment of the present application is shown;

[0060] Figure 5A-5B A schematic diagram of using a cache system according to another embodiment of the present application is shown;

[0061] Fig. 6A and Figure 6B A schematic diagram of using a cache system according to another embodiment of the present application is shown;

[0062] Figure 7A-7C A schematic diagram of using a cache system according to another embodiment of the present application is shown. DETAILED DESCRIPTION

[0063] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0064] Figure 2 A block diagram of a cache system according to an embodiment of the present application is shown.

[0065] The cache system includes a cache writing unit 220 , a cache query unit 230 and a cache management unit 240 .

[0066] The cache management unit 240 manages, for example, a hardware cache queue. Each entry in the cache queue records, for example, a logical address (LBA), a tag, and a cache unit index.

[0067] The logical address is the logical address indicated by the write command. Optionally, the logical address is replaced by a partial bit of the logical address or a hash value of the logical address. Still optionally, in the case where the write command indicates a physical address or other address, the entry of the cache queue records the physical address, other address, or the converted value of the address indicated by the write command.

[0068] The mark of the entry record of the cache queue indicates, for example, whether the cache unit corresponding to the entry accommodates the complete data of the logical address space corresponding to the entry. The size of the logical address space of each entry corresponds to an entry in the FTL table. Optionally, the mark also indicates which part or parts of the logical address space corresponding to the entry the data accommodated by the cache unit corresponding to the entry comes from.

[0069] The cache unit index recorded in the entry of the cache queue is used to index the cache unit. The cache unit is a storage space provided by a memory such as a memory outside the control component or a memory. The cache unit index indicates, for example, a memory address or number of the cache unit. As an example, the entry of the cache queue is bound to the cache unit, for example, each entry of the cache queue has a specified cache unit, so that the cache unit index recorded in the cache queue entry can be omitted, and the index of the cache unit corresponding to the entry is obtained according to the number of the entry in the cache queue.

[0070] The cache management unit also includes a merge counter 245 , the value of which indicates the number of entries in the cache queue whose corresponding storage units store data but do not accommodate the complete data of the logical address space.

[0071] The processor 210 is coupled to the cache write unit 220 to provide a write command to the cache write unit 220. Alternatively, the write command is processed by a hardware circuit different from the processor and is coupled to the cache write unit 220 to provide the write command to the cache write unit 220. Alternatively, the processor 210 is also coupled to the cache read unit 270 to provide a read command to the cache read unit 270.

[0072] The cache write unit 220 obtains the logical address (LBA) accessed by the write command according to the received write command, generates a tag corresponding to the write command, and adds the tag to the entry of the cache queue through the cache management unit 240. It can be understood that the logical address (LBA) space range accessed by the write command does not exceed the logical address (LBA) space of a single entry in the FTL table as an example. If the write command accesses a larger logical address (LBA) space, the processor 210 splits the write command into multiple sub-write commands, and the logical address (LBA) space range accessed by each sub-write command does not exceed the logical address (LBA) space of a single entry in the FTL table.

[0073] The cache management unit 240 operates the cache queue in a queue manner, for example, adding the logical address (LBA) and the tag provided by the cache write unit 220 to the entry at the end of the cache queue. Optionally, a cache unit index is generated according to the number of the entry being written in the cache queue, or an available cache unit is allocated to the entry being written, and the index of the allocated cache unit is recorded in the entry.

[0074] The cache write unit 220 generates a mark according to whether the logical address (LBA) accessed by the write command covers the complete logical address (LBA) space corresponding to the cache queue entry, and the mark indicates whether the logical address (LBA) accessed by the write command covers the logical address (LBA) space corresponding to the cache queue entry.

[0075] Furthermore, the cache management unit 240 also determines whether to increment the merge counter 245 according to the flag provided by the cache write unit 220. If the flag indicates, for example, whether the cache unit corresponding to the entry accommodates the complete data of the logical address space corresponding to the entry

[0076] The cache write unit 220 also provides the logical address (LBA) of the write command to the cache query unit 230 to query whether the logical address (LBA) hits the entry of the cache queue. The cache query unit 230 is coupled to each entry of the cache queue to compare the received logical address (LBA) with the logical addresses (LBA) of each entry of the cache queue to identify whether the received logical address (LBA) hits the entry of the cache queue. Optionally, if the entry of the cache queue records partial bits of the logical address or the converted value of the logical address, the cache query unit 230 intercepts the corresponding partial bits of the received logical address or performs the same conversion, and then compares it with each entry of the cache queue.

[0077] If the received logical address (LBA) hits one of the entries in the cache queue, the cache query unit 230 indicates the hit entry to the cache write unit 220. The cache write unit 220 writes the data corresponding to the write command to the cache unit corresponding to the index field of the hit entry. Optionally, the cache write unit 220 writes the data corresponding to the write command to the cache unit corresponding to the index field of the hit entry through the cache management unit 240, and optionally updates the hit entry in the cache queue.

[0078] Further, if the tag field of the entry of the hit cache queue indicates that the cache unit corresponding to the entry does not contain the complete data of the logical address space corresponding to the entry, a signal is provided to the processor 210. The processor 210 obtains the data corresponding to the logical address of the entry and writes it to the cache unit corresponding to the entry, so that the cache unit of the entry contains the complete data of the logical address space corresponding to the entry. This operation is called merging the cache units. In response to the completion of the merge of the cache units, the tag of the entry corresponding to the cache unit is updated to indicate that the cache unit corresponding to the entry contains the complete data of the logical address space corresponding to the entry.

[0079] If the received logical address (LBA) does not hit any entry in the cache queue, the cache query unit 230 indicates to the cache write unit 220 that there is no hit entry. The cache write unit 220 generates the content (logical address, tag, and optional cache unit index) of the entry to be filled into the cache queue according to the write command, and writes the generated content into the entry at the end of the cache queue through the cache query unit 230, and writes the data corresponding to the write command into the cache unit corresponding to the entry at the end of the queue. Further, if the tag field of the entry at the end of the cache queue indicates that the cache unit corresponding to the entry does not accommodate the complete data of the logical address space corresponding to the entry, a signal is provided to the processor 210. The processor 210 merges the entry at the end of the cache queue.

[0080] Optionally, the cache system also includes a cache read unit 270. The cache read unit 270 is coupled to the processor 210, the cache query unit, and the cache management unit 240. The cache read unit 270 receives a read command provided by the processor 210. The cache read unit 270 provides the cache query unit 230 with a logical address of the read command to identify whether the logical address of the read command hits an entry in the cache queue. If the cache query unit 230 indicates to the cache read unit 270 that the logical address of the read command hits an entry in the cache queue, the cache read unit accesses the cache unit indicated by the hit cache entry to obtain the data accessed by the read command. If the cache query unit 230 indicates to the cache read unit 270 that the logical address of the read command does not hit any entry in the cache queue, the cache read unit 270 indicates a miss to the processor 210, and the processor 210 continues to process the read command.

[0081] The cache queue has a limited number of entries. In one example, if the cache queue is filled, the cache queue is flushed to write the data contained in the cache unit corresponding to one, multiple or all entries of the cache queue to the NVM chip of the storage device. Further, in order to flush, if the tag field of the entry of one or more cache queues indicates that the cache unit corresponding to the entry does not contain the complete data of the logical address space corresponding to the entry, a signal is provided to the processor 210 so that the processor 210 performs a merge operation on the cache unit. After the merge operation is completed, the cache unit is flushed again. The entry of the cache queue corresponding to the cache unit being flushed is released and can be written to a new logical address (tag), tag and / or index.

[0082] Furthermore, in order to implement flushing of the cache queue, the number of cache units to be merged is obtained according to the merge counter 245. Each time a cache unit is merged, the merge counter 245 is decremented. After the merge counter 245 is decremented to 0, there are no cache units to be merged in the cache queue, and then the data of the cache units corresponding to each entry of the cache queue are written into the NVM chip.

[0083] Optionally, the flushing of the cache queue is controlled by the processor 210. During the flushing of the cache queue, the cache write unit 220 and / or the cache query unit suspends processing of write commands, and the cache read unit 270 suspends processing of read commands.

[0084] Figure 3 A flowchart of a method implemented by a cache system according to an embodiment of the present application is shown.

[0085] The cache system obtains a write command (310), obtains a logical address accessed by the write command, and determines whether the logical address accessed by the write command hits an entry in the cache queue (320), for example, by comparing the logical address accessed by the write command with the logical addresses of each entry in the cache queue to determine whether it hits.

[0086] If the logical address accessed by the write command hits an entry in the cache queue, the data to be written to the storage device by the write command is written into the cache unit corresponding to the hit entry in the cache queue, and the hit cache unit is updated (330). Optionally, the tag field of the hit entry is also updated.

[0087] If the logical address accessed by the write command does not hit an entry in the cache queue, an entry is added to the cache queue according to the write command (340). The added entry records, for example, the logical address of the write command, a flag indicating whether the cache unit corresponding to the entry accommodates complete data in the logical address space corresponding to the entry, and / or an index indicating the cache unit.

[0088] Optionally, in response to writing data to the cache unit corresponding to the entry of the cache queue, if the tag of the entry indicates that the corresponding cache unit does not accommodate the complete data of the logical address space corresponding to the entry, the merge counter 245 is incremented (see also Figure 2 ) and implement the merging of the cache units. Still optionally, the merging of the cache units is postponed and implemented when the cache queue is flushed.

[0089] It is determined whether the cache queue is full (350). If the cache queue is full (no free entries), the cache queue is also flushed. To flush the cache queue, the cache queue is also checked to see if there are cache units to be merged (360). For example, the merge counter 245 (see also Figure 2 ) indicates the number of cache units to be merged. A merge operation is performed on the cache units to be merged (370). For example, a signal is provided to a processor coupled to the cache system, and the processor obtains the logical address of the cache queue entry record indicating the cache unit to be merged, reads data from the NVM chip of the storage device according to the logical address, and then writes it into the cache unit to be merged.

[0090] And the cache unit corresponding to each entry of the cache queue is flashed, and the data stored in the cache unit is written into the NVM chip (380).

[0091] Figure 4A and 4B A schematic diagram of using a cache system according to an embodiment of the present application is shown.

[0092] See also Figure 4A, the cache queue includes 12 entries, 11 of which have been filled, each entry has a number and a logical address (LBA) is recorded. According to the number of the entry, the cache unit corresponding to the entry can be indexed. The value of the merge counter of the cache management unit is 0, indicating that there is no cache unit in the cache queue that needs to be merged. It can be understood that the number of the entry can be implicit without using a storage unit to store the number of the entry.

[0093] As an example, the cache write unit receives a write command to access a logical address (LBA=11). The logical address of the write command does not hit any entry in the cache queue, and the free entries in the cache queue are filled according to the write command.

[0094] See also Figure 4B , showing the cache queue after being filled. The filled entry is entry numbered 11, which records the logical address (LBA=11) accessed by the write command. And the merge counter of the cache queue is still 0. It can be understood that entry numbered 11 is the current tail of the cache queue. The cache management unit records the positions of the head and tail of the cache queue.

[0095] Furthermore, since the cache queue is full (no free entries), a flush operation is performed on the cache queue to write the data stored in the cache unit corresponding to each entry of the cache queue into the NVM chip of the storage device.

[0096] Figure 5A-5B A schematic diagram of using a cache system according to another embodiment of the present application is shown.

[0097] See also Figure 5A , the cache queue includes 9 entries, 7 of which have been filled, and each entry records the logical address (LBA), tag and index. The index of the entry indicates the cache unit corresponding to the entry. The value of the merge counter of the cache management unit is 2, indicating that there are 2 cache units in the cache queue that need to be merged. "Tag (P)" indicates the entries (520, 540) corresponding to the cache units to be merged, whose logical addresses are LBA=2 and LBA=4 respectively.

[0098] The cache write unit receives a write command instructing to write data to the logical address (LBA=4), and the write command does not write data to the complete logical address space corresponding to the cache entry recording the logical address (LBA=4).

[0099] The cache query unit queries the cache queue according to the logical address (LBA=4) and finds that it hits entry 540. Therefore, the cache write unit writes the data corresponding to the write command into the cache unit indicated by the index of entry 540 through the cache management unit.

[0100] The cache management unit identifies, based on the data already existing in the cache unit corresponding to entry 540 and the data written into the cache unit according to the write command, that the cache unit has not yet recorded the data of the complete logical address space of its corresponding entry, thereby setting the mark of entry 540 to "Mark (P)".

[0101] The cache system instructs the processor to merge the cache unit corresponding to entry 540, and reads the data of the address space corresponding to LBA=4 that is missing in the cache unit of entry 540 from the NVM chip. Figure 5B After the merge, the tag of entry 540 is modified from "Tag (P)" to "Tag" to indicate that it no longer needs to be merged. And accordingly, the merge counter is decremented to 1.

[0102] In another example according to the present application, in response to identifying that a write command hits entry 540 of the cache queue, the data portion of the address space of the logical address LBA=4 corresponding to the write command and the cache unit of the entry is further identified, and only the data portion of the address space of the logical address LBA=4 that is neither corresponding to the write command nor the cache unit of the entry is read from the NVM chip. For example, the address space of LBA=4 is divided into 4 parts, and the cache unit corresponding to the entry has recorded the first part. The write command is to write data to the second part, so the data of the third and fourth parts are read from the NVM chip and filled into the cache unit, and the data corresponding to the write command is written into the cache unit. Since the cache unit has recorded the complete data of the address space of the logical address (LBA=4) at this time, the "mark (P)" of the entry 540 is modified to "mark", and the merge counter is decremented to 1.

[0103] In another example according to the present application, a write command hits entry 540 of the cache queue, and the address space of the logical address LBA=4 is divided into 4 parts, and the first part has been recorded in the cache unit corresponding to the entry. The write command is to write data to the second part of the address space of the logical address LBA=4. The cache system writes the data corresponding to the write command into the cache unit. And it is recognized that the cache unit still has not recorded the complete data of the address space of the logical address (LBA=4), so the mark of entry 540 is still "mark (P)", and the merge counter is not updated. If the data corresponding to the write command is written to the cache unit, and the cache unit records the complete data of the address space of the logical address (LBA=4), the mark of entry 540 is modified to "mark", and the merge counter is decremented.

[0104] Fig. 6A and Figure 6B A schematic diagram of using a cache system according to another embodiment of the present application is shown.

[0105] See also Fig. 6A , the cache queue includes 9 entries, 7 of which are filled, and each entry records the logical address (LBA), tag and index. The value of the merge counter of the cache management unit is 2. "Tag (P)" indicates the entry of the corresponding cache unit to be merged.

[0106] The cache write unit receives a write command instructing to write data to the logical address (LBA=100), and the write command writes data to the complete logical address space of the logical address (LBA=100).

[0107] The cache query unit queries the cache queue according to the logical address (LBA=100) and finds that it does not hit any entry. In response, the cache write unit adds a new entry to the cache queue.

[0108] See also Figure 6B , shows the cache queue after being filled. The entry filled is the entry of the logical address (LBA=100). And the merge counter of the cache queue is still 2.

[0109] Figure 7A-7C A schematic diagram of using a cache system according to another embodiment of the present application is shown.

[0110] See also Fig. 7A ,The cache queue includes 12 entries, 11 of which are filled. Each entry records the logical address (LBA), tag and index. The value of the merge counter of the cache management unit is 3.

[0111] The cache write unit receives a write command instructing to write data to the logical address (LBA=120), and the write command writes data to the complete logical address space of the logical address (LBA=120).

[0112] The cache query unit queries the cache queue according to the logical address (LBA=120) and finds that it does not hit any entry. In response, the cache write unit adds a new entry to the cache queue.

[0113] See also Figure 7B , shows the cache queue after being filled. The entry filled is the entry of the logical address (LBA=120). And the merge counter of the cache queue is still 3.

[0114] Since the cache queue is full (no free entries), a flush operation is performed on the cache queue. Before the flush operation is performed, since the value of the merge counter is greater than 0, entries in the cache queue whose cache units do not contain complete data of the corresponding logical address space are merged.

[0115] See also Figure 7B, merge the entries of logical address (LBA=2), logical address (LBA=4) and logical address (LBA=8). According to the logical addresses of the entries, data is read from the NVM chip, and the read data is merged with the data in the cache unit corresponding to the entry.

[0116] In response to the merge being completed, the entry's flag is updated and the merge counter is decremented. Figure 7C , the merge counter is 0, indicating that the merge of all three entries has been completed.

[0117] Since the cache queue is full (no free entries), a flush operation is performed on the cache queue to write the data stored in the cache unit corresponding to each entry of the cache queue into the NVM chip of the storage device.

[0118] Although the present application is described with reference to examples, this is for illustrative purposes only and is not intended to limit the present application, and changes, additions and / or deletions to the embodiments may be made without departing from the scope of the present application.

[0119] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A control component, characterized in that: It includes a processor, a cache write unit, a cache management unit and a cache query unit; The processor provides a write command to the cache write unit; The cache write unit obtains a logical address from the write command and provides the logical address to the cache query unit; The cache query unit queries whether the logical address provided by the cache write unit hits an entry in the cache queue; In response to the cache query unit indicating that the logical address hits the first entry of the cache queue, the cache write unit writes the data to be written by the write command into the cache unit corresponding to the first entry; In response to the cache query unit indicating that the logical address does not hit any entry in the cache queue, the cache write unit adds the logical address and tag of the write command to the entry at the end of the cache queue through the cache management unit.

2. The control unit according to claim 1, characterized in that Also includes: The cache write unit generates a tag according to whether the logical address accessed by the write command covers the logical address space corresponding to the entry of the cache queue.

3. A control unit according to claim 1 or 2, characterized in that in, In response to writing the data to be written by the write command into the cache unit corresponding to the first entry, the cache management unit identifies whether the cache unit of the first entry records the complete data of the logical address space based on the data already existing in the cache unit corresponding to the first entry and the data written according to the write command.

4. The control unit according to claim 3, characterized in that in, In response to the cache unit of the first entry still not recording the complete data of the logical address space corresponding to the first entry, the mark state of the first entry is not changed; or In response to the cache unit of the first entry recording the complete data of the logical address space corresponding to the first entry, the mark state of the first entry is changed to complete the merging of the cache units of the first entry.

5. The control unit according to claim 4, characterized in that In response to the cache unit of the first entry still not recording complete data of the logical address space corresponding to the first entry, providing a signal to the processor; The processor obtains the data corresponding to the logical address of the first entry and writes it into the cache unit corresponding to the entry, so that the cache unit of the entry accommodates the complete data of the logical address space corresponding to the entry, and the processor completes the merging of the cache units.

6. The control unit according to claim 5, characterized in that The processor obtains data corresponding to the logical address of the first entry and writes the data into a cache unit corresponding to the entry, including: The processor reads the remaining data of the logical address space corresponding to the first entry from the NVM chip, and fills it into the cache unit of the first entry, so that the cache unit of the first entry accommodates the complete data of the logical address space corresponding to the entry, thereby realizing the merging of the cache units of the first entry.

7. A control unit according to claim 1 or 2, characterized in that In response to when the cache queue is flushed or the cache queue is filled, the mark of the first entry indicates that the first entry cache unit has not recorded the complete data of the logical address space corresponding to the first entry, and a signal is provided to the processor; the processor reads the remaining data of the logical address space corresponding to the first entry from the NVM chip and fills it into the cache unit of the first entry, thereby realizing the merging of the cache units of the first entry.

8. The control unit according to claim 7, characterized in that In response to flushing the cache queue or filling up the cache queue, if it is checked that there are cache units to be merged in the cache queue, all cache units to be merged are merged and then the data stored in the cache units are written into the non-volatile memory.

9. The control unit according to claim 7, characterized in that In response to the number of entries filled in the cache queue being greater than a first threshold or the number of entries not filled being less than a second threshold, the cache management unit provides a second signal to the processor; the processor performs a flush operation on the cache queue in response to receiving the second signal.

10. The control unit according to claim 1 or 2, characterized in that in, In response to the cache queue having cache units to be merged, the processor merges the cache units to be merged, and then writes the data stored in the cache units into the non-volatile memory.

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