Fast FPGA Interconnection and Splicing for Wire Highways

Abstract

The present disclosure relates to a field programmable gate array (FPGA) having non-highway wire segments for connection to logic blocks and highway wire segments in a highway network of highways. Each highway has multiple sets of highway wire segments connected in series. Each series connection is through a multiplexer. The multiplexer of the highway has an entrance ramp, an exit ramp, or both, for programmable connection to the wire segments according to the programming of the FPGA.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority of U.S. Provisional Application No. 63 / 144,882, filed on Feb. 2, 2021, entitled "Fast FPGA Interconnect Stitching for Wire Highways", which is hereby incorporated by reference in its entirety. Technical Field

[0003] The technical field of the present disclosure relates to field - programmable gate arrays (FPGAs), and more particularly, to routing and programmable interconnects in FPGAs. Background Art

[0004] Modern field - programmable gate arrays (FPGAs) contain various wires that can be connected together with static random - access memory (SRAM) programmable multiplexers (also referred to as multiplexers or muxes). The multiplexers typically select from among multiplexer inputs and drive one or more multiplexer outputs. A standard feature of an FPGA is that the various connections of these wires can be programmed according to the FPGA programming, for example, by an FPGA programmer (e.g., a CAD or computer - aided design system) representing a design in a design database. The lengths of these wires typically vary from spanning a single logic block to spanning significant portions of the chip. Short wires are used for local connections, while long wires are used for faster connections over longer distances. Long wires typically use metal layers with lower resistance to make them faster and are also often buffered to avoid a quadratic increase in delay with length (e.g., since wire capacitance and resistance each increase linearly with length, resulting in a quadratic increase in RC time delay).

[0005] FPGA architects must make trade - offs when deciding on the mix of wire - segment lengths in an FPGA. Shorter wires are more flexible because they can be more easily combined to implement any logic block on the chip. Longer wires offer the potential for faster paths over longer distances, but they are expensive and make it more difficult to use CAD tools effectively. Summary of the Invention

[0006] Embodiments of field - programmable gate arrays (FPGAs), wire highways, wire - highway networks, off - ramps and on - ramps of wire highways, structures, functions, and other aspects of multiplexers for connecting wire - highway wire segments and non - wire - highway wire segments, programmable connections, FPGA programming, computer - aided design (CAD) systems, CAD tools, and various devices and related methods are described herein.

[0007] One embodiment is a field programmable gate array. The FPGA includes wire segments. The wire segments include non-highway wire segments and highway wire segments. The non-highway wire segments are for connection to logic blocks. The highway wire segments are in a highway network of highways. Each highway includes multiple groups of highway wire segments connected in series. Each series connection is through a multiplexer. At least one multiplexer of each highway includes an entrance ramp. The entrance ramp is for connecting and selecting another wire segment according to the programming of the FPGA to drive the highway wire segments entering the highway. At least one multiplexer of each highway includes an exit ramp. The exit ramp is for connecting the highway wire segments to non-highway wire segments according to the programming of the FPGA.

[0008] One embodiment is a method of operating a field programmable gate array. The method includes programming an FPGA having wire segments including non-highway wire segments and highway wire segments to define a first function of the FPGA. The non-highway wire segments are for connection to logic blocks. The highway wire segments are in a highway network of highways. Each highway includes multiple groups of highway wire segments connected in series. Each series connection is through a multiplexer. The method includes programming an entrance ramp of at least one multiplexer of a highway for connecting and selecting another wire segment to drive the highway wire segments entering the highway to define a second function of the FPGA. The method includes programming an exit ramp of at least one multiplexer of a highway for connecting the highway wire segments to non-highway wire segments to define a third function of the FPGA.

[0009] One embodiment is a tangible, non-transitory, computer-readable medium having instructions thereon. The instructions, when run by a processor, cause the processor to program an FPGA to define a first function of the FPGA. The FPGA has multiple wire segments including non-highway wire segments and highway wire segments. The non-highway wire segments are for connection to logic blocks. The highway wire segments are in a highway network of highways. Each highway includes multiple groups of highway wire segments connected in series. Each series connection is through a multiplexer. The instructions cause the processor to program an entrance ramp of at least one multiplexer of a highway for connecting and selecting another wire segment to drive the highway wire segments entering the highway to define a second function of the FPGA. The instructions cause the processor to program an exit ramp of at least one multiplexer of a highway for connecting the highway wire segments to non-highway wire segments to define a third function of the FPGA. Description of the Drawings

[0010] The embodiments described herein will be more fully understood from the following detailed description and the accompanying drawings of various embodiments of the invention. However, these embodiments should not be considered as limiting the invention to these specific embodiments, but are merely for illustration and understanding.

[0011] Figure 1 Shows an entrance ramp to the ingress wire segment freeway in an embodiment.

[0012] Figure 2 Shows an exit ramp from the egress wire segment freeway in an embodiment.

[0013] Figure 3 Shows a freeway network with example entrance and exit ramps in an embodiment.

[0014] Figure 4A Shows a first type of programmable connection from a freeway wire segment of one wire segment freeway to a freeway wire segment of another wire segment freeway.

[0015] Figure 4B Shows a second type of programmable connection from a freeway wire segment of one wire segment freeway to a freeway wire segment of another wire segment freeway.

[0016] Figure 5A Shows a first type of programmable exit ramp connection.

[0017] Figure 5B Shows a second type of programmable exit ramp connection.

[0018] Figure 5C Shows a third type of programmable exit ramp connection.

[0019] Figure 5D Shows a fourth type of programmable exit ramp connection.

[0020] Figure 5E Shows a fifth type of programmable exit ramp connection.

[0021] Figure 6 Shows a CAD system for programming an FPGA using a design database.

[0022] Figure 7 Is a flowchart of a method of operating an FPGA, which can be practiced using various embodiments of freeways, freeway networks, entrance ramps, exit ramps, and programmable connections as described herein. Detailed Description

[0023] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail in order to avoid obscuring the present invention.

[0024] The techniques disclosed herein create a network of wire segments stitched together with limited flexibility but very low latency. Such a network of wire segments is referred to as a "highway", and may also be referred to as a wire highway or wire segment highway. Multiple such highways are referred to as a highway network or a highway wire network. There are different types of wire segments. Highway wire segments are used for highways, and non-highway wire segments are used for non-highways. In one embodiment, the highway wire network is stitched together so effectively that long wires are not needed - short wires stitched together are almost as fast and much more flexible. Techniques for stitching fast short wires together on an FPGA to replace the use of traditional long wire networks are disclosed.

[0025] In one embodiment, the wire segments that are part of a highway network are only connected to other wire segments of the same network (e.g., highway wire segments are connected to other highway segments along the highway through multiplexers), and also each wire segment has a very limited number of on-ramps and off-ramps that allow entry into and exit from the highway network (i.e., the highways of the highway network, respectively). That is, the on-ramps allow signals to enter the highway network, e.g., from a non-highway circuit, and the off-ramps allow signals to leave the highway network, e.g., into a non-highway circuit.

[0026] In one embodiment, an exemplary highway network is implemented such that each wire segment is driven by a 4:1 multiplexer implemented as a "flat" multiplexer, which in practice may have a delay very similar to that of a simple buffer. In one embodiment, the 4:1 multiplexer driving an eastward highway wire segment is driven by wire segments of the same type from the west, north, and south. Additionally, the 4:1 multiplexer is driven by a single wire from the west, which is from a different type of additional wire. Such an additional wire connection is referred to as an "on-ramp" and can be programmed according to the various connected FPGA programming. It should be understood that these compass directions are relative descriptions in context and should not be confused with absolute directions relative to the earth's magnetic direction or other locations.

[0027] In one embodiment, each wire segment in the highway network is connected to three other wire segments from the highway network and one exit ramp, and is not directly connected to any logic block. This additional wire connection is called an "exit ramp" and can be programmed according to various connected FPGA programming. Having a limited number of exit ramps reduces the load on the wires and helps make it faster.

[0028] The overall effect is limited flexibility in entering or leaving the highway network. Once in the high-speed network, the connection speed is very fast, enabling it to get very close to the target logic block while remaining on the fast network. In contrast, the typical long wire network on an FPGA is not as flexible.

[0029] Figure 1 An embodiment showing the connections and how to minimize the connections to each highway wire segment is shown. Referring to Figure 1 , the 4:1 multiplexer driving each highway wire segment is driven only by three highway wire segments plus one entry ramp from a different wire segment network. In the embodiment shown, wire highway 110 goes east, and the incoming highway wire segments include highway wire segment 102 from the north, highway wire segment 104 from the south, and highway wire segment 106 from the west. The non-highway wire segment 108 connected through the programmable connection of the entry ramp comes from the west.

[0030] In Figure 1 , the multiplexer 112 is shown driving all the highway wire segments of wire highway 110 and can be composed of multiple multiplexers each driving one of the highway wire segments. The other inputs of the other multiplexers are not shown but are easily designed. Generally, the entry ramp includes a programmable connection to the input terminal of the multiplexer. Various embodiments of the entry ramp further include electrical or electronic circuits or components that are easily designed and support design-specific in an appropriate technology, such as parts of the implementation of the multiplexer in an FPGA, and various geometries in the layers of an integrated circuit. In various embodiments, the multiplexer selects from among the multiplexer inputs to drive the highway wire segment as the output of the multiplexer. Specifically, in the embodiment shown in Figure 1 , the multiplexer 112 in the wire highway (e.g., going east) selects from among the three highway wire segments 102, 104, 106 and the programmable connection (e.g., according to FPGA programming) of the entry ramp connecting to the non-highway wire segment 108, all as inputs to the multiplexer 112, to drive one (or in a variant, multiple) of the highway wire segments in wire highway 110 as the output of the multiplexer 112.

[0031] Figure 2Shows an example of loading on a highway wire segment and how to minimize each highway wire segment. Refer to Figure 2 , each highway wire segment is only connected to three other highway wire segments and an exit ramp, and the exit ramp is connected to a different wire segment network. In the illustrated embodiment, the wire highway 202 is eastward and is connected to the multiplexer 212 that drives the northward highway wire segment 204, the multiplexer 214 that drives the eastward highway wire segment 206, the multiplexer 218 that drives the southward highway wire segment 210, and the multiplexer 216. The multiplexer 216 is programmably connected (e.g., programming the connection according to the FPGA programming) to the eastward non-highway wire segment 208 via the exit ramp and drives the non-highway wire segment 208. In various embodiments, the programmable connection that is part of the exit ramp can be implemented as a programmable connection from a highway wire to a non-highway wire, a programmable connection from a highway wire to the multiplexer 216 (or other wire or active circuit component in a variant), a hardwired connection from a highway wire to the multiplexer 216 of a hard structure, and a programmable output connection from the multiplexer 216 to the non-highway wire segment 208 or other wire segments in a variant, or other programmable connections according to the FPGA programming.

[0032] In Figure 2 , each of the multiplexers 212, 214, 216, 218 is shown as driving a single wire segment, e.g., the wire segments 204, 206, 208, 210, but can be composed of multiple multiplexers. In various embodiments, each multiplexer can be used to drive one of various highway wire segments or one of various non-highway wire segments through hardwiring or programmable connections. The other outputs of such other multiplexers are not shown but are easily designed. Generally, the exit ramp includes a programmable connection to another component that is not part of the highway to which the exit ramp belongs and can be used for such programmable connections. In various embodiments, the component that can be used for the programmable connection of the exit ramp of the multiplexer is a non-highway wire segment, which in turn can be programmably connected to additional circuits according to the FPGA programming. Further refer to Figures 4A to 5E to describe additional embodiments that include programmable connections to highway wires and non-highway wires. Various embodiments of the exit ramp further include electrical or electronic circuits or components that are easily designed and support design-specific in appropriate technologies, such as parts or all of the implementation of the multiplexer (e.g., the multiplexer 216) in an FPGA, and various geometries in the layers of an integrated circuit. In various embodiments, the multiplexer selects from among the multiplexer inputs of various highway wire segments including the wire highway to drive the multiplexer output that is programmably connected to the non-highway wire segment. Specifically, inFigure 2 In the illustrated embodiment, the multiplexer 216 for the exit ramp of the wire highway 202 (e.g., eastward) selects from among the highway wire segments of the wire highway 202 as inputs to the multiplexer 216 to drive one (or in a variant, multiple) of the non-highway wires 208 as the output of the multiplexer 216.

[0033] Figure 3 A highway network 300 with example entrance ramps and exit ramps in an embodiment is shown. There are multiple highways in different directions, such as the north-south highway 306, the south-north highway 308, the west-east highway 302, and the east-west highway 304. Each wire segment highway or wire highway 302, 304, 306, 308 has highway wire segments and multiplexers, such as multiplexers 310, 312, 314, 316, 318, 320, and reference may also be made to Figure 1 and Figure 2 . In each highway, multiple sets of highway wire segments are connected in series, with each series connection passing through a multiplexer. That is, a highway consists of multiple sets of highway wire segments and multiplexers, where a given set of highway wire segments is connected to the next set of highway wire segments through a multiplexer, and this structure repeats along the highway for successive sets of highway wire segments. A highway, more specifically the highway wire segments of the highway, can be connected to a logic block (not shown but well-known and understood) through an exit ramp and an entrance ramp (reference Figure 1 , Figure 2 and Figures 5B to 5E ). In a variant of the highway network 300, there can be more highways, fewer highways, separate highways in both directions (e.g., see Figure 2 , which shows the northward highway wire segment 204 and the southward highway wire segment 210), highway intersections with interconnections between highways (see Figure 1 , Figure 2 , Figure 4A , Figure 4B , Figure 5Aand its variants), highway intersections without interconnections (similar to overpasses or underpasses), other directions of the highway (e.g., it can be diagonal, other angles, zigzag or staircase steps), circular highways, star configurations, etc. Some of the multiplexers 312, 320, 324, 326 have exit ramps, some of the multiplexers 314, 320, 322, 328 have entrance ramps, some of the multiplexers 320 have both entrance ramps and exit ramps, and these are programmable according to FPGA programming (i.e., have programmable connections), where the variants are easy to design. For example, in one embodiment, all the multiplexers of all the highways in the highway network can have individually programmable connections for the entrance ramps and exit ramps according to FPGA programming, while in other embodiments, some specific multiplexers (i.e., subsets) of the multiplexers in the FPGA have this ability for entrance ramps, exit ramps, or both. Each embodiment has a design trade-off in terms of the versatility and connections (hardwired and programmable connections) of the multiplexers, the load on a given highway, and the resulting signal propagation speed and delay.

[0034] Figure 4A Shows a first type of programmable connection from a highway wire segment 401 of a wire segment highway 402 to a highway wire segment 403 of another wire segment highway 404. The multiplexer 406 belonging to the wire segment highway 402 has an exit ramp that is programmably connected to the output 412 of the multiplexer 406. The multiplexer 408 of the wire segment highway 404 has an entrance ramp that is programmably connected to the input 414 of the multiplexer 408. The FPGA programming programs these two programmable connections as a programmable connection 410 to connect to each other, such that the first type of programmable connection 410 directly connects the exit ramp of the multiplexer 406 of one highway 402 to the entrance ramp of the multiplexer 408 of another highway 404. In various embodiments, there may be various directions to connect the highway wire segments of various highways in various relative directions.

[0035] Figure 4BShows a second type of programmable connection from a highway wire segment 401 of a wire segment highway 402 to a highway wire segment 403 of another wire segment highway 404. The multiplexer 406 belonging to the wire segment highway 402 has an exit ramp that is programmably connected 416 to the output 412 of the multiplexer 406. The multiplexer 408 of the wire segment highway 404 has an entrance ramp that is programmably connected 420 to the input 414 of the multiplexer 408. The non-highway wire segment 418 can be used for the programmable connection. FPGA programming programs these two programmable connections 416, 420 to connect to the non-highway wire segment 418 and thus connect to each other through the non-highway wire segment 418, so that the second type of programmable connection connects the exit ramp of the multiplexer 406 of one highway 402 to the entrance ramp of the multiplexer 408 of another highway 404 through the non-highway wire segment 418. In various embodiments, there may be various directions to connect the highway wire segments of various highways in various relative directions. Refer to Figure 4A and Figure 4B , these embodiments and their variants apply to Figures 1 to 3 and its variants.

[0036] Figure 5A Shows a first type of programmable exit ramp connection 518. This programmable connection 518 is used to connect a highway wire segment 502 of a highway 508 in one direction 506 to another highway wire segment 514 of another highway 510 in the same direction 516 (i.e., parallel or straight, opposite to a perpendicular or reverse connection). In one embodiment, the programmable connection 518 connects the output 520 of the multiplexer 504 of the highway 508 to the input 522 of the multiplexer 512 of another highway 510. Thus, the programmable connection 518 connects the highway wire segment 502 to the highway wire segment 514 through the exit ramp of the multiplexer 504 and the entrance ramp of the multiplexer 512. The multiplexer 504 has the high-speed wire segment 502 as the input of the multiplexer 504, and the multiplexer 512 drives the high-speed wire segment 514 as the output of the multiplexer 512.

[0037] Figure 5BShows a second type of programmable off-ramp connection 524. This programmable connection 524 is used to connect a highway wire segment 502 of a highway 508 in one direction 506 at a right angle to a non-highway wire segment 526 in direction 528, which is perpendicular to the direction 506 of the highway 508. In one embodiment, the programmable connection 524 connects the output 520 of the multiplexer 504 of the highway 508 to the non-highway wire segment 526 available for such connection. Thus, the programmable connection 524 connects the highway wire segment 502 to the non-highway wire segment 526 through the off-ramp of the multiplexer 504, and the multiplexer 504 drives the non-highway wire segment 526 as the output of the multiplexer 504.

[0038] Figure 5C Shows a third type of programmable off-ramp connection 530. This programmable connection 530 is used to connect a highway wire segment 502 of a highway 508 in one direction 506 at a right angle to a non-highway wire segment 532 in direction 534, which is perpendicular to the direction 506 of the highway 508 and opposite to the direction 528 applied to Figure 5B In one embodiment, the programmable connection 530 connects the output 520 of the multiplexer 504 of the highway 508 to the non-highway wire segment 532 available for such connection. Thus, the programmable connection 530 connects the highway wire segment 502 to the non-highway wire segment 532 through the off-ramp of the multiplexer 504, and the multiplexer 504 drives the non-highway wire segment 532 as the output of the multiplexer 504.

[0039] Figure 5D Shows a fourth type of programmable off-ramp connection 536. This programmable connection 536 is used to connect a highway wire segment 502 of a highway 508 in one direction 506 to a non-highway wire segment 538 in direction 540, which is the same as (i.e., parallel to) the direction 506 of the highway 508. In one embodiment, the programmable connection 536 connects the output 520 of the multiplexer 504 of the highway 508 to the non-highway wire segment 538 available for such connection. Thus, the programmable connection 536 connects the highway wire segment 502 to the non-highway wire segment 538 through the off-ramp of the multiplexer 504, and the multiplexer 504 drives the non-highway wire segment 538 as the output of the multiplexer 504.

[0040] Figure 5EShows a fifth type of programmable exit ramp connection 542. This programmable connection 542 is used to reversely connect a highway wire segment 502 of a highway 508 in one direction 506 to a non-highway wire segment 544 in the opposite direction 546. In one embodiment, the programmable connection 542 connects the output 520 of the multiplexer 504 of the highway 508 to the non-highway wire segment 544 available for such connection. Thus, the programmable connection 542 connects the highway wire segment 502 to the non-highway wire segment 544 through the exit ramp of the multiplexer 504, and the multiplexer 504 drives the non-highway wire segment 544 as the output of the multiplexer 504.

[0041] Referring Figures 5A to 5E , these embodiments and their variations are applicable to Figures 1 to 3 and their variations.

[0042] Figure 6 Shows a CAD system 602 for programming an FPGA 612 using a design database 610. In various embodiments, the FPGA 612 has various features described above with reference to Figures 1 to 5E including programmable connections of other FPGAs for defining the functions of the programmed FPGA (e.g., programmable logic, programmable circuits, I / O), and the programmable connections of the above-described highways for further defining the functions of the programmed FPGA. In an operating scenario, a user 608 provides or develops a design database 610 representing a design to be implemented in the programmed FPGA 612. The development of the design database 610 can be completed using CAD tools 604 on the CAD system 602 or elsewhere and importing the design database 610 into the CAD system 602. Using an unprogrammed FPGA 612 coupled to the CAD system 602, such as by inserting the FPGA into a programming socket, the CAD system 602 continues to program the FPGA 612 according to the design database 610. The defined functions are installed into the FPGA 612 and then ready for operation, e.g., in the test verification of the CAD system 602, in a test fixture on a tester, or installed in a manufactured product. The operation of the FPGA 612 includes the FPGA 612 driving signals to, into, and out of the highway network and into all circuits programmed according to the FPGA programming and the design functions of the programmed FPGA 612 (e.g., all defined programmable connections).

[0043] Figure 7 Is a flowchart of a method for operating an FPGA, which can be practiced using various embodiments of highways, highway networks, entrance ramps, exit ramps, and programmable connections as described herein. The method can be embodied in instructions in a tangible, non-transitory, computer-readable medium and run by a processor.

[0044] In operation 702, the processor programs an FPGA having highway wire segments and non-highway wire segments to define a first function of the FPGA. This function can be captured in a design database that represents a circuit or system design to be implemented in the programmed FPGA.

[0045] In operation 704, the processor programs the entry ramp of the FPGA to define a second function of the FPGA. This function and programming include connections for the entry ramp.

[0046] In operation 706, the processor programs the exit ramp of the FPGA to define a third function of the FPGA. This function and programming include connections for the exit ramp.

[0047] In operation 708, the FPGA is operated in accordance with the first, second, and third functions. The operation of the FPGA can include verification, testing, or full-functional operation of the programmed FPGA in the system. It should be understood that operations 702, 704, 706 can be performed or combined in various orders, and the entire functionality of the programmed FPGA is understood to be a combination of the first, second, and third functions, each of which covers a portion of the entire functionality.

[0048] Some portions of the detailed descriptions above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, considered to be a self-consistent sequence of steps leading to a desired result. These steps are those requiring physical manipulation of physical quantities. Although not necessarily, these quantities typically take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. Sometimes, for the sake of generality, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0049] However, it should be borne in mind that all such and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless explicitly stated otherwise from the following discussion, it should be understood that throughout the description, discussions using terms such as "processing" or "computing" or "computing out" or "determining" or "displaying" refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system registers and memory into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage, transmission, or display devices.

[0050] The present invention also relates to an apparatus for performing the operations herein. The apparatus can be specially constructed for the required purposes or it can comprise a general purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

[0051] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The structure required for various of these systems will appear in the description below. In addition, the present invention has not been described in reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the present invention as described herein.

[0052] Machine-readable media includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media includes read-only memory ("ROM"); random access memory ("RAM"); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.); and the like.

[0053] Although many changes and modifications of the present invention will no doubt become apparent to those of ordinary skill in the art after reading the above description, it should be understood that any particular embodiment shown and described by way of illustration is not to be considered limiting. Thus, reference to the details of the various embodiments is not intended to limit the scope of the claims, which themselves recite only those features regarded as essential to the invention.

Claims

1. A field programmable gate array (FPGA), comprising: A plurality of wire segments, including non-highway wire segments for connecting to logic blocks and highway wire segments in a highway network of a highway; Each highway includes a plurality of groups of continuously connected highway wire segments, and each continuous connection is through a multiplexer; At least one multiplexer of each highway includes an entrance ramp for connecting and selecting another wire segment according to the programming connection of the FPGA to drive the highway wire segment entering the highway; And At least one multiplexer of each highway includes an exit ramp for connecting the highway wire segment to a non-highway wire segment according to the programming of the FPGA; Wherein, the plurality of exit ramps have programmable connections, and the programmable connections include a first type of exit ramp connection for connecting to another highway wire segment of another highway in a first direction, a second type of exit ramp connection for a first right-angle connection to another wire segment in a second direction, a third type of exit ramp connection for a second right-angle connection to another wire segment in a third direction opposite to the second direction, a fourth type of exit ramp connection for connecting to a non-highway wire segment in the first direction, and a fifth type of exit ramp connection for a reverse connection to a non-highway wire in a fifth direction opposite to the first direction.

2. The FPGA according to claim 1, wherein: Each exit ramp includes a multiplexer of the highway, and the multiplexer of the highway has the highway wire segment as an input and a programmable connection at the output of the multiplexer.

3. The FPGA according to claim 1, wherein: At least one multiplexer of each highway has a connection with a highway wire segment of another highway and a connection with a non-highway wire segment through a programmable connection that is an input of the multiplexer serving as the entrance ramp.

4. The FPGA according to claim 1, wherein: The highway wire of the first highway has a programmable connection with the highway wire of the second highway through a programmable connection from the exit ramp of the first highway to the entrance ramp of the second highway.

5. The FPGA according to claim 1, wherein: The highway wire of the first highway has a programmable connection with the highway wire of the second highway through a programmable connection of the exit ramp of the first highway, a non-highway wire, and the entrance ramp of the second highway.

6. A method of operating a field programmable gate array (FPGA), comprising: Programming an FPGA having a plurality of wire segments to define a first function of the FPGA, the plurality of wire segments including non-highway wire segments and highway wire segments, the non-highway wire segments for connecting to logic blocks, and the highway wire segments being in a highway network of a highway, each highway including a plurality of groups of continuously connected highway wire segments, and each continuous connection being through a multiplexer; Programming an entrance ramp of at least one multiplexer of a highway to define a second function of the FPGA, the entrance ramp for connecting and selecting another wire segment to drive the highway wire segment entering the highway; Programming an exit ramp of at least one multiplexer of a highway to define a third function of the FPGA, the exit ramp for connecting the highway wire segment to a non-highway wire segment; And Programming the plurality of exit ramps includes programming a first type of exit ramp connection for connecting to another highway wire segment of another highway along a first direction, programming a second type of exit ramp connection for making a first right-angle connection to another wire segment along a second direction, programming a third type of exit ramp connection for making a second right-angle connection to another wire segment along a third direction opposite to the second direction, programming a fourth type of exit ramp connection for connecting to a non-highway wire segment along the first direction, and programming a fifth type of exit ramp connection for making a reverse connection to a non-highway wire along a fifth direction opposite to the first direction.

7. The method of operating an FPGA according to claim 6, wherein: Programming the exit ramp includes programming the output connection of the multiplexer to connect to the non-highway wire segment.

8. The method of operating an FPGA according to claim 6, wherein: Programming the entrance ramp includes programming the input of the multiplexer to connect to the another wire segment, the another wire segment including a highway wire segment or a non-highway wire segment of another highway.

9. The method of operating an FPGA according to claim 6, further comprising: Programmatically connect the highway wire of the first highway to the highway wire of the second highway through the exit ramp of the first highway, wherein the exit ramp of the first highway has a programmable connection with the entrance ramp of the second highway.

10. The method of operating an FPGA according to claim 6, further comprising: Programmatically connect the highway wire of the first highway to the highway wire of the second highway through the programmable connection of the exit ramp of the first highway, the non-highway wire, and the entrance ramp of the second highway.

11. The method of operating an FPGA according to claim 6, further comprising: After all this programming, drive signals through the highway wire segments of the programmed FPGA.

12. A tangible, non-transitory, computer-readable medium having instructions thereon that, when executed by a processor, cause the processor to: Program an FPGA having multiple wire segments to define a first function of the FPGA, the multiple wire segments including non-highway wire segments and highway wire segments, the non-highway wire segments being for connection to logic blocks, the highway wire segments being in a highway network of a highway, each highway including multiple groups of consecutively connected highway wire segments, each consecutive connection being through a multiplexer; Program the entrance ramp of at least one multiplexer of the highway to define a second function of the FPGA, the entrance ramp being for connecting and selecting another wire segment to drive into the highway wire segment of the highway; Program the exit ramp of at least one multiplexer of the highway to define a third function of the FPGA, the exit ramp being for connecting the highway wire segment to the non-highway wire segment; And Programming the plurality of exit ramps includes programming a first type of exit ramp connection for connecting to another highway wire segment of another highway along a first direction, programming a second type of exit ramp connection for making a first right-angle connection to another wire segment along a second direction, programming a third type of exit ramp connection for making a second right-angle connection to another wire segment along a third direction opposite to the second direction, programming a fourth type of exit ramp connection for connecting to a non-highway wire segment along the first direction, and programming a fifth type of exit ramp connection for making a reverse connection to a non-highway wire along a fifth direction opposite to the first direction.

13. The computer-readable medium according to claim 12, wherein: Programming the exit ramp includes programming the output connection of the multiplexer of the highway to connect the highway wire segment to the non-highway wire segment.

14. The computer-readable medium according to claim 12, wherein: Programming the on-ramp includes programming the inputs of the multiplexer to connect to a highway wire segment or a non-highway wire segment of another highway.

15. The computer-readable medium according to claim 12, wherein the instructions further cause the processor to: Programmatically connect the highway wires of the first highway to the highway wires of the second highway through an exit ramp of the first highway, wherein the exit ramp of the first highway has a programmable connection to an entrance ramp of the second highway.

16. The computer-readable medium according to claim 12, wherein the instructions further cause the processor to: Programmatically connect the highway wires of the first highway to the highway wires of the second highway through a programmable connection of an exit ramp of the first highway, a non-highway wire, and an entrance ramp of the second highway.

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