Sensing-storage-computing integrated device, array and method based on composite dielectric gate structure

Abstract

The present invention discloses a sensing, storage and computing integrated device based on a composite dielectric gate structure, including a composite dielectric gate photosensitive detector and a composite dielectric gate transistor formed on the same P-type semiconductor substrate. The composite dielectric gate photosensitive detector is provided with a first bottom insulating dielectric layer, a first floating gate, a first top insulating dielectric layer and a first control gate in sequence above the substrate; the composite dielectric gate transistor is used to complete the calculation of the harmonic mean of the weight stored and the photosensitive photoelectrons, and is provided with a second bottom insulating dielectric layer, a second floating gate, a second top insulating dielectric layer and a second control gate in sequence above the substrate; the composite dielectric gate photosensitive detector and the composite dielectric gate transistor are provided with a source and a drain in the substrate, respectively. The device of the present invention can complete the calculation of the harmonic mean in the process of signal reading, and can be used to match the complex calculation of the subsequent image processing unit, reducing the computing power requirements and power consumption of the subsequent image processing.

Description

Technical Field

[0001] The present invention relates to a sensing-storage-computing integrated device, which is a new device integrating photosensitivity, storage and computing based on a composite dielectric grating structure. Background Art

[0002] CCD and CMOS-APS are the two most common imaging devices currently, and both have their own limitations. CCD has a slow operating speed and is difficult to integrate due to its complex control timing and voltage requirements; CMOS-APS uses photodiodes and has a complex structure, resulting in a low fill factor and a small full well charge.

[0003] In Chinese patent CN201210442007, a dual-transistor photosensitive detector is proposed. The characteristic of this detector is that a single semiconductor device can realize the complete reset, photosensitivity and readout functions, forming a complete pixel, which can greatly improve the pixel fill factor. As a new generation of imaging devices, this composite dielectric gate dual-transistor photosensitive detector has faster operating speed, larger fill factor, more full well charge and can be integrated with CMOS technology, which makes it have inherent advantages over CCD and CMOS-APS.

[0004] In order to meet the needs of intelligence, most current artificial intelligence systems read image data and then perform intelligent calculations through the CPU or GPU. However, the traditional von Neumann architecture has a bottleneck of storage wall, which makes it difficult to achieve a high energy efficiency ratio. Although storage and computing technology has emerged, it still needs to transmit all image data to the processing end for intelligent calculations, which has a bottleneck of transmission wall. Summary of the invention

[0005] In view of the fact that there is no system design based on the integration of sensing, storage and computing at present, the present invention aims to break the barriers of sensing, storage and computing, break through the transmission wall and storage wall, organically integrate the three, and provide a sensing, storage and computing integrated device and array based on a composite dielectric gate structure. Another object of the present invention is to provide an operating method of the above-mentioned device and array.

[0006] The technical solution adopted by the device of the present invention is as follows:

[0007] A sensing, storage and computing integrated device based on a composite dielectric gate structure comprises a composite dielectric gate photosensitive detector and a composite dielectric gate transistor formed on the same P-type semiconductor substrate, wherein the composite dielectric gate photosensitive detector is used to collect, store and read out sensitive photoelectrons, and a first bottom insulating dielectric layer, a first floating gate, a first top insulating dielectric layer and a first control gate are sequentially arranged above the substrate; the composite dielectric gate transistor is used to complete the calculation of the harmonic mean of the weight stored and the sensitive photoelectrons, and a second bottom insulating dielectric layer, a second floating gate, a second top insulating dielectric layer and a second control gate are sequentially arranged above the substrate; the composite dielectric gate photosensitive detector and the composite dielectric gate transistor are respectively provided with a source and a drain in the substrate.

[0008] Furthermore, the source of the composite dielectric gate photosensitive detector is shared with the source of the composite dielectric gate transistor.

[0009] The present invention provides an operating method of the above-mentioned sensing-storage-computing integrated device based on the composite dielectric gate structure, comprising the following steps:

[0010] (1) Resetting the weight: adjusting the second control gate and the P-type semiconductor substrate to be in a reverse bias state, so that the composite dielectric gate transistor generates FN tunneling, thereby completing the resetting of the weight;

[0011] (2) Writing of weights: ① adjusting the second control gate and the P-type semiconductor substrate to be in a forward bias state, so that the composite dielectric gate transistor generates FN tunneling, and the weight writing is completed; or ② adjusting the second control gate and the P-type semiconductor substrate to be in a forward bias state, the drain of the composite dielectric gate photosensitive detector is grounded, and the drain of the composite dielectric gate transistor is connected to a forward bias signal, so that the composite dielectric gate transistor generates hot electron injection, and the weight writing is completed;

[0012] (3) resetting the photoelectrons: adjusting the first control gate and the P-type semiconductor substrate to a zero bias state so that the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer disappears, thereby completing the resetting of the photoelectrons;

[0013] (4) Generation of photoelectrons: Photoelectrons are incident on the P-type semiconductor substrate, generating photogenerated electron-hole pairs;

[0014] (5) collecting photoelectrons: adjusting the first control gate and the P-type semiconductor substrate to be in a positive bias state, so that a depletion region is generated in the P-type semiconductor substrate below the first bottom insulating dielectric layer, and the photogenerated electron-hole pairs generated in step (4) are separated under the action of the vertical electric field, and the electrons are swept into the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer, and the holes are swept out of the substrate;

[0015] (6) Signal reading: Based on the positive bias voltage in step (5), the drain of the composite dielectric gate photosensitive detector is grounded, the second control gate is connected to a positive bias signal, the drain of the composite dielectric gate transistor is connected to the positive bias signal, and the output current of the composite dielectric gate transistor is read.

[0016] The present invention also provides an array of sensing-storage-computing integrated devices based on a composite dielectric gate structure, in which the above-mentioned sensing-storage-computing integrated devices are formed into an array using a NOR architecture: for the sensing-storage-computing integrated device array of N rows and M columns, there are a total of N first word line WL1 signals, which are respectively connected to the first control gates of the N sensing-storage-computing integrated devices; there are a total of N second word line WL2 signals, which are respectively connected to the second control gates of the N sensing-storage-computing integrated devices; there are a total of M source line SL signals, which are respectively connected to the drains of the M composite dielectric gate photosensitive detectors; there are a total of M bit line BL signals, which are respectively connected to the drains of the M composite dielectric gate transistors.

[0017] The present invention further provides an operation method of a sensing-storage-computing integrated device array based on a composite dielectric gate structure, comprising the following steps:

[0018] (1) Resetting the weight: adjusting WL2 and the P-type semiconductor substrate to be in a reverse bias state, so that the composite dielectric gate transistor in each device generates FN tunneling, thereby completing the resetting of the weight;

[0019] (2) Writing of weights: ① adjusting WL2 and the P-type semiconductor substrate to be in a forward bias state, so that the composite dielectric gate transistor in each device generates FN tunneling, and the weight writing is completed; or ② adjusting WL2 and the P-type semiconductor substrate to be in a forward bias state, SL is grounded, and BL is connected to a forward bias signal, so that the composite dielectric gate transistor in each device generates hot electron injection, and the weight writing is completed;

[0020] (3) Resetting of photoelectrons: adjusting WL1 and the P-type semiconductor substrate to a zero bias state so that the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device disappears, thereby completing the resetting of photoelectrons;

[0021] (4) Generation of photoelectrons: Photoelectrons are incident on the P-type semiconductor substrate, generating photogenerated electron-hole pairs;

[0022] (5) Collection of photoelectrons: adjusting WL1 and the P-type semiconductor substrate to be in a positive bias state, so that a depletion region is generated in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the photogenerated electron-hole pairs generated in step (4) are separated under the action of the vertical electric field, and the electrons are respectively swept into the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the holes are swept out of the substrate;

[0023] (6) Signal reading: Based on the positive bias voltage in step (5), SL is grounded, WL2 is connected to the positive bias signal, and BL is connected to the positive bias signal, and the output current of the device array is read respectively.

[0024] The device of the present invention can complete the calculation of the harmonic mean during the signal reading process, and can be used to match the complex calculation of the subsequent image processing unit, thereby reducing the computing power requirement and power consumption of the subsequent image processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a device structure diagram of the present invention;

[0026] Figure 2 is an AA' cross-sectional view of the device structure diagram of the present invention;

[0027] Figure 3 is an equivalent circuit diagram of the device of the present invention;

[0028] Figure 4 (a) is a symbol diagram of the device of the present invention, and (b) is a symbol simplified diagram of (a);

[0029] Figure 5 It is a diagram of the array structure of the present invention. DETAILED DESCRIPTION

[0030] The present invention provides a sensing-storage-computing integrated device based on a composite dielectric gate structure, the structure of which is as follows: Figure 1 As shown, it includes a composite dielectric gate photosensitive detector and a composite dielectric gate transistor formed on the same P-type semiconductor substrate. The composite dielectric gate photosensitive detector is provided with a first bottom insulating dielectric layer, a first floating gate, a first top insulating dielectric layer, and a first control gate in sequence above the substrate, and a source and a drain are provided on both sides of the substrate; the composite dielectric gate transistor is provided with a second bottom insulating dielectric layer, a second floating gate, a second top insulating dielectric layer, and a second control gate in sequence above the substrate, and a source and a drain are provided on both sides of the substrate. The source of the composite dielectric gate photosensitive detector of this embodiment is shared with the source of the composite dielectric gate transistor; the composite dielectric gate photosensitive detector is provided with two MOS capacitors and a channel, such as Figure 2 As shown ( Figure 1 AA' direction cross section).

[0031] The equivalent circuit of the sensing-storage-computing integrated device based on the composite dielectric gate structure is as follows: Figure 3 As shown, the composite dielectric gate photosensitive detector M1 and the composite dielectric gate transistor M2 both work in the linear region, and their currents are I D1 and I D2 The original threshold voltage of the composite dielectric grating photosensitive detector M1 is V TH1,0 , the stored photoelectric signal is V p, then its final threshold voltage is V TH1 =V TH1,0 +V p ; The original threshold voltage of the composite dielectric gate transistor M2 is V TH2,0 , the stored weight signal is V w , then its final threshold voltage is V TH2 =V TH2,0 +V w The signal applied to the first control gate is V WL1 , the signal applied to the second control gate is V WL2 The signal applied to the drain of the composite dielectric gate transistor is V ref , the signal at the source is V S , from which we can get:

[0032]

[0033] Among them, K 1 and K 2 are the transconductance coefficients of M1 and M2 respectively. After ignoring non-ideal effects, we can get:

[0034]

[0035] Right now:

[0036]

[0037] Among them, Opt represents the photosensitive signal, and Elec represents the storage signal of the composite dielectric gate transistor. Therefore, the device can realize the operation of the harmonic mean of the optical signal (photogenerated electrons collected by the composite dielectric gate photosensitive detector) and the electrical signal (weight stored by the composite dielectric gate transistor).

[0038] The symbol of the sensing, storage and computing integrated device based on the composite dielectric gate structure is as follows Figure 4 As shown in Figure (a), it includes a first control gate, a second control gate, a source, a drain and a substrate; considering that a P-type substrate is usually used, the symbol can be simplified to Figure 4 (b) The form of Figure .

[0039] Based on this, Figure 5 A sensing, storage and computing integrated array architecture with N rows and M columns is given, with a total of N first word line WL1 signals, which are respectively connected to N first control gates; a total of N second word line WL2 signals, which are respectively connected to N second control gates; a total of M source line SL signals, which are respectively connected to the drains of M composite dielectric gate photodetectors; and a total of M bit line BL signals, which are respectively connected to the drains of M composite dielectric gate transistors.

[0040] This embodiment provides a method for calculating the harmonic mean based on the array. Assume Figure 5The array size is 16×16, that is, N=16, M=16, and each sensing-storage-computing integrated device based on the composite dielectric gate structure in the array is denoted by M. i,j , where i is the row and j is the column, and the numbering starts from the lower left corner, that is, the sensing storage computing device based on the composite dielectric gate structure in the lower left corner is M 1,1 The sensing, storage and computing integrated device based on the composite dielectric gate structure in the upper right corner is numbered M 16,16 Assume that the original threshold voltage of the composite dielectric grating photosensitive detector in each composite dielectric grating structure sensing storage computing integrated device is V TH1,0 , the threshold voltage shift caused by photoelectrons is V opt ,Right now:

[0041]

[0042] Assume that the signals need to be weighted differently i,j The harmonic mean of is calculated, and the result is x i,j for:

[0043]

[0044] If the conventional solution is adopted, it is necessary to collect image signals After that, NM addition, multiplication and division operations are performed. If the scheme described in the present invention is adopted, NM addition, multiplication and division operations can be omitted. When the array scale is large enough, the energy consumption savings generated are huge. The specific scheme is as follows:

[0045] (1) Resetting weights: Adjust the second word line WL2 to -10V and the P-type semiconductor substrate to -3V, so that the composite dielectric gate transistor in each device generates FN tunneling, completing the weight reset. At this time, the original threshold voltage V of the composite dielectric gate transistor in each composite dielectric gate structure sensing, storage and computing integrated device is recorded. TH2 to negative values;

[0046] (2) Writing of weights: Adjust the second word line WL2 to 5V, the P-type semiconductor substrate to -3V, the source line SL to 0V, and the bit line BL to 3V, so that the composite dielectric gate transistor in each device generates hot electron injection to complete the writing of weights. Each device M i,j The original threshold voltage of the composite dielectric gate transistor is written as w i,j ;

[0047] (3) Resetting the photoelectrons: adjusting the first word line WL1 to -3V and the P-type semiconductor substrate to -3V, so that the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device disappears, completing the resetting of the photoelectrons;

[0048] (4) Generation of photoelectrons: Photoelectrons are incident on the P-type semiconductor substrate, generating photogenerated electron-hole pairs;

[0049] (5) Collection of photoelectrons: adjusting the first word line WL1 to 0V and the P-type semiconductor substrate to -3V, so that a depletion region is generated in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the photogenerated electron-hole pairs generated in step (4) are separated under the action of the vertical electric field, and the electrons are respectively swept into the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the holes are swept out of the substrate;

[0050] (6) Signal reading: Based on the bias voltage in step (5), the source line SL is connected to 0V, the second word line WL2 is connected to 5V, and the bit line BL is connected to 0.2V. The output current of the array device is read respectively (assuming K 1 =K 2 =K):

[0051]

[0052]

[0053]

[0054] Based on this, the array completes the calculation of the harmonic mean when reading out, eliminating NM addition, multiplication and division operations.

Claims

1. An operating method of a sensing-storage-computing integrated device based on a composite dielectric gate structure, wherein the sensing-storage-computing integrated device comprises a composite dielectric gate photosensitive detector and a composite dielectric gate transistor formed on the same P-type semiconductor substrate, wherein the composite dielectric gate photosensitive detector is used to collect, store and read out light-sensitive photoelectrons, and a first bottom insulating dielectric layer, a first floating gate, a first top insulating dielectric layer and a first control gate are sequentially arranged above the substrate; the composite dielectric gate transistor is used to complete the calculation of the harmonic mean of the weight stored therein and the light-sensitive photoelectrons, and a second bottom insulating dielectric layer, a second floating gate, a second top insulating dielectric layer and a second control gate are sequentially arranged above the substrate; the composite dielectric gate photosensitive detector and the composite dielectric gate transistor are respectively provided with a source and a drain in the substrate, characterized in that: The operation method comprises the following steps: (1) Resetting the weight: adjusting the second control gate and the P-type semiconductor substrate to be in a reverse bias state, so that the composite dielectric gate transistor generates FN tunneling, thereby completing the resetting of the weight; (2) Writing of weights: ① adjusting the second control gate and the P-type semiconductor substrate to be in a forward bias state, so that the composite dielectric gate transistor generates FN tunneling, and the weight writing is completed; or ② adjusting the second control gate and the P-type semiconductor substrate to be in a forward bias state, the drain of the composite dielectric gate photosensitive detector is grounded, and the drain of the composite dielectric gate transistor is connected to a forward bias signal, so that the composite dielectric gate transistor generates hot electron injection, and the weight writing is completed; (3) resetting the photoelectrons: adjusting the first control gate and the P-type semiconductor substrate to a zero bias state so that the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer disappears, thereby completing the resetting of the photoelectrons; (4) Generation of photoelectrons: Photoelectrons are incident on the P-type semiconductor substrate, generating photogenerated electron-hole pairs; (5) collecting photoelectrons: adjusting the first control gate and the P-type semiconductor substrate to be in a positive bias state, so that a depletion region is generated in the P-type semiconductor substrate below the first bottom insulating dielectric layer, and the photogenerated electron-hole pairs generated in step (4) are separated under the action of the vertical electric field, and the electrons are swept into the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer, and the holes are swept out of the substrate; (6) Signal reading: Based on the positive bias voltage in step (5), the drain of the composite dielectric gate photosensitive detector is grounded, the second control gate is connected to a positive bias signal, the drain of the composite dielectric gate transistor is connected to the positive bias signal, and the output current of the composite dielectric gate transistor is read.

2. The method for operating the sensing-storage-computing integrated device based on the composite dielectric gate structure according to claim 1, characterized in that: The source of the composite dielectric gate photosensitive detector is shared with the source of the composite dielectric gate transistor.

3. The operating method of the sensing-storage-computing integrated device based on the composite dielectric gate structure according to claim 1, characterized in that: The sensing, storage and computing integrated device is formed into an array using a NOR architecture: For the N rows and M columns of the sensing-storage-computing integrated device array, there are a total of N first word line WL1 signals, which are respectively connected to the first control gates of the N sensing-storage-computing integrated devices; there are a total of N second word line WL2 signals, which are respectively connected to the second control gates of the N sensing-storage-computing integrated devices; there are a total of M source line SL signals, which are respectively connected to the drains of the M composite dielectric gate photosensitive detectors; there are a total of M bit line BL signals, which are respectively connected to the drains of the M composite dielectric gate transistors.

4. The method for operating the sensing-storage-computing integrated device based on the composite dielectric gate structure according to claim 3, characterized in that: The operation method of the array comprises the following steps: 1) Resetting the weight: adjusting WL2 and the P-type semiconductor substrate to be in a reverse bias state, so that the composite dielectric gate transistor in each device generates FN tunneling, thereby completing the resetting of the weight; 2) Writing of weights: ① Adjusting WL2 and the P-type semiconductor substrate to be in a forward bias state, so that the composite dielectric gate transistor in each device generates FN tunneling, and the weight writing is completed; or ② Adjusting WL2 and the P-type semiconductor substrate to be in a forward bias state, SL is grounded, and BL is connected to a forward bias signal, so that the composite dielectric gate transistor in each device generates hot electron injection, and the weight writing is completed; 3) Resetting of photoelectrons: adjusting WL1 and the P-type semiconductor substrate to be in a zero bias state, so that the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device disappears, completing the resetting of photoelectrons; 4) Generation of photoelectrons: Photoelectrons are incident on the P-type semiconductor substrate, generating photogenerated electron-hole pairs; 5) Collection of photoelectrons: adjusting WL1 and the P-type semiconductor substrate to be in a positive bias state, so that a depletion region is generated in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the photogenerated electron-hole pairs generated in step 4) are separated under the action of the vertical electric field, and the electrons are respectively swept into the depletion region in the P-type semiconductor substrate below the first bottom insulating dielectric layer in each device, and the holes are swept out of the substrate; 6) Signal reading: Based on the positive bias voltage in step 5), SL is grounded, WL2 is connected to a positive bias signal, and BL is connected to a positive bias signal, and the output current of the device array is read respectively.

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