Pixel driving circuit, driving method thereof, and display panel

Abstract

The present disclosure relates to the field of display technologies, and provides a pixel driving circuit, a driving method thereof, and a display panel. The pixel driving circuit includes: a driving circuit, a compensation circuit, a data writing circuit, a first storage circuit, a second storage circuit, and a light emitting control circuit. The driving circuit is configured to input a driving current from a third node to a second node according to a signal of a first node; the compensation circuit is configured to connect the first node and the second node in response to a signal of a gate driving signal terminal; the data writing circuit is configured to transmit a signal of a data signal terminal to the third node in response to a signal of the gate driving signal terminal; the first storage circuit is connected between the first node and a first power supply terminal; the second storage circuit is connected between a fourth node and the first node; and the light emitting control circuit is configured to connect the first power supply terminal and the fourth node in response to a signal of an enable signal terminal. The pixel driving circuit can improve the uniformity of display of the display panel.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display panel. Background Art

[0002] In related technologies, a pixel driving circuit generally includes a driving transistor, and the driving transistor is configured to output a driving current to a light-emitting unit according to a data signal of its gate. However, since the driving current output by the driving transistor is also related to its own threshold voltage, the threshold voltage of the driving transistor will affect the magnitude of the current it outputs. At the same time, since it is difficult to make the threshold voltages of the driving transistors in the display panel exactly the same, under the action of the same data signal, uneven display will occur at different positions of the display panel.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] According to one aspect of the present disclosure, there is provided a pixel driving circuit, which includes: a driving circuit, a compensation circuit, a data writing circuit, a first storage circuit, a second storage circuit, and a light-emitting control circuit. The driving circuit is connected to a first node, a second node, and a third node, and is configured to input a driving current to the second node through the third node according to a signal of the first node; the compensation circuit is connected to the second node, the first node, and a gate driving signal terminal, and is configured to connect the first node and the second node in response to a signal of the gate driving signal terminal; the data writing circuit is connected to the third node, a data signal terminal, and the gate driving signal terminal, and is configured to transmit a signal of the data signal terminal to the third node in response to a signal of the gate driving signal terminal; the first storage circuit is connected between the first node and a first power supply terminal; the second storage circuit is connected between a fourth node and the first node, and the fourth node is connected to the third node; the light-emitting control circuit is connected to the first power supply terminal, the fourth node, and an enable signal terminal, and is configured to connect the first power supply terminal and the fourth node in response to a signal of the enable signal terminal.

[0005] In an exemplary embodiment of the present disclosure, the driving circuit includes: a driving transistor, a first pole of the driving transistor is connected to the third node, a second pole is connected to the second node, and a gate is connected to the first node.

[0006] In an exemplary embodiment of the present disclosure, the compensation circuit includes: a first transistor, a first pole of the first transistor is connected to the first node, a second pole is connected to the second node, and a gate is connected to the gate driving signal terminal; the data writing circuit includes: a second transistor, a first pole of the second transistor is connected to the data signal terminal, a second pole is connected to the third node, and a gate is connected to the gate driving signal terminal; the light emitting control circuit includes: a fourth transistor, a first pole of the fourth transistor is connected to the first power supply terminal, a second pole is connected to the fourth node, and a gate is connected to the enable signal terminal; the first storage circuit includes: a first capacitor, the first capacitor is connected between the first power supply terminal and the first node; the second storage circuit includes: a second capacitor, the second capacitor is connected between the fourth node and the first node.

[0007] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive a light emitting unit; the light emitting control circuit is further connected to the second node, the third node, and the fifth node, and the light emitting control circuit is configured to connect the first power supply terminal and the third node in response to a signal of the enable signal terminal, and is configured to connect the second node and the fifth node in response to a signal of the enable signal terminal; wherein, the fifth node is used to connect a first electrode of the light emitting unit.

[0008] In an exemplary embodiment of the present disclosure, the light emitting control circuit includes: a fifth transistor and a sixth transistor, a first pole of the fifth transistor is connected to the first power supply terminal, a second pole is connected to the third node, and a gate is connected to the enable signal terminal; a first pole of the sixth transistor is connected to the fifth node, a second pole is connected to the second node, and a gate is connected to the enable signal terminal.

[0009] In an exemplary embodiment of the present disclosure, the pixel driving circuit is used to drive a light emitting unit; the light emitting control circuit is further connected to the second node and the fifth node, and the light emitting control circuit is configured to connect the second node and the fifth node in response to a signal of the enable signal terminal, wherein, the fifth node is used to connect a first electrode of the light emitting unit; the pixel driving circuit further includes: a first reset circuit and a second reset circuit, the first reset circuit is connected to the first node, the first initial signal terminal, and the reset signal terminal, and is configured to transmit a signal of the first initial signal terminal to the first node in response to a signal of the reset signal terminal; the second reset circuit is connected to the fifth node, the gate driving signal terminal, and the second initial signal terminal, and is configured to transmit a signal of the second initial signal terminal to the fifth node in response to a signal of the gate driving signal terminal.

[0010] In an exemplary embodiment of the present disclosure, the first reset circuit includes: a seventh transistor, a first pole of the seventh transistor is connected to the first initial signal terminal, a second pole is connected to the first node, and a gate is connected to the reset signal terminal; the second reset circuit includes: an eighth transistor, a first pole of the eighth transistor is connected to the second initial signal terminal, a second pole is connected to the fifth node, and a gate is connected to the gate driving signal terminal.

[0011] In an exemplary embodiment of the present disclosure, the driving transistor is a P-type transistor.

[0012] According to one aspect of the present disclosure, there is provided a method for driving a pixel driving circuit for driving the above-mentioned pixel driving circuit. The driving method includes:

[0013] In the data writing stage, an effective level is input to the gate driving signal terminal, and an invalid level is input to the enable signal terminal;

[0014] In the light emitting stage, an invalid level is input to the gate driving signal terminal, and an effective level is input to the enable signal terminal.

[0015] According to one aspect of the present disclosure, there is provided a display panel, and the display panel includes the above-mentioned pixel driving circuit.

[0016] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings without creative efforts based on these drawings.

[0018] Figure 1 It is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure;

[0019] Figure 2 It is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure;

[0020] Figure 3 For Figure 2 It is a timing diagram of each control signal in a driving method of the pixel driving circuit shown;

[0021] Figure 4 For Figure 2 It is a state diagram of the pixel driving circuit shown in the reset stage;

[0022] Figure 5 For Figure 2 the state diagram of the pixel driving circuit shown during the data writing phase;

[0023] Figure 6 For Figure 2 the state diagram of the pixel driving circuit shown during the light emitting phase. Detailed implementation manners

[0024] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted.

[0025] The terms "a", "an", "the" are used to denote the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0026] This exemplary embodiment first provides a pixel driving circuit, as Figure 1 shown, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit may include: a driving circuit 1, a compensation circuit 2, a data writing circuit 3, a first storage circuit 4, a second storage circuit 5, and a light emitting control circuit 6. The driving circuit 1 is connected to a first node N1, a second node N2, and a third node N3, and is configured to input a driving current to the second node N2 through the third node N3 according to the signal of the first node N1; the compensation circuit 2 is connected to the second node N2, the first node N1, and a gate driving signal terminal Gate, and is configured to connect the first node N1 and the second node N2 in response to the signal of the gate driving signal terminal Gate; the data writing circuit 3 is connected to the third node N3, a data signal terminal Data, and the gate driving signal terminal Gate, and is configured to transmit the signal of the data signal terminal Data to the third node N3 in response to the signal of the gate driving signal terminal Gate; the first storage circuit 4 is connected between the first node N1 and a first power supply terminal VDD; the second storage circuit 5 is connected between a fourth node N4 and the first node N1, and the fourth node N4 is connected to the third node N3; the light emitting control circuit 6 is connected to the first power supply terminal VDD, the fourth node N4, and an enable signal terminal EM, and is configured to connect the first power supply terminal VDD and the fourth node N4 in response to the signal of the enable signal terminal EM.

[0027] In this exemplary embodiment, as Figure 1As shown, the driving circuit 1 may include: a driving transistor T3, where a first pole of the driving transistor T3 is connected to the third node N3, a second pole is connected to the second node N2, and a gate is connected to the first node N1. It should be understood that in other exemplary embodiments, the driving circuit 1 may also have other structures. For example, the driving circuit 1 may include a plurality of driving transistors connected in parallel. The plurality of driving transistors connected in parallel may be connected between the third node N3 and the second node N2, and their gates are all connected to the first node N1. This setting can increase the output current of the driving circuit 1.

[0028] In this exemplary embodiment, as Figure 1 shown, the compensation circuit 2 may include: a first transistor T1, where a first pole of the first transistor T1 is connected to the first node N1, a second pole is connected to the second node N2, and a gate is connected to the gate driving signal terminal Gate; the data writing circuit 3 may include: a second transistor T2, where a first pole of the second transistor T2 is connected to the data signal terminal Data, a second pole is connected to the third node N3, and a gate is connected to the gate driving signal terminal Gate; the light emitting control circuit 6 may include: a fourth transistor T4, where a first pole of the fourth transistor T4 is connected to the first power supply terminal VDD, a second pole is connected to the fourth node N4, and a gate is connected to the enable signal terminal EM; the first storage circuit 4 may include: a first capacitor C1, and the first capacitor C1 is connected between the first power supply terminal VDD and the first node N1; the second storage circuit 5 may include: a second capacitor C2, and the second capacitor C2 is connected between the fourth node N4 and the first node N1.

[0029] In this exemplary embodiment, the first transistor T1, the second transistor T2, the driving transistor T3, and the fourth transistor T4 may all be P-type transistors. It should be understood that in other embodiments, at least some of the first transistor T1, the second transistor T2, and the fourth transistor T4 may also be N-type transistors. N-type transistors have a smaller off-state leakage current, thereby reducing the leakage current of each node in the pixel driving circuit. For example, when the fourth transistor T4 is an N-type transistor, the N-type fourth transistor T4 can reduce the leakage current of the fourth node N4 through the fourth transistor T4. When the first transistor T1 is an N-type transistor, the N-type first transistor T1 can reduce the leakage current of the first node N1 through the first transistor T1.

[0030] In this exemplary embodiment, during the data writing stage, the pixel driving circuit can input an effective level to the gate driving signal terminal Gate and an ineffective level to the enable signal terminal EM. The light emitting control circuit 6 disconnects the first power supply terminal VDD and the fourth node N4 under the action of the ineffective level of the enable signal terminal EM. The data writing circuit 3 transmits the data signal of the data signal terminal Data to the third node N3 and the fourth node N4 under the action of the effective level of the gate driving signal terminal Gate. The compensation circuit 2 connects the first node N1 and the second node N2 under the action of the effective level of the gate driving signal terminal Gate, and the third node N3 writes the voltage Vdata + Vth to the first node N1, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving circuit 1. During the light emitting stage, the pixel driving circuit can input an ineffective level to the gate driving signal terminal Gate and an effective level to the enable signal terminal EM. The data writing circuit 3 disconnects the data signal terminal Data and the third node N3 under the action of the ineffective level of the gate driving signal terminal Gate, the compensation circuit 2 disconnects the first node N1 and the second node N2 under the action of the ineffective level of the gate driving signal terminal Gate, and the light emitting control circuit 6 connects the first power supply terminal VDD and the fourth node N4 under the action of the effective level of the enable signal terminal EM. The voltage of the fourth node N4 changes from Vdata to Vdd, where Vdd is the voltage of the first power supply terminal VDD. Based on the principle that the charge of the first node N1 remains unchanged before and after entering the light emitting stage, the voltage of the first node N1 becomes Vdata + Vth + (C2 / (C1 + C2))(Vdd - Vdata), where C1 is the capacitance value of the first storage circuit 4 and C2 is the capacitance value of the second storage circuit 5. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. In this embodiment, the output current I of the driving circuit 1 = (μWCox / 2L)(Vdata + Vth + (C2 / (C1 + C2))(Vdd - Vdata) - V3 - Vth) 2 = (μWCox / 2L)(Vdata + (C2 / (C1 + C2))(Vdd - Vdata) - V3) 2, where V3 is the voltage of the third node N3 in the light-emitting stage. It can be seen therefrom that in this exemplary embodiment, the output current of the pixel driving circuit has nothing to do with the threshold of the driving circuit 1, and this pixel driving circuit can avoid the problem of uneven display of the display panel caused by inconsistent thresholds of the driving circuit 1. In addition, the first capacitor C1 and the second capacitor C2 in this pixel driving circuit can make the voltage of the first node N1 more stable, so that the output current of the driving transistor in the light-emitting stage is more stable. Moreover, the first capacitor C1 and the second capacitor C2 can also adjust the output current of the driving transistor, or adjust the voltage range of the data signal when the output current range is certain.

[0031] It should be noted that the effective level is the level that can drive the target circuit. For example, when the target circuit is a P-type transistor, the effective level is the low level, and the logic of the invalid level is opposite to that of the effective level.

[0032] As Figure 2 shown, it is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit of the present disclosure. The pixel driving circuit is used to drive the light-emitting unit Oled. In Figure 1 the basis of the shown pixel driving circuit, the light-emitting control circuit 6 is further connected to the second node N2, the third node N3, and the fifth node N5. The light-emitting control circuit 6 is configured to connect the first power supply terminal VDD and the third node N3 in response to the signal of the enable signal terminal EM, and to connect the second node N2 and the fifth node N5 in response to the signal of the enable signal terminal EM; wherein, the fifth node N5 is used to connect the first electrode of the light-emitting unit Oled, and the second electrode of the light-emitting unit Oled can be connected to the second power supply terminal VSS. It should be understood that in other exemplary embodiments, the third node N3 can also be connected to other power supply terminals through a switching transistor.

[0033] In this exemplary embodiment, as Figure 2 shown, the light-emitting control circuit 6 may further include: a fifth transistor T5 and a sixth transistor T6. The first pole of the fifth transistor T5 is connected to the first power supply terminal VDD, the second pole is connected to the third node N3, and the gate is connected to the enable signal terminal EM; the first pole of the sixth transistor T6 is connected to the fifth node N5, the second pole is connected to the second node N2, and the gate is connected to the enable signal terminal EM.

[0034] In this exemplary embodiment, as Figure 2As shown, the pixel driving circuit may further include: a first reset circuit 7 and a second reset circuit 8. The first reset circuit 7 is connected to the first node N1, the first initial signal terminal Vinit1, and the reset signal terminal Re, and is configured to transmit the signal of the first initial signal terminal Vinit1 to the first node N1 in response to the signal of the reset signal terminal Re. The second reset circuit 8 is connected to the fifth node N5, the gate driving signal terminal Gate, and the second initial signal terminal Vinit2, and is configured to transmit the signal of the second initial signal terminal Vinit2 to the fifth node N5 in response to the signal of the gate driving signal terminal Gate.

[0035] In this exemplary embodiment, as Figure 2 shown, the first reset circuit 7 may include: a seventh transistor T7. The first pole of the seventh transistor T7 is connected to the first initial signal terminal Vinit1, the second pole is connected to the first node N1, and the gate is connected to the reset signal terminal Re. The second reset circuit 8 may include: an eighth transistor T8. The first pole of the eighth transistor T8 is connected to the second initial signal terminal Vinit2, the second pole is connected to the fifth node N5, and the gate is connected to the gate driving signal terminal Gate.

[0036] In this exemplary embodiment, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors. The first power supply terminal VDD may be a high-level power supply terminal, and the second power supply terminal VSS may be a low-level power supply terminal. It should be understood that in other embodiments, at least some of the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may also be N-type transistors. The N-type transistors have a smaller off-state leakage current, thereby reducing the leakage current of each node in the pixel driving circuit. For example, the seventh transistor T7 may be an N-type transistor, and the N-type seventh transistor T7 can reduce the leakage current of the first node N1 through the seventh transistor T7.

[0037] As Figure 3 shown, for Figure 2 shown is the timing diagram of each control signal in a driving method of the pixel driving circuit shown. Among them, Gate is the timing diagram of the gate driving signal terminal, EM is the timing diagram of the enable signal terminal, and Re is the timing diagram of the reset signal terminal. As Figure 3 shown, the pixel driving circuit may include three stages: a reset stage t1, a data writing stage t2, and a light emitting stage t3.

[0038] In the reset stage t1, as Figure 4 shown, for Figure 2State diagram of the pixel driving circuit during the reset phase. Among them, the transistors with a cross are in the off state, and the transistors without a cross are in the on state. During the reset phase t1, high-level signals are input to the enable signal terminal EM and the gate driving signal terminal Gate, and a low-level signal is input to the reset signal terminal Re. The first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned off, and the seventh transistor T7 is turned on. The first initial signal terminal Vinit1 inputs a first initial signal to the first node N1 to reset the first node N1.

[0039] During the data writing phase t2, as Figure 5 shown, it is Figure 2 State diagram of the pixel driving circuit during the data writing phase. Among them, the transistors with a cross are in the off state, and the transistors without a cross are in the on state. During the data writing phase t2, a low-level signal is input to the gate driving signal Gate, and high-level signals are input to the reset signal terminal Re and the enable signal terminal EM. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are turned off, and the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on. The data signal terminal Data writes a data signal to the third node N3 and the fourth node N4, and the third node N3 writes a voltage Vdata + Vth to the first node N1, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. At the same time, the second initial signal terminal Vinit2 writes a second initial signal to the fifth node N5 through the eighth transistor T8 to reset the fifth node N5. Among them, the voltages of the second initial signal and the first initial signal can be the same or different. In addition, in other exemplary embodiments, the gate of the eighth transistor T8 can also be connected to other signal terminals, and the second initial signal terminal Vinit2 can reset the fifth node N5 at other time periods. For example, the gate of the eighth transistor T8 can be connected to the reset signal terminal, so that the second initial signal terminal Vinit2 can reset the fifth node N5 during the reset phase t1.

[0040] During the light emitting phase t3, as Figure 6 shown, it is Figure 2The state diagram of the pixel driving circuit shown during the light-emitting stage. Among them, the transistors with a cross mark are in the off state, and the transistors without a cross mark are in the on state. During the light-emitting stage t3, a low-level signal is input to the enable signal terminal EM, and high-level signals are input to the reset signal terminal Re and the gate driving signal terminal Gate. The fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the seventh transistor T7, and the eighth transistor T8 are turned off. The first power supply terminal VDD inputs a voltage Vdd to the fourth node N4, and the voltage of the fourth node N4 changes from Vdata to Vdd. Based on the principle that the charge on the first node N1 does not change before and after entering the light-emitting stage, the voltage of the first node N1 becomes Vdata + Vth + (C2 / (C1 + C2))(Vdd - Vdata), where C1 is the capacitance value of the first capacitor C1, and C2 is the capacitance value of the second capacitor C2. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 , where μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the gate-source voltage difference of the driving transistor, and Vth is the threshold voltage of the driving transistor. The driving transistor T3 in the present disclosure outputs a current I = (μWCox / 2L)(Vdata + Vth + (C2 / (C1 + C2))(Vdd - Vdata) - Vdd - Vth) 2 = (μWCox / 2L)((C1 / (C1 + C2))(Vdata - Vdd)) 2 . It can be seen from this that in this exemplary embodiment, the output current of the pixel driving circuit has nothing to do with the threshold of the driving transistor T3, and this pixel driving circuit can avoid the problem of uneven display of the display panel caused by inconsistent thresholds of the driving transistor T3. In addition, the first capacitor C1 and the second capacitor C2 in this pixel driving circuit can make the voltage of the first node N1 more stable, so that the output current of the driving transistor during the light-emitting stage is more stable. And the first capacitor C1 and the second capacitor C2 can also adjust the output current of the driving transistor, or adjust the voltage range of the data signal when the output current range is certain.

[0041] In this exemplary embodiment, the pixel driving circuits in the display panel can be driven row by row, and the reset signal terminal Re in the pixel driving circuit of this row can be the same potential signal terminal as the gate driving signal terminal in the pixel driving circuit of the previous row.

[0042] This exemplary embodiment also provides a method for driving a pixel driving circuit for driving the above-mentioned pixel driving circuit. The driving method includes:

[0043] During the data writing stage, an effective level is input to the gate driving signal terminal Gate, and an ineffective level is input to the enable signal terminal EM;

[0044] During the light emitting stage, an ineffective level is input to the gate driving signal terminal Gate, and an effective level is input to the enable signal terminal EM.

[0045] This driving method has been described in detail in the above content and will not be elaborated here.

[0046] This exemplary embodiment further provides a display panel, which may include the above-mentioned pixel driving circuit. This display panel can be applied to display devices such as mobile phones, tablet computers, and televisions.

[0047] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the content disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed by the present disclosure. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0048] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only defined by the appended claims.

Claims

1. A pixel driving circuit, characterized in that, Comprising: A driving circuit, connected to a first node, a second node, and a third node, for inputting a driving current from the third node to the second node according to a signal of the first node; A compensation circuit, connected to the second node, the first node, and a gate driving signal terminal, for connecting the first node and the second node in response to a signal of the gate driving signal terminal; A data writing circuit, connected to the third node, a data signal terminal, and the gate driving signal terminal, for transmitting a signal of the data signal terminal to the third node in response to a signal of the gate driving signal terminal; A first storage circuit, connected between the first node and a first power supply terminal; A second storage circuit, connected between a fourth node and the first node, the fourth node being connected to the third node; A light emission control circuit, connected to the first power supply terminal, the fourth node, and an enable signal terminal, for connecting the first power supply terminal and the fourth node in response to a signal of the enable signal terminal.

2. The pixel driving circuit according to claim 1, wherein The driving circuit includes: A driving transistor, with a first pole connected to the third node, a second pole connected to the second node, and a gate connected to the first node.

3. The pixel driving circuit according to claim 1, characterized in that The compensation circuit includes: A first transistor, with a first pole connected to the first node, a second pole connected to the second node, and a gate connected to the gate driving signal terminal; The data writing circuit includes: A second transistor, with a first pole connected to the data signal terminal, a second pole connected to the third node, and a gate connected to the gate driving signal terminal; The light emission control circuit includes: A fourth transistor, with a first pole connected to the first power supply terminal, a second pole connected to the fourth node, and a gate connected to the enable signal terminal; The first storage circuit includes: A first capacitor, connected between the first power supply terminal and the first node; The second storage circuit includes: A second capacitor, connected between the fourth node and the first node.

4. The pixel driving circuit according to claim 1, wherein The pixel driving circuit is used to drive a light emitting unit; The light emission control circuit is further connected to the second node, the third node, and a fifth node, and is used to connect the first power supply terminal and the third node in response to a signal of the enable signal terminal, and is used to connect the second node and the fifth node in response to a signal of the enable signal terminal; Wherein, the fifth node is used to connect a first electrode of the light emitting unit.

5. The pixel driving circuit according to claim 4, wherein The light emission control circuit includes: A fifth transistor, with a first pole connected to the first power supply terminal, a second pole connected to the third node, and a gate connected to the enable signal terminal; A sixth transistor, with a first pole connected to the fifth node, a second pole connected to the second node, and a gate connected to the enable signal terminal.

6. The pixel driving circuit according to claim 1, wherein The pixel driving circuit is used to drive a light emitting unit; The light emission control circuit is further connected to the second node and the fifth node, and is used to connect the second node and the fifth node in response to a signal of the enable signal terminal, wherein the fifth node is used to connect a first electrode of the light emitting unit; The pixel driving circuit further includes: A first reset circuit, connected to the first node, a first initial signal terminal, and a reset signal terminal, for responding to a signal of the reset signal terminal to transmit a signal of the first initial signal terminal to the first node; A second reset circuit, connected to the fifth node, a gate driving signal terminal, and a second initial signal terminal, for responding to a signal of the gate driving signal terminal to transmit a signal of the second initial signal terminal to the fifth node.

7. The pixel driving circuit according to claim 6, wherein The first reset circuit includes: A seventh transistor, with a first pole connected to the first initial signal terminal, a second pole connected to the first node, and a gate connected to the reset signal terminal; The second reset circuit includes: An eighth transistor, with a first pole connected to the second initial signal terminal, a second pole connected to the fifth node, and a gate connected to the gate driving signal terminal.

8. The pixel driving circuit according to claim 2, wherein The driving transistor is a P-type transistor.

9. A method for driving a pixel driving circuit, characterized in that, For driving the pixel driving circuit according to any one of claims 1-8, the driving method includes: In the data writing stage, input an effective level to the gate driving signal terminal and an invalid level to the enable signal terminal; In the light emitting stage, input an invalid level to the gate driving signal terminal and an effective level to the enable signal terminal.

10. A display panel, characterized in that, Including the pixel driving circuit according to any one of claims 1-8.

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