write equalization

Abstract

This application relates to write equalization. A memory device includes a command interface configured to receive a write command and internal write adjustment (IWA) circuitry. The IWA circuitry is configured to receive the write command from the command interface, generate an internal write signal (IWS) based on the received write command, and train a data strobe (DQS) signal to generate a DQS signal having a set amount of phase alignment with a clock (CLK) of the memory device to capture data signals (DQ) using the IWS.

Description

[0001] Information related to divisional application

[0002] This case is a divisional application. The parent application of this divisional application is the invention patent application filed on November 27, 2020, with application number 202011353492.4 and invention title "Write Equalization". Technical Field

[0003] Embodiments of the present invention generally relate to the field of semiconductor devices. More specifically, embodiments of the present invention relate to modifying a write equalization signal in a memory device by modifying an internal write equalization loop. Background Technology

[0004] Semiconductor devices (e.g., memory devices) operate using timing with phase shifts of data signals, data strobes, and / or other signals. Data strobes are used to capture data. To ensure proper timing of the data strobe signals for data capture, write equalization can be used to adjust the timing of the data strobe signals to ensure proper data capture. Using write equalization allows the system to compensate for timing differences across modules between the clock path to each memory device and the clock path to the data signal (DQ) and the data strobe (DQS) path. Accurate write equalization is crucial; otherwise, timing differences cannot be mitigated, leading to off-specification device operation.

[0005] The embodiments of the present invention may address one or more of the problems raised above. Summary of the Invention

[0006] One aspect of the present invention relates to a memory device comprising: a command interface configured to: receive a write command; and an internal write adjustment (IWA) circuitry configured to: receive the write command from the command interface; generate an internal write signal (IWS) based on the write command; and a training data strobe (DQS) signal to generate a DQS signal having a set phase alignment amount with the clock (CLK) of the memory device, for capturing a data signal (DQ) using the IWS.

[0007] Another aspect of the invention relates to a method comprising: implementing internal write equalization in a memory device, comprising: setting a value in a mode register of the memory device, wherein the value corresponds to the number of clock cycles of a clock (CLK) that can be used to adjust the transmission of an internal write signal (IWS); determining whether the value in the mode register causes the phase alignment between an internal data strobe (DQS) signal and the CLK to be outside a predetermined phase misalignment amount; and adjusting the value in the mode register to change the phase alignment between the DQS signal and the CLK to within the predetermined phase misalignment amount.

[0008] Another aspect of the invention relates to an internal adjustment device comprising: a mode register configured to transmit a control signal based on a storage indication in the mode register; and a multiplexer configured to receive the control signal and a write command, wherein the multiplexer is configured to selectively transmit the write command based on the value of the control signal, wherein the mode register is configured to receive the storage indication to indicate whether the phase alignment between an internal data strobe (DQS) signal of the memory device and the clock of the memory device is outside a predetermined phase mismatch amount. Attached Figure Description

[0009] Figure 1 This is a simplified block diagram illustrating certain features of a memory device according to an embodiment of the present invention;

[0010] Figure 2 According to embodiments of the present invention, it is possible to Figure 1 A schematic diagram of the write capture circuitry system implemented in the command decoder and / or data path of the memory;

[0011] Figure 3 This is a flowchart of the first process of internal write equalization according to an embodiment;

[0012] Figure 4 This is an illustration of the combination according to the embodiments. Figure 3 The diagram shows the first instance of the minimum and maximum boundary cases of the internal write-balanced system.

[0013] Figure 5 This is an illustration of the combination according to the embodiments. Figure 3 The diagram shows the second instance of the minimum and maximum boundary cases of the internal writing equilibrium.

[0014] Figure 6 This is an illustration of the combination according to the embodiments. Figure 3 The diagram shows the third instance of the minimum and maximum boundary cases of the internal writing equilibrium.

[0015] Figure 7 This is a flowchart of the second process of internal write equalization according to an embodiment;

[0016] Figure 8 This describes the inclusion and combination according to the embodiments. Figure 7 The diagram shows the first instance of the minimum and maximum boundary cases of the internal write-balanced system.

[0017] Figure 9 This describes the inclusion and combination according to the embodiments. Figure 7 The diagram shows the second instance of the minimum and maximum boundary cases of the internal writing equilibrium; and

[0018] Figure 10 According to the embodiments Figure 2 A schematic diagram of a portion of the IWA. Detailed Implementation

[0019] One or more specific embodiments will be described below. To provide a concise description of these embodiments, not all features of the actual implementation are described in this specification. It should be understood that in the development of any such actual implementation (as in any engineering or design project), many implementation-specific decisions must be made to achieve specific goals of the developer that may vary with the implementation, such as compliance with system-related and business-related constraints. Furthermore, it should be understood that this development effort may be complex and time-consuming, but will still be a routine design, fabrication, and manufacturing task for those skilled in the art to which this invention pertains.

[0020] To ensure that the Data strobe (DQS) signal is properly timed to capture the data signal (DQ), write equalization can be used to adjust the DQS signal. In some embodiments, write equalization can be employed when the memory device is powered on, during clock changes, and / or due to system-level decisions (e.g., when too many changes occur in timing and timing is reset). Write equalization can be categorized as external write equalization and / or internal write equalization. External write equalization involves sending a signal back to the host device to inform the host device whether the system-level clock can be aligned with the DQS signal at the pin of memory device 10.

[0021] Internal write equalization can be performed after external write equalization. For example, internal write equalization allows the memory to offset the timing of its initiation of internal write commands (e.g., internal write signals (IWS)) to be captured by the DQS domain. Therefore, after receiving a write from the host device, internal write equalization utilizes the IWS circuitry to initiate the IWS and can execute it using instructions from the host device. Internal write equalization causes the initiation to occur a number (N) cycles earlier than the programming CAS (Column Access Strobe) write delay (CWL) for the memory device to ensure that the DQS signal can properly capture the IWS.

[0022] Dual Data Rate Type 5 Synchronous Dynamic Access Memory (DDR5 SDRAM) devices feature internal write equalization, which includes a final positive phase shift of the Data strobe (DQS) signal via the host device. After completing two write equalization steps (external and internal equalization, i.e., the entire write equalization training process), the DDR5 specification allows a timing offset (DQS to CLK phase alignment) between -0.5tCK (DQS minus half a clock pulse) and +0.5tCK (DQS plus half a clock pulse), where tCK is the time for one tick of the clock (CK).

[0023] Keeping timing deviations within specification is useful, especially when multiple memory classes exist and share the DQ and DQS buses. This is because switching between classes of memory device 10 (e.g., from write to class 0 to write to class 1) typically involves adding timing bubbles (one or more clock cycles). If the timing deviation is outside specification, additional clock cycles are added to the timing bubble, which degrades memory performance. There are boundary cases where timing deviations after write-level training can fall outside the specification's 1tCK window when internal error sources (e.g., certain voltage, temperature, and / or clock rate conditions, path matching delays, CAS (Column Access Strobe) delays, internal changes to write cycles, etc.) occur.

[0024] Therefore, this embodiment describes a technique and circuit system that modifies and / or mitigates out-of-specification timing deviations after write equalization (e.g., write-level training). Generally, the resolution during internal write equalization is one clock cycle. Ideally, after external write equalization adjustments are completed, an aligned DQS and clock signal will be generated. However, due to internal error sources, the aligned DQS and clock signal may be misaligned (i.e., out of phase with each other by more than a threshold amount, such as a quarter clock cycle). Therefore, when the mode register is loaded to offset the internal timing of the write signal (IWS) with a resolution of one clock cycle, the internal write equalization process can cause out-of-specification deviations between the DQS and the clock. This embodiment changes this resolution from one clock cycle to half a clock cycle for writing the Internal Cycle Adjustment (WICA) value based on timing relationships.

[0025] Please refer to the diagram below. Figure 1 This is a simplified block diagram illustrating specific features of the memory device 10. Specifically, Figure 1 The block diagram is a functional block diagram illustrating the specific functionality of the memory device 10. According to one embodiment, the memory device 10 may be a DDR5 SDRAM memory device. Compared to previous generations of DDR SDRAM, various features of DDR5 SDRAM allow for reduced power consumption, more bandwidth, and greater storage capacity.

[0026] Memory device 10 may include a plurality of memory banks 12. For example, the memory banks 12 may be DDR5 SDRAM memory banks. Memory banks 12 may be provided on one or more chips (e.g., SDRAM chips) arranged on a dual in-line memory module (DIMM). As will be understood, each DIMM may contain a plurality of SDRAM memory chips (e.g., x8 or x16 memory chips). Each SDRAM memory chip may contain one or more memory banks 12. Memory device 10 represents a portion of a single memory chip (e.g., an SDRAM chip) having a plurality of memory banks 12. For DDR5, the memory banks 12 may be further arranged to form memory bank groups. For example, for 8 gigabyte (Gb) DDR5 SDRAM, the memory chip may contain 16 memory banks 12 arranged in 8 memory bank groups, each memory bank group containing 2 memory banks. For example, for 16Gb DDR5 SDRAM, the memory chip may contain 32 memory banks 12 arranged in 8 memory bank groups, with each memory bank group containing 4 memory banks. Depending on the application and design of the overall system, various other configurations, organization, and sizes of the memory banks 12 on the memory device 10 may be utilized.

[0027] The memory device 10 may include a command interface 14 and an input / output (I / O) interface 16. The command interface 14 is configured to provide several signals (e.g., signal 15) from an external device (not shown) (e.g., a processor or controller). The processor or controller may provide various signals 15 to the memory device 10 to facilitate the transfer and reception of data to be written to or read from the memory device 10.

[0028] As will be understood, command interface 14 may include several circuits (for example, clock input circuitry 18 and command address input circuitry 20) to ensure proper handling of signal 15. Command interface 14 may receive one or more clock signals from an external device. Generally, Double Data Rate (DDR) memory utilizes a differential pair of system clock signals, referred herein to as the real clock signal (Clk_t / ) and the bar clock signal (Clk_b). The positive clock edge of DDR refers to the point where the rising real clock signal Clk_t / crosses the falling bar clock signal Clk_b, while the negative clock edge indicates the transition of the falling real clock signal Clk_t and the rise of the bar clock signal Clk_b. Commands (e.g., read commands, write commands, etc.) are typically entered on the positive edge of the clock signal, and data is transmitted or received on both the positive and negative clock edges.

[0029] Clock input circuit 18 receives a real clock signal (Clk_t / ) and a bar clock signal (Clk_b) and generates an internal clock signal CLK. The internal clock signal CLK is supplied to an internal clock generator, such as a delay-locked loop (DLL) circuit 30. DLL circuit 30 generates a phase-controlled internal clock signal LCLK based on the received internal clock signal CLK. The phase-controlled internal clock signal LCLK is supplied to, for example, an I / O interface 16 and used as a timing signal to determine the output timing for reading data.

[0030] The internal clock signal / phase CLK can also be provided to various other components within the memory device 10 and can be used to generate various additional internal clock signals. For example, the internal clock signal CLK can be provided to the command decoder 32. The command decoder 32 can receive command signals from the command bus 34 and can decode the command signals to provide various internal commands. For example, the command decoder 32 can provide command signals to the DLL circuit 30 via bus 36 to coordinate the generation of the phase-controlled internal clock signal LCLK. The phase-controlled internal clock signal LCLK can be used, for example, to time data via the I / O interface 16.

[0031] Furthermore, the command decoder 32 can decode commands (e.g., read commands, write commands, mode register setting commands, activation commands, etc.) and provide access to a specific memory bank 12 corresponding to the command via bus path 40. As will be understood, the memory device 10 may include various other decoders (e.g., row decoders and column decoders) to facilitate access to the memory bank 12. In one embodiment, each memory bank 12 includes a memory bank control block 22 that provides the necessary decoding (e.g., row decoders and column decoders) and other features (e.g., timing control and data control) to facilitate the execution of commands traveling to and from the memory bank 12.

[0032] Memory device 10 performs operations, such as read and write commands, based on command / address signals received from an external device (e.g., a processor). In one embodiment, the command / address bus may be a 14-bit bus that houses command / address signals (CA<13:0>). Command / address signals to command interface 14 are timed using clock signals (Clk_t and Clk_b). The command interface may include command address input circuitry 20 configured to receive and transmit commands to provide access to memory bank 12, for example, via command decoder 32. Additionally, command interface 14 may receive a chip select signal (CS_n). The CS_n signal enables memory device 10 to process commands input to the CA<13:0> bus. Access to a specific memory bank 12 within memory device 10 is encoded on the CA<13:0> bus using the command.

[0033] Additionally, command interface 14 can be configured to receive several other command signals. For example, a die-terminated command / address (CA_ODT) signal can be provided to facilitate proper impedance matching within memory device 10. A reset command (RESET_n) can be used, for example, to reset command interface 14, status registers, state machines, and the like during power-up. Command interface 14 can also receive a command / address inversion (CAI) signal, which can be provided to invert the state of command / address signals CA<13:0> on the command / address bus, for example, depending on the command / address routing for a particular memory device 10. A mirror (MIR) signal can also be provided to facilitate mirroring functionality. The MIR signal can be used to multiplex signals so that it can exchange certain routes of signals used to implement the signal to memory device 10 based on the configuration of multiple memory devices in a particular application. Various signals can also be provided to facilitate testing of memory device 10, such as a test enable (TEN) signal. For example, the TEN signal can be used to put memory device 10 into test mode for connectivity testing.

[0034] Command interface 14 can also be used to provide alarm signals (ALERT_n) to the system processor or controller for certain errors that may be detected. For example, if a cyclic redundancy check (CRC) error is detected, an alarm signal (ALERT_n) can be transmitted from memory device 10. Other alarm signals may also be generated. Furthermore, the bus and pins used for transmitting alarm signals (ALERT_n) from memory device 10 can be used as input pins during certain operations, such as connectivity test modes performed using the TEN signal, as described above.

[0035] By transmitting and receiving data signals 44 through I / O interface 16, data can be sent to and from memory device 10 using the commands and timing signals discussed above. More specifically, data can be sent to or retrieved from memory bank 12 via data path 46, which includes multiple bidirectional data buses. Data I / O signals, commonly referred to as DQ signals, are typically transmitted and received on one or more bidirectional data buses. For some memory devices, such as DDR5 SDRAM memory devices, I / O signals can be divided into high-order and low-order bytes. For example, for x16 memory devices, I / O signals can be divided into high-order and low-order I / O signals corresponding to, for example, the high-order and low-order bytes of a data signal (e.g., DQ<15:8> and DQ<7:0>).

[0036] To allow for higher data rates within memory device 10, some memory devices (e.g., DDR memory devices) may utilize a data strobe signal, commonly referred to as the DQS signal. The DQS signal is driven by an external processor or controller transmitting data (e.g., for write commands) or by memory device 10 itself (e.g., for read commands). For read commands, the DQS signal is actually an additional data output (DQ) signal with a predetermined pattern. For write commands, the DQS signal is used as a clock signal to capture the corresponding input data. Like the clock signals (Clk_t and Clk_b), the DQS signal can be provided as a differential pair of data strobe signals (DQS_t and DQS_b) to provide differential pair signaling during read and write operations. For some memory devices, such as DDR5 SDRAM memory devices, the differential pair of the DQS signal can be divided into high-bit and low-bit data strobe signals (e.g., UDQS_t and UDQS_b; LDQS_t and LDQS_b) corresponding to the high-bit and low-bit bytes of data, for example, sent to or from memory device 10.

[0037] like Figure 1 As described, the command decoder 32 and / or data path 46 may include an internal write adjustment (IWA) circuitry 48, which can be used to phase-shift the IWS and / or DQS to maintain a specific phase relationship therebetween. An impedance (ZQ) calibration signal can also be provided to the memory device 10 via the I / O interface 16. The ZQ calibration signal can be provided to a reference pin and can be used to tune the output driver and ODT values ​​by adjusting the pull-up and pull-down resistors across process, voltage, and temperature (PVT) values. Since PVT characteristics can affect the ZQ resistor value, the ZQ calibration signal can be provided to the ZQ reference pin to adjust the resistance to calibrate the input impedance to a known value. As will be understood, a precision resistor is typically coupled between the ZQ pin on the memory device 10 and GND / VSS external to the memory device 10. This resistor acts as a reference for adjusting the drive strength of the internal ODT and I / O pins.

[0038] Additionally, a loopback signal can be provided to memory device 10 via I / O interface 16. The loopback signal can be used during testing or debugging to configure memory device 10 in a mode where the memory device 10 loops back through the same pin. For example, the loopback signal can be used to configure memory device 10 to test its data output (DQ). The loopback may include both data and strobe pulses or may only include the data pin. This is typically intended for monitoring data captured by memory device 10 at I / O interface 16.

[0039] As will be understood, various other components, such as power supply circuitry (for receiving external VDD and VSS signals), mode registers (for defining various modes of programmable operation and configuration), read / write amplifiers (for amplifying signals during read / write operations), and temperature sensors (for sensing the temperature of memory device 10), may also be incorporated into memory device 10. Therefore, it should be understood that... Figure 1 The block diagram is provided only to highlight certain functional features of the memory device 10 to aid in the subsequent detailed description.

[0040] Figure 2 This is a schematic diagram of a write capture circuitry system 50, which may be implemented in the command decoder 32 and / or data path 46 and utilizes an internal write signal transmitted from the IWA circuitry system 48. The write capture circuitry system 50 receives an external DQS (XDQSt) signal 51 (e.g., UDQS_t) operating at the same speed as an external clock and can be turned on or off. In some embodiments, the external DQS signal 51 may be accompanied by an external bar DQS (XDQSb) signal 52 complementary to the external DQS signal 51. These signals may be transmitted to an amplifier 53 to provide a DQS signal 54 and / or a complementary DQS dummy signal 56. The amplifier 53 modulates the power of the external DQS signal 51 from an external level to a level suitable for use in the memory device 10.

[0041] The DQS signal 54 is used to capture the IWS 58 in the data path 46 on the correct cycle using the trigger 60 to successfully initiate a write burst and capture incoming write data using the capture writer 62 in the DQS domain. The external DQS signal 51 may have an unknown phase relationship with the internal clock (CLK) that generates the IWS 58, but a crossover to the clock domain (e.g., IWS 58) in the DQS domain will occur at the trigger 60. Therefore, the phase relationship of the external DQS signal 51 will be calibrated with respect to the external clock to position the external DQS signal 51 to properly capture the IWS 58 and allow for a degree of external variation. Furthermore, in some embodiments, as illustrated, the trigger 60 may capture the IWS 58 at the falling edge of the DQS signal 54. Additionally or alternatively, the IWS 58 may be captured at the rising edge of the DQS signal 54.

[0042] The DQS signal 54 can be adjusted (i.e., external write equalization) to ensure that the DQS signal 54 is aligned with CLK at the memory pin of memory device 10. This adjustment can be implemented using one or more mode register bits, such as MR2.1 = Write Equalization (WL) training mode, which, when enabled (e.g., set to 1), will cause the IWS 58 to be driven onto the DQ bus by the successful (or unsuccessful) capture of the DQS signal 54 ("1" = successful capture). The external WL may include, for example, coarse tuning adjustment, which includes the transmission of a write command, determining whether a write command has been captured (DQ=1), and adjusting the DQS signal 54 by positive steps, repeating this until the write command is captured. The external WL may additionally include, for example, fine tuning adjustment following the coarse tuning adjustment, which includes the transmission of an additional write command, determining whether an additional write command has been captured (DQ=1), and adjusting the DQS signal 54 by negative steps (smaller in size than positive steps) until the write command is not captured. Once this occurs, the external write-down (WL) is complete, and the DQS signal 54 is aligned with CLK at the memory pin of memory device 10 (e.g., tDQSoffset = 0). At this point, the internal write-down can continue.

[0043] Figure 3 A flowchart illustrating one method 64 of performing an internal write lock (WL) is provided. The internal WL process alters the clock cycle (CLK) of the write command being shifted out of the DQS domain; that is, the internal WL controls the transfer of the IWS 58 from the IWA circuitry 48 so that the IWS 58 can be properly captured in the DQS domain. This method 64 can be performed, for example, by the IWA circuitry 48.

[0044] As shown, method 64 begins after the external WL is completed in step 66. In step 68, a negative timing adjustment (e.g., tWL_ADJ_start) can be applied to the DQS signal 54. This step 68 can be performed at the end of the data stream to correct timing, and can be performed, for example, in conjunction with the specifications of memory device 10. In step 70, the internal WL is started (e.g., internal WL training mode). In conjunction with step 70, one or more mode registers used in conjunction with the start of the internal WL are set. For example, mode register MR2.1 (which is applied to both the external WL and the internal WL) is set to (or held to) 1. An additional mode register used is, for example, MR2.7 = internal write timing (write internal loop adjustment or "WICA" mode), which, when enabled (set to 1), will cause IWS 58 to initiate earlier from the CAS-Write-Delay (CWL) offset of IWA circuit system 48. The other mode register used is MR3.3:0 = WICA value (WICA is the loop number from which memory device 10 will initiate IWS earlier from the CWL offset). As explained in step 70, the above mode registers are initially set as follows: mode register MR2.1 = 1, mode register MR2.7 = 1, and the initial value of WICA = 0.

[0045] In step 72, the mode register MR3.3:0 is set to the current WICA value, which in this case is 0, since this is the first time method 64 has been used. A write command is issued in step 74, and it is determined in step 76 whether the write command has been captured (as captured write 62). If no write command has been captured (e.g., no captured write 62 exists), the WICA value is iteratively adjusted, for example, by one clock cycle (causing the IWA circuitry 48 to send the IWS 58 one clock cycle earlier), and steps 72, 74, 76, and 77 are repeated until a write command (as captured write 62 exists) is captured in step 76 using the adjusted WICA value. At this point, MR3.3:0 is set to a value indicating the current value of the WICA, i.e., the WICA value that initiates the timing of the IWS 58 by the IWA circuitry 48. This process completes the coarse tuning of the internal WL.

[0046] The capture write 62 may not always be consistent with a clock resolution of the WICA value described above. For example, a WICA value of 3 can be applied to a capture write 62 with a capture delay of 2.5 clock cycles (i.e., initiating IWS 58 from the clock domain three clock cycles in advance, even if the capture write 62 is initiated at least 2.5 clock cycles in advance). Therefore, to compensate for this mismatch between the WICA value and the actual capture timing of the capture write 62, fine tuning can be applied as part of method 64. In step 78, the fine tuning process of method 64 is performed.

[0047] In step 78, the DQS signal 54 is adjusted by a negative step size (i.e., the DQS signal 54 is backed up by an amount less than the resolution of WICA, here less than one clock cycle, for example, a quarter clock (0.25tCK) or less). In step 80, a write command is issued, and in step 82 it is determined whether the write command is captured (as captured write 62). If the write command is captured (e.g., captured write 62 exists), then the DQS signal 54 is again adjusted by a value less than one clock cycle, and the process of steps 78, 80, and 82 is repeated until the write command is not captured (e.g., thereby capturing write signal 62 is almost (e.g., within 0.25tCK or less) not captured).

[0048] At this point, in step 84, a positive timing adjustment (e.g., tWL_ADJ_end) can be applied to the DQS signal 54. This step 68 can be performed at the end of the data stream to correct the timing, and can be performed, for example, in conjunction with the specifications of the memory device 10. It should be noted that tWL_ADJ_start in step 68 and tWL_ADJ_end in step 84 are intended to perform timing adjustments to move the IWS 58 capture from the boundary conditions (clock cycles) in which the IWS is captured. Therefore, tWL_ADJ_start in step 68 and tWL_ADJ_end in step 84 are used as buffer adjustments, and the amount of buffering applied can be user-set and / or can be part of the specifications of the memory device 10.

[0049] At this point, in step 86, the internal WL is exited. This step 86 includes setting the values ​​of mode register MR2.1 = 0, mode register MR2.7 = 1, and setting MR3.3:0 to a value indicating the WICA cycle determined from steps 72, 74, 76, and 77. In step 88, the entire write equalization operation is ended (completed). At this point, the DQS signal 54, set to the clock timing, may not have a phase of zero due to the buffers described above, for example, tWL_ADJ_start in step 68 and / or tWL_ADJ_end in step 84. Instead, the DQS signal 54 may have an offset (e.g., tDQSoffset) between half a clock cycle earlier (-0.5tCK) and half a clock cycle later (+0.5tCK), and is still within the tolerances or specifications of the memory device 10.

[0050] The following Figures 4 to 6 Describe examples of timing scenarios that may occur when the internal WL method 64 described above is implemented. For Figures 4 to 6There is a preamble setting (Wpre) for how many clock pulses (CLK) are transmitted before the input data. In this embodiment, the DQS signal 54 switches twice before the clock edge of the captured data (i.e., Wpre = 2). Similarly, for Figures 4 to 6 The clock rate (tCK) = 40 picoseconds (ps). Therefore, a quarter clock rate (0.25tCK) = 100ps. Similarly, for... Figures 4 to 6 The unit is tCK, unless otherwise specified.

[0051] Figure 4 The diagram illustrates the minimum boundary case 90 and maximum boundary case 92 for the DQS signal 54. Neither minimum boundary case 90 nor maximum boundary case 92 results in a final offset (e.g., tDQSoffset) outside the clock, which is half a clock ahead (-0.5tCK) or half a clock behind (+0.5tCK). As illustrated, a CLK clock waveform 94 exists in each of minimum boundary case 90 and maximum boundary case 92. Regarding minimum boundary case 90, at the end of the external WL (step 66), the DQS signal 54 and the clock are aligned (e.g., tDQSoffset is equal to or less than 0.1ps). Box 96 on the clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0052] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 102), DQS signal 54 and clock alignment are performed (e.g., tDQSoffset is equal to or less than 0.1 ps). In conjunction with waveform 104, DQS pulse 98 is subjected to a negative timing adjustment (as associated with step 68). This adjustment may be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the minimum boundary case 90, a given value of WICA, due to its incremental increase, almost (e.g., at 0.25tCK or less) misses the capture of the write command.

[0053] Once the write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 106. Waveform 106 illustrates that the fine-tuning process of method 64 is backed up by approximately 1 tCK (time 107) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 108, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25 tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 110 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 108 indicates that the final tDQSoffset is -0.5 tCK, i.e., the DQS signal 54 has an offset half a clock ahead of CLK.

[0054] Regarding the maximum boundary case 92, at the end of the outer WL (step 66), the DQS signal 54 and CLK are aligned (e.g., tDQSoffset is equal to or less than 0.1ps). Box 96 on the CLK clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0055] DQS pulse 98 has a falling edge 100 for capturing a write command. After the external WL (illustrated by waveform 102), DQS signal 54 and CLK are aligned (e.g., tDQSoffset is equal to or less than 0.1 ps). In conjunction with waveform 104, DQS pulse 98 is subjected to a negative timing adjustment (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the maximum boundary case 92, a given value of WICA is used because it almost (e.g., at 0.25tCK or less) captures the write command.

[0056] Once the write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 112. Waveform 112 illustrates that the fine-tuning process of method 64 is backed up by -0.1 ps (time 113) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 114, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 116 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 114 indicates that the final tDQSoffset is +0.5tCK, i.e., the DQS signal 54 has an offset that is half a clock later than CLK.

[0057] therefore, Figure 4 The boundary cases are described, whereby a given WICA value results in almost (e.g., within 0.25tCK or less) capture of the write command (maximum boundary case 92), which also results in a minimum fine-tuning process applied in conjunction with the internal WL. Other boundary cases describe a given WICA setting as almost (e.g., within 0.25tCK or less) missing capture of the write command (minimum boundary case 90), which results in an additional increment of the WICA value to allow capture of the write command and a corresponding large fine-tuning process applied in conjunction with the internal WL. However, if the DQS signal 54 and CLK are aligned after the external WL ends (e.g., tDQSoffset is equal to or less than 0.1ps) (step 66), then the final (result) offset for the boundary cases will be -0.5tCK and +0.5tCK (i.e., within the given specifications or tolerances of the memory device 10).

[0058] However, situations may arise where tWL_ADJ_start in step 68 and / or tWL_ADJ_end in step 84 cause the DQS signal 54 to have a phase mismatch with CLK greater than 0.5 cycles after training (e.g., phase alignment setting amount) (tDQSoffset > ±0.5tCK). For example, internal mismatches may occur from the external WL, where changes in voltage and temperature impair internal path matching. Similarly, resolution errors in the external WL may cause misalignment of the CLK and DQS signals 54. Similarly, internal WICA multiplexer errors may occur when the initiation of IWS 58 from the early CWK offset is changed from one WICA value to another, along with additional types and causes of errors. Figure 5 and 6 This section describes an example where an initial error or other error in the matching of the DQS signal 54 and CLK causes the DQS signal 54 to have a phase mismatch of more than 0.5 cycles with CLK after training (tDQSoffset > ±0.5tCK).

[0059] Figure 5The diagram illustrates minimum boundary case 118 and maximum boundary case 120 for the DQS signal 54, which result in a final offset (e.g., tDQSoffset) within half a clock cycle (-0.5tCK) before CLK but outside half a clock cycle (+0.5tCK) after CLK. As illustrated, a clock waveform 94 of CLK exists in each of minimum boundary case 118 and maximum boundary case 120. Regarding minimum boundary case 118, at the end of the external WL (step 66), the DQS signal 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0060] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 99), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). In conjunction with waveform 101, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the minimum boundary case 118, a given value of WICA almost misses capturing the write command because it is incremented.

[0061] Once the write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 122. Waveform 122 illustrates that the fine-tuning process of method 64 is backed up by approximately 1 tCK (time 123) until a failure boundary is determined (step 82). Thereafter, as illustrated by waveform 124, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25 tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 129 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 124 indicates that the final tDQS offset is -0.25 tCK, i.e., the DQS signal 54 has an offset of less than half a clock cycle earlier than CLK (i.e., within the given specifications or tolerances of the memory device 10).

[0062] Regarding the maximum boundary case 120, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in the minimum boundary case 118 (e.g., tDQSoffset is equal to approximately 100 ps). Box 96 on the clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0063] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 99), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). In conjunction with waveform 101, DQS pulse 98 is subjected to a negative timing adjustment (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the maximum boundary case 120, a given value of WICA almost captures the write command because it is incremented.

[0064] Once the write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 126. Waveform 126 illustrates that the fine-tuning process of method 64 is backed up by -0.1 ps (time 127) until a failure boundary is determined (step 82). Thereafter, as illustrated by waveform 128, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 125 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 128 indicates that the final tDQSoffset is +0.75tCK, i.e., the DQS signal 54 has a deviation of three-quarters of a clock cycle later than CLK (i.e., outside the given specifications or tolerances of the memory device 10). In this way, when applying method 64, an error occurs that causes the boundary conditions for the maximum boundary case 120 to fail.

[0065] Figure 6 The diagram illustrates minimum boundary case 130 and maximum boundary case 132 for the DQS signal 54. Minimum boundary case 130 and maximum boundary case 132 result in a final offset (e.g., tDQSoffset) that is half a clock ahead (-0.5tCK) but half a clock behind (+0.5tCK) of CLK. As illustrated, a clock waveform 94 of CLK exists in each of minimum boundary case 130 and maximum boundary case 132. Regarding minimum boundary case 130, at the end of the external WL (step 66), the DQS signal 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0066] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 103), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100 ps). In conjunction with waveform 105, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the minimum boundary case 130, a given value of WICA almost misses capturing the write command because it is incremented.

[0067] Once the write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 134. Waveform 134 illustrates that the fine-tuning process of method 64 is backed up by approximately 1 tCK (time 135) until a failure boundary is determined (step 82). Thereafter, as illustrated by waveform 136, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25 tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 138 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 136 indicates that the final tDQSoffset is -0.85 tCK, i.e., the DQS signal 54 has an offset greater than half a clock cycle earlier than CLK (i.e., outside the given specifications or tolerances of memory device 10). In this way, when applying method 64, an error causes the boundary conditions for minimum boundary case 130 to fail.

[0068] Regarding the maximum boundary case 132, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in the minimum boundary case 130 (e.g., tDQSoffset is equal to approximately -100ps). Box 96 on the clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0069] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 103), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100 ps). In conjunction with waveform 105, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the maximum boundary case 132, a given value of WICA almost captures the write command because it is incremented.

[0070] Once a write command is captured, the fine-tuning process of method 64 is performed (e.g., steps 78, 80, and 82), resulting in waveform 140. Waveform 140 illustrates that the fine-tuning process of method 64 is backed up by -0.1 ps (time 141) until a failure boundary is determined (step 82). Thereafter, as illustrated by waveform 142, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to illustrate the write command in block 144 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 142 indicates that the final tDQSoffset is +0.25tCK, i.e., the DQS signal 54 has a deviation of one-quarter of a clock cycle later than CLK (i.e., within the given specifications or tolerances of the memory device 10).

[0071] therefore, Figure 5 The description specifies boundary conditions (maximum boundary condition 120) for a given WICA value that result in near capture of a write command and also cause the DQS signal 54 to deviate from a given specification or tolerance of the memory device 10. Similarly, Figure 6 The description outlines a boundary condition (minimum boundary condition 130) with a given WICA setting that causes a missed capture write command and also causes the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10. To ensure that the boundary condition does not cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10, the following description is provided in conjunction with... Figure 7 A second embodiment of the internal WL is described.

[0072] Figure 7 A flowchart illustrating method 146 for performing an internal write loop (WL) in conjunction with another embodiment is provided. The internal WL process alters the clock cycle (CLK) in which write commands are shifted out of the DQS domain; that is, the internal WL controls the transmission of the IWS 58 from the IWA circuitry 48 so that the IWS 58 can be appropriately captured in the DQS domain. This method 146 can be performed, for example, by the IWA circuitry 48.

[0073] As shown, method 146 begins after the external write loop (WL) is completed in step 66. In step 68, a negative timing adjustment (e.g., tWL_ADJ_start) can be applied to the DQS signal 54. This step 68 can be performed at the end of the data stream to correct timing, and can be performed, for example, in conjunction with the specifications of memory device 10. In step 148, the internal write loop (e.g., internal write loop training mode) is started. In conjunction with step 148, one or more mode registers used in conjunction with the start of the internal write loop are set. For example, mode register MR2.1 (which applies to both the external and internal write loops) is set to (or kept at 1) 1. An additional mode register used is, for example, MR2.7 = internal write timing (write internal loop adjustment or "WICA" mode), which, when enabled (set to 1), will cause the IWS 58 to initiate earlier from the CAS-Write-Delay (CWL) offset of the IWA circuit system 48. The other mode register used is MR3.3:0 = WICA value (WICA is the loop number from which memory device 10 will initiate IWS earlier from the CWL offset). Another mode register, MR11.7 = WICAhalfStep (when enabled, this mode register allows the effective WICA to decrease by 0.5tCK). As explained in step 148, the above mode registers are initially set as follows: mode register MR2.1 = 1, mode register MR2.7 = 1, initial value for WICA = 0, and initial value for WICAhalfStep = 0.

[0074] In step 72, the mode register MR3.3:0 is set to the current WICA value, which in this case is 0, because this is the first time method 146 has been used. A write command is issued in step 74, and it is determined in step 76 whether the write command has been captured (as captured write 62). If no write command has been captured (e.g., captured write 62 does not exist), the WICA value is iteratively adjusted, for example, by one clock cycle (causing the IWA circuitry 48 to send IWS 58 one clock cycle earlier), and steps 72, 74, 76, and 77 are repeated until a write command (captured write 62 exists) is captured in step 726 using the adjusted WICA value. At this point, MR3.3:0 is set to a value indicating the current value of the WICA, i.e., the WICA value that initiates the timing of IWS 58 by the IWA circuitry 48. This process completes the coarse tuning of the internal WL.

[0075] In contrast to method 64, where the next step is step 78, method 146 moves to step 150 after coarse tuning of the internal WL is completed. Starting at step 150, it is determined whether a boundary condition (e.g., maximum boundary condition 120 or minimum boundary condition 130) exists that would cause the DQS signal 54 to deviate from a given specification or tolerance of the memory device 10 (and this determination is corrected). That is, method 146 includes a boundary condition detection and correction process. As part of this boundary condition detection and correction process, in step 150, the DQS signal 54 is reduced (i.e., negatively shifted) by a value, for example, one-quarter of the clock pulse of CLK (-0.25tCK). This step 150 initiates the boundary test portion of the boundary condition detection and correction process. In step 152, it is determined whether a write command is captured after shifting the DQS signal 54 by said value (-0.25tCK) to determine whether a given WICA nearly captures a write command, for example, in maximum boundary condition 120.

[0076] If no write command is captured in step 152, a near-boundary condition is determined, and in step 154, the DQS signal 54 is adjusted to a value of, for example, +0.25tCK (e.g., the opposite of the value used in step 150). Additionally, in step 154, the mode register MR11.7 is enabled (i.e., set to 1), which causes the mode register MR11.7 to allow an effective WICA decrease of 0.5tCK. Therefore, when WICA is incremented in step 154 ​​(i.e., WICA = WICA + 1), the net effect will be WICA = WICA + 0.5. This operation provides a correction to the value of WICA with finer resolution when a near-boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0077] In step 156, an integrity check is performed (i.e., to determine whether a write command is captured using a new, finer-resolution WICA value), and if a write command is captured, then the fine-tuning process of the internal WL begins at step 78. Alternatively, if no write command is captured in step 156, then the process ends at step 88 with the generation of an error signal.

[0078] Returning to step 152, if a write command is captured in step 152, then it is determined that the near-boundary condition does not exist. Therefore, method 146 proceeds to determine if a far boundary exists. In step 158, the DQS signal 54 is reduced (i.e., negatively shifted) by a set value, for example, half the clock pulse of CLK (-0.5tCK). This step 158 initiates the far-boundary test portion of the boundary condition detection and correction process. In step 160, it is determined whether a write command was captured after shifting the DQS signal 54 by a set value in conjunction with the previous negative value (i.e., -0.75tCK) from step 150, to determine whether the previous WICA for the given value nearly missed capturing a write command, for example, in minimum boundary case 130.

[0079] If a write command is captured in step 160, then a far boundary condition is determined, and in step 162, the DQS signal 54 is adjusted by, for example, a value of +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158). Additionally, in step 162, the mode register MR11.7 is enabled (i.e., set to 1), which causes the mode register MR11.7 to allow an effective WICA decrease of 0.5tCK. Therefore, when WICA is incremented in step 154, the net effect will be WICA = WICA - 0.5. This operation provides a correction for the value of WICA with finer resolution when a near boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0080] In step 156, an integrity check is performed (i.e., to determine whether a write command is captured using a new, finer-resolution WICA value), and if a write command is captured, then the fine-tuning process of the internal WL begins at step 78. Alternatively, if no write command is captured in step 156, then the process ends at step 88 with the generation of an error signal.

[0081] Returning to step 160, if no write command is captured, it is determined that no far boundary condition exists, and in step 164, the DQS signal 54 is adjusted to a value of, for example, +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158) without any corresponding adjustment to the original WICA value. An integrity check is then performed in step 156 (i.e., determining whether a write command was captured using the original WICA value), and if a write command is captured, the fine-tuning process of the internal WL begins at step 78. Alternatively, if no write command is captured in step 156, the process ends at step 88 with the generation of an error signal.

[0082] In this way, method 146 allows for the detection of boundary cases / conditions (e.g., maximum boundary case 120 and minimum boundary case 130) and the correction of the resulting DQS signal 54 with deviations outside a given specification or tolerance of the memory device 10 via modification of the WICA value (i.e., by allowing finer resolution by allowing changes to the WICA value of the resulting tDQSoffset). The following is about... Figure 8 and 9 This describes an example of a timing scenario that may occur when the internal WL method 146 is implemented.

[0083] Figure 8 The diagram illustrates the minimum boundary case 166, non-boundary case 168, and maximum boundary case 170 for the DQS signal 54. These cases, when implementing method 146, result in a final offset (e.g., tDQSoffset) within half a clock cycle (-0.5tCK) before the clock and within half a clock cycle (+0.5tCK) after the clock. It should be noted that minimum boundary case 166 is similar to minimum boundary case 118 but results in a different tDQSoffset, and maximum boundary case 170 is similar to maximum boundary case 120 but results in a different tDQSoffset due to the boundary detection and correction process of method 146. As illustrated, a clock waveform 94 of CLK exists in each of the minimum boundary case 166, non-boundary case 168, and maximum boundary case 170. Regarding minimum boundary case 166, at the end of the outer WL (step 66), the DQS signal 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0084] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 99), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). In conjunction with waveform 101, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the minimum boundary case 166, a given value of WICA almost misses capturing the write command because it is incremented.

[0085] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed, resulting in waveform 122. Waveform 122 illustrates that the fine-tuning process of method 64 is reversed by approximately 1tCK (time 123) until the failure boundary is determined (step 82). However, instead of generating waveform 122, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 172.

[0086] Proceed to step 152, and in this example, capture the write command. This results in the determination that no near-boundary condition exists. Therefore, the process (method 146) continues to determine if a far boundary exists. In conjunction with step 158, the DQS signal 54 is reduced (i.e., negatively shifted) by a set value, for example, half the clock pulse of CLK (-0.5tCK). This results in a DQS represented by waveform 174, which illustrates that the DQS signal 54 has been adjusted to the sum of the values ​​from step 150 and step 158 (e.g., -0.75tCK). The far-boundary test portion of the boundary condition detection and correction process is performed using waveform 174, and in step 160, it is determined whether waveform 174 is used to capture the write command.

[0087] In this example, the capture was successful. Therefore, a far boundary condition was determined, and in step 162, the DQS signal 54 was adjusted to a value of, for example, +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158). Additionally, in step 162, the mode register MR11.7 was enabled (i.e., set to 1), which caused the mode register MR11.7 to allow an effective WICA decrease of 0.5tCK. Therefore, when WICA is incremented in step 162 (i.e., WICA = WICA + 1), the net effect will be WICA = WICA + 0.5. This operation provides a correction for the value of WICA with finer resolution when a near boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0088] At this point, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 176. Waveform 176 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 177) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 178, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture a write command, illustrated in block 180 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 178 indicates that the final tDQSoffset is 0.25tCK, i.e., the DQS signal 54 has a deviation within a given specification or tolerance of the memory device 10.

[0089] Regarding non-boundary case 168, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in minimum boundary case 166 (e.g., tDQSoffset is equal to approximately 100 ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0090] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 99), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). In conjunction with waveform 101, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command.

[0091] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed, resulting in waveform 182. Waveform 182 illustrates that the fine-tuning process of method 64 is reversed by approximately 0.5tCK (time 183) until the failure boundary is determined (step 82). However, instead of generating waveform 182, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 172.

[0092] Proceed to step 152, and in this example, capture the write command. This results in the determination that no near-boundary condition exists. Therefore, the process (method 146) continues to determine if a far boundary exists. In conjunction with step 158, the DQS signal 54 is reduced (i.e., negatively shifted) by a set value, for example, half the clock pulse of CLK (-0.5tCK). This results in a DQS represented by waveform 174, which illustrates that the DQS signal 54 has been adjusted to the sum of the values ​​from step 150 and step 158 (e.g., -0.75tCK). The far-boundary test portion of the boundary condition detection and correction process is performed using waveform 174, and in step 160, it is determined whether waveform 174 is used to capture the write command.

[0093] In this example, capture is unsuccessful. Therefore, it is determined that no far boundary condition exists, and in step 164, the DQS signal 54 is adjusted to a value, for example, +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158), without any corresponding adjustment to the original WICA value. At this point, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 184. Waveform 184 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 185) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 186, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 188 (indicating the alignment edge of the DQS signal 54). The waveform 186 described indicates that the final tDQS offset is 0.25tCK, that is, the DQS signal 54 has a deviation within the given specifications or tolerances of the memory device 10.

[0094] Regarding the maximum boundary case 170, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in the minimum boundary case 166 (e.g., tDQSoffset is equal to approximately 100 ps). Box 96 on the clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0095] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 99), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately 100 ps). In conjunction with waveform 101, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command.

[0096] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed, resulting in waveform 126. Waveform 126 illustrates that the fine-tuning process of method 64 is reversed by -0.1 ps (time 127) until the failure boundary is determined (step 82). However, instead of generating waveform 126, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 172.

[0097] Step 152 is performed, and for this example, no write command is captured. This results in the determination of a near-boundary condition. Therefore, the process (method 146) proceeds to step 154 ​​and adjusts the DQS signal 54 by, for example, +0.25tCK (e.g., the opposite of the value used in step 150). Additionally, in step 154, the mode register MR11.7 is enabled (i.e., set to 1), which causes the mode register MR11.7 to allow the effective WICA to decrease by 0.5tCK. Therefore, when WICA is incremented in step 154 ​​(i.e., WICA = WICA + 1), the net effect will be WICA = WICA + 0.5. This operation provides a correction for the value of WICA with finer resolution when a near-boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0098] At this point, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 190. Waveform 190 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 191) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 192, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 194 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 208 indicates that the final tDQSoffset is 0.25tCK, i.e., the DQS signal 54 has a deviation within a given specification or tolerance of the memory device 10. This contrasts with the boundary case (maximum boundary case 120) described above, whereby a given WICA value results in a near capture of the write command and also causes the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10. In this way, method 146 operates to correct the deviation to allow proper operation within the given specifications or tolerances of the memory device 10 when facing the maximum boundary and the initially misaligned DQS signal 54 and CLK.

[0099] Figure 9 The diagram illustrates the minimum boundary case 196, non-boundary case 198, and maximum boundary case 200 for the DQS signal 54. These cases, when implementing method 146, result in a final offset (e.g., tDQSoffset) within half a clock cycle (-0.5tCK) before the clock and half a clock cycle (+0.5tCK) after the clock cycle (CLK). It should be noted that minimum boundary case 196 is similar to minimum boundary case 130 but results in a different tDQSoffset, and maximum boundary case 200 is similar to maximum boundary case 132 but results in a different tDQSoffset due to the boundary detection and correction process of method 146. As illustrated, a clock waveform 94 of CLK exists in each of the minimum boundary case 196, non-boundary case 198, and maximum boundary case 200. Regarding minimum boundary case 196, at the end of the outer WL (step 66), the DQS signal 54 and CLK are misaligned (e.g., tDQSoffset is equal to approximately -100ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0100] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 103), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100 ps). In conjunction with waveform 105, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command. Regarding the minimum boundary case 196, a given value of WICA almost misses capturing the write command because it is incremented.

[0101] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed, resulting in waveform 134. Waveform 134 illustrates that the fine-tuning process of method 64 is regressed by approximately 1tCK (time 135) until the failure boundary is determined (step 82). However, instead of generating waveform 134, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 202.

[0102] Proceed to step 152, and for this example, capture the write command. This results in the determination that no near-boundary condition exists. Therefore, the process (method 146) continues to determine if a far boundary exists. In conjunction with step 158, the DQS signal 54 is reduced (i.e., negatively shifted) by a set value, for example, half the clock pulse of CLK (-0.5tCK). This results in the DQS signal 54 represented by waveform 204, which illustrates that the DQS signal 54 has been adjusted to the sum of the values ​​from step 150 and step 158 (e.g., -0.75tCK). The far-boundary test portion of the boundary condition detection and correction process is performed using waveform 204, and in step 160, it is determined whether waveform 204 is used to capture the write command.

[0103] In this example, capture is successful. Therefore, a far boundary condition is determined, and in step 162, the DQS signal 54 is adjusted to a value of, for example, +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158). Additionally, in step 162, the mode register MR11.7 is enabled (i.e., set to 1), which causes the mode register MR11.7 to allow an effective WICA reduction of 0.5tCK. Therefore, when WICAhalfStep is enabled in step 162, the net effect will be WICA = WICA - 0.5. This operation provides a correction to the value of WICA with finer resolution when a near boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0104] At this point, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 206. Waveform 206 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 207) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 208, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 210 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 208 indicates that the final tDQSoffset is -0.35tCK, i.e., the DQS signal 54 has a deviation within a given specification or tolerance of the memory device 10. This contrasts with the boundary case (minimum boundary case 130) described above, where a given WICA value leads to a near miss of the capture write command and also causes the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10. In this way, method 146 operates to correct the deviation to allow proper operation within the given specifications or tolerances of the memory device 10 when faced with the minimum boundary and the initially misaligned DQS signal 54 and CLK.

[0105] Regarding non-boundary case 198, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in minimum boundary case 166 (e.g., tDQSoffset is equal to approximately 100 ps). Box 96 on clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0106] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 103), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100 ps). In conjunction with waveform 105, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command.

[0107] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed, resulting in waveform 212. Waveform 212 illustrates that the fine-tuning process of method 64 is reversed by approximately 0.5tCK (time 183) until the failure boundary is determined (step 82). However, instead of generating waveform 212, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 202.

[0108] Proceed to step 152, and for this example, capture the write command. This results in the determination that no near-boundary condition exists. Therefore, the process (method 146) continues to determine if a far boundary exists. In conjunction with step 158, the DQS signal 54 is reduced (i.e., negatively shifted) by a set value, for example, half the clock pulse of CLK (-0.5tCK). This results in the DQS signal 54 represented by waveform 204, which illustrates that the DQS signal 54 has been adjusted to the sum of the values ​​from step 150 and step 158 (e.g., -0.75tCK). The far-boundary test portion of the boundary condition detection and correction process is performed using waveform 204, and in step 160, it is determined whether waveform 204 is used to capture the write command.

[0109] In this example, capture is unsuccessful. Therefore, it is determined that no far boundary condition exists, and in step 164, the DQS signal 54 is adjusted to a value of, for example, +0.75tCK (e.g., the opposite of the sum of the values ​​used in steps 150 and 158) without any corresponding adjustment to the original WICA value. At this time, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 214. Waveform 214 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 215) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 216, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 218 (indicating the alignment edge of the DQS signal 54). The waveform 216 described indicates that the final tDQS offset is -0.25tCK, that is, the DQS signal 54 has a deviation within the given specifications or tolerances of the memory device 10.

[0110] Regarding the maximum boundary case 200, at the end of the outer WL (step 66), the DQS signal 54 and CLK are similarly misaligned as the DQS signal 54 and CLK in the minimum boundary case 166 (e.g., tDQSoffset is equal to approximately -100ps). Box 96 on the clock waveform 94 indicates the alignment edge (the falling edge of the preamble before the first data bit).

[0111] DQS pulse 98 has a falling edge 100 for capturing a write command. As previously described, after the external WL (illustrated by waveform 103), DQS signals 54 and CLK are misaligned (e.g., tDQSoffset equals approximately -100 ps). In conjunction with waveform 105, a negative timing adjustment is applied to DQS pulse 98 (as associated with step 68). This adjustment can be, for example, -0.75tCK. WICA is increased (in conjunction with steps 72, 74, 76, and 77) until the falling edge 100 of DQS pulse 98 captures the write command.

[0112] For illustrative purposes, the fine-tuning process of method 64 (e.g., steps 78, 80, and 82) is performed to obtain waveform 140. Waveform 140 illustrates that the fine-tuning process of method 64 is reversed by -0.1 ps (time 141) until the failure boundary is determined (step 82). However, instead of generating waveform 140, the DQS signal 54 is adjusted (step 150). The DQS signal 54 is reduced (i.e., negatively shifted) by a certain value, for example, one-quarter of the clock pulse of CLK (-0.25tCK), which produces waveform 202.

[0113] Step 152 is performed, and for this example, no write command is captured. This results in the determination of a near-boundary condition. Therefore, the process (method 146) proceeds to step 154 ​​and adjusts the DQS signal 54 by, for example, +0.25tCK (e.g., the opposite of the value used in step 150). Additionally, in step 154, the mode register MR11.7 is enabled (i.e., set to 1), which causes the mode register MR11.7 to allow the effective WICA to decrease by 0.5tCK. Therefore, when WICA is incremented in step 154 ​​(i.e., WICA = WICA + 1), the net effect will be WICA = WICA + 0.5. This operation provides a correction for the value of WICA with finer resolution when a near-boundary condition is detected, which would otherwise cause the DQS signal 54 to deviate from the given specifications or tolerances of the memory device 10.

[0114] At this point, the fine-tuning process of method 146 is performed (e.g., steps 78, 80, and 82), resulting in waveform 220. Waveform 220 illustrates that the fine-tuning process of method 64 is backed up by 0.5tCK (time 221) until the failure boundary is determined (step 82). Thereafter, as illustrated by waveform 222, a positive timing adjustment (e.g., tWL_ADJ_end) is applied to the DQS signal 54. As illustrated, this positive timing adjustment is +1.25tCK, and it causes the DQS pulse 98 to have its falling edge 100 used to capture the write command illustrated in block 224 (indicating the alignment edge of the DQS signal 54). The illustrated waveform 222 indicates that the final tDQSoffset is -0.25tCK, i.e., the DQS signal 54 has a deviation within a given specification or tolerance of the memory device 10.

[0115] like Figure 8 and 9 As demonstrated in the examples described herein, method 146 operates to implement a boundary condition detection and correction process, which allows the detection of boundary conditions (e.g., maximum boundary condition 170 and minimum boundary condition 196) and correction of the resulting DQS signal 54, which would otherwise have deviations outside the given specifications or tolerances of the memory device 10, via modification of the WICA value (i.e., by allowing a finer resolution by allowing changes to the WICA value of the resulting tDQSoffset). Figure 10 This describes a portion of the IWA circuit system 48 used in the implementation and / or execution of method 146.

[0116] Figure 10This is a schematic diagram of a CAS write delay (CWL) offset 226 as part of the IWA circuit system 48. The CWL offset 226 receives a CLK and a write command along path 228. CLK is transmitted as an input clock signal to multiple flip-flop circuits 230. The outputs of individual flip-flop circuit systems 230 are each transmitted to a corresponding multiplexer 232, whereby the multiplexer 232 is controlled via control signals generated by multiplexer control logic 234 and transmitted via multiplexer control bus 236. The multiplexer control logic 234 operates to generate control signals based on received inputs from the CWL mode register 238 and the WICA mode register 240, which may be MR3.3:0. In some embodiments, the CWL offset 226 may count clock cycles based on the settings of the CWL mode register 238. Additionally, the control signals are operable to select the transmission of the write command from one of the multiplexers 232 along path 242.

[0117] Additionally, CWL offset 226 includes an additional flip-flop 244 that receives the inverted (i.e., 180-degree out-of-phase) CLK as a clock control signal. The CWL offset also includes a WICAhalfstep mode register 246. WICAhalfstep mode register 246 can be, for example, mode register MR11.7, and when enabled, WICAhalfstep mode register 246 allows the effective WICA to decrease by 0.5tCK. The output of WICAhalfstep mode register 246 operates to control each of multiplexers 248 and 250. As illustrated, the output of WICAhalfstep mode register 246, when enabled, activates multiplexer 248, thereby allowing write commands from flip-flop 244 to be transmitted to buffer 252 for output from CWL offset 226 as IWS 58. For example, this occurs when the WICAhalfstep mode register 246 has been enabled (e.g., set to 1) in step 154 ​​or 162, thus altering the write command shifted out of the CWL offset 226 as the clock cycle of IWS 58. Similarly, the output of the WICAhalfstep mode register 246, when enabled, activates the multiplexer 250 (already via inverter 254), allowing the write command from path 242 to be transferred to buffer 252 as the output of the CWL offset 226 as IWS 58 (i.e., unaffected by the WICAhalfstep mode register 246, and therefore not requiring the combination as described above). Figure 7 Steps 154 and 162 describe changing the resolution of the WICA value.

[0118] While the invention can be readily presented in various modifications and alternatives, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it should be understood that the invention is not intended to be limited to the specific forms disclosed. Rather, the invention is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0119] The techniques proposed and claimed herein are referenced and applied to practical and concrete examples that significantly improve the technical field, and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements designated as “component for [performing a function]” or “step for [performing a function]”, then those elements are intended to be interpreted in accordance with 35U.SC112(f). However, for any claim containing elements designated in any other manner, such elements are not intended to be interpreted in accordance with 35U.SC112(f).

Claims

1. An internal write adjustment device, comprising: A mode register configured to transmit control signals based on stored indications in the mode register; and A multiplexer configured to receive the control signal and write command, wherein the multiplexer is configured to selectively transmit the write command based on the value of the control signal, wherein the mode register is configured to receive the memory indication to indicate whether the phase alignment between the internal data strobe (DQS) signal of the memory device and the clock of the memory device is outside a predetermined phase mismatch amount after the coarse tuning process of the internal write equalization (WL) of the internal write adjustment device.

2. The internal write adjustment device of claim 1, further comprising a second multiplexer configured to receive a second write command, wherein the second multiplexer is configured to selectively transmit the second write command.

3. The internal write adjustment device of claim 2, comprising an inverter coupled to the mode register and the second multiplexer, wherein the inverter is configured to receive the control signal and invert the control signal into an inverted control signal having a second value different from the value of the control signal, wherein the second multiplexer is configured to receive the inverted control signal and selectively transmit the second write command based on the second value of the inverted control signal.

4. The internal write adjustment device of claim 2, further comprising an output configured to transmit one of the write command and the second write command as an internal write signal IWS to capture a data signal DQ using the IWS.

5. The internal write adjustment device of claim 1, wherein the storage indication is set to a first value once a first boundary condition between the DQS signal and the clock is detected.

6. The internal write adjustment device of claim 5, wherein the storage indication is set to the first value once a second boundary condition between the DQS signal and the clock is detected.

7. The internal write adjustment device of claim 6, wherein the storage indication is set to a second value once neither the first boundary condition nor the second boundary condition is detected.

8. An internal write adjustment device, comprising: A mode register, configured to transmit control signals; and An internal write adjustment circuitry is configured to transmit a first write command based on the value of a control signal determined in response to the phase difference between the internal data strobe DQS signal and the clock signal of the memory device following a coarse tuning process of the internal write equalization WL of the internal write adjustment device.

9. The internal write adjustment device of claim 8, further comprising a second internal write adjustment circuitry configured to transmit a second write command based on the value of the control signal.

10. The internal write adjustment device of claim 9, wherein the internal write adjustment circuitry is configured to transmit the first write command when the value of the control signal includes a first value, wherein the second internal write adjustment circuitry is configured to transmit the second write command when the value of the control signal includes a second value.

11. The internal write adjustment device of claim 9, further comprising an output configured to transmit one of the first write command and the second write command as an internal write signal IWS to capture a data signal DQ using the IWS.

12. The internal write adjustment device of claim 8, wherein the mode register is configured to set the value of the control signal to a first value once a first boundary condition between the DQS signal and the clock signal is detected.

13. The internal write adjustment device of claim 12, wherein the mode register is configured to set the value of the control signal to the first value once a second boundary condition between the DQS signal and the clock signal is detected.

14. The internal write adjustment device of claim 13, wherein the mode register is configured to set the value of the control signal to a second value once neither the first boundary condition nor the second boundary condition is detected.

15. A method for a memory device, comprising: Determine the phase difference between the internal data strobe (DQS) signal and the clock signal of the memory device after the coarse tuning process of the internal write equalization (WL) of the internal write adjustment device of the memory device; The value of the control signal is set based on the determination of the phase difference between the internal DQS signal and the clock signal; The control signal is transmitted when the value includes the first value to control the transmission of the first write command.

16. The method of claim 15, further comprising transmitting the control signal to control the transmission of a second write command when the value includes a second value.

17. The method of claim 16, further comprising transmitting one of the first write command and the second write command as an internal write signal IWS to capture a data signal DQ using the IWS.

18. The method of claim 16, further comprising setting the value of the control signal to the first value once a first boundary condition between the DQS signal and the clock signal is detected.

19. The method of claim 18, further comprising setting the value of the control signal to the first value once a second boundary condition between the DQS signal and the clock signal is detected.

20. The method of claim 19, further comprising setting the value of the control signal to a second value once neither the first boundary condition nor the second boundary condition is detected.

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