Memory device and method for operating the same

Abstract

Embodiments of the present disclosure relate to memory devices and methods for operating memory devices. A memory device can perform various memory tests without increasing the size of the memory device. The memory device includes: a first pad for receiving external ROM data from a memory controller; a second pad for receiving an external clock signal corresponding to the external ROM data from the memory controller; and control logic connected to the first and second pads and configured to perform operations corresponding to the external ROM data in response to the external clock signal in a test mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2021-0015000, filed on February 2, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to an electronic device, and more particularly to a memory device and a method for operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device such as a computer or smartphone. A storage device may include a memory device for storing data and a memory controller for controlling the memory device. Memory devices are categorized as volatile memory devices and non-volatile memory devices.

[0005] A volatile memory device is a memory device in which data is stored only when power is supplied and the stored data disappears when power is interrupted. Volatile memory devices may include static random access memory (SRAM), dynamic random access memory (DRAM), and the like.

[0006] Non-volatile memory devices are memory devices in which data does not disappear even when power is interrupted. Non-volatile memory devices may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEROM), flash memory, etc. Summary of the Invention

[0007] Various embodiments of the present disclosure provide a memory device capable of performing various memory tests without increasing the size of the memory device, and an operating method of the memory device.

[0008] According to one aspect of the present disclosure, a memory device is provided, comprising: a first pad configured to receive external ROM data from a memory controller; a second pad configured to receive an external clock signal corresponding to the external ROM data from the memory controller; and control logic connected to the first pad and the second pad and configured to perform an operation corresponding to the external ROM data in response to the external clock signal in a test mode.

[0009] According to another aspect of the present disclosure, a method for operating a memory device is provided, the method comprising: receiving external ROM data from a memory controller through a first pad; receiving an external clock signal corresponding to the external ROM data from the memory controller through a second pad; and in response to a test mode, performing an operation corresponding to the external ROM data based on the external clock signal.

[0010] According to another aspect of the present disclosure, a memory device is provided, including: a ROM configured to store internal ROM data; a first pad configured to receive external ROM data from a memory controller; and control logic connected to the ROM and the first pad and configured to perform one of an operation corresponding to the internal ROM data and an operation corresponding to the external ROM data according to an operation mode.

[0011] According to another aspect of the present disclosure, a method for operating a memory device is provided, the method comprising: performing a first test operation on the memory device based on first test data in response to a first clock; and performing a second test operation on the memory device based on second test data in response to a second clock, wherein the first clock is generated from the memory device and the first test data is stored in a memory included in the memory device, and wherein the second clock and the second test data are provided externally. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Embodiments of the present disclosure will now be described more fully with reference to the accompanying drawings; however, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the embodiments to those skilled in the art.

[0013] In the accompanying drawings, dimensions may be exaggerated for clarity. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always refer to the same elements.

[0014] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0015] Figure 2 is a diagram illustrating an embodiment according to the present disclosure Figure 1 is a diagram of signals exchanged between a memory controller and a memory device shown in .

[0016] Figure 3 is a diagram illustrating an embodiment according to the present disclosure Figure 1 Schematic diagram of a memory device shown in .

[0017] Figure 4 is a diagram illustrating an embodiment according to the present disclosure Figure 3 Schematic diagram of an embodiment of a memory cell array shown in .

[0018] Figure 5 is a diagram illustrating an embodiment according to the present disclosure Figure 4 Circuit diagram of a memory block among the memory blocks shown in .

[0019] Figure 6 is a diagram illustrating an embodiment according to the present disclosure Figure 4 A circuit diagram of another embodiment of a memory block among the memory blocks shown in FIG.

[0020] Figure 7 is a diagram illustrating an embodiment according to the present disclosure Figure 4 A circuit diagram of yet another embodiment of a memory block among the memory blocks shown in .

[0021] Figure 8 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0022] Figure 9 is a diagram illustrating control logic according to an embodiment of the present disclosure.

[0023] Figure 10 is a diagram illustrating a ROM data receiver according to an embodiment of the present disclosure.

[0024] Figure 11 is a diagram illustrating a clock signal receiver according to an embodiment of the present disclosure.

[0025] Figure 12 is a timing diagram illustrating an operation corresponding to external ROM data according to an embodiment of the present disclosure.

[0026] Figure 13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0027] Figure 14 is a diagram illustrating an embodiment according to the present disclosure Figure 1 Schematic diagram of the memory controller shown in .

[0028] Figure 15 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0029] Figure 16 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0030] Figure 17is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] The specific structures or functions disclosed herein are merely for the purpose of describing the embodiments according to the concepts of the present disclosure. The embodiments according to the concepts of the present disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments set forth herein.

[0032] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0033] refer to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 for controlling the operation of the memory device 100. The storage device 50 may be a device for storing data under the control of a host 300, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0034] The storage device 50 may be manufactured as any of various types of storage devices according to a host interface as a communication scheme with the host 300. For example, the storage device 50 may be implemented with any of various types of storage devices such as a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a small size MMC (RS-MMC), a micro MMC (micro-MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card (SMC), a memory stick, etc.

[0035] The memory device 50 may be manufactured as any of various types of packages. For example, the memory device 50 may be manufactured as any of various types of packages such as package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer fabrication package (WFP), and wafer stacked package (WSP).

[0036] The memory device 100 may store data and may operate under the control of the memory controller 200. The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells for storing data.

[0037] Each memory cell can operate as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, and a quad-level cell (QLC) storing four data bits.

[0038] The memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. A memory block may include a plurality of pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0039] In one embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SDRAM, a low power DDR (LPDDR) SDRAM, a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a perpendicular NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for convenience of description, a case where the memory device 100 is a NAND flash memory is described.

[0040] The memory device 100 can receive a command CMD and an address ADDR from the memory controller 200 and access the area selected by the address ADDR in the memory cell array. The memory device 100 can perform the operation indicated by the command CMD on the area selected by the address ADDR. For example, the memory device 100 can perform a write operation (program operation), a read operation, and an erase operation. In a program operation, the memory device 100 can program data in the area selected by the address ADDR. In a read operation, the memory device 100 can read data from the area selected by the address ADDR. In an erase operation, the memory device 100 can erase data stored in the area selected by the address ADDR.

[0041] In one embodiment, the memory device 100 can be set to various operation modes, such as a normal mode and a test mode. The normal mode may be a mode in which general operations such as read operations, program operations, and erase operations are performed under the control of the memory controller 200. The test mode may be a mode in which test operations for checking various errors that may occur in the memory device 100 are performed. For example, the test mode may be activated after a power-on reset operation, after a reset operation of the memory device 100, or in response to a test operation request from the host 300.

[0042] The memory device 100 can perform operations based on various algorithms by using a ROM (not shown) and a microcontroller (not shown) included in the memory device 100. The memory device 100 can perform various tests on the memory device 100 based on ROM data stored in the ROM. Therefore, as the number of tests on the memory device 100 increases, the size of the ROM for storing ROM data corresponding to the tests increases. Therefore, a method of performing various tests on the memory device 100 without increasing the size of the memory device 100 may be needed.

[0043] In one embodiment, the memory device 100 may include a first pad 141 , a second pad 142 , and control logic 130 .

[0044] In one embodiment, each of the first pad 141 and the second pad 142 may be any one of pads (or pins) for exchanging signals between the memory device 100 and the memory controller 200 .

[0045] The first pad 141 can receive external ROM data from an external device (not shown). The external device may refer to a device connected to the memory device 100 to transmit data, signals, etc. For example, the first pad 141 can receive external ROM data from the memory controller 200. The external ROM data is data received from outside the memory device 100 and may include an algorithm for performing a test of the memory device 100, an algorithm for performing internal operations such as a program operation, a read operation, or an erase operation, etc. Based on the external ROM data provided from the external device, the memory device 100 can perform various additional tests on the memory device 100.

[0046] The second pad 142 may receive an external clock signal from an external device. For example, the second pad 142 may receive an external clock signal from the memory controller 200. The external clock signal may represent a trigger signal that allows execution of an operation corresponding to the external ROM data. For example, an operation corresponding to the external ROM data may be executed in response to the external clock signal.

[0047] The control logic 130 may be connected to the first pad 141 and the second pad 142. In addition, the control logic 130 may receive external ROM data from an external device through the first pad 141 and receive an external clock signal from the external device through the second pad 142. In one embodiment, in a test mode, the control logic 130 may perform an operation corresponding to the external ROM data in response to the external clock signal.

[0048] Therefore, according to an embodiment of the present disclosure, operations corresponding to ROM data received from an external device are performed by using the ROM data and a clock signal received from the external device, so that various memory tests can be performed without increasing the size of a memory device.

[0049] The memory controller 200 may control overall operations of the memory device 50 .

[0050] When power is applied to the memory device 50, the memory controller 200 may execute instructions, such as firmware (FW). When the memory device 100 is a flash memory device, the FW may include a host interface layer (HIL) for controlling communication with the host 300, a flash translation layer (FTL) for controlling communication between the host and the memory device 100, and a flash interface layer (FIL) for controlling communication with the memory device 100.

[0051] In one embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and convert the LBA into a physical block address (PBA), which represents the address of a memory cell included in the memory device 100 where the data is to be stored. In this specification, LBA and "logical address" or "logical address" may have the same meaning. In this specification, PBA and "physical address" may have the same meaning.

[0052] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. in response to a request from the host 300. In a program operation, the memory controller 200 may provide a program command, a PBA, and data to the memory device 100. In a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. In an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0053] In one embodiment, the memory controller 200 can autonomously generate commands, addresses, and data regardless of whether there is any request from the host 300, and transmit the commands, addresses, and data to the memory device 100. For example, the memory controller 200 can provide commands, addresses, and data to the memory device 100, which are used to perform read and program operations, along with performing wear leveling, read reclamation, garbage collection, etc.

[0054] In one embodiment, the memory controller 200 may control at least two memory devices 100. The memory controller 200 may control the memory devices according to an interleaving scheme to improve operation performance. The interleaving scheme may be a scheme for controlling operations on at least two memory devices 100 to overlap with each other.

[0055] The host 300 may communicate with the storage device 50 using at least one of various communication standards or interfaces, such as Universal Serial Bus (USB), Serial AT Attachment (SATA), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), FireWire, Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMediaCard (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM).

[0056] Figure 2 is a diagram illustrating an embodiment according to the present disclosure Figure 1 is a diagram of signals exchanged between a memory controller and a memory device shown in .

[0057] refer to Figure 2 , the memory device 100 can communicate with the memory controller 200 through an input / output (DQ) line, a chip enable (CE) line, a write enable (WE_N) line, a read enable (RE_N) line, an address latch enable (ALE) line, a command latch enable (CLE) line, a write protect (WP_N) line, and a ready / busy (RB) line.

[0058] exist Figure 2, a connection relationship between a memory device 100 and a memory controller 200 is illustrated. However, in some embodiments, the present disclosure may be equally applied to a connection relationship between a memory controller 200 and a plurality of memory devices. For example, an input / output (DQ) line, a chip enable (CE) line, a write enable (WE_N) line, a read enable (RE_N) line, an address latch enable (ALE) line, a command latch enable (CLE) line, a write protect (WP_N) line, and a ready / busy (RB) line may be included in one channel, and the memory controller 200 and the plurality of memory devices may be connected to each other through the corresponding channels. Therefore, when the memory controller 200 transmits a signal through a line included in one channel, all memory devices connected to the corresponding channel or a memory device selected by the memory controller 200 from among the memory devices connected to the corresponding channel may receive the signal.

[0059] The input / output (DQ) lines can input commands, addresses, and data to the memory device 100, or output data from the memory device 100 to the memory controller 200. The input / output (DQ) lines can be configured with 8 lines to transmit / receive 8-bit data, and each line can transmit / receive 1-bit data. However, the number of input / output (DQ) lines is not limited to 8 and can be expanded to 16 or 32 in various embodiments.

[0060] The chip enable (CE) line can transmit a chip enable (CE) signal as a signal indicating that operation of the memory device 100 is possible. The chip enable (CE) signal can be selectively applied to memory devices connected to the same channel. When the chip enable (CE) signal falls to low, the chip enable (CE) signal can indicate that all operations in the corresponding memory device 100 are possible. When the chip enable (CE) signal is high, the chip enable (CE) signal can indicate that the corresponding memory device 100 is in a standby state.

[0061] The memory device 100 may receive a read enable (RE_N) signal via a read enable (RE_N) line and a write enable (WE_N) signal via a write enable (WE_N) line. The read enable (RE_N) signal may be triggered when data is loaded into the memory controller 200, and the write enable (WE_N) signal may be triggered when a command and address are loaded into the memory device 100. When the write enable (WE_N) signal changes from low to high, i.e., at the rising edge of the write enable (WE_N) signal, the command and address may be input to the selected memory device 100. In another embodiment, when the write enable (WE_N) signal changes from high to low, i.e., at the falling edge of the write enable (WE_N) signal, the command and address may be input to the selected memory device 100.

[0062] The memory device 100 may receive a command latch enable (CLE) signal via a command latch enable (CLE) line. When a command CMD is input to the memory device 100, the command latch enable (CLE) signal may go high. In addition, the memory device 100 may receive an address latch enable (ALE) signal via an address latch enable (ALE) line. When an address is input to the memory device 100, the address latch enable (ALE) signal may go high.

[0063] The memory device 100 may receive a write protect (WP_N) signal through a write protect (WP_N) line. The write protect (WP_N) signal may be a signal for inactivating program and erase operations of a memory cell array.

[0064] When an operation is performed in the memory device 100, the ready / busy (RB) signal transmitted to the ready / busy (RB) line may have a low state. When the ready / busy (RB) signal is in a low state, the memory device 100 does not exchange any signals with the outside. When the ready / busy (RB) signal is high, the memory device 100 is in a ready state. When the memory device 100 is in the ready state, the memory device 100 may exchange signals with the outside.

[0065] Figure 3 is a diagram illustrating an embodiment according to the present disclosure Figure 1 Schematic diagram of a memory device 100 shown in FIG.

[0066] refer to Figure 3 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , a control logic 130 , a first pad 141 , a second pad 142 , a ROM 150 , and a clock signal generator 160 .

[0067] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a page buffer group 123 via bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include a plurality of pages.

[0068] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0069] Each of the memory cells included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0070] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, under the control of the control logic 130, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLm or discharge the applied voltages.

[0071] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0072] The row decoder 121 is connected to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines may include normal word lines and dummy word lines. In one embodiment, the row lines RL may also include pipe select lines.

[0073] The row decoder 121 operates under the control of the control logic 130. The row decoder 121 receives a row address RADD from the control logic 130.

[0074] The row decoder 121 decodes the row address RADD. The row decoder 121 selects at least one memory block from the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0075] For example, in a program operation, the row decoder 121 may apply a program voltage to a selected word line and apply a program pass voltage having a level different from (e.g., lower than) the program voltage to unselected word lines. In a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and apply a verification pass voltage having a level higher than the verification voltage to unselected word lines.

[0076] In a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level higher than the read voltage to unselected word lines.

[0077] In one embodiment, the erase operation of the memory device 100 is performed in units of memory blocks. During the erase operation, the row decoder 121 may select a memory block according to the decoded address. During the erase operation, the row decoder 121 may apply a reference voltage (e.g., a ground voltage) to a word line connected to the selected memory block.

[0078] The voltage generator 122 operates under the control of the control logic 130. The voltage generator 122 generates a plurality of voltages by using an external power supply voltage supplied to the memory device 100. Specifically, the voltage generator can generate various operating voltages Vop used in program, read, and erase operations in response to the operation signal OPSIG. For example, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0079] In one embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0080] In one embodiment, the voltage generator 122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage.

[0081] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors under the control of the control logic 130 .

[0082] The generated plurality of voltages may be supplied to the memory cell array 110 by the row decoder 121 .

[0083] The page buffer group 123 includes first to mth page buffers PB1 to PBm. The first to mth page buffers PB1 to PBm are connected to the memory cell array 110 through the first to mth bit lines BL1 to BLm, respectively. The first to mth page buffers PB1 to PBm operate under the control of the control logic 130. Specifically, the first to mth page buffers PB1 to PBm can operate in response to the page buffer control signal PBSIGNALS. For example, the first to mth page buffers PB1 to PBm can temporarily store data received through the first to mth bit lines BL1 to BLm, or sense the voltage or current of the bit lines BL1 to BLm during a read or verify operation.

[0084] Specifically, in a programming operation, when a programming voltage is applied to a selected word line, the first to mth page buffers PB1 to PBm can transmit the data DATA received through the input / output circuit 125 to the selected memory cell through the first to mth bit lines BL1 to BLm. The memory cells of the selected page are programmed according to the transmitted data DATA. The memory cells connected to the bit lines to which a programming enable voltage (e.g., a ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibit voltage (e.g., a power supply voltage) is applied can be maintained. In a program verification operation, the first to mth page buffers PB1 to PBm read page data from the selected memory cell through the first to mth bit lines BL1 to BLm.

[0085] In a read operation, the first to mth page buffers PB1 to PBm read data DATA from memory cells of a selected page through the first to mth bit lines BL1 to BLm and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124 .

[0086] In an erase operation, the first to mth page buffers PB1 to PBm may float the first to mth bit lines BL1 to BLm.

[0087] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may transfer data with the first to mth page buffers PB1 to PBm through the data lines DL, or transfer data with the input / output circuit 125 through the column lines CL.

[0088] The input / output circuit 125 can transmit the reference signal to the control logic 130. Figure 1The memory controller 200 described herein receives a command CMD and an address ADDR, or exchanges data DATA with the column decoder 124 .

[0089] In one embodiment, the input / output circuit 125 can be Figure 2 The input / output (DQ) lines shown in FIG. 1 receive a command CMD, an address ADDR, and data DATA input from the memory controller 200 , or output data DATA to the memory controller 200 .

[0090] In one embodiment, the input / output circuit 125 may be connected to the first pad 141. Figure 3 , a case is illustrated in which the first pad 141 is directly connected to the input / output circuit 125. However, in some embodiments, the first pad 141 may be directly connected to the control logic 130.

[0091] In a read operation or a verification operation, the sensing circuit 125 may generate a reference current in response to the enable bit VRYBIT signal and output a pass or fail signal PASS / FAIL by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0092] The control logic 130 can control the peripheral circuit 120 by outputting the operation signal OPSIG, the row address RADD, the page buffer control signal PBSIGNALS, and the enable bit VRYBIT in response to the command CMD and the address ADDR. In addition, the control logic 130 can determine whether the verification operation passes or fails in response to the pass signal PASS or the fail signal FAIL.

[0093] In one embodiment, the control logic 130 can be Figure 2 The input / output (DQ) line, chip enable (CE) line, write enable (WE_N) line, read enable (RE_N) line, address latch enable (ALE) line, command latch enable (CLE) line, write protect (WP_N) line and ready / busy (RB) line shown in the figure are used to receive the chip enable (CE) signal, the write enable (WE_N) signal, the read enable (RE_N) signal, the address latch enable (ALE) signal, the command latch enable (CLE) signal, the write protect (WP_N) signal and the ready / busy signal RB.

[0094] In one embodiment, the control logic 130 may be connected to the first pad 141 , the second pad 142 , the ROM 150 , and the clock signal generator 160 .

[0095] In one embodiment, control logic 130 may receive external ROM data O_RDATA from first pad 141. For example, control logic 130 may receive external ROM data O_RDATA from first pad 141 through input / output circuit 125. Control logic 130 may receive external clock signal O_CLOCK from second pad 142.

[0096] ROM 150 may store internal ROM data I_RDATA. The internal ROM data I_RDATA is data pre-stored in memory device 100 and may include an algorithm for performing a test of memory device 100 or an algorithm for performing internal operations such as a program operation, a read operation, or an erase operation. In one embodiment, control logic 130 may receive the internal ROM data I_RDATA from ROM 150.

[0097] The clock signal generator 160 may generate an internal clock signal I_CLOCK corresponding to the internal ROM data I_RDATA. The internal clock signal I_CLOCK may indicate a trigger signal that allows an operation corresponding to the internal ROM data I_RDATA to be performed. For example, an operation corresponding to the internal ROM data I_RDATA may be performed in response to the internal clock signal I_CLOCK. In one embodiment, the control logic 130 may receive the internal clock signal I_CLOCK from the clock signal generator 160.

[0098] Figure 4 is a diagram illustrating an embodiment according to the present disclosure Figure 3 Schematic diagram of an embodiment of a memory cell array shown in .

[0099] refer to Figure 4 , the memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate (not shown). The plurality of memory cells may be arranged along +X, +Y, and +Z directions. The structure of each memory block will be referred to as Figure 5 and Figure 6 Describe in more detail.

[0100] Figure 5 is a diagram illustrating an embodiment according to the present disclosure Figure 4 1 to 3. A circuit diagram of any one memory block BLKa among the memory blocks BLK1 to BLKz shown in FIG.

[0101] refer to Figure 5, the memory block BLKa may include a plurality of memory cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m memory cell strings are arranged in a row direction (i.e., +X direction). Figure 5 Two memory cell strings arranged in the column direction (ie, +Y direction) are illustrated. However, this is for convenience of description, and it is understood that three or more memory cell strings may be arranged in the column direction.

[0102] Each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0103] The select transistors SST and DST and the memory cells MC1 to MCn may have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer. In one embodiment, a pillar for providing a channel layer may be provided in each memory cell string. In one embodiment, a pillar for providing at least one of a channel layer, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer may be provided in each memory cell string.

[0104] The source select transistor SST of each memory cell string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0105] In one embodiment, source selection transistors of memory cell strings arranged on the same row are connected to a source selection line extending in the row direction, and source selection transistors of memory cell strings arranged on different rows are connected to different source selection lines. Figure 5 , the source selection transistors of the memory cell strings CS11 to CS1m on the first row are connected to the first source selection line SSL1. The source selection transistors of the memory cell strings CS21 to CS2m on the second row are connected to the second source selection line SSL2.

[0106] In another embodiment, the source selection transistors of the memory cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0107] The first to nth memory cells MC1 to MCn of each memory cell string are connected between a source select transistor SST and a drain select transistor DST.

[0108] The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged sequentially in a direction opposite to the +Z direction and are connected in series between the source select transistor SST and the pipe transistor PT. The (p+1)th to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and are connected in series between the pipe transistor PT and the drain select transistor DST. The first to pth memory cells MC1 to MCp and the (p+1)th to nth memory cells MCp+1 to MCn are connected via the pipe transistor PT. The gate electrodes of the first to nth memory cells MC1 to MCn of each memory cell string are connected to the first to nth word lines WL1 to WLn, respectively.

[0109] The gate of the pipe transistor PT of each memory cell string is connected to the pipe line PL.

[0110] The drain select transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The memory cell strings arranged in the row direction are connected to the drain select lines extending in the row direction. The drain select transistors of the memory cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of the memory cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0111] Memory cell strings arranged in the column direction are connected to bit lines extending in the column direction. Figure 5 , the memory cell strings CS11 and CS21 on the first column are connected to the first bit line BL1. The memory cell strings CS1m and CS2m on the m-th column are connected to the m-th bit line BLm.

[0112] Memory cells connected to the same word line in memory cell strings arranged in a row constitute a single page. For example, memory cells connected to the first word line WL1 in memory cell strings CS11 to CS1m on the first row constitute one page. Memory cells connected to the first word line WL1 in memory cell strings CS21 to CS2m on the second row constitute another page. When any one of drain select lines DSL1 and DSL2 is selected, memory cell strings arranged in a row can be selected. When any one of word lines WL1 to WLn is selected, a page can be selected in the selected memory cell string.

[0113] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be connected to odd bit lines, respectively.

[0114] In one embodiment, at least one memory cell among the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the reliability of the operation of the memory block BLKa is improved. On the other hand, the size of the memory block BLKa increases. When the number of dummy memory cells decreases, the size of the memory block BLKa decreases. On the other hand, the operational reliability of the memory block BLKa may deteriorate.

[0115] In order to efficiently control at least one dummy memory cell, the dummy memory cell may have a desired threshold voltage. Before or after an erase operation of the memory block BLKa, a programming operation may be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation is performed, the threshold voltage of the dummy memory cell controls the voltage applied to the dummy word line connected to the corresponding dummy memory cell so that the dummy memory cell has the desired threshold voltage.

[0116] Figure 6 is a diagram illustrating an embodiment according to the present disclosure Figure 4 FIG. 4 is a circuit diagram of another embodiment BLKb of a memory block among the memory blocks BLK1 to BLKz shown in FIG.

[0117] refer to Figure 6, the memory block BLKb may include a plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction. Each of the plurality of memory cell strings CS11' to CS1m' and CS21' to CS2m' includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST stacked on a substrate (not shown) below the memory block BLKb.

[0118] The source select transistor SST of each memory cell string is connected between a common source line CSL and memory cells MC1 to MCn. The source select transistors of the memory cell strings arranged on the same row are connected to the same source select line. The source select transistors of the memory cell strings CS11' to CS1m' arranged on the first row are connected to a first source select line SSL1. The source select transistors of the memory cell strings CS21' to CS2m' arranged on the second row are connected to a second source select line SSL2. In another embodiment, the source select transistors of the memory cell strings CS11' to CS1m' and CS21' to CS2m' can be connected in common to one source select line.

[0119] The first to nth memory cells MC1 to MCn of each memory cell string are connected in series between a source select transistor SST and a drain select transistor DST. Gate electrodes of the first to nth memory cells MC1 to MCn are connected to first to nth word lines WL1 to WLn, respectively.

[0120] The drain select transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the memory cell strings arranged in the row direction are connected to the drain select line extending in the row direction. The drain select transistors of the memory cell strings CS11' to CS1m' on the first row are connected to the first drain select line DSL1. The drain select transistors of the memory cell strings CS21' to CS2m' on the second row are connected to the second drain select line DSL2.

[0121] Therefore, in addition to Figure 6 In each memory cell string, except for the pipe transistor PT, Figure 6 The memory block BLKb has Figure 5 The circuit of the memory block BLKa is similar to the circuit.

[0122] In another embodiment, even bit lines and odd bit lines may be provided instead of the first to mth bit lines BL1 to BLm. In addition, even-numbered memory cell strings among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to even bit lines, respectively, and odd-numbered memory cell strings among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be connected to odd bit lines, respectively.

[0123] In one embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source select transistor SST and the memory cells MC1 to MCp. Alternatively, at least one dummy memory cell can be provided to reduce the electric field between the drain select transistor DST and the memory cells MCp+1 to MCn. When the number of dummy memory cells increases, the reliability of the operation of the memory block BLKb is improved. On the other hand, the size of the memory block BLKb increases. When the number of dummy memory cells decreases, the size of the memory block BLKb decreases. On the other hand, the operational reliability of the memory block BLKb may deteriorate.

[0124] In order to efficiently control at least one dummy memory cell, the dummy memory cell may have a desired threshold voltage. Before or after an erase operation of the memory block BLKb, a programming operation may be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation is performed, the threshold voltage of the dummy memory cell controls the voltage applied to the dummy word line connected to the corresponding dummy memory cell so that the dummy memory cell has the desired threshold voltage.

[0125] Figure 7 is a diagram illustrating an embodiment according to the present disclosure Figure 4 0 is a circuit diagram of yet another embodiment BLKi of a memory block among the memory blocks BLK1 to BLKz shown in FIG.

[0126] refer to Figure 7, in the memory block BLKi, a plurality of word lines arranged in parallel with each other may be connected between a first selection line and a second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block BLKi may include a plurality of memory cell strings ST connected between bit lines BL1 to BLm and a common source line CSL. The bit lines BL1 to BLm may be respectively connected to the memory cell strings ST, and the common source line CSL may be commonly connected to the memory cell strings ST. The memory cell strings ST may be configured identically to one another, and therefore, the memory cell string ST connected to the first bit line BL1 will be described in detail as an example.

[0127] The memory cell string ST may include a source select transistor SST, a plurality of memory cells MC1 to MC16, and a drain select transistor DST, which are connected in series between a common source line CSL and a first bit line BL1. At least one drain select transistor DST may be included in one memory cell string ST, and a greater number of source select transistors than the number of source select transistors SST shown in the figure and a greater number of memory cells than the number of memory cells MC1 to MC16 shown in the figure may be included in one memory cell string ST.

[0128] The source of the source select transistor SST may be connected to a common source line SL, and the drain of the drain select transistor DST may be connected to a first bit line BL1. Memory cells MC1 to MC16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different memory cell strings ST may be connected to a source select line SSL, and the gates of the drain select transistors DST included in different memory cell strings ST may be connected to a drain select line DSL. The gates of the memory cells MC1 to MC16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different memory cell strings ST may be referred to as a physical page PG. Therefore, a physical page PG corresponding to the number of word lines WL1 to WL16 may be included in a memory block BLKi.

[0129] A memory cell can store one bit of data. A memory cell is generally referred to as a single-level cell (SLC). A physical page PG can store one logical page (LPG) of data. One LPG of data can include data bits corresponding to the number of cells included in one physical page PG.

[0130] A memory cell can store two or more bits of data, and a physical page PG can store two or more LPG data.

[0131] Figure 8 is a diagram illustrating a memory device 100 according to an embodiment of the present disclosure.

[0132] Figure 8 The memory device 100 shown in FIG. Figure 2 The memory device 100 shown in FIG. Figure 8 The first pad 141, the second pad 142, the ROM 150 and the clock signal generator 160 shown in FIG. 1 may respectively represent Figure 3 1 , the first pad 141 , the second pad 142 , the ROM 150 , and the clock signal generator 160 are shown in FIG.

[0133] refer to Figure 8 , the memory device 100 may include a control logic 130 , a first pad 141 , a second pad 142 , a ROM 150 , and a clock signal generator 160 .

[0134] In one embodiment, the control logic 130 may receive a test command TEST_CMD from the memory controller 200. The test command TEST_CMD may be a command for activating the operation mode of the memory device 100 to the test mode. The control logic 130 may set the operation mode of the memory device 100 to the test mode in response to the test command TEST_CMD.

[0135] In one embodiment, the control logic 130 may receive the external ROM data O_RDATA from the first pad 141 . In addition, the control logic 130 may receive the external clock signal O_CLOCK from the second pad 142 .

[0136] The first pad 141 may receive the external ROM data O_RDATA from the memory controller 200 . The first pad 141 may transmit the external ROM data O_RDATA to the control logic 130 .

[0137] The second pad 142 may receive the external clock signal O_CLOCK corresponding to the external ROM data O_RDATA from the memory controller 200. The second pad 142 may transmit the external clock signal O_CLOCK to the control logic 130.

[0138] In one embodiment, each of the first pad 141 and the second pad 142 may be connected to a Figure 2, an input / output (DQ) line, a chip enable (CE) line, a write enable (WE_N) line, a read enable (RE_N) line, an address latch enable (ALE) line, a command latch enable (CLE) line, a write protect (WP_N) line, and a ready / busy (RB) line shown in . For example, the first pad 141 can be a pad connected to the input / output (DQ) line. That is, the first pad 141 can be an input / output (DQ) pad that receives data input from the memory controller 200 or outputs data to the memory controller 200. For example, the second pad 142 can be a pad connected to the read enable (RE_N) line. That is, the second pad 142 can be a read enable (RE_N) pad that receives a read enable (RE_N) signal from the memory controller 200.

[0139] In one embodiment, the control logic 130 may receive the internal ROM data I_RDATA from the ROM 150 . In addition, the control logic 130 may receive the internal clock signal I_CLOCK from the clock signal generator 160 .

[0140] In one embodiment, the control logic 130 may perform one of an operation corresponding to the internal ROM data I_RDATA and an operation corresponding to the external ROM data O_RDATA according to an operation mode of the memory device 100. For example, in a normal mode, the control logic 130 may perform an operation corresponding to the internal ROM data I_RDATA in response to the internal clock signal I_CLOCK. In another example, in a test mode, the control logic 130 may perform an operation corresponding to the external ROM data O_RDATA in response to the external clock signal O_CLOCK.

[0141] Figure 9 is a diagram illustrating control logic according to an embodiment of the present disclosure.

[0142] Figure 9 The control logic 900 shown in FIG. Figure 3 or Figure 8 In addition, the control logic 130 shown in FIG. Figure 9 The first pad 141, the second pad 142, the ROM 150 and the clock signal generator 160 shown in FIG. 1 may respectively represent Figure 3 or Figure 8 1 , the first pad 141 , the second pad 142 , the ROM 150 , and the clock signal generator 160 are shown in FIG.

[0143] refer to Figure 9 , the control logic 900 may include a test mode controller 910 , a ROM data receiver 920 , a clock signal receiver 930 , and a microcontroller 940 .

[0144] The test mode controller 910 may generate a test mode control signal MODE_SIG for activating a test mode. In one embodiment, the test mode may be activated in various situations, such as after a power-on reset operation, after a reset operation of the memory device 100, and in response to a test operation request from the host 300. For example, the test mode controller 910 may receive a test command from the memory controller 200. The test mode controller 910 may generate the test mode control signal MODE_SIG and transmit the test mode control signal MODE_SIG to the ROM data receiver 920 and the clock signal receiver 930. The ROM data receiver 920 and the clock signal receiver 930 may perform operations corresponding to the test mode in response to the test mode control signal MODE_SIG.

[0145] The ROM data receiver 920 may receive one of the internal ROM data I_RDATA and the external ROM data O_RDATA according to an operation mode of the memory device 100 .

[0146] In one embodiment, in the normal mode, the ROM data receiver 920 may receive the internal ROM data I_RDATA from the ROM 150. The ROM data receiver 920 may transmit the internal ROM data I_RDATA to the microcontroller 940.

[0147] Furthermore, in one embodiment, in the test mode, the ROM data receiver 920 may receive external ROM data O_RDATA from the memory controller 200 through the first pad 141. For example, the ROM data receiver 920 may receive the external ROM data O_RDATA through the first pad 141 in response to the test mode control signal MODE_SIG. The ROM data receiver 920 may transmit the external ROM data O_RDATA to the microcontroller 940.

[0148] The clock signal receiver 930 may receive one of the internal clock signal I_CLOCK and the external clock signal O_CLOCK according to an operation mode of the memory device 100 .

[0149] In one embodiment, in the normal mode, the clock signal receiver 930 may receive the internal clock signal I_CLOCK from the clock signal generator 160. The clock signal receiver 930 may transmit the internal clock signal I_CLOCK to the microcontroller 940.

[0150] Furthermore, in one embodiment, in the test mode, the clock signal receiver 930 may receive the external clock signal O_CLOCK from the memory controller 200 through the second pad 142. For example, the clock signal receiver 930 may receive the external clock signal O_CLOCK through the second pad 142 in response to the test mode control signal MODE_SIG. The clock receiver 930 may transmit the external clock signal O_CLOCK to the microcontroller 940.

[0151] According to a mode of operating the memory device 100 , the microcontroller 940 may perform an operation corresponding to the internal ROM data I_RDATA in response to the internal clock signal I_CLOCK or perform an operation corresponding to the external ROM data O_RDATA in response to the external clock signal O_CLOCK.

[0152] In one embodiment, in the normal mode, the microcontroller 940 may perform operations corresponding to the internal ROM data I_RDATA in response to the internal clock signal I_CLOCK.

[0153] Furthermore, in one embodiment, in the test mode, the microcontroller 940 may perform an operation corresponding to the external ROM data O_RDATA in response to the external clock signal O_CLOCK.

[0154] Therefore, according to an embodiment of the present disclosure, operations corresponding to ROM data are performed by using ROM data and a clock signal received from an external device, so that various memory tests can be performed without increasing the size of a memory device.

[0155] Figure 10 is a diagram illustrating a ROM data receiver 920 according to an embodiment of the present disclosure.

[0156] Figure 10 The ROM data receiver 920 shown in FIG. 1 may represent Figure 9 ROM data receiver 920 shown in FIG. In addition, Figure 10 The first pad 141, ROM 150, test mode controller 910 and microcontroller 940 shown in FIG. 1 may respectively represent Figure 9 The first pad 141, the ROM 150, the test mode controller 910 and the microcontroller 940 are shown in FIG.

[0157] refer to Figure 10 , the ROM data receiver 920 may include a first MUX 921 .

[0158] In one embodiment, the first MUX 921 may receive internal ROM data I_RDATA from the ROM 150 or external ROM data O_RDATA from the first pad 141. The first MUX 921 may output one of the internal ROM data I_RDATA and the external ROM data O_RDATA according to an operation mode.

[0159] For example, the first MUX 921 may receive a test mode control signal MODE_SIG from the test mode controller 910. The first MUX 921 may operate according to the test mode. Therefore, the first MUX 921 may output the external ROM data O_RDATA to the microcontroller 940 in response to the test mode control signal MODE_SIG.

[0160] In one embodiment, the microcontroller 940 may include an external ROM data latch 941 storing the external ROM data O_RDATA. The external ROM data latch 941 may store the external ROM data O_RDATA received from the first pad 141 through the ROM data receiver 920.

[0161] Figure 11 is a diagram illustrating a clock signal receiver 930 according to an embodiment of the present disclosure.

[0162] Figure 11 The clock signal receiver 930 shown in FIG. 1 may represent Figure 9 In addition, Figure 11 The second pad 142, the clock signal generator 160, the test mode controller 910 and the microcontroller 940 shown in FIG. 1 may respectively represent Figure 9 , the second pad 142 , the clock signal generator 160 , the test mode controller 910 , and the microcontroller 940 shown in FIG.

[0163] refer to Figure 11 , the clock signal receiver 930 may include a second MUX 931 .

[0164] In one embodiment, second MUX 931 may receive internal clock signal I_CLOCK from clock signal generator 160 or external clock signal O_CLOCK from second pad 142. Second MUX 931 may output one of internal clock signal I_CLOCK and external clock signal O_CLOCK according to an operation mode.

[0165] For example, the second MUX 931 may receive a test mode control signal MODE_SIG from the test mode controller 910. The second MUX 931 may operate according to the test mode. Therefore, the second MUX 931 may output the external clock signal O_CLOCK to the microcontroller 940 in response to the test mode control signal MODE_SIG.

[0166] In one embodiment, the microcontroller 940 may perform an operation corresponding to the external ROM data O_RDATA stored in the external ROM data latch 941 in response to the external clock signal O_CLOCK.

[0167] Figure 12 is a timing diagram illustrating an operation corresponding to external ROM data according to an embodiment of the present disclosure.

[0168] exist Figure 12 , the first pad 141 is an input / output (DQ) pad receiving a signal of an input / output (DQ) line, and the second pad 142 is a read enable (RE_N) pad receiving a read enable (RE_N) signal.

[0169] refer to Figure 12 , illustrates signals of an input / output (DQ) line, a signal ROMDATA LATCH of an external ROM data latch 941, a read enable (RE_N) signal, and an external clock signal O_CLOCK.

[0170] The memory device 100 may receive external ROM data ROM DATA1 to ROM DATA4 from the outside through input / output (DQ) lines. In addition, the external ROM data ROM DATA1 to ROM DATA4 may be stored in the external ROM data latch 941.

[0171] Subsequently, the memory device 100 can receive the external clock signal O_CLOCK when the read enable (RE_N) signal is low. For example, when the read enable (RE_N) signal changes from a high state to a low state, the external clock signal O_CLOCK can be activated to a high state at T1. At T1, the memory device 100 can perform an operation corresponding to the first external ROM data ROM DATA1 stored in the external ROM data latch 941. In addition, when the read enable (RE_N) signal changes from a high state to a low state, the external clock signal O_CLOCK can be activated to a high state at T2. At T2, the memory device 100 can perform an operation corresponding to the second external ROM data ROM DATA2 stored in the external ROM data latch 941. In addition, when the read enable (RE_N) signal changes from a high state to a low state, the external clock signal O_CLOCK can be activated to a high state at T3. At T3 , the memory device 100 may perform an operation corresponding to the third external ROM data ROM DATA3 stored in the external ROM data latch 941 .

[0172] In addition, although Figure 12 , the memory device 100 receives the external clock signal O_CLOCK when the read enable (RE_N) signal is low, but the present disclosure is not limited thereto. In one embodiment, the memory device 100 may receive the external clock signal O_CLOCK when the read enable (RE_N) signal is high. When the read enable (RE_N) signal changes from a low state to a high state, the external clock signal O_CLOCK may be activated to a high state.

[0173] Figure 13 is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure.

[0174] Figure 13 The method of operation shown in can be performed by, for example Figure 2 or Figure 8 1. The memory device 100 shown in FIG.

[0175] refer to Figure 13 , in operation S1301 , the memory device 100 may generate a test mode control signal for activating a test mode of the memory device 100 .

[0176] In operation S1303, the memory device 100 may receive external ROM data from the memory controller 200 through the first pad. For example, the memory device 100 may receive the external ROM data through the first pad in response to a test mode control signal.

[0177] In operation S1305 , the memory device 100 may store external ROM data.

[0178] In operation S1307, the memory device 100 may receive an external clock signal corresponding to the external ROM data from the memory controller 200 through the second pad. For example, the memory device 100 may receive the external clock signal through the second pad in response to the test mode control signal.

[0179] In operation S1309 , the memory device 100 may perform an operation corresponding to the external ROM data based on the external clock signal in response to the test mode.

[0180] Figure 14 is a diagram illustrating an embodiment according to the present disclosure Figure 1 Schematic diagram of the memory controller shown in .

[0181] refer to Figure 1 and Figure 14 , the memory controller 200 may include a processor 220 , a RAM 230 , an error correction circuit 240 , a ROM 250 , a host interface 270 , and a flash memory interface 280 .

[0182] The processor 220 may control the overall operation of the memory controller 200. The RAM 230 may be used as a buffer memory, a cache memory, a working memory, etc. of the memory controller 200.

[0183] The error correction circuit 240 may perform error correction. The error correction circuit 240 may perform error correction code (ECC) encoding on data to be written to the memory device via the flash memory interface 280. The ECC-encoded data may be transmitted to the memory device via the flash memory interface 280. The error correction circuit 240 may perform ECC decoding on data received from the memory device via the flash memory interface 280. As an example, the error correction circuit 240 may be included in the flash memory interface 280 as a component of the flash memory interface 280.

[0184] ROM 260 may store various information for the operation of memory controller 200 in the form of firmware. In one embodiment, ROM 260 may represent Figure 2 or Figure 8 The different components of ROM 150 are shown in FIG.

[0185] The memory controller 200 may communicate with an external device (eg, the host 300 , an application processor, etc.) through the host interface 270 .

[0186] The memory controller 200 can communicate with the memory device 100 through the flash interface 280. The memory controller 200 can transmit commands, addresses, control signals, etc. to the memory device 100 and receive data DATA through the flash interface 280. For example, the flash interface 280 may include a NAND interface.

[0187] Figure 15 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0188] refer to Figure 15 , the memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0189] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the read, write, erase, and background operations of the memory device 2200. The memory controller 2100 provides an interface between the memory device 2200 and the host. The memory controller 2100 drives the firmware for controlling the memory device 2200. The memory controller 2100 can communicate with the reference Figure 1 The memory controller 200 described in the embodiment of the present invention is identically implemented. The memory device 2200 can be implemented in the same manner as the memory controller 200 described in the embodiment of the present invention. Figure 2 The memory device 100 described is implemented identically.

[0190] As an example, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an ECC circuit.

[0191] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) according to a specific communication protocol. As an example, the memory controller 2100 can communicate with an external device through at least one of various communication standards or interfaces, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 can be defined by at least one of the various communication standards or interfaces mentioned above.

[0192] As an example, the memory device 2200 may be implemented using various non-volatile memory devices, such as electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0193] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a Compact Flash (CF) card, a Smart Media Card (SM and SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a Universal Flash Storage (UFS).

[0194] Figure 16 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0195] refer to Figure 16 , an SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals with the host 3100 through a signal connector 3001 and receives power through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0196] In one embodiment, the SSD controller 3210 may be used as a reference Figure 1 The memory controller 200 is described.

[0197] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to signals received from the host 3100. As an example, the signals may be signals based on an interface between the host 3100 and the SSD 3200. For example, the signals may be signals defined by at least one of the following communication standards or interfaces: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0198] The auxiliary power supply 3230 is connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can receive power PWR input from the host 3100 and charge the power PWR. When the power supply from the host 3100 is not smooth, the auxiliary power supply 3230 can provide power to the SSD 3200. For example, the auxiliary power supply 3230 can be located in the SSD 3200 or external to the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0199] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0200] Figure 17 is a block diagram illustrating a user system to which a storage device is applied according to an embodiment of the present disclosure.

[0201] refer to Figure 17 , the user system 4000 includes an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 and a user interface 4500 .

[0202] The application processor 4100 may drive components, an operating system (OS), user programs, and the like included in the user system 4000. As an example, the application processor 4100 may include a controller, an interface, a graphic engine, and the like for controlling the components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0203] Memory module 4200 can operate as a main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. As an example, application processor 4100 and memory module 4200 may be packaged based on a package-on-package (PoP) and provided as one semiconductor package.

[0204] The network module 4300 can communicate with external devices. As an example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. As an example, the network module 4300 can be included in the application processor 4100.

[0205] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit the data stored therein to the application processor 4100. For example, the storage module 4400 can be implemented using a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory having a three-dimensional structure. For example, the storage module 4400 can be provided as a removable drive such as a memory card or an external drive of the user system 4000.

[0206] As an example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be associated with a reference Figure 1 The memory device 100 described in the foregoing description operates identically. The memory module 4400 may be used with reference to Figure 1 The described storage devices 50 operate identically.

[0207] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. As an example, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyroscope sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0208] According to the present disclosure, a memory device capable of performing various memory tests without increasing the size of the memory device and an operating method of the memory device can be provided.

[0209] Although the present disclosure has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described embodiments, but should be determined not only by the appended claims but also by their equivalents.

[0210] In the above-described embodiments, all operations may be selectively performed or some operations may be omitted. In each embodiment, the operations are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. In other words, it will be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0211] In addition, embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, they are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments and many variations are possible within the spirit and scope of the present disclosure. It should be clear to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A memory device comprising: a first pad configured to receive external ROM data from a memory controller, the external ROM data being received from outside the memory device; a second pad configured to receive an external clock signal corresponding to the external ROM data from the memory controller, the external clock signal being received from outside the memory device; as well as The control logic is connected to the first pad and the second pad and is configured to perform an operation corresponding to the external ROM data in synchronization with the external clock signal in a test mode.

2. The memory device of claim 1 , wherein the control logic comprises: a test mode controller configured to generate a test mode control signal for activating the test mode; as well as The microcontroller is configured to execute the operation corresponding to the external ROM data in response to the external clock signal. 3 . The memory device of claim 2 , wherein the control logic further comprises a ROM data receiver configured to receive the external ROM data through the first pad in response to the test mode control signal. 4 . The memory device of claim 3 , wherein the microcontroller comprises an external ROM data latch configured to store the external ROM data. 5 . The memory device of claim 2 , wherein the control logic further comprises a clock signal receiver configured to receive the external clock signal through the second pad in response to the test mode control signal. 6 . The memory device of claim 1 , wherein the first pad is an input / output pad that receives data input from the memory controller or outputs the data to the memory controller. 7 . The memory device of claim 1 , wherein the second pad is a read enable pad that receives a read enable signal from the memory controller.

8. A method for operating a memory device, the method comprising: receiving external ROM data from a memory controller through a first pad, the external ROM data being received from outside the memory device; receiving an external clock signal corresponding to the external ROM data from the memory controller through a second pad, the external clock signal being received from outside the memory device; as well as In response to a test mode, an operation corresponding to the external ROM data is performed in synchronization with the external clock signal. 9 . The method of claim 8 , further comprising generating a test mode control signal for activating the test mode. 10 . The method of claim 9 , wherein in the receiving of the external ROM data, the external ROM data is received in response to the test mode control signal.

11. The method of claim 10, further comprising storing the external ROM data. 12 . The method of claim 9 , wherein in receiving the external clock signal, the external clock signal is received in response to the test mode control signal. 13 . The method according to claim 8 , wherein the first pad is an input / output pad that receives data input from the memory controller or outputs the data to the memory controller. 14 . The method of claim 8 , wherein the second pad is a read enable pad that receives a read enable signal from the memory controller.

15. A memory device comprising: ROM, configured to store internal ROM data; a clock signal generator configured to generate an internal clock signal corresponding to the internal ROM data; a first pad configured to receive external ROM data from a memory controller; a second pad configured to receive an external clock signal corresponding to the external ROM data from the memory controller; as well as The control logic is connected to the ROM, the clock signal generator, the first pad, and the second pad, and is configured to perform one of an operation corresponding to the internal ROM data and an operation corresponding to the external ROM data according to an operation mode.

16. The memory device of claim 15, wherein the control logic comprises: a ROM data receiver configured to receive one of the internal ROM data and the external ROM data according to the operation mode; a clock signal receiver configured to receive one of the internal clock signal and the external clock signal according to the operation mode; as well as The microcontroller is configured to: execute the operation corresponding to the internal ROM data in response to the internal clock signal, or execute the operation corresponding to the external ROM data in response to the external clock signal according to the operation mode. 17 . The memory device of claim 16 , wherein the control logic further comprises a test mode controller configured to generate a test mode control signal for activating a test mode.

18. The memory device according to claim 17, wherein the ROM data receiver receives the external ROM data through the first pad in response to the test mode control signal, and The clock signal receiver receives the external clock signal through the second pad in response to the test mode control signal.

19. The memory device of claim 18, wherein the microcontroller comprises an external ROM data latch configured to store the external ROM data.

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