Error avoidance based on voltage distribution parameters

Abstract

This application relates to error avoidance based on voltage distribution parameters. A method can include receiving a request to read data from a memory cell of a memory device coupled with a processing device, determining a voltage distribution parameter value associated with the memory cell, determining a set of read levels associated with the voltage distribution parameter value, where each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, and reading data from the memory cell using the determined set of read levels. The voltage distribution parameter value can be determined by identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels, and determining the voltage distribution parameter value based on the particular voltage distribution. The voltage distribution parameter value can be a voltage value included in the particular voltage distribution.

Description

Technical Field

[0001] The embodiments of this disclosure generally relate to memory subsystems, and more specifically to error avoidance using characteristics of voltage distribution. Background Technology

[0002] A memory subsystem may include one or more memory devices for storing data. These memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] In one aspect, this application provides a method comprising: receiving, by a processing device, a request to read data from a memory cell of a memory device coupled to the processing device; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a corresponding voltage distribution of the memory cell; and reading data from the memory cell of the memory device using the determined set of read levels.

[0004] In another aspect, this application provides a system comprising: a memory; and a processing means communicatively coupled to the memory, the processing means performing operations including: receiving a request to read data from a memory cell of the memory device coupled to the processing means; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a corresponding voltage distribution of the memory cell; and reading data from the memory cell of the memory device using the determined set of read levels.

[0005] In another aspect, this application provides a non-transitory machine-readable storage medium for storing instructions that cause a processing device to perform operations including: receiving a request from a memory cell of a memory device coupled to the processing device; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a corresponding voltage distribution of the memory cell; and reading data from the memory cell of the memory device using the determined set of read levels. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for illustration and understanding only.

[0007] Figure 1 Examples of computing systems including a memory subsystem are shown according to some embodiments of the present disclosure.

[0008] Figure 2 The illustration schematically depicts time-voltage shifts caused by the slow charge loss exhibited by a three-level memory cell, according to some embodiments of the present disclosure.

[0009] Figure 3 The diagram schematically illustrates the distributed voltage corresponding to specific characteristics of the voltage distribution according to some embodiments of the present disclosure, as well as the voltage distribution and the change of the distributed voltage over time.

[0010] Figure 4A and 4B An example of reading a level manager component according to some embodiments of this disclosure is described.

[0011] Figure 5A This is a flowchart of an example method for determining a read level based on the distributed voltage of a memory cell and reading data using the determined read level, according to aspects of this disclosure.

[0012] Figure 5B This is a flowchart of an example method for determining a read level based on the distributed voltage of a block and reading data using the determined read level, according to aspects of this disclosure.

[0013] Figure 6 This is a flowchart of an example method for performing a distributed voltage calibration scan according to aspects of this disclosure to determine the distributed voltage of a block and store the distributed voltage in a block metadata table.

[0014] Figure 7 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0015] This disclosure relates to error avoidance in memory devices using voltage distribution parameters, such as voltage corresponding to the voltage distribution and its change over time as the voltage distribution is attributed to slow charge loss. The memory subsystem may be a memory device, a memory module, or a combination of both. The following is in conjunction with… Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0016] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states related to the number of bits being stored. Logic states may be represented by binary values ​​(e.g., “0” and “1”) or combinations of these values.

[0017] Data operations can be performed by the memory subsystem. Data operations can be initiated by the host. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem and to read data from a memory device on the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) can be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction codes (ECC), parity check codes), data version (e.g., to distinguish between new and old data being written), a valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0018] A memory device comprises multiple memory cells, each of which may store one or more bits of information, depending on the type of memory cell. A memory cell can be programmed (written to) by applying a voltage to it, which causes the memory cell to retain a charge, thereby allowing modulation of the voltage distribution generated by the memory cell. Furthermore, precise control over the amount of charge stored in a memory cell allows the use of multiple threshold voltage levels corresponding to different logic levels. Multiple threshold levels allow a single memory cell to store multiple bits of information: using 2... n A memory cell operating at different threshold voltage levels can store n bits of information. Therefore, a read operation can be performed by comparing the measured voltage exhibited by the memory cell with one or more threshold voltage levels to distinguish between two logic levels of a single-level cell and multiple logic levels of a multi-level cell.

[0019] In this document, "block" refers to a set of contiguous or non-contiguous memory pages. An example of a "block" is an "erasable block," which is the smallest erasable unit of memory, while a "page" is the smallest writable unit of memory. Each page contains a set of memory cells. A memory cell is an electronic circuit that stores information. "Superblock" in this document refers to a set of blocks that span multiple dies written in an interleaved manner. In some cases, a superblock may span all dies within a storage device, such as an SSD. A superblock may contain multiple blocks from a single die, for example, one per plane. Drives typically manage data erasure and programming on a superblock basis.

[0020] "Read level" will refer to the voltage level in this document. The read levels are numbered L1 to 2 in ascending order of voltage. n , where n is the number of bits that can be stored in the cell. As an example, for a three-level cell (TLC) corresponding to 3 bits per cell, there can be 8 threshold distributions (levels), and 7 read thresholds (read threshold voltages) can be used to distinguish between levels. "Read level value" will refer herein to a voltage or digital-to-audio converter (DAC) value, representing the voltage applied to the read element (typically the control gate for a NAND cell) for the purpose of reading the cell. "Read level offset" will refer herein to the components of the equation that determines the read level value. Read level offsets can be summed (e.g., read level value = offset_a + offset_b + ...). "Read level base" will refer herein to one of the read level offsets. For example, the read level base can be stored in the metadata of the memory device. Each read level can correspond to one of the threshold levels described above. "Calibration" will refer herein to changing the read level value (possibly by adjusting the read level offset or read level base) to better match the ideal read level used for reading or a set of reads.

[0021] A write operation stores a logic value, such as zero or one, in a memory cell by applying a "programming" voltage corresponding to the logic value to the write gate of the memory cell. A read operation is performed by applying a read voltage to the control gate of the memory cell and determining whether the read voltage is sufficient to overcome the voltage stored at the cell. As an example, in a single-level cell, a first voltage level (e.g., 0 volts) may correspond to logic one, and a second voltage level (e.g., 3 volts) may correspond to logic zero. Logic zero can be stored by applying 3 volts to the write gate, and logic one corresponds to an erase distribution, which in this example corresponds to 0 volts. To read the cell, a voltage can be applied to the control gate of the cell. If the applied read voltage causes the transistor to conduct, the voltage stored in the cell is less than the applied voltage. Therefore, a voltage between the first and second voltage levels can then be applied to the control gate to determine whether logic zero or one is stored in the cell. For example, if 1.5 volts are applied to the control gate and the cell threshold voltage is 3 volts (logic zero), the transistor does not conduct (because the applied 1.5 volts cannot overcome the written 3 volts), and the stored value is determined to be logic zero. Alternatively, if the cell threshold voltage is 0 volts (logic one) and 1.5 volts are applied to the control gate, the transistor conducts (because the applied 1.5 volts overcome the written volts), thereby indicating logic one.

[0022] As discussed above, n information bits can be stored in memory cells using multiple voltage levels. A read voltage level can be understood as corresponding to a valley between two voltage distributions, as described below. The read voltage level can be between two threshold voltages, each of which separates the voltage level from the other. To store n information bits, 2... n Threshold distribution (level). To read 2 n Two threshold distributions can be established to create 2 n-1 read threshold (read value). For example, to store two information bits that can represent four different logic values, the corresponding threshold voltages could be 1 volt, 2 volts, and 3 volts. A specific logic value can be stored in the cell by applying a programming voltage level corresponding to the logic value to the cell's write gate. Then, to read the two information bits from the cell, three operations can be performed to identify the voltage that overcomes the voltage stored in the cell: apply 0.5 volts to the control gate and read (e.g., by determining if the transistor is conducting), apply 1.5 volts and read, and apply 2.5 volts and read. The result can be used to determine the values ​​of the two logic bits. If applying 0.5 volts causes the transistor to conduct, then 0.5 volts has overcome the written voltage, so the written voltage is 0 volts (e.g., logic zero). Similarly, if applying 1.5 volts causes the transistor to conduct, then the written voltage is 1 volt (e.g., logic one), and the threshold voltage is 1.5 volts. If applying 2.5 volts causes the transistor to conduct, then the written voltage is 2 volts (e.g., logic three). Otherwise, the written voltage is 3 volts (e.g., logic 2). During writing, the voltage applied to the write gate is inaccurate and traverses a distribution of voltages that can be represented as near each of the programming voltage levels across several memory cells. Therefore, in a cell that can be interpreted as representing the voltage of two bits, there are four corresponding threshold voltage distributions. Each distribution can be understood as a curve with a peak representing the highest probability of occurrence at the corresponding programming voltage level. Each voltage distribution may have a decreasing probability of occurrence to the left and right of the peak. The probability of occurrence may decrease towards a minimum value, which is close to 0 at voltages to the left and right of the peak (below and above the programming voltage level). The voltage of the minimum probability of occurrence may correspond to the threshold voltage at the boundary between the voltage distribution and adjacent voltage distributions.

[0023] Due to a phenomenon known as Slow Charge Loss (“SCL”), the threshold voltage of a memory cell changes over time as the cell's charge degrades; this is called “time-voltage shift” (because charge degradation shifts the voltage distribution along the voltage axis towards a lower voltage level). Time-voltage shift (TVS) will be used herein to refer to the change in the measured voltage of a cell over time. TVS can include various components, such as inherent charge loss, system charge loss, fast charge loss, etc. Memory fabricated using certain NAND technologies typically exhibits more TVS than floating-gate NAND. TVS typically increases with program-erase cycles (PECs), higher temperatures, and higher programming voltages. TVS exhibits significant die-to-die variation. In memories exhibiting TVS, the threshold voltage changes rapidly initially (immediately after the memory cell is programmed) and then slows down approximately logarithmically with respect to the time elapsed since the cell programming event. If not mitigated, time-voltage shift caused by slow charge loss can lead to an increased bit error rate in read operations.

[0024] This disclosure addresses the above and other deficiencies by providing a memory subsystem controller that determines a read level suitable for mitigating time voltage shift by measuring voltage distribution parameter values ​​(“parameter values”) of each block or group of blocks stored in a memory device and identifying read level values ​​corresponding to the parameter values. The memory subsystem controller can use the read level values ​​to mitigate time voltage shift when reading data from a block or group of blocks. The parameter value can be, for example, a voltage corresponding to a specific characteristic of the voltage distribution of a memory cell. The specific characteristic can be, for example, a feature of the voltage distribution, such as the peak, median, mean, or magnitude of the voltage distribution. The parameter value changes over time and can correspond to the amount of time voltage shift of the memory cell. The memory subsystem controller can use the specific parameter value to determine a read level suitable for the amount of time voltage shift corresponding to the specific parameter value. “Distribution voltage” will be used herein to refer to a distribution parameter value, which is a voltage and corresponds to a specific characteristic of the voltage distribution of a memory cell. For example, a distribution voltage can be understood as a voltage value corresponding to the peak value of the voltage distribution. The distribution voltage can be the median, mean, magnitude, or other characteristic of the voltage distribution. The voltage distribution can be a specific voltage distribution within the voltage distribution of a memory cell. For example, the seventh voltage distribution (or other designated voltage distribution) of a three-level memory cell can store voltages representing eight values ​​corresponding to eight voltage distributions numbered 0 to 7. The memory subsystem controller can look up the read level value corresponding to a specific parameter value in a mapping table that maps parameter values ​​to corresponding read level values. For example, the mapping table can be a voltage mapping table that maps distributed voltages to read levels. A voltage mapping table can be generated from empirical data using a process that identifies distributed voltages corresponding to suitable read level values ​​(e.g., read level values ​​that produce low error rates, high accuracy, etc.).

[0025] In some embodiments, interpolation can be used to determine the read level of a distributed voltage that is not present in the voltage map. If the distributed voltage is not in the voltage map, the memory subsystem controller can determine the read level value of the distributed voltage by interpolation between two selected voltage values ​​in the map that are respectively greater than and less than the distributed voltage. For example, the first selected voltage value could be the largest voltage value in the map that is less than the distributed voltage, and the second selected voltage value could be the smallest voltage value in the map that is greater than the distributed voltage. The read level can be determined as the average of the first and second voltage values. For example, the difference between the first voltage and the distributed voltage can be used to weight the read level value associated with the first value relative to the read level value associated with the second value in a weighted average calculation.

[0026] In a particular embodiment, instead of measuring the distributed voltage of a block for each memory read operation, the memory subsystem controller may measure the distributed voltage of a block less frequently and store the distributed voltage in a block metadata table or another mapping table that associates a block with the distributed voltage. For example, the distributed voltage of a block may be measured, and the distributed voltage may be stored in the block metadata table whenever the time since the block was programmed has increased by a threshold amount (e.g., 50%) relative to the previous time when the distributed voltage of the block was measured. The memory subsystem controller may then retrieve the distributed voltage of a particular block from the block metadata table, for example, by looking up the distributed voltage corresponding to the block in the block metadata table for each memory read operation. The memory subsystem controller may then use the voltage mapping table to determine the read level corresponding to the distributed voltage. Storing the distributed voltage in association with the block in this way and accessing the stored distributed voltage in a read operation enables read operations to be performed quickly and efficiently without the considerable additional latency required to identify the read level based on the distributed voltage.

[0027] Distributed voltage can be understood as representing the “position” of a distribution along an axis. This position may correspond to a characteristic of a specific voltage distribution (e.g., the 7th voltage distribution) of a memory cell, such as a peak value. As time increases after programming, the position of the characteristic of the specific distribution, represented by the distributed voltage, shifts towards a lower voltage reflecting a state of time-voltage shift. The memory subsystem controller can measure the distributed voltage as the value of the voltage at a specific memory cell within a block. The measured distributed voltage can be used to determine the read level value of the memory cell and other memory cells that may have similar amounts of time-voltage shift, such as other memory cells storing data in the same block or superblock as the measured memory cell. At a specific time after programming, the memory subsystem can mitigate the time-voltage shift effect by measuring the position (“distribution position”) (e.g., the median voltage of the distribution) of the characteristic voltage distribution at the specific memory cell during a read operation and mapping the measured position (e.g., the distributed voltage) to a read level value previously determined to correspond to the distribution position. The memory subsystem can then use the read level value to read data from the memory cell.

[0028] Advantages of this disclosure include (but are not limited to) a smaller number of operations required to determine the read level compared to other techniques that attempt to mitigate the effects of time voltage shift. For example, according to this disclosure, the operation of determining the read level offset can be performed on demand (e.g., in response to a request to access a specific block), without the additional overhead or complexity of garbage collection-related operations that may run indefinitely during system operation. The read level offset of a block or group of blocks changes according to the age of the block because the distributed voltage changes to the value corresponding to the older block due to the time voltage shift effect itself. Furthermore, entries in the block metadata table can be deleted when a block is written.

[0029] Figure 1 Example computing system 100 including memory subsystem 110 according to some embodiments of the present disclosure is shown. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations of such devices.

[0030] The memory subsystem 110 may be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0032] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0033] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and to read data from the memory subsystem 110.

[0034] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transmit data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0035] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0036] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory. The crosspoint array of non-volatile memory can be combined with a stackable cross-grid data access array to perform bit storage based on changes in volume resistance. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0037] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion of memory cells as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages that can refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0038] Although non-volatile memory devices such as 3D cross-point non-volatile memory cell arrays and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0039] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-decoded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0040] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0041] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is shown to include a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0042] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to perform the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions for accessing the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0043] In some implementations, the memory subsystem 110 may use a striping scheme, in which each data payload (e.g., user data) utilizes multiple dies of the memory devices 130, 140 (e.g., NAND flash memory devices), such that the payload is distributed across a subset of the dies, while the remaining one or more dies are used to store error correction information (e.g., parity bits). Accordingly, the set of blocks distributed across the set of dies of the memory device using a striping scheme is referred to herein as a "superblock".

[0044] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0045] In some embodiments, memory device 130 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0046] The memory subsystem 110 includes a read level manager component 113 that determines an appropriate read level for a memory cell based on voltages associated with specific characteristics of the voltage distribution of the memory cell. As described above, time-voltage shift causes the threshold read level of a memory cell to change over time. The read level determined based on the distributed voltage, as described below, mitigates the effect of time-voltage shift. When data is written to a memory cell, the amount of voltage placed on the cell's gate to be written to is not precise. Therefore, in order to write a specified target voltage to several memory cells, there exists a distribution of voltages near each of the target voltages. The voltage distribution can be a distribution of threshold voltages across multiple memory cells programmed to be in a specific state associated with the voltage distribution.

[0047] The read level manager component 113 can perform a calibration scan at a specific time to measure the distributed voltage associated with a specific characteristic of the voltage distribution of one or more cells in each block (or superblock or other memory cell), and store the measured distributed voltage in a block metadata table in association with the block. For a read operation, the read level manager component 113 can determine the distributed voltage corresponding to the block by looking up the block in the block metadata table and retrieving the distributed voltage corresponding to the block from the block metadata table. The read level manager component 113 can then determine a suitable read level for the read operation by looking up the read level corresponding to the voltage in a voltage mapping table, and perform the read operation by reading data from the block using the read level.

[0048] In a particular embodiment, the memory subsystem controller 115 includes at least a portion of the read level manager component 113. For example, the memory subsystem controller 115 may include a processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the read level manager component 113 is part of the host system 120, an application, or an operating system. Further details regarding the read level manager component 113 are described below.

[0049] Figure 2 This illustrates a time-voltage shift caused, at least in part, by the slow charge loss exhibited by a three-level memory cell, according to an embodiment of the present disclosure. Although Figure 2 The illustrative example utilizes a three-level cell, but the same observations can be made, and therefore, the same remedy can be applied to single-level cells and any memory cell with multiple levels. A memory cell can be programmed (written to) by applying a voltage (e.g., a programming voltage) to it, thereby generating the charge stored in the memory cell. Precise control of the amount of charge stored in a memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thus effectively allowing a single memory cell to store multiple bits of information. With 2 n A memory cell operating at different threshold voltage levels can store n bits of information.

[0050] Each illustration in Figures 210 and 230 shows a programming voltage distribution 220A to 220N (also referred to herein as a “programming distribution”, “voltage distribution”, or “distribution”) for a memory cell programmed to encode a corresponding logic level by a corresponding write level (which may be assumed to be at the midpoint of the program distribution). Programming distributions 220A to 220N illustrate a range (e.g., a normal distribution of threshold voltages) of threshold voltages used for programming memory cells at a corresponding write level (e.g., a programming voltage). To distinguish adjacent programming distributions (corresponding to two different logic levels), read threshold voltage levels are defined (shown by vertical dashed lines) such that any measured voltage below the read threshold level is associated with one of a pair of adjacent programming distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other of a pair of adjacent distributions. In Figure 210, eight states of the memory cell are shown below the corresponding programming distribution (except for states marked ER, which are erase states and their distribution is not shown). Each state corresponds to a logic level. Threshold voltage levels are labeled Va-Vh. As shown, any measured voltage below Va is associated with the ER state. The states labeled P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 22A-220N, respectively.

[0051] The time since programming (TAP) will refer in this document to the time since the cell was written and is the primary driver of time-voltage shift (TVS) as a function of temperature. TAP can be estimated (e.g., inferred from data state metrics) or measured directly (e.g., based on the controller clock). Cells, blocks, pages, block series, etc., are new (or relatively new) with (relatively) small TAPs and old (or relatively old) with (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be performed (e.g., performing a reference calibration 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes).

[0052] As can be seen from example graphs 210 and 230, which respectively reflect the time after programming (TAP) 0 (immediately following programming) and T hours TAP (where T is the number of hours), the programming distribution changes over time primarily due to slow charge loss. To reduce the read bit error rate, the corresponding read threshold voltage can be adjusted to compensate for the shift in the programming distribution shown by the vertical dashed line. In various embodiments of this disclosure, the time voltage shift is selectively tracked for the die group based on measurements performed at one or more representative dies of the die group. Based on measurements characterizing the time voltage shift and operating temperature of the dies in the die group performed on representative dies of the die group, the read threshold voltage offset for reading the memory cells of the dies in the die group is updated and applied to the base read threshold level to perform a read operation.

[0053] Figure 3 The diagram schematically illustrates a distributed voltage corresponding to specific characteristics of a voltage distribution, as well as the voltage distribution and the change of the distributed voltage over time, according to some embodiments of the present disclosure. Although Figure 3 The illustrative example utilizes a three-level cell, but the same observations can be made, and therefore the same remedies can be applied to single-level cells and any memory cell with multiple levels. Figure 3 Chart 300 shows the voltage distribution of memory cells at time 0 hours after programming, and chart 350 shows the voltage distribution of memory cells at subsequent TAP hours. As described above... Figure 2 As described, the voltage distribution 320A-G has shifted after T hours, as shown in Figure 350.

[0054] Each of Figures 300 and 350 illustrates seven programming voltage distributions 320A-320G for memory cells programmed to encode corresponding logic levels via corresponding write levels (which can be assumed to be at the midpoint of the programming distribution). The programming distributions 320A to 320G are similar to those described above regarding... Figure 2The programming distributions described are 220A to 220N. Each memory cell has eight states, including an erase state corresponding to a voltage below the first voltage distribution 320A, and seven logic level states corresponding to the seven voltage distributions 320A to 320G.

[0055] The voltage distribution 320A to 320G illustrates the range (e.g., a normal distribution of the threshold voltage) of a memory cell used for programming at a corresponding write level (e.g., programming voltage). As described above relative to... Figure 2 As described, in order to distinguish adjacent programming distributions (corresponding to two different logic levels), a read threshold voltage level is defined (shown by the vertical dashed line) such that any measured voltage below the read threshold level is associated with one of the programming distributions in a pair of adjacent programming distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other programming distribution in a pair of adjacent distributions.

[0056] Each voltage distribution 320A-320G corresponds to a logic level. The read threshold voltage levels are labeled Va-Vh. Any measured voltage below Va is associated with an erase state. For example, a measured voltage is associated with an erase state or one of the seven programming states P1-P7, depending on the relationship between the measured voltage and a threshold or threshold pair, as shown in Table 1 below.

[0057] lower threshold Upper threshold state none Va erase Va Vb P1 Vb Vc P2 Vc Vd P3 Vd Ve P4 Ve Vf P5 Vf Vg P6 Vg none P7

[0058] Table 1

[0059] As shown in Table 300, at TAP = 0, the threshold voltage levels have values ​​Va = -0.8, Vb = 0.3, Vc = 1.3, Vd = 1.9, Ve = 2.7, Vf = 3.7, and Vg = 4.5 volts. The distributed voltage can be calculated based on one or more of the voltage distributions 320A-320G. For example, the distributed voltage may correspond to a position on the voltage axis of a characteristic such as the peak value 330 of the seventh distribution 320G. The distributed voltage can be calculated as a function of the seventh distribution 320G, such as the median, mean, magnitude, or other function of the distribution. In the example of Table 300, the distributed voltage is shown as Vmedian 340, which is calculated as the median of the seventh distribution 320G at TAP = 0 and has a value of 4.9 volts.

[0060] As shown in Table 350, at TAP = T hours, the threshold voltage levels have values ​​of Va = -0.8, Vb = 0.3, Vc = 1.2, Vd = 1.8, Ve = 2.4, Vf = 3.3, and Vg = 4.2 volts. The peak value of the seventh distribution 320G at TAP = T is shown as peak value 360. In the example of Table 350, the distribution voltage is shown as Vmedian 370, which is calculated as the median of the seventh distribution 320G at TAP = T and has a value of 4.7 volts.

[0061] Although specific characteristics of a particular voltage distribution, such as the median of the seventh voltage distribution, have been described above, any suitable characteristic of any voltage distribution can be used to determine the distributed voltage. For example, the mean of the sixth voltage distribution 320F can be used as the distributed voltage. As another example, the distributed voltage can be calculated as the 90th percentile of the seventh voltage distribution, which corresponds to the lower right side of the distribution. In another example, the distributed voltage can be calculated as the mean (e.g., average) of the 25th and 75th percentiles of the seventh voltage distribution. In yet another example, the distributed voltage can be calculated as the mean of the means of the sixth and seventh voltage distributions. In a particular embodiment, a higher-numbered distribution is used to calculate the distributed voltage because higher-numbered distributions move faster over time than lower-numbered distributions, and therefore carry a stronger signal of the TVS. However, in other embodiments, one or more lower-numbered distributions can be used to calculate the distributed voltage. For example, the distributed voltage can be calculated as the mean of the means of the first distribution 320A and the seventh distribution 320G.

[0062] Figure 4A An example of a read level manager 402 according to some embodiments of the present disclosure is depicted. The read level manager 402 may correspond to... Figure 1 The memory subsystem controller 115 shown in the diagram has a read level manager component 113. The read level manager 402 may include a voltage map table 406, which may be stored in the local memory 119 of the memory subsystem controller 115 or other suitable memory (e.g., the memory of the host system 120). The voltage map table 406 may store a mapping between distributed voltages and sets of read levels. For each distributed voltage associated with a set of read levels, the voltage map table 406 may include a mapping containing the distributed voltage V. M and the set of read levels RL1 M -RLN M The line. In Figure 4A In the example, voltage mapping table 406 contains three entries for distributed voltages, 4.9, 4.7 and 4.3, as shown in Table 2 below.

[0063]

[0064] Table 2

[0065] The instance read levels for distributed voltages of 4.9V and 4.7V in voltage mapping table 406 correspond to... Figure 3 The threshold voltages associated with Vmedian = 4.9V and Vmedian = 4.7V are specified. Although voltage map 406 is described as containing read levels that can be used in read operations, voltage map 406 may alternatively or additionally contain read level offsets that can be added to the base read levels to determine the read levels to be used in read operations. Voltage map 406 may be generated by a voltage map generator (not shown), for example, using an empirical process. The empirical process may, for example, perform read operations on memory cells 432 of memory device 130 using a range of distributed voltages and analyze the results received from memory cells 432 to determine the read levels of the range of distributed voltages, as described below. In one embodiment, empirical data may be generated during the verification testing of one or more memory devices (e.g., NAND memory devices) and appropriately averaged and reduced to represent the expected voltage map. In another embodiment, empirical data may be generated during the manufacturing process of the memory device (e.g., NAND) to include a large total number of dies, utilizing a similar data reduction process to represent the dies in a single voltage map. In another embodiment, empirical data may be collected and streamlined into voltage mapping tables during the manufacturing process of a storage device (e.g., an SSD) to represent dies within a group of storage devices or a single storage device. In yet another embodiment, empirical data may be generated for each die within a storage device during the storage device manufacturing process, and a separate voltage mapping table may be used for each die within a storage device.

[0066] The read level manager 402 may also include a data read component 410, which can receive read requests, determine appropriate read levels, and read data from one or more memory devices (e.g., memory device 130) using the determined read levels. The data read component 410 may include a read request receiver 412, a distributed voltage determiner 413, a read level determiner 420, and a data reader 426. The read request receiver 412 may receive data read requests from the memory subsystem controller 115 or other components of the memory subsystem 110, or from the host 120. The data read request may specify a block, for example, as a block ID.

[0067] The distributed voltage determiner 413 determines the distributed parameter values, such as distributed voltage, of the block specified in the read request. For example, to determine the distributed voltage of a group of memory cells 432 specified in or associated with the read request, the distributed voltage determiner 413 may send a voltage measurement request to the voltage measurement component 438 (arrow 415). The voltage measurement request may contain an identifier or address that identifies the memory cell 432 whose voltage is to be measured. The voltage measurement component 438 may measure the distributed voltage of the memory cell 432 specified in or associated with the read request (arrow 444). The voltage measurement component 438 may measure the distributed voltage by, for example, performing a read operation on the group of memory cells containing the specified memory cell 432, as described below. The voltage measurement component 438 may receive the measured distributed voltage from the memory cell 432 (arrow 446). The voltage measurement component 438 may then send the distributed voltage to the distributed voltage determiner 413 (arrow 417).

[0068] The read level determiner 420 can send a query for a specified distributed voltage to the voltage map table 406 (arrow 422). If the voltage map table 406 contains a mapping from the specified distributed voltage to the corresponding read level, the corresponding read level can be provided to the read level determiner 420 (arrow 424).

[0069] If voltage map 406 does not contain a mapping from a specified distributed voltage to a read level, read level determiner 420 may perform interpolation between the first and second distributed voltages present in voltage map 406 to determine a read level corresponding to the specified distributed voltage based on other read levels present in voltage map 406. In the following description, the specified distributed voltage is referred to as the "target distributed voltage". The difference between the first value and the target distributed voltage can be used to weight the read level voltage associated with the first value relative to the read level value associated with the second value in a weighted average calculation. The first distributed voltage can be identified as the closest distributed voltage less than the target parameter value, such as the maximum value of the distributed voltage less than the target distributed voltage in the voltage map. The second distributed voltage can be identified as the closest distributed voltage greater than the target distributed voltage, such as the minimum value of the distributed voltage greater than the target distributed voltage in the voltage map. Therefore, interpolation can be performed between the read level value associated with the first value and the read level value associated with the second value to determine the read level value associated with the target distributed voltage.

[0070] The difference between the target distributed voltage and the nearest distributed voltages in the voltage mapping table that are less than and greater than the target distributed voltage can be used to interpolate each read level value of the target distributed voltage as a weighted average of the corresponding read level values ​​of the nearest distributed voltages that are less than and greater than the target distributed voltage. The weight corresponding to each read level value of the nearest distributed voltage less than the target distributed voltage can be proportional to the difference between the nearest distributed voltage less than the target distributed voltage and the target distributed voltage. Similarly, the weight corresponding to each read level value of the nearest distributed voltage greater than the target distributed voltage can be proportional to the difference between the nearest distributed voltage greater than the target distributed voltage and the target distributed voltage. The read level determiner 420 can determine each read level value of the target distributed voltage as a weighted average of the corresponding read level values ​​associated with the nearest distributed voltages greater than and less than the target distributed voltage.

[0071] For example, if the target distributed voltage is 4.8V, and the first and second values ​​are 4.7V and 4.9V respectively, then the target distributed voltage of 4.8V is at half the difference between the first and second values. Accordingly, the determined read level value can be calculated as a weighted average, where the read level value associated with the first value has a weight of 0.5 and the read level value associated with the second value also has a weight of 0.5. The distributed voltage and the associated determined read level values ​​can be stored in a voltage map table, so subsequent read requests for the same target distributed voltage can retrieve the read level value without interpolation.

[0072] As an example, the following shows the read level generated by interpolation for a target distributed voltage of 4.8V that is not in the voltage map. The target voltage 4.8V is between a first voltage of 4.7V and a second voltage of 4.9V, both of which are in the voltage map before interpolation. The result of the interpolation, i.e., the row for the target voltage 4.8V, is shown in Table 3 below. The read level determiner 420 that performs the interpolation stores the target distributed voltage associated with the read level generated by the interpolation in the voltage map 406. Because the target distributed voltage 4.8V is half the difference between the upper entry (4.9V) and the lower entry (4.8V), both the upper and lower entries have a weight of 0.5. The controller can interpolate between the upper and lower entries by calculating each read level value as a weighted average, ReadLevelAbove*0.5 + ReadLevelBelow*0.5. Therefore, the interpolated read levels for a distributed voltage of 4.8V are -0.8, 0.3, 1.2, 1.8, 2.4, 3.3, and 4.2 volts, as shown in Table 3.

[0073]

[0074] Table 3

[0075] In a particular embodiment, if the read level value in voltage map 406 is a read level offset rather than a read level, the read level determiner 420 may add the read level offset to the base read level to determine the read level to be used in the read operation. If interpolation is performed on the read level offset, the base read level may be associated with the same distribution as the interpolated read level value to produce a total read level value. The memory system controller may then use the total read level value to perform the read operation.

[0076] Data reader 426 can read data from a block using a read level from read level determiner 420. Data reader 426 can apply a read level to one or more memory cells 432 of memory device 130 (arrow 428) and read data from memory cells 432 (arrow 434). Data reader 426 can then provide the data to memory subsystem controller 115 or other components of host 120.

[0077] Alternatively or additionally, voltage measurement component 438 can measure the distributed voltage by performing a sufficient number of read operations using a threshold voltage within a certain range to measure the voltage distribution of the memory cells and calculating the median (or other function) of the measured voltage distribution. For example, the distributed voltage can be measured at the memory cell identified by the voltage measurement request (arrow 415). Voltage measurement component 438 can determine the distributed voltage by, for example, identifying characteristics of the distribution (e.g., peaks, which may be the location of the distribution with the highest ratio) and determining the voltage corresponding to the identified location of the characteristics. Therefore, the value of the measured distributed voltage can be the voltage corresponding to the portion of the distribution with the highest ratio. The distributed voltage can be understood as representing the position of the distribution along the voltage axis.

[0078] In a particular embodiment, to generate voltage map 406, a trial-and-error technique can be used to identify read level values ​​from memory cells that produce desired results, such as low error rate, high accuracy, or other desired results for each of a selected range of distributed voltage values. For each selected distributed voltage, the corresponding read level value that produces the desired result can be associated with the selected distributed voltage and stored in the voltage map. As an example, one or more selected ranges of distributed voltages can be used to evaluate read error counts or other performance criteria during the operation or simulation of similar memory cells. For each distributed voltage in the selected range, a desired set of read level values ​​corresponding to the voltage distribution of the memory cell being operated or simulated can be identified by operating or simulating the memory cell for the set of read level values ​​within the range of read level values. The distributed voltage corresponding to the identified set of desired read level values ​​can be associated with the identified set of desired read level values ​​and stored in the voltage map.

[0079] Because the voltage distribution shifts towards lower voltages over time, and the relationship between the measured distribution voltage and the read level can be determined, for example, by measuring the number of memory cells, the voltage-read level relationship can be used to map the distribution voltage, which can be represented as a voltage, to read level values ​​for a specific distribution. Furthermore, because the shift of each distribution in a multi-level cell is correlated, the voltage relationship can be used to map the distribution voltage to a set of read level values ​​corresponding to the voltage distribution of the multi-level memory cells, such as seven read level values ​​in an eight-level architecture (where one level corresponds to an erase state). The voltage relationship can be represented, for example, as a mapping, such as voltage mapping table 406, which maps each distribution voltage, which can be represented as a voltage, to a set of read level values. The set of read level values ​​may contain the read level value for each of the voltage distributions of the memory cells. Each read level value in the set may, for example, be a read level value that can be added to a base, or a read level offset that can be added to a base read level value. Furthermore, in some embodiments, the read level or read level offset on table 406 may be determined based on a programmed erase cycle.

[0080] As described above, upon receiving a request to read data from a memory cell, the memory subsystem controller 115 can determine a read level value for the memory cell based on the distributed voltage. The memory subsystem controller can measure the distributed voltage at the memory cell. The previously determined distributed voltage can be a distributed voltage measured at the memory cell or another memory cell. The memory subsystem controller can then look up the read level value associated with the measured or previously determined distributed voltage in voltage mapping table 406 and use the read level value to read data from the memory cell.

[0081] The number or range of distributed voltage values ​​for generating entries in voltage map 406 can be determined based on several factors, such as characteristics of the memory device, including the resolution of the measured distributed voltage values ​​(e.g., distributed voltage resolution), the suitability of the entries for interpolation, the minimum and maximum values ​​of the distributed voltage, and the amount of memory (e.g., local memory 119) or other storage space available for storing voltage map 406.

[0082] In a particular embodiment, voltage map 406 may contain an entry for every possible value of the distributed voltage. If the number of possible values ​​is relatively small, for example, if the resolution of the distributed voltage is coarse enough that the memory available for storing voltage map 406 is sufficient to store an entry for every possible value of the distributed voltage, then a voltage map generator (not shown) may include an entry for every possible value of the distributed voltage in the map. For example, if the distributed voltage is measured as a voltage represented by a digital audio converter (DAC) unit, the number of possible distributed voltages may be relatively small. If sufficient storage space is available, voltage map 406 may contain an entry for every possible DAC value (e.g., for each possible DAC value, an entry mapping the DAC value to a corresponding read level value). When the memory subsystem controller 115 performs a read operation on a block, the controller 115 may use voltage map 406 to identify the read level value corresponding to the block (e.g., a block, superblock, or other unit) by measuring the distributed voltage of the group of memory cells in which the data of the block is stored, and identifying the read level value associated with the distributed voltage in the voltage map. Because the voltage map 406 in this example contains an entry for every possible distributed voltage, and each measured value of the distributed voltage is one of the possible values, the memory subsystem controller 115 can identify the entry in the voltage map 406 that specifies the read level value for each block to be read.

[0083] Alternatively, the voltage map generator may select a subset of possible values ​​of the distributed voltage and generate a voltage map 406 containing entries for each value in the subset, and may use interpolation to determine the read level of voltages that are not present in the map, as described above.

[0084] Figure 4B An example of a read level manager 403 according to some embodiments of the present disclosure is depicted. The read level manager 403 may correspond to... Figure 1 The memory subsystem controller 115 shown in the image has a read level manager component 113. The read level manager 403 may contain a block metadata table 404 and a voltage mapping table 406. Tables 404 and 406 may be stored in the local memory 119 of the memory subsystem controller 115 or other suitable memory (e.g., the memory of the host system 120). The block metadata table 404 may store the mapping between blocks and distributed voltages. For each block associated with a distributed voltage, the block metadata table 404 may contain a block identifier (ID) "N" containing the block and the associated distributed voltage V. N The line. In Figure 4BIn this example, block metadata table 404 contains an entry mapping block ID "0" to distributed voltage 4.9, indicating that distributed voltage 4.3 has been determined for block ID "0". Block metadata table 404 also contains entries mapping block ID "0" to distributed voltage 4.9, and entries mapping block ID "2" to distributed voltage 4.7. Block metadata table 404 may be generated by calibration component 440 and / or data reading component 410. Entries may be removed from block metadata table 404 by data writing component, as described below.

[0085] In a particular embodiment, the distributed voltage and the associated determined read level value may be associated with a block and stored in the block metadata table 404, so that subsequent read requests for the same value of the distributed voltage can retrieve the read level value. The determined distributed voltage and read level values ​​may be stored in the block metadata table, provided, for example, there is sufficient memory or other storage device available to store those values ​​for each in the block. In another embodiment, each of the distributed voltage and associated read level values ​​in the voltage map table may be stored in the block metadata table instead of the voltage map table, in which case the map table is not necessary. The voltage map table 406 may store a mapping between sets of distributed voltages and read levels. The voltage map table 406 is described above in relation to... Figure 4A Further description.

[0086] The level manager 403 may also include a data reading component 410, a calibration component 440, and a data writing component 450. As described above... Figure 4A As described, data read component 410 can receive read requests, determine appropriate read levels, and read data from one or more memory devices (e.g., memory device 130) using the determined read levels. Data read component 410 may include read request receiver 412, distributed voltage determiner 414, read level determiner 420, and data reader 426. Read request receiver 412 may receive data read requests from memory subsystem controller 115 or other components of memory subsystem 110, or from host 120. Data read requests may specify blocks, for example, as block IDs.

[0087] The distributed voltage determiner 414 is similar to the one mentioned above. Figure 4AThe distributed voltage determiner 413 is described. The distributed voltage determiner 414 can determine the distributed parameter value, such as the distributed voltage, of the block specified in the read request. For example, the distributed voltage determiner 414 can query the block metadata table 404 to obtain the distributed voltage with the block ID specified in the read request (arrow 416). If the block metadata table 404 contains the specified block ID, for example, if there is an entry in the metadata table 404 that maps the specified block ID to the distributed voltage, then the distributed voltage determiner 414 can provide the corresponding distributed voltage to the read level determiner 420 (arrow 418), which can determine the read level as described below.

[0088] If the block metadata table 404 does not contain a specified block ID, the distributed voltage determiner 414 can measure the parameter value (e.g., distributed voltage) of the block specified in the read request and store the determined distributed characteristics in the block metadata table 404 in association with the block ID. The distributed voltage determiner 414 can measure the distributed voltage relative to the voltage measurement component 438 of the calibration component 440 as described below.

[0089] Alternatively, if the block metadata table 404 does not contain a specified block ID, the data read component 410 may use a default read level or pass the read request to another component of the memory subsystem controller 115, which may perform the read operation. Although the parameter value is voltage in the examples described herein, the parameter value can be any suitable data state metric. As used herein, "data state metric" refers to a quantity measured or inferred from the state of data stored on the memory device. Specifically, a data state metric may reflect the state of time-voltage shifts, the degree of read interference, and / or other measurable functions of data state. A data state metric may be a function of a set of component state metrics (e.g., a weighted sum).

[0090] If the block metadata table 404 contains a specified block ID, then as described above, the distributed voltage determiner 414 can receive the distributed voltage associated with the block ID from the block metadata table 404 (arrow 418). The read level determiner 420 can send a query for the specified distributed voltage to the voltage mapping table 406 (arrow 422). If the voltage mapping table 406 contains a mapping from the specified distributed voltage to the corresponding read level, then the corresponding read level can be provided to the read level determiner 420 (arrow 424).

[0091] If voltage mapping table 406 does not contain a mapping from the specified target distributed voltage to the read level, then read level determiner 420 may perform interpolation, as described above relative to... Figure 4AAs described above. The read level determiner 420, which performs interpolation, can associate the target distributed voltage with the block ID of the block that generated its read level and store it in the block metadata table 404. The read level determiner 420 can also associate the target distributed voltage with the read level generated by interpolation and store it in the voltage mapping table 406, as described above relative to... Figure 4A As described.

[0092] Data reader 426 can read data from a block using a read level from read level determiner 420. Data reader 426 can apply a read level to one or more memory cells 432 of memory device 130 (arrow 428) and read data from memory cells 432 (arrow 434). Data reader 426 can then provide the data to memory subsystem controller 115 or other components of host 120.

[0093] The calibration component 440 can generate or update the block metadata table 404 separately from or at a different time than the read operation performed by the data read component 410. For example, the calibration component 440 can perform the calibration operation to generate or update the block metadata table 404 by measuring the distributed voltage of one or more groups of memory cells 432 storing the data for each block, and storing the measured distributed voltage in the block metadata table 404 in association with the corresponding block ID. In this way, the block metadata table 404 can be generated and updated without delaying the read operation performed by the data read component 410. The calibration component 440 can perform the calibration operation at periodic times or at other times as part of a calibration scan.

[0094] Calibration component 440 may include voltage measurement component 438, which can determine the distributed voltage of each block (arrow 444) by performing one or more measurement operations on one or more groups of memory units 432 where data of the blocks are stored, for example, similar to Figure 4A The voltage measurement component 438. The measurement operation to determine the distributed voltage of the block can, for example, measure at least a threshold number of voltages using a range of read levels. The voltage measurement component 438 can identify voltages corresponding to characteristics based on the measured voltages. The measured voltages in the memory unit 432 can be a digital representation of the voltages displayed by the memory unit 432. For example, an analog-to-digital converter (ADC) such as a successive approximation ADC can be used by the voltage measurement component 438 to perform the measurement.

[0095] Alternatively or additionally, the distributed voltage can be determined by performing a sufficient number of read operations using a threshold voltage range to measure the voltage distribution of the memory cells and calculating the median (or other function) of the measured voltage distribution. For example, the distributed voltage can be measured at a group of memory cells 432 representing a portion of the data in the memory block. The memory subsystem controller can determine the distributed voltage by, for example, identifying a characteristic of the distribution, such as a peak, which may be the location of the distribution with the highest ratio; and determining the voltage corresponding to the identified location of the characteristic. Therefore, the measured value of the distributed voltage may be the voltage corresponding to the portion of the distribution with the highest ratio. The distributed voltage can be understood as representing the location of the distribution along a voltage axis. Parameter values ​​can be associated with the block and stored in the block metadata table 404, so that subsequent read requests for the block can access the parameter values ​​more efficiently (e.g., without performing measurement operations on the memory cells). The block metadata table can be stored in the local memory 119 of the memory subsystem.

[0096] The calibration component 440 may receive the distributed voltage measured from the memory unit 432 (arrow 446) and store the measured distributed voltage in the block metadata table 404 in association with the block ID of the block (arrow 448). The calibration component 440 may, for example, repeatedly perform a calibration operation at time intervals, such that the distributed voltage associated with the block ID in the block metadata table is updated over time to reflect the change in distributed voltage according to the time voltage shift.

[0097] Data writing component 450 can handle requests to write data to a block. Because writing data to a block involves relocating valid block data to another block (e.g., via garbage collection or folding) and then erasing the block, writing data to a block resets the read threshold of the block's memory cells by an amount that has shifted back to 0 volts or at least close to 0 volts. Therefore, the distributed voltage stored in the block metadata table 404 can be reset accordingly, for example, by deleting the block's entry from the block metadata table 404, or by changing the distributed voltage associated with the block in the block metadata table 404 to the initial distributed voltage corresponding to an initial time when very little or no time voltage shift has occurred (e.g., TAP = 0, as...). Figure 3(As shown in Figure 300). Accordingly, the write request receiver 452 of the data writing component 450 receives each request to write data to the block, and the block metadata table updater 454 resets the entry corresponding to the block in the block metadata table 404. For example, the metadata table updater 454 may delete the block entry from the metadata table 404, or change the distribution voltage associated with the block in the metadata table 404 to the initial distribution voltage described above. The metadata table updater 454 may send a delete or update operation to the block metadata table 404 (arrow 456). The delete or update operation may include resetting or deleting the block ID from the block metadata table 404. The data writer 458 may write data to the block after or in parallel with the metadata table 404 update operation. Subsequently, the calibration component 440 may update the distribution voltage associated with the block in the metadata table 404 to a time-varying parameter value, thereby mitigating the effect of time voltage shift on the read operation.

[0098] As described above, upon receiving a request to read data from a memory cell associated with a block or block group, the memory subsystem controller 115 may determine the read level value of the memory cell based on the distributed voltage. The memory subsystem controller may measure the distributed voltage at the memory cell or retrieve a previously determined distributed voltage. The previously determined distributed voltage may be a distributed voltage measured at the memory cell or at another memory cell associated with the block or block group. The previously determined distributed voltage may be retrieved from the block metadata table 404 or other data structures that associate the previously determined data state with the block or block group. The memory subsystem controller may then look up the read level value associated with the measured or previously determined distributed voltage in a voltage map table and use the read level value to read data from the memory cell.

[0099] The memory subsystem controller 115 may periodically perform a calibration process to measure the distributed voltage of each memory cell (e.g., block, block group, or other memory cell). The calibration process associates each memory cell with a distributed voltage determined for that memory cell. The memory subsystem controller may measure the distributed voltage as part of the calibration process. For example, during the calibration process, the memory subsystem controller may measure the distributed voltage at a specific time and again at a subsequent time (e.g., at periodic intervals) or after a threshold time period following the next write operation associated with the memory cell. The calibration process may also delete entries that are no longer needed from the block metadata table 404, for example, because the block has been written to since the last update of the block metadata table entry. The calibration process may be performed as part of a calibration scan. Alternatively or additionally, the memory subsystem controller may delete or request the deletion of the block metadata table entry for a particular block after it has been written to (because the write resets the time voltage shift) or erased (because the block is no longer in use) or otherwise becomes unused.

[0100] Figure 5A This is a flowchart of an example method 500 for determining a read level based on the distributed voltage of a memory cell and reading data using the determined read level, according to aspects of this disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1 The read level manager component 113 executes the process. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0101] At operation 510, the processing device may receive a request to read data from a memory cell of a memory device coupled to the processing device. At operation 512, the processing device may determine a voltage distribution parameter value associated with a memory cell of the memory device. At operation 514, the processing device may determine a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a corresponding voltage distribution of the memory cell. At operation 516, the processing device may use the determined set of read levels to read data from the memory cell of the memory device.

[0102] Figure 5B This is a flowchart of an example method 501 for determining a read level based on the distributed voltage of a block and reading data using the determined read level, according to aspects of this disclosure. Method 501 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 501 is performed by… Figure 1 The read level manager component 113 executes the process. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0103] At operation 520, the processing device may receive a request to read data from a block of a memory device coupled to the processing device. At operation 522, the processing device may determine voltage distribution parameter values ​​associated with the block of the memory device, wherein determining the voltage distribution parameter values ​​associated with the block of the memory device includes identifying voltage distribution parameter values ​​in a block metadata table, wherein the block metadata table includes a plurality of records, each of which maps a value of a block identifier to a value of a voltage distribution parameter. At operation 524, the processing device may determine a set of read levels associated with the voltage distribution parameter values, wherein each read level in the set of read levels corresponds to a corresponding voltage distribution of at least one memory cell of the memory device, wherein at least a portion of the block is stored in the at least one memory cell. At operation 526, the processing device may read data from the block of the memory device using the determined set of read levels.

[0104] Figure 6 This is a flowchart of an example method 600 for performing a distributed voltage calibration scan according to aspects of this disclosure, which determines the distributed voltage of a block and stores the distributed voltage in a block metadata table. Method 600 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions running or executed on the processing device), or a combination thereof. In some embodiments, method 600 is performed by… Figure 1 The read level manager component 113 executes the process. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes can be executed in different orders, and some processes can be executed in parallel. Furthermore, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0105] At operation 610, the processing device can determine the distribution voltage based on blocks of the memory device by measuring at least a threshold number of voltages and identifying voltages corresponding to characteristics of the distribution. The characteristics of the distribution can be, for example, the peak value of the distribution. The distribution voltage can be determined as a function or property of the distribution, such as the mean, median, modulus, or other properties of the distribution. At operation 620, the processing device can associate the voltages corresponding to the characteristics with block identifiers of blocks of the memory device and store them in a block metadata table.

[0106] At operation 630, the processing device may determine the time-to-program (TSP) of a block of the memory device. The determined time is referred to in the following description of operation 640 as a variable called “TSP” with an associated time unit. The time unit may be, for example, seconds. At operation 640, the processing device may schedule subsequent calibration of the block at a subsequent time corresponding to an increase of X% of the block's TSP relative to the current time (i.e., a subsequent execution of method 600 starting at operation 610). The current time may be, for example, the time at which operation 640 is executed. For example, the subsequent time may correspond to a 50% increase in the block's TSP; in this case, the subsequent time may be determined as the future current time + 0.50 * TSP, or 0.50 * TSP time units (e.g., seconds). The value X may be any desired numerical percentage.

[0107] Figure 7 An example machine of computer system 700 is shown, within which an instruction set executable for causing the machine to perform any one or more of the methods discussed herein is provided. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (The operation of the read level manager component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment within the capacity of a server or client machine in a client-server network environment.

[0108] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or jointly execute a set (or sets of sets) of instructions to perform any or more of the methods discussed herein.

[0109] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0110] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication on network 720.

[0111] The data storage system 718 may include a machine-readable storage medium 724 (also called a computer-readable medium) on which one or more instruction sets 726 or software embodying any one or more methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0112] In one embodiment, instruction 726 includes instructions for implementing a component corresponding to a read level manager (e.g., Figure 1 The machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, but the term "machine-readable storage medium" should be understood to include a single medium or multiple media storing the one or more instruction sets. The term "machine-readable storage medium" should also be understood to include any medium capable of storing or encoding instruction sets executable by a machine and causing the machine to perform any one or more methods of this disclosure. The term "machine-readable storage medium" should be accordingly understood to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0113] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. An algorithm here and generally is considered a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0114] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. This disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0115] The present invention also relates to an apparatus for performing the operations described herein. This apparatus may be specifically constructed for a particular purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0116] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the teachings and procedures herein, or it may prove convenient to construct more specialized devices to implement the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0117] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine-readable storage medium, such as a read-only memory (“ROM”), random access memory (“RAM”), disk storage medium, optical storage medium, flash memory components, etc.

[0118] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications can be made to the present disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A method for reading a memory device, comprising: receiving, by a processing device, a request to read data from a memory cell of the memory device coupled with the processing device; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, wherein determining the set of read levels associated with the voltage distribution parameter value comprises: in response to determining that a voltage mapping table does not include the voltage distribution parameter value, determining the set of read levels using interpolation based on first and second parameter values included in the voltage mapping table, wherein the set of read levels is determined as an average of a first set of read levels corresponding to the first parameter value and a second set of read levels corresponding to the second parameter value; and reading data from the memory cell of the memory device using the determined set of read levels.

2. The method of claim 1, wherein determining the voltage distribution parameter value associated with the memory cell of the memory device comprises: identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels; and determining the voltage distribution parameter value based on the particular voltage distribution.

3. The method of claim 2, wherein the voltage distribution parameter value comprises a voltage value included in the particular voltage distribution of the memory cell.

4. The method of claim 2, wherein determining the voltage distribution parameter value comprises determining a median, mean, or mode of the particular voltage distribution.

5. The method of claim 1, wherein the voltage mapping table comprises a plurality of records, and each record maps a value of a voltage distribution parameter to a set of values of a read level.

6. The method of claim 1, wherein determining the set of read levels associated with the voltage distribution parameter value further comprises: in response to determining that the voltage mapping table includes the voltage distribution parameter value, retrieving the determined set of read levels from the voltage mapping table, wherein the determined set of read levels is associated with the voltage distribution parameter value in the voltage mapping table.

7. The method of claim 1, wherein the voltage distribution parameter value is between the first and second parameter values, wherein the voltage mapping table maps the first parameter value to the first set of read levels in the voltage mapping table and further maps the second parameter value to the second set of read levels in the voltage mapping table.

8. The method of claim 1, wherein determining the set of read levels using interpolation comprises: identifying the first parameter value in the voltage mapping table, wherein the first parameter value is a maximum of one or more parameter values in the voltage mapping table that are less than the voltage distribution parameter value; determining a first weight based on a difference between the voltage distribution parameter value and the first parameter value; determining a second weight based on a difference between the voltage distribution parameter value and the second parameter value; and determining the set of read levels using the first and second weights. identifying the second parameter value in the voltage map, wherein the second parameter value is a minimum of one or more parameter values in the voltage map that are greater than the voltage distribution parameter value; determining a second weight based on a difference between the voltage distribution parameter value and the second parameter value; and determining the set of read levels based on a weighted average of the first set of read levels and the second set of read levels, wherein the first set of read levels is weighted according to the first weight and the second set of read levels is weighted according to the second weight.

9. The method of claim 1, wherein reading data from the memory cell using the determined set of read levels comprises: measuring a voltage of the memory cell; and identifying a logic level to which the measured voltage corresponds, wherein identifying the logic level comprises comparing the measured voltage to one or more of the read levels, wherein the data read from the memory cell comprises the identified logic level.

10. The method of claim 1, wherein the read levels comprise a plurality of read level offsets, and reading data from the memory cell using the determined set of read levels comprises: determining a plurality of adjusted read levels, wherein each adjusted read level is based on a sum of a base read level and a read level offset corresponding to the base read level, wherein the data is read from the memory cell using the adjusted read levels.

11. A storage system comprising: a memory; and a processing device communicably coupled to the memory, the processing device performing operations comprising: receiving a request to read data from a memory cell of a memory device coupled to the processing device; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, wherein determining the set of read levels associated with the voltage distribution parameter value comprises: in response to determining that a voltage map does not include the voltage distribution parameter value, determining the set of read levels using interpolation based on first and second parameter values included in the voltage map, wherein the set of read levels is determined as an average of a first set of read levels corresponding to the first parameter value and a second set of read levels corresponding to the second parameter value; and reading data from the memory cell of the memory device using the determined set of read levels.

12. The storage system of claim 11, wherein determining the voltage distribution parameter value associated with the memory cell of the memory device comprises: identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels; and determining the voltage distribution parameter value based on the particular voltage distribution.

13. The storage system of claim 12, wherein the voltage distribution parameter value comprises a voltage value included in the particular voltage distribution of the memory cell.

14. The storage system of claim 12, wherein determining the voltage distribution parameter value comprises determining a median, mean, or mode of the particular voltage distribution.

15. The storage system of claim 11, wherein the voltage mapping table comprises a plurality of records, and each record maps a value of a voltage distribution parameter to a set of values of read levels.

16. A non-transitory machine-readable storage medium storing instructions that cause a processing device to perform operations comprising: receiving a request to read data from a memory cell of a memory device coupled with the processing device; determining a voltage distribution parameter value associated with the memory cell of the memory device; determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the determined set of read levels corresponds to a respective voltage distribution of the memory cell, wherein determining the set of read levels associated with the voltage distribution parameter value comprises: in response to determining that a voltage mapping table does not include the voltage distribution parameter value, determining the set of read levels using interpolation based on first and second parameter values included in the voltage mapping table, wherein the set of read levels is determined as an average of a first set of read levels corresponding to the first parameter value and a second set of read levels corresponding to the second parameter value; and reading data from the memory cell of the memory device using the determined set of read levels.

17. The non-transitory machine-readable storage medium of claim 16, wherein determining the voltage distribution parameter value associated with the memory cell of the memory device comprises: identifying a particular voltage distribution of the memory cell by sampling the memory cell at a plurality of voltage levels; and determining the voltage distribution parameter value based on the particular voltage distribution.

18. The non-transitory machine-readable storage medium of claim 17, wherein the voltage distribution parameter value comprises a voltage value included in the particular voltage distribution of the memory cell.

19. The non-transitory machine-readable storage medium of claim 17, wherein determining the voltage distribution parameter value comprises determining a median, mean, or mode of the particular voltage distribution.

20. The non-transitory machine-readable storage medium of claim 16, wherein the voltage mapping table comprises a plurality of records, and each record maps a value of a voltage distribution parameter to a set of values of read levels.

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