Storage device and operation method thereof

Abstract

The present invention provides a storage device and an operation method thereof. The storage device includes a plurality of word lines, and the operation method of the storage device includes: performing a precharge operation on the word lines, applying a selected word line voltage to a first selected word line group of the word lines and applying an unselected word line voltage to a first unselected word line group of the word lines in a first round, applying the selected word line voltage to a second selected word line group of the word lines and applying the unselected word line voltage to a second unselected word line group of the word lines in a second round, wherein the first selected word line group is different from the second selected word line group and the first unselected word line group is different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

Description

Technical Field

[0001] The present invention belongs to the field of storage technology and relates to a storage device and an operating method thereof. Background Art

[0002] Currently, the demand for storage capacity is getting higher and higher. Therefore, flash memory such as triple-level cells (TLC), quad-level cells (QLC) and penta-level cells (QLC) have been developed to increase storage density.

[0003] However, during programming, programming charge horizontal or vertical spread may be encountered, especially in high threshold voltage situations. In short term (shorter than milliseconds), the "lower bound (LB) threshold voltage spread" caused by fast charge horizontal movement must be controlled. In long term (longer than milliseconds), retention charge loss caused by charge horizontal movement must also be suppressed. Summary of the invention

[0004] The invention relates to a storage device and an operation method thereof, which can effectively suppress the threshold voltage diffusion and the charge loss caused by the horizontal movement of the charge.

[0005] According to an example of the present disclosure, a method for operating a storage device is proposed, the storage device includes multiple word lines, and the method for operating the storage device includes: performing a precharge operation on the word lines, in a first round, applying a selected word line voltage to a first selected word line group of the word lines and applying an unselected word line voltage to a first unselected word line group of the word lines, in a second round, applying the selected word line voltage to a second selected word line group of the word lines and applying the unselected word line voltage to a second unselected word line group of the word lines, wherein the first selected word line group is different from the second selected word line group and the first unselected word line group is different from the second unselected word line group; performing an erase operation on the word lines; and performing a programming operation on the word lines.

[0006] According to an example of the present disclosure, a storage device is provided, comprising: a controller; and a storage array coupled to the controller, the storage array comprising a plurality of word lines. The controller is configured to: perform a precharge operation on the word lines, apply a selected word line voltage to a first selected word line group of the word lines and apply an unselected word line voltage to a first unselected word line group of the word lines in a first round, apply the selected word line voltage to a second selected word line group of the word lines and apply the unselected word line voltage to a second unselected word line group of the word lines in a second round, wherein the first selected word line group is different from the second selected word line group and the first unselected word line group is different from the second unselected word line group; perform an erase operation on the word lines; and perform a program operation on the word lines.

[0007] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A functional block diagram of a storage device according to an embodiment of the present disclosure is shown.

[0009] Figure 1B A schematic diagram of a memory array according to an embodiment of the present disclosure is shown.

[0010] Figure 2 A flow chart of an operating method of a storage device according to an embodiment of the present disclosure is shown.

[0011] Figure 3A A voltage waveform diagram according to an embodiment of the present disclosure is shown.

[0012] Figure 3B A voltage waveform diagram according to another embodiment of the present disclosure is shown.

[0013] Figure 4A and Figure 4B A schematic diagram of a pre-charging operation round according to the first embodiment of the present disclosure is shown.

[0014] Figure 5A and Figure 5B A schematic diagram of a pre-charging operation round according to the second embodiment of the present disclosure is shown.

[0015] FIG. 6A to FIG. 6D A schematic diagram of a pre-charging operation round according to the third embodiment of the present disclosure is shown.

[0016] Fig. 7A A comparison diagram of short-term threshold voltage (Vt) spread according to an embodiment of the present disclosure and the prior art is shown.

[0017] Figure 7B The threshold voltage (Vt) width reduction ratio is shown.

[0018] Fig. 8A A comparison diagram of high temperature long-term threshold voltage diffusion according to an embodiment of the present disclosure and the prior art is shown.

[0019] Figure 8B Shows the lower bound threshold voltage retention loss.

[0020]

Explanation of symbols

[0021] 100: Storage device

[0022] 110: Controller

[0023] 120: Storage array

[0024] BL: Bit Line

[0025] SSL: string select line

[0026] GSL: Global Selection Line

[0027] DWL_inner: inner redundant word line

[0028] DWL_outer: outer redundant word line

[0029] WL1~WLN: word line

[0030] 210~230: Steps

[0031] L7A1~L7G1, L7A2~L7G2: Curve

[0032] L8A1~L8G1, L8A2~L8G2, L8A3~L8G3, L81~L82: Curve DETAILED DESCRIPTION

[0033] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] The technical terms in this specification refer to the customary terms in the technical field. If some terms are explained or defined in this specification, the interpretation of these terms shall be based on the explanation or definition in this specification. Each embodiment of the present disclosure has one or more technical features. Under the premise of possible implementation, technicians in this technical field may selectively implement some or all of the technical features in any embodiment, or selectively combine some or all of the technical features in these embodiments.

[0035] Please refer to Figure 1A, which illustrates a functional block diagram of a storage device 100 according to an embodiment of the present disclosure. The storage device 100 includes: a controller 110 and a storage array 120. The controller 110 is coupled to the storage array 120. The controller 110 controls the operation of the storage array 120, such as but not limited to, pre-filling operation, erase operation, programming operation, etc.

[0036] Please refer to Figure 1B , which is a schematic diagram of a memory array 120 according to an embodiment of the present disclosure. The memory array 120 includes: a plurality of bit lines BL, a string selection line SSL, a global selection line GSL, a plurality of inner redundant word lines DWL_inner, a plurality of outer redundant word lines DWL_outer, and a plurality of word lines WL1~WLN (N is a positive integer).

[0037] Please refer to Figure 2 , which depicts a flow chart of an operation method of a storage device according to an embodiment of the present disclosure. In step 210, a precharge operation is performed. In step 220, an erase operation is performed. In step 230, a programming operation is performed. In a possible embodiment of the present disclosure, the details of the erase operation and the programming operation may not be particularly limited here. The details of performing the precharge operation in the embodiment of the present disclosure will be described below.

[0038] Figure 3A A voltage waveform diagram according to an embodiment of the present disclosure is shown. Figure 3B A voltage waveform diagram according to another embodiment of the present disclosure is shown. Figure 3A and Figure 3B , VSWL represents a selected word line voltage applied to at least one selected word line, VBL represents a bit line voltage applied to these bit lines, VUWL represents an unselected word line voltage applied to at least one unselected word line, VDWL_outer represents an outer redundant word line voltage applied to these outer redundant word lines DWL_outer, VDWL_inner represents an inner redundant word line voltage applied to these inner redundant word lines DWL_inner, VSSL represents a string selection line voltage applied to the string selection line, and VGSL represents a global selection line voltage applied to the global selection line.

[0039] In the disclosed embodiment, each pre-charging operation loop includes four stages: an off stage (t0A and t0B), a first pre-on stage (t1A and t1B), a second pre-on stage (t2A and t2B) and a pre-filling stage (t3A and t3B).

[0040] Please refer to Figure 3A .

[0041] In the off phase t0A, all voltages are at a logic low level (for example but not limited to 0V).

[0042] In the first pre-conduction stage t1A, the bit line voltage VBL is turned to a logic high level to pre-conduct the bit line BL. As for the selected word line voltage VSWL, the unselected word line voltage VUWL, the outer redundant word line voltage VDWL_outer, the inner redundant word line voltage VDWL_inner, the string selection line voltage VSSL and the overall selection line voltage VGSL, they maintain a logic low level. Therefore, the first pre-conduction stage t1A can also be called a bit line pre-conduction stage to pre-conduct the bit line.

[0043] In the second pre-conduction stage t2A, the selected word line voltage VSWL transitions to the first selected word line voltage VSWL1; the bit line voltage VBL is maintained at a logic high level; the unselected word line voltage VUWL transitions to a logic high level; the outer redundant word line voltage VDWL_outer transitions to a logic high level; the inner redundant word line voltage VDWL_inner transitions to a logic high level; and the string selection line voltage VSSL and the overall selection line voltage VGSL maintain a logic low level. Therefore, the second pre-conduction stage t2A can also be called an unselected word line pre-conduction stage to pre-conduct the unselected word line.

[0044] In the pre-charge phase t3A, the selected word line voltage VSWL is increased from the first selected word line voltage VSWL1 to the second selected word line voltage VSWL2 (for example but not limited to, the second selected word line voltage VSWL2 is equal to Vgpgm); the bit line voltage VBL is maintained at a logic high level; the unselected word line voltage VUWL is maintained at a logic high level; the outer redundant word line voltage VDWL_outer is maintained at a logic high level; the inner redundant word line voltage VDWL_inner is maintained at a logic high level; and the string selection line voltage VSSL and the overall selection line voltage VGSL are maintained at a logic low level.

[0045] In a possible embodiment of the present disclosure, Figure 3AFor example, the logic high level of the bit line voltage VBL can be the value of the power supply VCC or higher. The value of the power supply VCC falls between 1.2V and 3.3V, and the logic high level of the bit line voltage VBL can be between 1V and 4V; the first selected word line voltage VSWL1 is greater than 0V but less than the second selected word line voltage VSWL2 (i.e., 0 < VSWL1 < VSWL2); the second selected word line voltage VSWL2 is a programming voltage (usually between 15V and 25V); the logic high level of the unselected word line voltage VUWL is approximately a difference between the programming voltage and a first predetermined voltage (such as 15V). Therefore, the logic high level of the unselected word line voltage VUWL is between 0V and 10V; the logic high level of the internal redundant word line voltage VDWL_inner is greater than or equal to the sum of the highest threshold value of the memory cell and a second predetermined voltage (for example, but not limited to, 1.5V). The highest threshold value of the memory cell is usually between 5V and 6V. Therefore, the logic high level of the internal redundant word line voltage VDWL_inner is greater than or equal to 6.5V; the logic high level of the external redundant word line voltage VDWL_outer is less than the difference between the logic high level of the internal redundant word line voltage VDWL_inner and a third predetermined voltage (for example, but not limited to, 2V). Therefore, the logic high level of the external redundant word line voltage VDWL_outer is less than 4.5V (for example, it is between 2V and 4.5V).

[0046] Now, please refer to Figure 3B . Basically, the off-phase t0B and the first pre-conduction phase t1B are the same as or similar to the off-phase t0A and the first pre-conduction phase t1A, so the details are omitted here.

[0047] In the second pre-conduction phase t2B, the selected word line voltage VSWL is maintained at the logic low level; the bit line voltage VBL is maintained at the logic high level; the unselected word line voltage VUWL transitions to the first unselected word line voltage VUWL1; the external redundant word line voltage VDWL_outer transitions to the logic high level; the internal redundant word line voltage VDWL_inner transitions to the logic high level; and the string select line voltage VSSL and the global select line voltage VGSL remain at the logic low level. Therefore, the second pre-conduction phase t2B can also be called the unselected word line pre-conduction phase.

[0048] During the pre-charge stage t3B, the selected word line voltage VSWL transitions to a logic high level; the bit line voltage VBL is maintained at a logic high level; the unselected word line voltage VUWL increases from the first unselected word line voltage VUWL1 to the second unselected word line voltage VUWL2; the external redundant word line voltage VDWL_outer is maintained at a logic high level; the internal redundant word line voltage VDWL_inner is maintained at a logic high level; and the string select line voltage VSSL and the overall select line voltage VGSL remain at a logic low level. Among them, a part of the second pre-conduction stage t2B overlaps with the pre-charge stage t3B.

[0049] In a possible embodiment of the present disclosure, taking Figure 3B as an example, the logic high level of the bit line voltage VBL, the logic high level of the internal redundant word line voltage VDWL_inner, and the logic high level of the external redundant word line voltage VDWL_outer may be the same as Figure 3A . In Figure 3B , the logic high level of the selected word line voltage VSWL may be the same as the programming voltage (usually between 15V and 25V); the first unselected word line voltage VUWL1 is greater than 0V but less than the second unselected word line voltage VUWL2 (i.e., 0 < VUWL1 < VUWL2); the second unselected word line voltage VUWL2 may be the difference (between 0V and 10V) between the programming voltage (usually between 15V and 25V) and the first predetermined voltage (for example, 15V).

[0050] Now, the details of the pre-charge operation of the embodiment of the present disclosure will be described. When performing each pre-charge operation cycle, one or more target word lines are selected from these word lines WL1~WLN as the selected word line group, and the remaining word lines are regarded as the unselected word line group. Therefore, the selected word line voltage VSWL is applied to the selected word line group, and the unselected word line voltage VUWL is applied to the unselected word line group.

[0051] Now, it will be described how to select the "selected word line group" and the "unselected word line group".

[0052] First Embodiment:

[0053] In the first embodiment of the present disclosure, the word lines WL1~WLN are divided into an "odd word line group" and an "even word line group". That is, in the first embodiment, the "odd word line group" includes: word lines WL1, WL3,..., WL(N - 1). The "even word line group" includes: word lines WL2, WL4,..., WLN (when N is a positive even integer).

[0054] Figure 4A And Figure 4BA schematic diagram of a precharge operation round according to the first embodiment of the present disclosure is shown. For the convenience of explanation, in the first precharge operation round, the "odd word line group" is selected as the "selected word line group" and the "even word line group" is selected as the "unselected word line group", as shown in FIG. Figure 4A As shown; and, in the second precharge operation round, the "even word line group" is selected as the "selected word line group" and the "odd word line group" is selected as the "unselected word line group", as Figure 4B It should be understood that the present disclosure is not limited thereto.

[0055] That is, in the first embodiment, in the first precharge operation round, the selected word line voltage VSWL (eg Figure 3A or Figure 3B ) is applied to the “odd word line group” (including: word lines WL1, WL3, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the "even word line group" (including: word lines WL2, WL4, ...). Then, in the second precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the “even word line group” (including: word lines WL2, WL4, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the “odd word line group” (including: word lines WL1, WL3, ...).

[0056] Of course, the present disclosure is not limited thereto. In a possible variation of the first embodiment, in the first precharge operation round, the "even word line group" is selected as the "selected word line group" and the "odd word line group" is selected as the "unselected word line group"; and in the second precharge operation round, the "odd word line group" is selected as the "selected word line group" and the "even word line group" is selected as the "unselected word line group". This is also within the spirit of the present disclosure.

[0057] As can be seen from the above, in the first embodiment, the pre-charging operation can be completed in two rounds.

[0058] Second embodiment

[0059] In the second embodiment of the present disclosure, the word lines WL1-WLN are divided into a "first word line group" and a "second word line group". The "first word line group" includes a plurality of "first word line sub-groups", each of which includes i adjacent continuous word lines (i is a positive integer), and the "second word line group" includes a plurality of "second word line sub-groups", each of which includes j adjacent continuous word lines (j is a positive integer). The "first word line sub-groups" and the "second word line sub-groups" are interlaced with each other.

[0060] In the second embodiment, in the first precharge operation round, the selected word line voltage VSWL is applied to the "first word line group" and the unselected word line voltage VUWL is applied to the "second word line group". Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group". Of course, the present disclosure is not limited thereto.

[0061] For easier understanding, several examples are given below to explain the second embodiment.

[0062] Figure 5A and Figure 5B A schematic diagram of a pre-charge operation round according to the second embodiment of the present disclosure is shown. Figure 5A and Figure 5B . Take i=2 and j=1 as an example. Among the word lines WL1~WLN, word lines WL1 and WL2 belong to one of the "first word line subgroups" of the "first word line group"; word line WL3 belongs to one of the "second word line subgroups" of the "second word line group"; word lines WL4 and WL5 belong to one of the "first word line subgroups" of the "first word line group"; word line WL6 belongs to one of the "second word line subgroups" of the "second word line group", and the rest can be deduced in the same way. Therefore, in the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the “first word line group” (word lines WL1, WL2, WL4, WL5, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the “second word line group” (word lines WL3, WL6, ...), such as Figure 5A Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group", as shown in FIG. Figure 5B Of course, the present disclosure is not limited thereto.

[0063] Alternatively, in the second embodiment of the present disclosure, i=2 and j=2 are used as an example for explanation. Among the word lines WL1~WLN, word lines WL1 and WL2 belong to one of the "first word line subgroups" of the "first word line group"; word lines WL3 and WL4 belong to one of the "second word line subgroups" of the "second word line group"; word lines WL5 and WL6 belong to one of the "first word line subgroups" of the "first word line group"; word lines WL7 and WL8 belong to one of the "second word line subgroups" of the "second word line group", and the rest can be deduced in the same way. Therefore, in the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B) is applied to the “first word line group” (word lines WL1, WL2, WL5, WL6, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the "second word line group" (word lines WL3, WL4, WL7, WL8, ...). Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group". Of course, the present disclosure is not limited thereto.

[0064] Alternatively, in the second embodiment of the present disclosure, i=3 and j=1 are used as an example for explanation. Among the word lines WL1~WLN, word lines WL1~WL3 belong to one of the "first word line subgroups" of the "first word line group"; word line WL4 belongs to one of the "second word line subgroups" of the "second word line group"; word lines WL5~WL7 belong to one of the "first word line subgroups" of the "first word line group"; word line WL8 belongs to one of the "second word line subgroups" of the "second word line group", and the rest can be deduced in the same way. Therefore, in the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the “first word line group” (word lines WL1~WL3, WL5~WL7, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the "second word line group" (word lines WL4, WL8, ...). Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group". Of course, the present disclosure is not limited thereto.

[0065] Alternatively, in the second embodiment of the present disclosure, i=3 and j=2 are used as an example for explanation. Among the word lines WL1~WLN, word lines WL1~WL3 belong to one of the "first word line subgroups" of the "first word line group"; word lines WL4 and WL5 belong to one of the "second word line subgroups" of the "second word line group"; word lines WL6~WL8 belong to one of the "first word line subgroups" of the "first word line group"; word lines WL9 and WL10 belong to one of the "second word line subgroups" of the "second word line group", and the rest can be deduced in the same way. Therefore, in the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the “first word line group” (word lines WL1~WL3, WL6~WL8, ...) and the unselected word line voltage VUWL (such as Figure 3A or Figure 3B) is applied to the "second word line group" (word lines WL4, WL5, WL9, WL10, ...). Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group". Of course, the present disclosure is not limited thereto.

[0066] In a possible variation of the second embodiment of the present disclosure, in the first precharge operation round, the selected word line voltage VSWL is applied to the "second word line group" and the unselected word line voltage VUWL is applied to the "first word line group". Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "first word line group" and the unselected word line voltage VUWL is applied to the "second word line group". This is also within the spirit of the present disclosure.

[0067] It can be seen from the above that in the second embodiment, the pre-charging operation can be completed in two rounds.

[0068] Third embodiment

[0069] The word lines WL1~WLN are divided into a "selected word line group" and an "unselected word line group". The "selected word line group" includes adjacent continuous k (k is a positive integer) word lines, and the "unselected word line group" includes the remaining (Nk) word lines, and a different selected word line is selected in each round.

[0070] For ease of understanding, k=2 is used as an example for explanation below, but it should be understood that the present disclosure is not limited thereto. FIG. 6A to FIG. 6D A schematic diagram of a pre-charge operation round according to the third embodiment of the present disclosure is shown. FIG. 6A to FIG. 6D . In the third embodiment, in the first round, word lines WL1~WL2 are selected as the "selected word line group", and the remaining word lines WL3~WLN are the "unselected word line group"; in the second round, word lines WL3~WL4 are selected as the "selected word line group", and the remaining word lines (WL1~WL2, WL5~WLN) are the "unselected word line group". In the third round, word lines WL5~WL6 are selected as the "selected word line group", and the remaining word lines (WL1~WL4, WL7~WLN) are the "unselected word line group". In the (N / 2)th round, word lines WL(N-1)~WLN are selected as the "selected word line group", and the remaining word lines (WL1~WL(N-2)) are the "unselected word line group". In the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the "selected word line group" (word lines WL1~WL2) while the unselected word line voltage VUWL (such as Figure 3A or Figure 3B) is applied to the "unselected word line group" (word lines WL3~WLN). Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL3~WL4) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1~WL2, WL5~WLN). Then, in the third precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL5~WL6) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1~WL4, WL7~WLN). And so on. In the (N / 2)th precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL(N-1) to WLN) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1 to WL(N-2)). Of course, the present disclosure is not limited thereto.

[0071] Alternatively, in a possible variation of the third embodiment (k=3), in the first round, word lines WL1~WL3 are selected as the "selected word line group", and the remaining word lines WL4~WLN are the "unselected word line group"; in the second round, word lines WL4~WL6 are selected as the "selected word line group", and the remaining word lines (WL1~WL3, WL7~WLN) are the "unselected word line group". In the third round, word lines WL7~WL9 are selected as the "selected word line group", and the remaining word lines (WL1~WL6, WL10~WLN) are the "unselected word line group". In the (N / 3)th round, word lines WL(N-2)~WLN are selected as the "selected word line group", and the remaining word lines (WL1~WL(N-3)) are the "unselected word line group". In the first precharge operation round, the selected word line voltage VSWL (such as Figure 3A or Figure 3B ) is applied to the "selected word line group" (word lines WL1~WL3) while the unselected word line voltage VUWL (such as Figure 3A or Figure 3B ) is applied to the "unselected word line group" (word lines WL4~WLN). Then, in the second precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL4~WL6) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1~WL3, WL7~WLN). Then, in the third precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL7~WL9) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1~WL6, WL10~WLN). And so on. In the (N / 3)th precharge operation round, the selected word line voltage VSWL is applied to the "selected word line group" (WL(N-2)~WLN) and the unselected word line voltage VUWL is applied to the "unselected word line group" (WL1~WL(N-3)).

[0072] Please refer to Fig. 7A , which shows a comparison diagram of short-term threshold voltage (Vt) diffusion according to an embodiment of the present disclosure and the prior art. Fig. 7A In the figure, curves L7A1~L7G1 represent the short-term threshold voltage (Vt) distribution curves of the storage device applying an embodiment of the present disclosure in state A (Astate) to state G (G state); curves L7A2~L7G2 represent the short-term threshold voltage distribution curves of the existing storage device (not applying the embodiment of the present disclosure) in state A to state G.

[0073] Please refer to Figure 7B , which shows the reduction ratio of the threshold voltage (Vt) width, wherein the horizontal axes A to G represent states A to G respectively, and the vertical axis represents the reduction ratio of the threshold voltage width under states A to G. The reduction ratio of the threshold voltage width is defined as the ratio of the "short-term threshold voltage distribution width of the memory device applying an embodiment of the present disclosure" to the "short-term threshold voltage distribution width of the existing memory device (not applying the embodiment of the present disclosure)" under states A to G respectively. For example, under state A, the "short-term threshold voltage distribution width of the memory device applying an embodiment of the present disclosure" is between 0.45V and 0.7V, while the "short-term threshold voltage distribution width of the existing memory device (not applying the embodiment of the present disclosure)" is between 0.5V and 1V, so the reduction ratio of the threshold voltage width is 0.7 to 0.9.

[0074] Depend on Fig. 7A and Figure 7B It can be seen that an embodiment of the present disclosure can indeed effectively narrow the short-term threshold voltage (Vt) distribution (the degree of narrowing can reach more than 10%).

[0075] Please refer to Fig. 8A , which shows a comparison diagram of high temperature long-term threshold voltage diffusion according to an embodiment of the present disclosure and the prior art. Fig. 8A In the figure, curves L8A1~L8G1 represent high temperature long-term threshold voltage distribution curves of a storage device applying an embodiment of the present disclosure in state A (Astate) to state G (G state) respectively (high temperature long term means a threshold voltage distribution curve measured in a high temperature environment after being placed for a long period of time after programming); curves L8A2~L8G2 represent high temperature long-term threshold voltage distribution curves of an existing storage device (not applying the embodiment of the present disclosure) in state A to state G respectively; curves L8A3~L8G3 represent threshold voltage distribution curves of an existing storage device (not applying the embodiment of the present disclosure) in state A to state G respectively (obtained from testing immediately after programming).

[0076] Please refer to Figure 8B, which shows the lower bound threshold voltage retention loss, where A to G on the horizontal axis represent states A to G respectively.

[0077] Curve L81 represents the value obtained by subtracting curves L8A3~L8G3 from curves L8A1~L8G1, and curve L82 represents the value obtained by subtracting curves L8A3~L8G3 from curves L8A2~L8G2. The sum of the values ​​of curve L81 in state A to state G can be obtained by about -2.7V, and the sum of the values ​​of curve L82 in state A to state G can be obtained by about -3.6V. Therefore, the improvement that can be obtained by the embodiment of the present disclosure is about 0.9V (-2.7V-3.6V=0.9V).

[0078] Depend on Fig. 8A and Figure 8B It can be seen that an embodiment of the present disclosure can indeed effectively narrow the high temperature long-term threshold voltage (Vt) distribution.

[0079] In the disclosed embodiment, the channel level can be greatly improved by applying the selected word line voltage and the unselected word line, and the generated hot carriers can be used to fill the space region. In addition, the space region filled with carriers can suppress the threshold voltage diffusion caused by the rapid level of charge, thereby narrowing the threshold voltage distribution. In addition, the space region filled with carriers can reduce the long-term charge level movement, thereby changing the charge retention loss.

[0080] In the embodiment of the present disclosure, the operation time of one round is about hundreds of μs. Therefore, the operation time of the embodiment of the present disclosure is about 10 times faster than that of the prior art (which requires several milliseconds (ms)).

[0081] The embodiments of the present disclosure may be applied to three-dimensional (3D) flash memory, for example, vertical channel type 3D flash memory, vertical gate type 3D flash memory, charge trapping type 3D flash memory, and floating gate type 3D flash memory.

[0082] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person skilled in the art with common knowledge in the technical field to which the present invention belongs may make various modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

[0083] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for operating a storage device, the storage device comprising a plurality of word lines, the method for operating the storage device comprising: Performing a precharge operation on the word lines, in a first precharge operation round, applying a selected word line voltage to a first selected word line group of the word lines and applying an unselected word line voltage to a first unselected word line group of the word lines, and in a second precharge operation round, applying the selected word line voltage to a second selected word line group of the word lines and applying the unselected word line voltage to a second unselected word line group of the word lines, wherein the first selected word line group is different from the second selected word line group and the first unselected word line group is different from the second unselected word line group; performing an erase operation on the word lines; and A programming operation is performed on the word lines.

2. The method for operating a storage device according to claim 1, wherein: In a non-selected word line pre-conduction phase of the first pre-charge operation round, the selected word line voltage is switched to a first selected word line voltage and the non-selected word line voltage is switched to a logic high level; as well as In a precharge phase of the first precharge operation round, the selected word line voltage is increased from the first selected word line voltage to a second selected word line voltage and the unselected word line voltage is maintained at the logic high level. Among them, each pre-charge operation round includes 4 stages: a closing stage, a first pre-conduction stage, a second pre-conduction stage and a pre-charge stage; the first selected word line voltage is greater than 0 volts but less than the second selected word line voltage, the second selected word line voltage is equal to a programming voltage, and the logic high level of the unselected word line voltage is a difference between the programming voltage and a first predetermined voltage.

3. The method for operating a storage device according to claim 1, wherein: In a non-selected word line pre-conduction phase of the first pre-charge operation round, the selected word line voltage is maintained at a logic low level and the non-selected word line voltage is switched to a first non-selected word line voltage; as well as In a precharge phase of the first precharge operation round, the selected word line voltage is switched to a logic high level and the unselected word line voltage is increased from the first unselected word line voltage to a second unselected word line voltage, wherein the unselected word line pre-conduction phase partially overlaps with the precharge phase, Among them, each pre-charge operation round includes 4 stages: a closing stage, a first pre-conduction stage, a second pre-conduction stage and a pre-charge stage; the logic high level of the selected word line voltage is a programming voltage, the first unselected word line voltage is greater than 0 volts but less than the second unselected word line voltage, and the second unselected word line voltage is equal to a difference between the programming voltage and a first predetermined voltage.

4. The method for operating a storage device according to claim 1, wherein: The word lines include an odd word line group and an even word line group, the first selected word line group includes any one of the odd word line group and the even word line group, and the first unselected word line group includes the other of the odd word line group and the even word line group.

5. The method for operating a storage device according to claim 1, wherein: The word lines include a first word line group and a second word line group, the first word line group includes a plurality of first word line subgroups, each of the first word line subgroups includes i adjacent and continuous word lines, i is a positive integer, and the second word line group includes a plurality of second word line subgroups, each of the second word line subgroups includes j adjacent and continuous word lines, j is a positive integer, and the first word line subgroups and the second word line subgroups are interlaced with each other; the first selected word line group includes any one of the first word line group and the second word line group, and the first unselected word line group includes the other of the first word line group and the second word line group; or The word lines are N word lines, N is a positive integer, the first selected word line group includes k adjacent continuous word lines, and the first unselected word line group includes the remaining (Nk) word lines of the word lines, k is a positive integer.

6. A storage device, comprising: a controller; as well as A memory array is coupled to the controller, the memory array comprising a plurality of word lines. The controller architecture consists of: Performing a precharge operation on the word lines, in a first precharge operation round, applying a selected word line voltage to a first selected word line group of the word lines and applying an unselected word line voltage to a first unselected word line group of the word lines, and in a second precharge operation round, applying the selected word line voltage to a second selected word line group of the word lines and applying the unselected word line voltage to a second unselected word line group of the word lines, wherein the first selected word line group is different from the second selected word line group and the first unselected word line group is different from the second unselected word line group; performing an erase operation on the word lines; and A programming operation is performed on the word lines.

7. The storage device according to claim 6, wherein: In a non-selected word line pre-conduction phase of the first pre-charge operation round, the selected word line voltage is switched to a first selected word line voltage and the non-selected word line voltage is switched to a logic high level; as well as In a precharge phase of the first precharge operation round, the selected word line voltage is increased from the first selected word line voltage to a second selected word line voltage and the unselected word line voltage is maintained at the logic high level. Among them, each pre-charge operation round includes 4 stages: a closing stage, a first pre-conduction stage, a second pre-conduction stage and a pre-charge stage; the first selected word line voltage is greater than 0 volts but less than the second selected word line voltage, the second selected word line voltage is equal to a programming voltage, and the logic high level of the unselected word line voltage is a difference between the programming voltage and a first predetermined voltage.

8. The storage device according to claim 6, wherein: In a non-selected word line pre-conduction phase of the first pre-charge operation round, the selected word line voltage is maintained at a logic low level and the non-selected word line voltage is switched to a first non-selected word line voltage; as well as In a precharge phase of the first precharge operation round, the selected word line voltage is switched to a logic high level and the unselected word line voltage is increased from the first unselected word line voltage to a second unselected word line voltage, wherein the unselected word line pre-conduction phase partially overlaps with the precharge phase, Among them, each pre-charge operation round includes 4 stages: a closing stage, a first pre-conduction stage, a second pre-conduction stage and a pre-charge stage; the logic high level of the selected word line voltage is a programming voltage, the first unselected word line voltage is greater than 0 volts but less than the second unselected word line voltage, and the second unselected word line voltage is equal to a difference between the programming voltage and a first predetermined voltage.

9. The storage device according to claim 6, wherein: The word lines include an odd word line group and an even word line group, the first selected word line group includes any one of the odd word line group and the even word line group, and the first unselected word line group includes the other of the odd word line group and the even word line group.

10. The storage device according to claim 6, wherein: The word lines include a first word line group and a second word line group, the first word line group includes a plurality of first word line subgroups, each of the first word line subgroups includes i adjacent and continuous word lines, i is a positive integer, and the second word line group includes a plurality of second word line subgroups, each of the second word line subgroups includes j adjacent and continuous word lines, j is a positive integer, and the first word line subgroups and the second word line subgroups are interlaced with each other; the first selected word line group includes any one of the first word line group and the second word line group, and the first unselected word line group includes the other of the first word line group and the second word line group; or The word lines are N word lines, N is a positive integer, the first selected word line group includes k adjacent continuous word lines, and the first unselected word line group includes the remaining (Nk) word lines among the word lines, k is a positive integer.

Images