Semiconductor device

Abstract

Provided is a semiconductor device capable of preventing malfunction of a gate drive circuit caused by negative voltage noise. The semiconductor device includes a pad (2), a control circuit (5), a plurality of high-potential-side circuit regions (10u, 10v, 10w) that are different in distance from the pad and each have a gate drive circuit (6u, 6v, 6w), a set-side level shifter (71, 73, 75), a reset-side level shifter (72, 74, 76), and a ring wiring (8u, 8v, 8w), a set-side wiring (21) that electrically connects the pad and the set-side level shifter, and a reset-side wiring (22) that electrically connects the pad and the reset-side level shifter, wherein the ring wiring (8v, 8w) on the side closer to the pad is electrically connected to the set-side wiring and the reset-side wiring via the ring wiring (8u) on the side farther from the pad.

Description

Technical Field

[0001] This invention relates to semiconductor devices such as high voltage integrated circuit devices (HVIC). Background Technology

[0002] Previously, transformers and optocouplers were used to electrically isolate the gates of semiconductor power switching elements such as insulated-gate bipolar transistors (IGBTs) that constitute bridge circuits for power conversion. However, in recent years, high-voltage integrated circuit devices (hereinafter referred to as "HVICs") that do not require electrical insulation have been used primarily in small-capacity applications to achieve cost reduction (see Patent Document 1 and Non-Patent Document 1).

[0003] The HVIC includes a gate drive circuit for driving the gate of a semiconductor power switching element, a control circuit for controlling the gate drive circuit, and a level shifter for signal transmission between the control circuit and the gate drive circuit. The control circuit operates with ground potential (GND potential) as a reference. The gate drive circuit operates with a floating VS potential as a reference. The gate drive circuit and the control circuit are isolated from each other by a high-voltage junction termination region (HVJT). The high-voltage junction termination region is composed of a high-voltage diode with the gate drive circuit side (VS terminal side) as the cathode and the control circuit side (GND terminal side) as the anode.

[0004] The level shifter is, for example, constructed from a high-voltage n-channel MOSFET. It integrates two level shifters: a set-side level shifter and a reset-side level shifter, which are integrated with the high-voltage junction termination region. The sources of both the set-side and reset-side level shifters are connected to the GND pad via two separate wirings: a set-side wiring and a reset-side wiring.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: Japanese Patent No. 3214818 Specification

[0008] Non-patent literature

[0009] Non-Patent Literature 1: Proc. of The 11th Int. Symp. on Power Semiconductor Devices and ICs IEEE and IEEE J 1999 pp. 333-336 Summary of the Invention

[0010] The problem the invention aims to solve

[0011] In the HVICs described in Patent Document 1 and Non-Patent Document 1, negative voltage noise, known as -Vs noise, occurs at the VS terminal of the HVIC along with the switching operation of the semiconductor power switching element. Due to mounting or control circuit layout reasons, the GND pad is not necessarily positioned symmetrically with respect to the set-side level shifter and the reset-side level shifter, resulting in a difference in wiring resistance between the source of the set-side level shifter and the GND pad compared to the source of the reset-side level shifter. Because of this difference, sometimes only one of the set-side and reset-side level shifters is falsely triggered when negative voltage noise occurs, causing a false inversion of the gate drive circuit output.

[0012] In view of the above problems, the object of the present invention is to provide a semiconductor device that can prevent malfunction of the gate drive circuit caused by negative voltage noise.

[0013] Solution for solving the problem

[0014] One aspect of the present invention is a semiconductor device comprising: (a) a pad; (b) a control circuit that uses a first potential applied to the pad as a reference potential; and (c) a plurality of high-potential side circuit regions, the plurality of high-potential side circuit regions being at different distances from the pad, each of the plurality of high-potential side circuit regions having a gate drive circuit, a set-side level shifter, and a reset-side level shifter, wherein the gate drive circuit uses a second potential of a floating potential as a reference potential, the set-side level shifter converts a set signal with the first potential as a reference potential into a set signal with the second potential as a reference, and the reset-side level shifter converts a set signal with the first potential as a reference potential into a set signal with the second potential as a reference. The reset signal of the bit is transformed into a reset signal based on the second potential; (d) a set-side routing that electrically connects the pad to the set-side level shifter of the high-potential side circuit region farthest from the pad; and (e) a reset-side routing that electrically connects the pad to the reset-side level shifter of the high-potential side circuit region farthest from the pad, wherein the set-side level shifter of the high-potential side circuit region located on the side closer to the pad than the high-potential side circuit region farthest from the pad is electrically connected to the pad via the set-side routing, and the reset-side level shifter of the high-potential side circuit region located on the side closer to the pad than the high-potential side circuit region farthest from the pad is electrically connected to the pad via the reset-side routing.

[0015] The aim of another aspect of the present invention is a semiconductor device comprising: (a) a pad; (b) a control circuit that uses a first potential applied to the pad as a reference potential; and (c) a plurality of high-potential side circuit regions, the plurality of high-potential side circuit regions being at different distances from the pad, each of the plurality of high-potential side circuit regions having a gate drive circuit, a set-side level shifter, a reset-side level shifter, and a ring wiring, wherein the gate drive circuit uses a second potential of a floating potential as a reference potential, the set-side level shifter transforms a set signal with the first potential as a reference potential into a set signal with the second potential as a reference, and the reset-side level shifter... The device converts a reset signal with a first potential as the reference potential into a reset signal with a second potential as the reference potential. The loop wiring is connected to the set-side level shifter and the reset-side level shifter; (d) the set-side wiring electrically connects the pad to the set-side level shifter of each of the multiple high-potential side circuit regions; and (e) the reset-side wiring electrically connects the pad to the reset-side level shifter of each of the multiple high-potential side circuit regions, wherein the loop wiring of the high-potential side circuit region located on the side closer to the pad is electrically connected to the set-side wiring and the reset-side wiring via the loop wiring of the high-potential side circuit region located on the side farther from the pad.

[0016] The effects of the invention

[0017] According to the present invention, a semiconductor device is provided that can prevent malfunction of the gate drive circuit caused by negative voltage noise. Attached Figure Description

[0018] Figure 1 This is a top view of a semiconductor device according to an embodiment of the present invention.

[0019] Figure 2 This is a top view of the semiconductor device according to an embodiment of the present invention, with a portion omitted.

[0020] Figure 3 From Figure 1 A cross-sectional view observed along the AA direction.

[0021] Figure 4 From Figure 1 A cross-sectional view observed along the BB direction.

[0022] Figure 5 This is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

[0023] Figure 6 This is a table that shows the relationship between the state of the level shifter and the gate drive output.

[0024] Figure 7This is a top view of the semiconductor device involved in the comparative example.

[0025] Figure 8 This is a circuit diagram of the semiconductor device involved in the comparative example.

[0026] Figure 9 This is a top view showing the path of the noise current when -Vs noise occurs in the U phase of the semiconductor device involved in the comparative example.

[0027] Figure 10 This is a circuit diagram showing the path of the noise current when -Vs noise occurs in the U phase of the semiconductor device involved in the comparative example.

[0028] Figure 11 This is a graph showing the noise current when -Vs noise occurs in the U phase of the semiconductor device involved in the comparative example.

[0029] Figure 12 This is a graph showing the gate-source voltage generated by the level shifter in phase W when -Vs noise occurs in phase U of the semiconductor device involved in the comparative example.

[0030] Figure 13 These are other top views of the semiconductor device involved in the comparative example.

[0031] Figure 14 This is yet another top view of the semiconductor device involved in the comparative example.

[0032] Figure 15 This is a top view showing the path of the noise current when -Vs noise occurs in the U phase of the semiconductor device according to an embodiment of the present invention.

[0033] Figure 16 This is a top view showing the path of the noise current when -Vs noise occurs in the W phase of the semiconductor device according to an embodiment of the present invention.

[0034] Figure 17 This is a circuit diagram showing the path of the noise current when -Vs noise occurs in the W phase of the semiconductor device according to an embodiment of the present invention.

[0035] Figure 18 This is a graph showing the noise current when -Vs noise occurs in the W phase of the semiconductor device according to an embodiment of the present invention.

[0036] Figure 19 This is a graph showing the gate-source voltage generated by the level shifter in phase U when -Vs noise occurs in phase W of the semiconductor device according to an embodiment of the present invention.

[0037] Figure 20This is a table showing the GND wiring resistance of the semiconductor device according to the embodiments and comparative examples of the present invention.

[0038] Figure 21 This is a top view of a semiconductor device according to a first variation of an embodiment of the present invention.

[0039] Figure 22 This is a top view of a semiconductor device according to a second variation of an embodiment of the present invention.

[0040] Figure 23 This is a top view of a semiconductor device according to a third variation of an embodiment of the present invention.

[0041] Figure 24 This is a top view of a semiconductor device according to a fourth variation of an embodiment of the present invention.

[0042] Figure 25 This is a top view of a semiconductor device according to a fifth variation of an embodiment of the present invention.

[0043] Figure 26 This is a top view of a semiconductor device according to a sixth variation of an embodiment of the present invention. Detailed Implementation

[0044] The embodiments and variations thereof of the present invention will now be described with reference to the accompanying drawings. In the drawings, the same or similar parts are labeled with the same or similar reference numerals, and repeated descriptions are omitted. The drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of thicknesses of each layer, etc., may sometimes differ from actual conditions. Furthermore, the drawings may include parts with different dimensional relationships or ratios. Additionally, the embodiments shown below are illustrative of apparatuses and methods for embodying the technical concept of the present invention; the technical concept of the present invention does not specify the material, shape, structure, or arrangement of structural components as described below.

[0045] In this specification, "carrier supply region" refers to the semiconductor region that supplies majority carriers constituting the main current, such as the source region of a field-effect transistor (FET) and a system induction transistor (SIT), and the emitter region of an insulated-gate bipolar transistor (IGBT). In addition, in system induction (SI) thyristors and gate-to-turn-off (GTO) thyristors, the anode region serves as the carrier supply region. Furthermore, "carrier receiving region" refers to the semiconductor region that receives majority carriers constituting the main current, such as the drain region of a FET and a SIT, and the collector region of an IGBT. In SI thyristors and GTO thyristors, the cathode region functions as the carrier receiving region. Finally, "control electrode" refers to the gate electrode of a FET, SIT, IGBT, SI thyristor, and GTO thyristor, which has the function of controlling the flow of the main current between the aforementioned carrier supply region and carrier receiving region.

[0046] Furthermore, the definitions of up and down, etc., in the following description are merely for illustrative purposes and are not intended to limit the technical concept of the present invention. For example, if the object is rotated 90° for observation, the term "up and down" becomes "left and right," and if the object is rotated 180° for observation, the relationship between "up and down" will be reversed, which is perfectly reasonable.

[0047] Furthermore, in the following description, the case where the first conductivity type is p-type and the second conductivity type is n-type is illustrated illustratively. However, the conductivity types can also be chosen in the opposite relationship, with the first conductivity type being n-type and the second conductivity type being p-type. Additionally, the "+" and "-" notations attached to "n" and "p" respectively indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without "+" and "-" notations. However, even semiconductor regions labeled with the same "n" and "n" do not necessarily mean that the impurity concentrations of each semiconductor region are strictly the same. Furthermore, in the following description, unless otherwise explicitly specified, the components and regions defined by "first conductivity type" and "second conductivity type" refer to components and regions made of semiconductor material.

[0048] (Implementation Method)

[0049] <Structure of Semiconductor Devices>

[0050] As a semiconductor device according to an embodiment of the present invention, an HVIC for driving a three-phase inverter is described. Figure 1 As shown, the semiconductor device according to the embodiments of the present invention has a control circuit 5 as a low-potential side circuit region and multi-phase (3-phase) high-potential side circuit regions 10u, 10v, and 10w such as U phase, V phase, and W phase on the same semiconductor substrate (semiconductor chip) 1. As the semiconductor substrate 1, a silicon (Si) substrate can be used, for example.

[0051] The high-potential side circuit regions of phases U, V, and W are 10u, 10v, and 10w along... Figure 1 The circuits are arranged in a vertical column. The high-potential side circuit region 10u of phase U includes a gate drive circuit 6u, an annular high-voltage junction termination region (HVJT) 9u surrounding the gate drive circuit 6u, and an annular wiring (ring wiring) 8u surrounding the HVJT 9u. The gate drive circuit 6u operates based on the floating potential VS potential. The ring wiring 8u is formed by connecting a first wiring 8u1 electrically connected to the set-side level shifter 71 and a second wiring 8u2 electrically connected to the reset-side level shifter 72 in a manner that surrounds the gate drive circuit 6u.

[0052] Furthermore, the high-potential side circuit region 10u of phase U includes a level shifter (set-side level shifter) 71 for setting signal transmission and a level shifter (reset-side level shifter) 72 for resetting signal transmission, integrated with the HVJT 9u and located around the gate drive circuit 6u. These two level shifters, set-side level shifter 71 and reset-side level shifter 72, are used to transmit signals in a two-input manner, using a set signal and a reset signal. The set-side level shifter 71 and reset-side level shifter 72 are, for example, constructed from high-voltage n-channel MOSFETs. The carrier supply region (source region) 71s of the set-side level shifter 71 and the source region 72s of the reset-side level shifter 72 are connected to the loop wiring 8u. The carrier receiving region (drain region) 71d of the set-side level shifter 71 and the drain region 72d of the reset-side level shifter 72 are connected to the gate drive circuit 6u.

[0053] The high-potential side circuit region 10V of phase V includes a gate drive circuit 6V, a ring-shaped HVJT 9V disposed around the gate drive circuit 6V, and a ring-shaped wiring (ring wiring) 8V disposed around the HVJT 9V. The gate drive circuit 6V operates based on the floating potential VS potential. The ring wiring 8V is constructed by connecting a first wiring 8V1 electrically connected to the set-side level shifter 73 and a second wiring 8V2 electrically connected to the reset-side level shifter 74 to each other in a manner that surrounds the gate drive circuit 6V.

[0054] Furthermore, the high-potential side circuit region 10V of phase V includes a set-side level shifter 73 and a reset-side level shifter 74, integrated with the HVJT 9V and located around the gate drive circuit 6V. The set-side level shifter 73 and the reset-side level shifter 74 are, for example, constructed from high-voltage n-channel MOSFETs. The source region 73s of the set-side level shifter 73 and the source region 74s of the reset-side level shifter 74 are connected to the loop wiring 8V. The drain region 73d of the set-side level shifter 73 and the drain region 74d of the reset-side level shifter 74 are connected to the gate drive circuit 6V.

[0055] The high-potential side circuit region 10w of phase W includes a gate drive circuit 6w, an annular HVJT 9w disposed around the gate drive circuit 6w, and an annular wiring (annular wiring) 8w disposed around the HVJT 9w. The gate drive circuit 6w operates based on the floating potential VS potential. The annular wiring 8w is formed by connecting a first wiring 8w1 electrically connected to the set-side level shifter 75 and a second wiring 8w2 electrically connected to the reset-side level shifter 76 in a manner that surrounds the gate drive circuit 6w.

[0056] Furthermore, the high-potential side circuit region 10w of phase W includes a set-side level shifter 75 and a reset-side level shifter 76, which are integrated with the HVJT 9w and located around the gate drive circuit 6w. The set-side level shifter 75 and the reset-side level shifter 76 are, for example, constructed from high-voltage n-channel MOSFETs. The source region 75s of the set-side level shifter 75 and the source region 76s of the reset-side level shifter 76 are connected to the loop wiring 8w. The drain region 75d of the set-side level shifter 75 and the drain region 76d of the reset-side level shifter 76 are connected to the gate drive circuit 6w.

[0057] Control circuit 5 is positioned at the end of the high-potential side circuit region 10w of phase W, which is the end of the arrangement of high-potential side circuit regions 10u, 10v, and 10w of phases U, V, and W. Control circuit 5 is positioned closest to phase W's high-potential side circuit region 10w and farthest from phase U's high-potential side circuit region 10u, 10v, and 10w. Control circuit 5 operates based on the ground potential (GND potential) and controls the high-potential side circuit regions 10u, 10v, and 10w of phases U, V, and W.

[0058] Pads 2 (GND pad), 3u, 3v, and 3w (HIN pad), and pad 4 (VCC pad) are arranged around the control circuit 5. Pad 2 is given a GND potential as the reference potential of the control circuit 5. Pads 3u, 3v, and 3w are given input signals HIN(U), HIN(V), and HIN(W) to the control circuit 5. Pad 4 is electrically connected to the power supply of the control circuit 5 and is given a VCC potential as the power supply potential of the control circuit 5.

[0059] GND pad 2 is positioned closest to the high-potential side circuit region 10w of phase W (U, V, W) and furthest from the high-potential side circuit region 10u, 10v, 10w of phase U. GND pad 2 is located at the lower right corner of the planar pattern of semiconductor substrate 1. GND pad 2 is connected to control circuit 5 via wiring 20. GND pad 2 is connected to one end of set-side wiring 21 and one end of reset-side wiring 22. Set-side wiring 21 and reset-side wiring 22 are positioned above the ring wirings 8u, 8v, 8w. Set-side wiring 21 has a straight-line pattern and is configured to extend along the right side of semiconductor substrate 1. The other end of set-side wiring 21 is electrically connected via contact hole 24 to the ring wiring 8u, which is positioned below set-side wiring 21.

[0060] On the other hand, the reset-side wiring 22 has an L-shaped pattern, with a portion extending along the lower edge of the semiconductor substrate 1 and a portion extending along the left side of the semiconductor substrate 1. The other end of the reset-side wiring 22 is electrically connected via a contact hole 23 to a ring-shaped wiring 8u located on a lower layer than the reset-side wiring 22. Since the GND pad 2 is located at the lower right corner of the planar pattern of the semiconductor substrate 1, the length of the reset-side wiring 22 is longer than the length of the set-side wiring 21.

[0061] The source region 71s of the set-side level shifter 71 of phase U is electrically connected to the GND pad 2 via a loop wiring 8u and a set-side wiring 21. The source region 72s of the reset-side level shifter 72 of phase U is electrically connected to the GND pad 2 via a loop wiring 8u and a reset-side wiring 22. That is, the set-side wiring 21 electrically connects the GND pad 2 to the set-side level shifter 71 in the high-potential side circuit region 10u furthest from the GND pad 2. The reset-side wiring 22 electrically connects the GND pad 2 to the reset-side level shifter 72 in the high-potential side circuit region 10u furthest from the GND pad 2.

[0062] A connecting wire 81 is arranged above the loop wires 8u and 8v, overlapping the area between the loop wire 8u of the U phase and the loop wire 8v of the V phase. The connecting wire 81 is arranged on the same wiring layer as, for example, the set-side wiring 21 and the reset-side wiring 22. The loop wire 8u is electrically connected to the connecting wire 81 via a contact hole 82. The loop wire 8v is electrically connected to the connecting wire 81 via a contact hole 83. The connecting wire 81 is constructed by connecting a first connecting wire 81a and a second connecting wire 81b. The first connecting wire 81a electrically connects the first wires 8u1 and 8v1 of the high-potential side circuit regions 10u and 10v of the U phase and V phase, respectively. The second connecting wire 81b electrically connects the second wires 8u2 and 8v2 of the high-potential side circuit regions 10u and 10v of the U phase and V phase.

[0063] The source region 73s of the set-side level shifter 73 of phase V is electrically connected to the GND pad 2 via loop wiring 8V, connection wiring 81, loop wiring 8U, and set-side wiring 21. The source region 74s of the reset-side level shifter 74 of phase V is electrically connected to the GND pad 2 via loop wiring 8V, connection wiring 81, loop wiring 8U, and reset-side wiring 22.

[0064] A connecting wire 84 is arranged above the loop wires 8V and 8W, overlapping the area between the loop wire 8V of the V phase and the loop wire 8W of the W phase. The connecting wire 84 is arranged on the same wiring layer as, for example, the connecting wire 81, the set-side wiring 21, and the reset-side wiring 22. The loop wire 8V is electrically connected to the connecting wire 84 via a contact hole 85. The loop wire 8W is electrically connected to the connecting wire 84 via a contact hole 86. The connecting wire 84 is constructed by connecting a first connecting wire 84a and a second connecting wire 84b. The first connecting wire 84a electrically connects the first wires 8v1 and 8w1 of the high-potential side circuit regions 10V and 10W of the V and W phases, respectively. The second connecting wire 84b electrically connects the second wires 8v2 and 8w2 of the high-potential side circuit regions 10V and 10W of the U and V phases.

[0065] The source region 75s of the set-side level shifter 75 of phase W is electrically connected to the GND pad 2 via loop wiring 8w, connection wiring 84, loop wiring 8v, connection wiring 81, loop wiring 8u, and set-side wiring 21. The source region 76s of the reset-side level shifter 76 of phase W is electrically connected to the GND pad 2 via loop wiring 8w, connection wiring 84, loop wiring 8v, connection wiring 81, loop wiring 8u, and reset-side wiring 22.

[0066] That is, in the semiconductor device according to the embodiments of the present invention, the loop wiring 8w of the W phase, which is relatively close to the GND pad 2, is electrically connected to the GND pad 2 via the loop wiring 8u of the U phase and the loop wiring 8v of the V phase, which are relatively far from the GND pad 2. Additionally, the loop wiring 8v of the V phase, which is relatively close to the GND pad 2, is electrically connected to the GND pad 2 via the loop wiring 8u of the U phase, which is relatively far from the GND pad 2. Furthermore, the set-side level shifters 73 and 75 of the high-potential side circuit regions 10v and 10w, located on the side closer to the GND pad 2 than the high-potential side circuit region 10u, which is farthest from the GND pad 2, are electrically connected to the GND pad 2 via the set-side wiring 21. Additionally, the reset-side level shifters 74 and 76 of the high-potential side circuit regions 10v and 10w, located on the side closer to the GND pad 2 than the high-potential side circuit region 10u, which is furthest from the GND pad 2, are electrically connected to the GND pad 2 via the reset-side wiring 22.

[0067] Figure 2 The text is incomplete and contains errors. A more accurate translation would require the full context. Figure 1 The diagram shows the upper-side set-side wiring 21, reset-side wiring 22, connection wiring 81, and connection wiring 84, but the planar layout of contact holes 23, 24, 82, 83, 85, and 86 is omitted. VCC pad 4 is connected to one end of VCC wiring 41. VCC wiring 41 is configured in a... Figure 1 The set-side wiring 21, reset-side wiring 22, connection wiring 81, and connection wiring 84 are shown in the lower layer. The VCC wiring 41 has an L-shaped planar pattern and is configured to extend along the left side of the semiconductor substrate 1.

[0068] Three VCC wires, 42, 43, and 44, branch off from VCC wire 41. VCC wire 42 is configured to extend between the loop wire 8u of phase U and the loop wire 8v of phase V. VCC wire 43 is configured to extend between the loop wire 8v of phase V and the loop wire 8w of phase W. VCC wire 44 is configured to extend between the loop wire 8w of phase W and the control circuit 5. Figure 2 The diagram is omitted, but an n-type semiconductor region is provided on the semiconductor substrate 1 directly below the VCC wirings 42-44. This n-type semiconductor region is connected to the VCC wirings and fixed at the VCC potential. This n-type semiconductor region prevents noise currents that could cause damage or malfunction from flowing through the high-potential side circuit regions 10u, 10v, 10w of adjacent phases or the control circuit 5 when negative voltage noise occurs. Alternatively, a structure without VCC wirings 41-44 is also possible.

[0069] Figure 3 Showing from Figure 1 The cross-section observed in the AA direction includes the reset-side level shifter 72. For example... Figure 3As shown, the semiconductor device according to the embodiment of the present invention includes an n-type well region 11 disposed on the upper part of a p-type semiconductor substrate 1. A p-type junction isolation region (slit region) 13 is disposed in the n-type well region 11. The p-type junction isolation region 13 has a depth penetrating the n-type well region 11 and reaching the p-type semiconductor substrate 1, thereby isolating the n-type well region 11. An n-type junction isolation region 13 is disposed on the upper part of the n-type well region 11, which is inside the p-type junction isolation region 13. + Type pickup area 16. In n + The pickup area 16 is provided with a pickup electrode 112 that is connected to the VB terminal, which is the high-potential side power supply terminal of the gate drive circuit 6u.

[0070] An n-type well region 11 is provided with an impurity concentration lower than that of the n-type well region 11, in a manner connected to the n-type well region 11. - Type 12 pressure-resistant zone. And, with n - A p-type base region 14 is provided in a manner that connects the p-type withstand voltage regions 12. Above the p-type base region 14, a p-type base region with a higher impurity concentration than the p-type base region 14 is provided in a ring shape. + Type contact region 17. In n-type well region 11, n - Insulating films 101, 102, and 103 are provided on the p-type withstand voltage region 12 and the p-type base region 14. For example... Figure 3 As schematically shown in the diagram, by n - The pn junction between the p-type withstand voltage region 12 and the p-type base region 14 forms a high-voltage diode D1, and this high-voltage diode D1 constitutes... Figure 1 The HVJT 9u is shown in the figure.

[0071] Reset-side level shifter 72 will n - The p-type base region 12 serves as a drift region, and the reset-side level shifter 72 is a high-voltage n-channel MOSFET. The reset-side level shifter 72 has a region on the upper part of the p-type base region 14 that corresponds to the p-type base region 14. + Type contact area 17 adjacent grounding setting n + The source polar region is 72s. In p... + Type contact area 17 and n + The source pole region 72s is equipped with a type p + Type contact area 17 and n + A ring-shaped wiring 8u, serving as the source electrode, is connected to the source region 72s. The ring-shaped wiring 8u is connected to the reset-side wiring 22 via the contact hole 23.

[0072] The reset-side level shifter 72 has an n-type well region 11 located on the upper part of the n-type well region 11. + Type 72d drain region. In n + A type drain region 72d is provided with a type n +A drain electrode 104 is connected to the p-type drain region 72d. A gate electrode 111 is provided in the portion of the p-type base region 14 between the annular wiring 8u, which serves as the source electrode, and the drain electrode 104, separated by a gate insulating film.

[0073] A level-shifting resistor 113, made of polysilicon or the like, is disposed on the n-type well region 11, separated by an insulating film 101. A first electrode 114 and a second electrode 115 are disposed at both ends on the upper surface side of the level-shifting resistor 113. Figure 3 For convenience, solid lines are used to represent the electrical connection between the pickup electrode 112 and the first electrode 114. However, it can also be formed as a wiring layer on the same layer as the pickup electrode 112 and the first electrode 114 and connected to them, or it can be formed as a wiring layer on a different layer from the pickup electrode 112 and the first electrode 114 and connected to them via vias. Furthermore, in Figure 3 For convenience, the electrical connection between the drain electrode 104 and the second electrode 115 is represented by solid lines. However, it can also be formed as a wiring layer on the same layer as the drain electrode 104 and the second electrode 115 and connected to them, or it can be formed as a wiring layer on a different layer from the drain electrode 104 and the second electrode 115 and connected to them via vias. The pickup electrode 112 is electrically connected to the drain region 72d of the reset-side level shifter 72 via the level shift resistor 113. Figure 1 The structure of the set-side level shifters 71, 73, 75 and the reset-side level shifters 74, 76 shown in the figure is similar to... Figure 3 The reset-side level shifter 72 shown in the figure has the same construction.

[0074] Figure 4 Showing from Figure 1 This includes the cross-section observed in the BB direction of the connecting wiring 81. For example... Figure 4 As shown on the right, the high-potential side circuit region 10u includes an n-type well region 11 disposed on the upper part of the p-type semiconductor substrate 1. An n-type well region 11 is disposed on the upper part of the n-type well region 11. + Type pickup area 15. In n + The pickup area 15 is provided with a pickup electrode 116 that is connected to the VB terminal, which is the high-potential side power supply terminal of the gate drive circuit 6u.

[0075] An n-type well region 11 is provided with an impurity concentration lower than that of the n-type well region 11, in a manner connected to the n-type well region 11. - Type 12 pressure-resistant zone. And, with n - A p-type base region 14 is provided in a manner that connects the p-type withstand voltage regions 12. Above the p-type base region 14, a p-type base region with a higher impurity concentration than the p-type base region 14 is provided in a ring shape.+ Type contact area 17. In p + The contact area 17 is provided with a connection to p + The ring wiring 8u is connected to the contact area 17.

[0076] like Figure 4 As shown on the left, the high-potential side circuit region 10V includes an n-type well region 11a disposed on the upper part of the p-type semiconductor substrate 1. An n-type well region 11a is disposed on the upper part of the n-type well region 11a. + Type pickup area 15a. In n + The pickup area 15a is provided with a pickup electrode 117 that is connected to the VB terminal, which is the high-potential side power supply terminal of the gate drive circuit 6V.

[0077] An n-type well region 11a is provided with an impurity concentration lower than that of the n-type well region 11a, in a manner connected to the n-type well region 11a. - Type 12a pressure-resistant zone. Furthermore, with n - A p-type base region 14a is provided in a manner connected to the p-type withstand voltage region 12a. Above the p-type base region 14a, a p-type base region with a higher impurity concentration than the p-type base region 14a is provided in a ring shape. + Type contact area 17a. In p + The contact area 17a is provided with a contact with p + The 8V ring wiring is connected to the contact area 17a.

[0078] like Figure 4 As shown in the center, an n-type semiconductor region 18 is disposed on the upper part of the p-type semiconductor substrate 1 and between the n-type well regions 11 and 11a. An n-type semiconductor region with a higher impurity concentration than the n-type semiconductor region 18 is disposed on the upper part of the n-type semiconductor region 18. + Type contact area 19. In n + The contact area 19 is provided with n + The VCC wiring 42 is connected to the contact area 19. The n-type semiconductor region 18 is fixed to the VCC potential via the VCC wiring 42. A connecting wiring 81 is provided on the VCC wiring 42 through an insulating film 103. One end of the connecting wiring 81 is connected to the annular wiring 8u via a contact hole 82, and the other end of the connecting wiring 81 is connected to the annular wiring 8v via a contact hole 83. Figure 1 The construction around the connecting wiring 84 shown in the figure is similar to Figure 4 The same construction is shown around the connecting wiring 81.

[0079] Figure 5This illustrates the equivalent circuit of the semiconductor device according to an embodiment of the present invention. The gates of the set-side level shifter 71 and the reset-side level shifter 72 of phase U are connected to the control circuit 5. The drain of the set-side level shifter 71 is connected to the level shift resistor r1 and the gate drive circuit 6u. The source of the set-side level shifter 71 is connected to the GND pad 2 via the wiring resistor Rsetu. The drain of the reset-side level shifter 72 is connected to the level shift resistor r2 and the gate drive circuit 6u. The source of the reset-side level shifter 72 is connected to the GND pad 2 via the wiring resistor Rrstu. The level shift resistors r1 and r2 are connected to the high-potential (VB potential) side of the power supply 61. The gate drive circuit 6u is connected to both the high-potential (VB potential) side and the low-potential (VS potential) side of the power supply 61.

[0080] The gates of the set-side level shifter 73 and the reset-side level shifter 74 of phase V are connected to the control circuit 5. The drain of the set-side level shifter 73 is connected to the level shift resistor r3 and the gate drive circuit 6V. The source of the set-side level shifter 73 is connected to the GND pad 2 via wiring resistors Rsetuv and Rsetu. The drain of the reset-side level shifter 74 is connected to the level shift resistor r4 and the gate drive circuit 6V. The source of the reset-side level shifter 74 is connected to the GND pad 2 via wiring resistors Rrstuv and Rrstu. The level shift resistors r3 and r4 are connected to the high-potential (VB potential) side of the power supply 62. The gate drive circuit 6V is connected to both the high-potential (VB potential) side and the low-potential (VS potential) side of the power supply 62.

[0081] The gates of the set-side level shifter 75 and the reset-side level shifter 76 of phase W are connected to the control circuit 5. The drain of the set-side level shifter 75 is connected to the level shift resistor r5 and the gate drive circuit 6w. The source of the set-side level shifter 75 is connected to the GND pad 2 via wiring resistors Rsetvw, Rsetuv, and Rsetu. The drain of the reset-side level shifter 76 is connected to the level shift resistor r6 and the gate drive circuit 6w. The source of the reset-side level shifter 76 is connected to the GND pad 2 via wiring resistors Rrstvw, Rrstuv, and Rrstu. The level shift resistors r5 and r6 are connected to the high-potential (VB potential) side of the power supply 63. The gate drive circuit 6w is connected to both the high-potential (VB potential) side and the low-potential (VS potential) side of the power supply 63.

[0082] Next, refer to Figure 5The following description focuses on an example of the switching operation of a semiconductor device according to an embodiment of the present invention. When the input signal HIN(U) input to the control circuit 5 changes from a low (L) level to a high (H) level, the control circuit 5 turns on the set-side level shifter 71 for a fixed time and transmits a set signal SET based on the GND potential to the set-side level shifter 71. The set-side level shifter 71 transforms the set signal SET from the control circuit 5 based on the GND potential into a set signal SET based on the floating potential VS potential and then transmits it to the gate drive circuit 6u. The gate drive circuit 6u changes its output HO(U) from the L level to the H level based on the set signal SET based on the VS potential from the set-side level shifter 71. The gate of a semiconductor power switching element such as an IGBT is driven by the output HO(U) of the gate drive circuit 6u. The semiconductor power switching element is the element located on the high-potential side of the two elements connected in series between the power supply and ground of a 3-phase inverter.

[0083] On the other hand, when the input signal HIN(U) to the control circuit 5 changes from H level to L level, the control circuit 5 turns on the reset-side level shifter 72 for a fixed time, transmitting the reset signal RST based on the GND potential to the reset-side level shifter 72. The reset-side level shifter 72 transforms the GND-based reset signal RST from the control circuit 5 into a VS-based reset signal RST and transmits it to the gate drive circuit 6u. The gate drive circuit 6u, based on the VS-based reset signal RST from the reset-side level shifter 72, causes its output HO(U) to change from H level to L level. The switching operations of the V phase and W phase are the same as those of the U phase.

[0084] Figure 6 This indicates the relationship between the states of the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 and the outputs of the gate drive circuits 6u, 6v, 6w. State A is when all three level shifters (71, 73, 75 and 72, 74, 76) are off, and the outputs of the gate drive circuits 6u, 6v, 6w remain unchanged. State B is when the set-side level shifters 71, 73, 75 are off and the reset-side level shifters 72, 74, 76 are on, and the gate drive circuits 6u, 6v, 6w are off. State C is when the set-side level shifters 71, 73, 75 are on and the reset-side level shifters 72, 74, 76 are off, and the gate drive circuits 6u, 6v, 6w are on. State D is when the set-side level shifters 71, 73, and 75 and the reset-side level shifters 72, 74, and 76 are all turned on, and the outputs of the gate drive circuits 6u, 6v, and 6w remain unchanged.

[0085] <Comparative Example>

[0086] Next, the semiconductor device involved in the comparative example will be described. The semiconductor device involved in the comparative example is similar to... Figure 1 The semiconductor device involved in the embodiments of the present invention shown differs in that, as Figure 7 As shown, the set-side wiring 21 is connected to the ring wiring 8V and 8W via contact holes 122 and 124, and the reset-side wiring 22 is connected to the ring wiring 8V and 8W via contact holes 121 and 123. Figure 1 The semiconductor device involved in the embodiment of the present invention shown is also different in that it does not have connecting wires 81, 84 for connecting the loop wires 8u, 8v, 8w to each other.

[0087] Figure 8 This illustrates the equivalent circuit of the semiconductor device involved in the comparative example. In the semiconductor device involved in the comparative example, the source of the set-side level shifter 75 of phase W is connected to the GND pad 2 via a wiring resistor Rsetw. The source of the reset-side level shifter 76 of phase W is connected to the GND pad 2 via a wiring resistor Rrstw. Figure 7 As shown, the length of the set-side wiring 21 from the GND pad 2 to the connection with the set-side level shifter 75 of phase W and the length of the reset-side wiring 22 from the GND pad 2 to the connection with the reset-side level shifter 76 are different. Therefore Figure 8 The wiring resistors Rsetw and Rrstw shown have a large difference.

[0088] The source of the set-side level shifter 73 of phase V is connected to the GND pad 2 via wiring resistors Rsetw and Rsetvw. The source of the reset-side level shifter 74 of phase V is connected to the GND pad 2 via wiring resistors Rrstw and Rrstvw. The source of the set-side level shifter 71 of phase U is connected to the GND pad 2 via wiring resistors Rsetw, Rsetvw, and Rsetuv. The source of the reset-side level shifter 72 of phase U is connected to the GND pad 2 via wiring resistors Rrstw, Rrstvw, and Rrstuv.

[0089] In the semiconductor device involved in the comparative example, along with the switching operation of the semiconductor power switching element, a negative voltage noise, referred to as -Vs noise, is generated at the VS terminal of each phase. For example... Figure 9 and Figure 10 As shown, when -Vs noise occurs in phase U, the high-voltage diode HVJT 9u constituting phase U becomes forward biased, and noise current flows from GND pad 2 to the Vs terminal. Figure 9 and Figure 10 In the diagram, the noise current is represented by a dashed line with an arrowhead. For example... Figure 9 As shown, noise current flows through the set-side wiring 21, the reset-side wiring 22, and the loop wirings 8u, 8v, and 8w. Since these wirings have resistances R0 to R12, voltage drops occur at these locations. Due to these voltage drops, the source potentials of the set-side level shifter 73 and the reset-side level shifter 74 in phase V, and the set-side level shifter 75 and the reset-side level shifter 76 in phase W, are lower than the potential of the GND pad 2.

[0090] For example, when the noise current is set to Is, the wiring resistance from GND pad 2 to the source of the set-side level shifter 75 of phase W is set to Rsetw, and the wiring resistance from GND pad 2 to the source of the reset-side level shifter 76 of phase W is set to Rrstw, a voltage drop of Is × Rsetw occurs at the source of the set-side level shifter 75 of phase W, and a voltage drop of Is × Rrstw occurs at the source of the reset-side level shifter 76. The wiring resistances Rsetw and Rrstw are... Figure 9 The combined resistance of the wiring resistors R0 to R12 shown is mainly determined by the resistance values ​​of the wiring resistors R0 to R4.

[0091] On the other hand, except when the set-side level shifter 75 and reset-side level shifter 76 of phase W are driven, the gate potentials of the set-side level shifter 75 and reset-side level shifter 76 are GND. Therefore, due to the decrease in the source potential of the set-side level shifter 75 and reset-side level shifter 76 of phase W, a positive voltage is applied between the gate and source of the set-side level shifter 75 and reset-side level shifter 76. If this voltage exceeds the threshold voltage of the set-side level shifter 75 and reset-side level shifter 76, an unintentional turn-on of the set-side level shifter 75 and reset-side level shifter 76 occurs.

[0092] To prevent such malfunctions of the set-side level shifters 71, 73, and 75, and the reset-side level shifters 72, 74, and 76, such as... Figure 6 As shown in states A and D, the gate drive circuits 6u, 6v, and 6w are configured to not change their output when simultaneously input with a set signal and a reset signal. Therefore, if the wiring resistance between the set-side level shifters 71, 73, and 75 and GND pad 2 is the same as the wiring resistance between the reset-side level shifters 72, 74, and 76 and GND pad 2, then -Vs noise will cause the set-side level shifters 71, 73, and 75, as well as the reset-side level shifters 72, 74, and 76, to be falsely triggered simultaneously. Figure 6As shown in state D, the outputs of the gate drive circuits 6u, 6v, and 6w remain unchanged.

[0093] However, in the semiconductor device involved in the comparative example, the wiring resistance between the set-side level shifters 71, 73, 75 and the GND pad 2 differs from the wiring resistance between the reset-side level shifters 72, 74, 76 and the GND pad 2. For example... Figure 9 As shown, the wiring resistance of the reset-side wiring 22 is greater than the wiring resistance of the set-side wiring 21 by a corresponding amount of wiring resistance R0. For example, when R0 = 0.86Ω, R1 = R2 = 0.71Ω, R3 = R4 = R7 = R8 = R11 = R12 = 0.47Ω, and R5 = R6 = R9 = R10 = 0.34Ω, the wiring resistance Rsetw from GND pad 2 to the source of the set-side level shifter 75 of phase W is approximately 0.51Ω, and the wiring resistance Rrstw from GND pad 2 to the source of the reset-side level shifter 76 of phase W is approximately 0.57Ω.

[0094] When the threshold voltages of the set-side level shifter 75 and the reset-side level shifter 76 are, for example, 1.5V, a voltage of 1.5V or more is applied between the gate and source of the reset-side level shifter 76 due to a noise current of approximately 2.6A or more, causing the reset-side level shifter 76 to malfunction. On the other hand, the set-side level shifter 75 malfunctions due to a noise current of approximately 3.0A or more. Therefore, when a noise current of approximately 2.6A to 3.0A flows, only the reset-side level shifter 76 malfunctions. If the period during which only the reset-side level shifter 76 malfunctions exceeds the filtering period, the gate drive circuit 6w malfunctions.

[0095] Figure 11 This represents the noise current when -Vs noise occurs in the U phase of the semiconductor device involved in the comparative example. Figure 12 This represents the gate-source voltage at the set-side level shifter 75 and the reset-side level shifter 76 of phase W when -Vs noise occurs in phase U of the semiconductor device involved in the comparative example. For example... Figure 12 As shown, in the semiconductor device involved in the comparative example, the voltage difference between the set-side level shifter 75 and the reset-side level shifter 76 is large, so the gate drive circuit 6w is prone to malfunction.

[0096] Here, consider as follows Figure 13 As shown, the GND pad 2 is positioned at the center in the left-right direction of the semiconductor substrate 1, thereby making the wiring resistance between the set-side level shifters 71, 73, 75 and the GND pad 2 equal to the wiring resistance between the reset-side level shifters 72, 74, 76 and the GND pad 2. Furthermore, consider... Figure 14As shown, a GND wiring 120 is connected to the GND pad 2, and the GND wiring 120 is extended to the center in the left-right direction of the semiconductor substrate 1 to connect with the set-side wiring 21 and the reset-side wiring 22. This makes the wiring resistance between the set-side level shifters 71, 73, 75 and the GND pad 2 the same as the wiring resistance between the reset-side level shifters 72, 74, 76 and the GND pad 2.

[0097] However, due to installation and control circuit layout issues, it is difficult to implement as described above. Figure 13 and Figure 14 In the planar layout shown, generally speaking, the wiring resistance between the set-side level shifters 71, 73, 75 and GND pad 2 differs from the wiring resistance between the reset-side level shifters 72, 74, 76 and GND pad 2. Due to this difference, only one of the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 will be falsely triggered when -Vs noise occurs, thus becoming... Figure 6 In state B or state C, the outputs of the gate drive circuits 6u, 6v, and 6w are incorrectly reversed. This problem is significant in the W phase, which is closer to the GND pad 2.

[0098] <The Function and Effects of Semiconductor Devices>

[0099] In contrast, in the semiconductor device according to the embodiments of the present invention, such as Figure 1 As shown, the loop wirings 8v and 8w of the V-phase and W-phase, which are relatively close to the GND pad 2, are electrically connected to the GND pad 2 via the loop wiring 8u of the U-phase, which is relatively far from the GND pad 2. Thus, the wiring paths of the V-phase and W-phase loop wirings 8v and 8w and the GND pad 2 are extended to the same extent. Therefore, although the GND pad 2 is located asymmetrically with respect to the set and reset sides, similar to the semiconductor device involved in the comparative example, the ratio Rset / Rrst of the wiring resistance Rset from the source of the set-side level shifters 73 and 75 of the V-phase and W-phase to the GND pad 2 and the wiring resistance Rrst from the source of the reset-side level shifters 74 and 76 to the GND pad 2 is closer to 1 than that of the semiconductor device involved in the comparative example.

[0100] Next, refer to Figure 15 To illustrate the case where -Vs noise is applied to the U phase in the semiconductor device according to the embodiments of the present invention. Figure 15In the diagram, dashed lines with arrows schematically represent the noise current path when phase U is subjected to -Vs noise. Additionally, the wiring resistances R0 to R12 of the set-side wiring 21, reset-side wiring 22, and loop wirings 8u, 8v, and 8w are schematically represented. When phase U is subjected to -Vs noise, the noise current flows through the set-side wiring 21, reset-side wiring 22, and loop wirings 8u, 8v, and 8w, generating voltage drops at these locations.

[0101] However, most of the noise current flows through the loop wiring 8u of phase U, while the noise current flowing to the loop wirings 8v and 8w of phases V and W is small. Therefore, the voltage drop of the source potentials of the set-side level shifters 73 and 75 and the reset-side level shifters 74 and 76 of phases V and W is not significantly different on the set-side and reset-side. Thus, even if a false triggering occurs in the set-side level shifters 73 and 75 and the reset-side level shifters 74 and 76 of phases V and W, it becomes negligible because both the set-side and reset-side are simultaneously activated. Figure 6 In state D4, there is no false inversion of the output of the gate drive circuit 6V and 6W.

[0102] Furthermore, during the application of -Vs noise, the set-side level shifter 71 and the reset-side level shifter 72 of phase U are reverse biased. Therefore, even if a voltage above the threshold voltage is applied between the gate and source due to the voltage drop at the set-side wiring 21, the reset-side wiring 22 and the loop wiring 8u, no signal is transmitted and no erroneous reversal of the output of the gate drive circuit 6u occurs.

[0103] Next, refer to Figure 16 and Figure 17 To illustrate the case where -Vs noise is applied to the W phase in the semiconductor device according to the embodiments of the present invention. Figure 16 as well as Figure 17 In the diagram, a dashed line with an arrowhead schematically represents the noise current path when phase W is subjected to -Vs noise. For example... Figure 16 As shown, when -Vs noise is applied to phase W, noise current flows through the set-side wiring 21, reset-side wiring 22, and loop wiring 8u, which connect the GND pad 2 to the set-side level shifter 71 and reset-side level shifter 72 of phase U. The noise current also flows into phase W via the connection wiring 81 and loop wiring 8v connecting phase U to phase V, and the connection wiring 84 and loop wiring 8w connecting phase V to phase W. Due to this noise current, voltage drops occur in the set-side wiring 21, reset-side wiring 22, loop wiring 8u, connection wiring 81, loop wiring 8v, connection wiring 84, and loop wiring 8w, potentially causing false triggering of the set-side level shifters 71 and 73 and the reset-side level shifters 72 and 74 of phases U and V.

[0104] Here, in the semiconductor device involved in the comparative example, the wiring resistance ratio Rrst / Rset of the set-side level shifter 75 and the reset-side level shifter 76 of phase W among the U, V, and W phases is the largest, which easily leads to false inversion of the output of the gate drive circuit 6w caused by false triggering of the set-side level shifter 75 and the reset-side level shifter 76. On the other hand, in the semiconductor device involved in the embodiment of the present invention, the wiring resistance ratio Rrst / Rset of the set-side level shifter 71 and the reset-side level shifter 72 of phase U among the U, V, and W phases is the largest. However, the wiring resistance ratio Rrst / Rset of the set-side level shifter 71 and the reset-side level shifter 72 of phase U in the semiconductor device involved in the embodiment of the present invention is closer to 1 than the wiring resistance ratio Rrst / Rset of the set-side level shifter 75 and the reset-side level shifter 76 of phase W in the semiconductor device involved in the comparative example.

[0105] Figure 18 This refers to the noise current in the W phase of a semiconductor device when -Vs noise occurs, as described in the embodiments of the present invention. Figure 19 This refers to the gate-source voltage generated by the set-side level shifter 71 and the reset-side level shifter 72 in the U phase when -Vs noise occurs in the W phase of the semiconductor device, as described in the embodiments of the present invention. Figure 19 As shown, in the semiconductor device according to the embodiments of the present invention, the voltage difference ratio between the set-side level shifter 71 and the reset-side level shifter 72 is... Figure 12 The voltage difference between the set-side level shifter 75 and the reset-side level shifter 76 of the W phase in the semiconductor device shown in the comparative example is small, which can prevent the output of the gate drive circuit 6u from being erroneously reversed.

[0106] Figure 20 The semiconductor device shown is an embodiment of the present invention. Figure 20 The semiconductor device described herein (referred to as "the present invention") and the comparative examples thereof ( Figure 20 A detailed comparison of the GND wiring resistance in the "existing configuration" is provided. In the semiconductor device involved in the comparative example, the resistance ratio of the wiring resistance between the GND pad and the level shifter on the set side and reset side of phase W in the three phases is the largest, at 1.126, and the difference in source voltage drop is as large as 0.168V. In contrast, in the semiconductor device according to the embodiment of the present invention, the resistance ratio of the wiring resistance between the GND pad and the level shifter on the set side and reset side of phase U in the three phases is the largest, at 1.024, which is smaller than the resistance ratio of phase W in the semiconductor device involved in the comparative example, and the difference in source voltage drop is 0.034V, which is smaller than the difference of phase W in the semiconductor device involved in the comparative example.

[0107] <First Variation>

[0108] The semiconductor device involved in the first variation of the embodiments of the present invention and Figure 1 The semiconductor device involved in the embodiments of the present invention shown differs in that, as Figure 21 As shown, the set-side level shifters 71, 73, and 75 for phases U, V, and W, and the reset-side level shifters 72, 74, and 76 are arranged along the vertical direction of the paper. The other structures of the semiconductor device according to the first modification of the embodiment of the present invention are the same as those according to the embodiment of the present invention, and therefore repeated descriptions are omitted.

[0109] In the semiconductor device according to the first variation of the present invention, there is no particular limitation on the arrangement position of the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 of the U-phase, V-phase, and W-phase. For example, the arrangement of the set-side level shifters 71, 73, 75 and the reset-side level shifters 72, 74, 76 of the U-phase, V-phase, and W-phase along the vertical direction of the paper also achieves the same effect as the semiconductor device according to the embodiment of the present invention.

[0110] <Second Variation>

[0111] The semiconductor device involved in the second variation of the embodiments of the present invention and Figure 1 The semiconductor device involved in the embodiments of the present invention shown differs in that, as Figure 22 As shown, the set-side wiring 21 is positioned below the reset-side wiring 22. The set-side wiring 21 is disposed on the same wiring layer as the ring wirings 8u, 8v, and 8w, separated from them. The set-side wiring 21 is connected to the connection wiring 25, which is positioned above the set-side wiring 21, via a contact hole 26. The connection wiring 25 is connected to the ring wiring 8u via a contact hole 24. Other structures of the semiconductor device according to the second modification of the embodiment of the present invention are the same as those according to the embodiment of the present invention, and therefore repeated descriptions are omitted.

[0112] Even when the set-side wiring 21 is positioned lower than the reset-side wiring 22, the semiconductor device according to the second variation of the present invention can connect the set-side wiring 21 to the ring wiring 8u via the connecting wiring 25, achieving the same effect as the semiconductor device according to the embodiment of the present invention.

[0113] <Third Variation>

[0114] The semiconductor device involved in the third variation of the embodiments of the present invention and Figure 1The semiconductor device involved in the embodiments of the present invention shown differs in that, as Figure 23 As shown, there are no VCC wirings 41-44. The semiconductor device according to the third variation of the embodiment of the present invention differs from the semiconductor device according to the embodiment of the present invention in that the set-side wiring 21 and the reset-side wiring 22 are disposed on the same wiring layer as the ring wirings 8u, 8v, and 8w.

[0115] The set-side wiring 21 is configured separately from the ring wirings 8u, 8v, and 8w. The set-side wiring 21 is connected to the connection wiring 25, which is layered above the set-side wiring 21, via a contact hole 26. The connection wiring 25 is connected to the ring wiring 8u via a contact hole 24. The reset-side wiring 22 is configured separately from the ring wirings 8u, 8v, and 8w. The reset-side wiring 22 is connected to the connection wiring 27, which is layered above the set-side wiring 22, via a contact hole 28. The connection wiring 27 is connected to the ring wiring 8u via a contact hole 23. Other structures of the semiconductor device according to the third modification of the embodiment of the present invention are the same as those according to the embodiment of the present invention, and therefore repeated descriptions are omitted.

[0116] Even in the case where there is no VCC wiring 41-44 and the set-side wiring 21 and reset-side wiring 22 are disposed on the same wiring layer as the ring wiring 8u, 8v, 8w, the semiconductor device according to the third variation of the present invention can connect the set-side wiring 21 and reset-side wiring 22 to the ring wiring 8u via the connecting wiring 25, 27, and achieve the same effect as the semiconductor device according to the embodiment of the present invention.

[0117] <Fourth Variation>

[0118] The semiconductor device involved in the fourth variation of the embodiments of the present invention and Figure 23 The common feature of the semiconductor devices involved in the third variation shown is that, as Figure 24 As shown, there are no VCC wirings 41-44, and the set-side wiring 21 and reset-side wiring 22 are disposed on the same wiring layer as the ring wirings 8u, 8v, and 8w. However, the semiconductor device according to the fourth modification of the present invention differs from the semiconductor device according to the third modification in that the connecting wirings 25 and 27 are not used, and the set-side wiring 21 and reset-side wiring 22 are directly connected to the ring wiring 8u. For example, in Figure 24 In this process, the ends of the set-side wiring 21 and the reset-side wiring 22 are extended to the side of the ring wiring 8u, thereby directly connecting the set-side wiring 21 and the reset-side wiring 22 to the ring wiring 8u.

[0119] Furthermore, the semiconductor device involved in the fourth variation of the embodiments of the present invention is... Figure 23The difference in the semiconductor device involved in the third variation shown is that the loop wiring 8u, 8v, 8w of the U phase, V phase, and W phase are directly connected to each other.

[0120] Furthermore, connecting wires 81 and 84, positioned above the loop wirings 8u, 8v, and 8w, are arranged in a manner that overlaps with the portions directly connected to the loop wirings 8u, 8v, and 8w of phases U, V, and W. The loop wirings 8u and 8v are connected to the connecting wire 81 via contact holes 82 and 83. The loop wirings 8v and 8w are connected to the connecting wire 84 via contact holes 85 and 86. By configuring the connecting wires 81 and 84, wiring resistance can be reduced. Alternatively, the connecting wires 81 and 84 may be omitted, and the loop wirings 8u, 8v, and 8w may be directly connected to each other. The other structures of the semiconductor device according to the fourth modification of the embodiment of the present invention are the same as those according to the embodiment of the present invention, and therefore, repeated descriptions are omitted.

[0121] The semiconductor device according to the fourth variation of the present invention, in the case where the set-side wiring 21 and the reset-side wiring 22 are directly connected to the ring wiring 8u, or the ring wirings 8u, 8v, and 8w are directly connected to each other, also achieves the same effect as the semiconductor device according to the embodiment of the present invention.

[0122] <Fifth Variation>

[0123] The semiconductor device involved in the fifth variation of the embodiments of the present invention and Figure 1 The semiconductor device involved in the embodiments of the present invention shown differs in that, as Figure 25 As shown, the first wiring 8u1, 8v1, 8w1, which are electrically connected to the set-side level shifters 71, 73, 75 of the high-potential side circuit regions 10u, 10v, 10w of phases U, V, and W, are separate from the second wiring 8u2, 8v2, 8w2, which are electrically connected to the reset-side level shifters 72, 74, 76.

[0124] exist Figure 25 In the diagram, the p-type base region 14 disposed on the semiconductor substrate 1 and the n-type semiconductor regions 18, 18a, and 18b disposed on the semiconductor substrate 1 and located directly below the VCC wirings 42, 43, and 44 are schematically represented by dashed lines. The VCC wirings 42, 43, and 44 are electrically connected to the n-type semiconductor regions 18, 18a, and 18b via contact holes 42a, 43a, and 44a.

[0125] The first wirings 8u1 and 8v1 of the adjacent high-potential side circuit regions 10u and 10v of phase U and phase V are separated from each other, and the second wirings 8u2 and 8v2 are separated from each other. The first wirings 8v1 and 8w1 of the adjacent high-potential side circuit regions 10v and 10w of phase V and phase W are separated from each other, and the second wirings 8v2 and 8w2 are separated from each other.

[0126] The first wiring 8w1 of the high-potential side circuit region 10w of the W phase, located closer to the GND pad 2, is electrically connected to the set-side wiring 21 via the first wiring 8v1 of the high-potential side circuit region 10v of the V phase, located farther from the GND pad 2. The second wiring 8w2 of the high-potential side circuit region 10w of the W phase, located closer to the GND pad 2, is electrically connected to the reset-side wiring 22 via the second wiring 8v2 of the high-potential side circuit region 10v of the V phase, located farther from the GND pad 2.

[0127] The first wiring 8v1 of the high-potential side circuit region 10v of the V phase, located closer to the GND pad 2, is electrically connected to the set-side wiring 21 via the first wiring 8u1 of the high-potential side circuit region 10u of the U phase, located farther from the GND pad 2. The second wiring 8v2 of the high-potential side circuit region 10v of the V phase, located closer to the GND pad 2, is electrically connected to the reset-side wiring 22 via the second wiring 8u2 of the high-potential side circuit region 10u of the U phase, located farther from the GND pad 2.

[0128] Furthermore, the semiconductor device involved in the fifth variation of the embodiments of the present invention is... Figure 1 The semiconductor device involved in the embodiment of the present invention shown differs in that the first connecting wires 81a and 84a that electrically connect the first wirings 8u1, 8v1, and 8w1 of the high-potential side circuit regions 10u, 10v, and 10w of the U-phase, V-phase, and W-phase to each other are separated from the second connecting wires 81b and 84b that electrically connect the second wirings 8u2, 8v2, and 8w2 of the high-potential side circuit regions 10u, 10v, and 10w of the U-phase, V-phase, and W-phase to each other.

[0129] The first connecting wires 81a and 84a and the second connecting wires 81b and 84b are wires that are positioned above the first wires 8u1, 8v1, 8w1 and the second wires 8u2, 8v2, 8w2 of the high-potential side circuit regions 10u, 10v, and 10w of phases U, V, and W, respectively. The first connecting wire 81a electrically connects the adjacent first wires 8u1 and 8v1 of the high-potential side circuit regions 10u and 10v of phases U and V to each other via contact holes 82a and 83a. The second connecting wire 81b electrically connects the second wires 8u2 and 8v2 of the high-potential side circuit regions 10u and 10v of phases U and V to each other via contact holes 82b and 83b.

[0130] The first connecting wire 84a electrically connects the adjacent first wires 8v1 and 8w1 of the high-potential side circuit regions 10V and 10W of the V and W phases to each other via contact holes 85a and 86a. The second connecting wire 84b electrically connects the adjacent second wires 8v2 and 8w2 of the high-potential side circuit regions 10V and 10W of the V and W phases to each other via contact holes 85b and 86b. Other structures of the semiconductor device according to the fifth modification of the embodiment of the present invention are the same as those according to the embodiment of the present invention, and therefore repeated descriptions are omitted.

[0131] According to the fifth variation of the present invention, the semiconductor device also has the same effect as the semiconductor device according to the embodiments of the present invention in the following structure: the first wirings 8u1, 8v1, 8w1 electrically connected to the set-side level shifters 71, 73, 75 are separated from the second wirings 8u2, 8v2, 8w2 electrically connected to the reset-side level shifters 72, 74, 76; and the first connecting wirings 81a, 84a electrically connecting the first wirings 8u1, 8v1, 8w1 of the high-potential side circuit regions 10u, 10v, 10w of the U-phase, V-phase, and W-phase are separated from the second connecting wirings 81b, 84b electrically connecting the second wirings 8u2, 8v2, 8w2 of the high-potential side circuit regions 10u, 10v, 10w of the U-phase, V-phase, and W-phase are separated from each other.

[0132] <Sixth Variation>

[0133] The semiconductor device involved in the sixth variation of the embodiments of the present invention and Figure 25 The common feature of the semiconductor devices involved in the fifth variation of the embodiments of the present invention shown is that, as Figure 26 As shown, the first wiring 8u1, 8v1, 8w1, which are electrically connected to the set-side level shifters 71, 73, 75 of the high-potential side circuit regions 10u, 10v, 10w of phases U, V, and W, are separate from the second wiring 8u2, 8v2, 8w2, which are electrically connected to the reset-side level shifters 72, 74, 76.

[0134] However, the semiconductor device involved in the sixth variation of the embodiments of the present invention is similar to... Figure 25 The semiconductor device involved in the fifth variation of the embodiment of the present invention shown is different in that a first connecting wire electrically connecting the first wirings 8u1, 8v1, 8w1 of the same high-potential side circuit regions 10u, 10v, 10w is connected to a second connecting wire electrically connecting the second wirings 8u2, 8v2, 8w2 of the same high-potential side circuit regions 10u, 10v, 10w to form connecting wires 81, 84.

[0135] exist Figure 26 In, with Figure 25 Similarly, the n-type semiconductor regions 18, 18a, and 18b directly below the p-type base region 14 and VCC wirings 42, 43, and 44 are schematically represented by dashed lines. VCC wirings 42, 43, and 44 are electrically connected to the n-type semiconductor regions 18, 18a, and 18b via contact holes (not shown). The other structures of the semiconductor device according to the sixth modification of the present invention are the same as those according to the fifth modification of the present invention, and therefore repeated descriptions are omitted.

[0136] According to the sixth variation of the present invention, the semiconductor device also achieves the same effect as the semiconductor device according to the embodiments of the present invention in the following case: the first wirings 8u1, 8v1, 8w1 electrically connected to the set-side level shifters 71, 73, 75 are separated from the second wirings 8u2, 8v2, 8w2 electrically connected to the reset-side level shifters 72, 74, 76, and the first connecting wirings 8u1, 8v1, 8w1 electrically connected to the first wirings 8u1, 8v1, 8w1 of the same high-potential side circuit regions 10u, 10v, 10w, and the second connecting wirings 8u2, 8v2, 8w2 electrically connected to the second wirings 8u2, 8v2, 8w2 of the same high-potential side circuit regions 10u, 10v, 10w are connected to form connecting wirings 81, 84.

[0137] (Other implementation methods)

[0138] As described above, the present invention has been illustrated through embodiments and variations thereof, but it should not be construed as limiting the invention by the discussion and drawings that constitute a part of this disclosure. Based on this disclosure, those skilled in the art will recognize various alternative embodiments, examples, and application techniques.

[0139] For example, the structures disclosed in each embodiment and its variations of the present invention can be appropriately combined without contradiction. For example, in the semiconductor devices according to the embodiments of the present invention, and in the semiconductor devices according to the first to fourth variations of the embodiments of the present invention, the ring-shaped wirings 8u, 8v, and 8w can be replaced with the first wirings 8u1, 8v1, and 8w1 and the second wirings 8u2, 8v2, and 8w2 that are separated from each other, as in the semiconductor devices according to the fifth and sixth variations of the embodiments of the present invention.

[0140] Furthermore, in embodiments of the present invention, such as Figure 1As shown, the GND pad 2 is positioned at the right corner of the semiconductor substrate 1, but the position of the GND pad 2 is not particularly limited. For example, the GND pad 2 may be positioned at the left corner of the semiconductor substrate 1, and the length of the set-side wiring 21 may be longer than the length of the reset-side wiring 22.

[0141] Furthermore, in the embodiments of the present invention, a case in which a Si substrate is used as the semiconductor substrate 1 is exemplified. In addition to the case in which Si is used, it can also be applied to the case in which semiconductor (wide bandgap semiconductor) materials such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN) have a wider bandgap than Si.

[0142] Furthermore, while the example shown is of an HVIC semiconductor device, it can also be applied to semiconductor devices other than HVIC. For example, it is particularly effective for semiconductor devices subjected to high voltages of tens of volts or more.

[0143] Explanation of reference numerals in the attached figures

[0144] 1: Semiconductor substrate (semiconductor chip); 2: GND pad; 3u, 3v, 3w: Input pads; 4: VCC pad; 5: Control circuit; 6u, 6v, 6w: Gate drive circuit; 8u, 8v, 8w: Ring wiring; 8u1, 8v1, 8w1: First wiring; 8u2, 8v2, 8w2: Second wiring; 9u, 9v, 9w: High-voltage junction termination region; 10u, 10v, 10w: High-potential side circuit region; 11, 11a: n-type well region; 12, 12a: n -13: P-type junction isolation region (slit region); 14, 14a: P-type base region; 15, 15a, 16: Pickup region; 17, 17a, 19: Contact region; 18, 18a, 18b: N-type semiconductor region; 20: Wiring; 21: Set-side wiring; 22: Reset-side wiring; 23, 24, 26, 28: Contact holes; 25, 27: Connection wiring; 41, 42, 43, 44: VCC wiring; 42a, 43a, 44a: Contact holes; 61, 62, 63: Power supply; 71, 73, 75: Set-side level shifter; 72, 74, 76: Reset-side level shifter; 71d, 72d, 73d, 74d, 75d, 7 6d: Drain region; 71s, 72s, 73s, 74s, 75s, 76s: Source region; 81, 84: Connection wiring; 81a, 84a: First connection wiring; 81b, 84b: Second connection wiring; 82, 82a, 82b, 83, 83a, 83b, 85, 85a, 85b, 86, 86a, 86b: Contact holes; 101, 102, 103: Insulating film; 104: Drain electrode; 111: Gate electrode; 112, 116, 117: Pick-up electrode; 113: Level shift resistor; 114: First electrode; 115: Second electrode; 120: GND wiring; 121, 122, 123, 124: Contact holes.

Claims

1. A semiconductor device, characterized in that, have: solder pads; The control circuit uses the first potential applied to the pad as a reference potential; Multiple high-potential side circuit regions are provided, each at a different distance from the pad. Each high-potential side circuit region includes a gate drive circuit, a set-side level shifter, and a reset-side level shifter. The gate drive circuit uses a second potential of the floating potential as a reference potential. The set-side level shifter transforms a set signal with the first potential as the reference potential into a set signal with the second potential as the reference potential. The reset-side level shifter transforms a reset signal with the first potential as the reference potential into a reset signal with the second potential as the reference potential. Set-side routing electrically connects the pad to the set-side level shifter in the high-potential-side circuit region furthest from the pad; and The reset-side wiring electrically connects the pads to the reset-side level shifter in the high-potential-side circuit region furthest from the pads. The set-side level shifter located in the high-potential side circuit region that is closer to the pad than the high-potential side circuit region furthest from the pad is electrically connected to the pad via the set-side wiring. The reset-side level shifter located in the high-potential side circuit region that is closer to the pad than the high-potential side circuit region that is furthest from the pad is electrically connected to the pad via the reset-side wiring.

2. The semiconductor device according to claim 1, characterized in that, The lengths of the set-side wiring and the reset-side wiring are different.

3. The semiconductor device according to claim 1 or 2, characterized in that, The plurality of high-potential side circuit regions each have a first wiring electrically connected to the set-side level shifter and a second wiring electrically connected to the reset-side level shifter. The first wiring in the high-potential side circuit region located on the side closer to the pad is electrically connected to the set-side wiring via the first wiring in the high-potential side circuit region located on the side farther from the pad. The second wiring in the high-potential side circuit region located on the side closer to the pad is electrically connected to the reset side wiring via the second wiring in the high-potential side circuit region located on the side farther from the pad.

4. The semiconductor device according to claim 3, characterized in that, It also has: A first connection wiring electrically connects the first wirings of different high-potential side circuit regions to each other. as well as The second connection wiring electrically connects the second wirings of different high-potential side circuit regions to each other.

5. The semiconductor device according to claim 3, characterized in that, It also has: A first connection wiring electrically connects the first wirings of adjacent high-potential side circuit regions to each other. as well as The second connection wiring electrically connects the second wirings of adjacent high-potential side circuit regions to each other.

6. The semiconductor device according to claim 5, characterized in that, The first connection wire, which electrically connects the first wirings of the same high-potential side circuit regions to each other, is connected to the second connection wire, which electrically connects the second wirings of the same high-potential side circuit regions to each other.

7. The semiconductor device according to claim 3, characterized in that, The first wiring and the second wiring are connected within the same high-potential side circuit region.

8. The semiconductor device according to claim 7, characterized in that, The first and second wirings connected are loop wirings configured to surround the gate drive circuit.

9. The semiconductor device according to any one of claims 4 to 6, characterized in that, The first connection wiring and the second connection wiring are wirings that are positioned above the first wiring and the second wiring of each of the plurality of high-potential side circuit regions.

10. The semiconductor device according to claim 3, characterized in that, The first wiring of adjacent high-potential side circuit regions is separated from each other, and the second wiring of adjacent high-potential side circuit regions is separated from each other.

11. The semiconductor device according to claim 4, characterized in that, It also includes VCC wiring, which is configured below the first connection wiring and the second connection wiring and is electrically connected to the power supply of the control circuit.

12. The semiconductor device according to claim 3, characterized in that, The first wiring of adjacent high-potential side circuit regions is directly connected, and the second wiring of adjacent high-potential side circuit regions is directly connected.

13. A semiconductor device comprising: solder pads; The control circuit uses the first potential applied to the pad as a reference potential; Multiple high-potential side circuit regions are provided, each at a different distance from the pad. Each high-potential side circuit region includes a gate drive circuit, a set-side level shifter, a reset-side level shifter, and a ring wiring. The gate drive circuit uses a second potential of the floating potential as a reference potential. The set-side level shifter converts a set signal with the first potential as the reference potential into a set signal with the second potential as the reference potential. The reset-side level shifter converts a reset signal with the first potential as the reference potential into a reset signal with the second potential as the reference potential. The ring wiring is connected to the set-side level shifter and the reset-side level shifter. Set-side wiring electrically connects the pads to the set-side level shifters of each of the plurality of high-potential-side circuit regions; and The reset-side wiring electrically connects the pads to the reset-side level shifters of each of the plurality of high-potential-side circuit regions. in, The loop wiring in the high-potential side circuit region located on the side closer to the pad is electrically connected to the set-side wiring and the reset-side wiring via the loop wiring in the high-potential side circuit region located on the side farther from the pad.

14. The semiconductor device according to claim 13, characterized in that, The set-side wiring and the reset-side wiring are positioned above the respective ring wiring of the plurality of high-potential side circuit regions, and are connected to the ring wiring of the high-potential side circuit region located on the side furthest from the pad via contact holes.

15. The semiconductor device according to claim 13, characterized in that, The set-side wiring and the reset-side wiring are configured on the same layer as the ring wiring of each of the plurality of high-potential side circuit regions. The semiconductor device further includes interconnect wiring disposed above the set-side wiring and the reset-side wiring, the interconnect wiring electrically connecting the set-side wiring and the reset-side wiring to the loop wiring located on the side furthest from the pads in the high-potential side circuit region.

16. The semiconductor device according to claim 13, characterized in that, The set-side wiring and the reset-side wiring are configured on the same layer as the loop wiring of each of the plurality of high-potential side circuit regions. The set-side wiring and the reset-side wiring are directly connected to the loop wiring of the high-potential side circuit region located on the side furthest from the pad.

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