Semiconductor device and semiconductor device manufacturing method

Abstract

A memory cell of a semiconductor device includes a stacked structure, a receiving space penetrating the stacked structure, a barrier layer, a floating gate layer, and a channel layer. The stacked structure includes at least one control layer, at least two dielectric layers, and at least one erase layer. The receiving space includes a first receiving portion and a plurality of second receiving portions communicating with the first receiving portion. The first receiving portion penetrates the stacked structure. The second receiving portion is coplanar with the control layer. The barrier layer and the floating gate layer are received within the second receiving portion, and the floating gate layer is insulated from the control layer by the barrier layer. The erase layer cooperates with the floating gate layer to form an electron flow path during a data erase operation. The present invention also provides a method for manufacturing a semiconductor device.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and in particular to a 3D flash memory device. Background Art

[0002] In the current semiconductor industry, three-dimensional (3D) flash memory can retain stored information for long periods of time without power, and offers advantages such as high integration, fast storage speed, and ease of erasure and rewriting. During data write and erase operations, electrons migrate between the floating gate and the channel layer through a tunnel dielectric layer, depending on the voltage between the floating gate and the control gate. Repeated data write and erase operations can degrade the performance of the tunnel dielectric layer, leading to a decrease in the memory's data storage capabilities. Summary of the Invention

[0003] The main purpose of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device, aiming to solve the problems of degradation of tunnel dielectric layer performance and degradation of memory data storage function in the prior art.

[0004] A semiconductor device includes a plurality of memory cells; each of the memory cells includes:

[0005] A stacked structure comprising at least one control layer, at least two dielectric layers, and at least one erase layer; wherein the erase layer and the control layer are isolated by the dielectric layer;

[0006] A receiving space penetrating the stacked structure; the receiving space includes a first receiving portion and a plurality of second receiving portions communicating with the first receiving portion; the first receiving portion penetrates the stacked structure; the second receiving portion is coplanar with the control layer;

[0007] a barrier layer received in the second receiving portion;

[0008] a floating gate layer, housed in the second housing portion and insulated from the control layer by the barrier layer;

[0009] a channel layer, housed in the first housing portion;

[0010] The erasure layer is used to cooperate with the floating gate layer to form an electron flow path when performing a data erasure operation.

[0011] A method for manufacturing a semiconductor device, for manufacturing a semiconductor device, comprising the following steps:

[0012] Providing a stacked structure consisting of at least one first sacrificial layer, at least two dielectric layers, and at least one second erase layer; wherein the second sacrificial layer is isolated from the first sacrificial layer by the dielectric layer;

[0013] Etching the stacked structure to form a receiving space; wherein the receiving space includes a first receiving portion and a plurality of second receiving portions communicating with the first receiving portion; the first receiving portion penetrates the corresponding stacked structure; and the second receiving portion is coplanar with the first sacrificial layer;

[0014] forming a barrier layer and a floating gate layer in sequence in the receiving space;

[0015] removing the portion of the floating gate layer located in the first receiving space so that the barrier layer and the floating gate layer are completely received in the second receiving portion;

[0016] forming a tunnel dielectric layer, a channel layer and a filling layer in sequence in the first receiving portion;

[0017] removing the first sacrificial layer and the second sacrificial layer;

[0018] A control layer is formed at the position after the first sacrificial layer is removed, and an erase layer is formed at the position after the second sacrificial layer is removed to constitute the semiconductor device. The erase layer cooperates with the floating gate layer to form an electron flow path when performing a data erase operation.

[0019] The semiconductor device and semiconductor device manufacturing method described above, by providing the erase layer embedded in the dielectric layer, and during the erase operation, the erase layer cooperates with the floating gate layer to form an electron flow path, thereby avoiding data writing and data erasing through the same path, reducing the loss of the tunnel dielectric layer caused by repeated data erase operations, and improving the service life of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0021] Figure 1 It is a schematic cross-sectional view of the semiconductor device of the present invention along the horizontal direction.

[0022] Figure 2 It is a schematic cross-sectional view of the semiconductor device of the present invention along the vertical direction.

[0023] Figure 3 for Figure 1 A schematic cross-sectional view of the erase layer along the horizontal direction.

[0024] Figure 4 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to the present invention.

[0025] Figure 5 for Figure 4 The schematic cross-sectional view of the structure corresponding to step S10 along the vertical direction.

[0026] Figure 6 for Figure 4 Step S11 is a schematic cross-sectional view of the corresponding structure along the vertical direction.

[0027] Figure 7 for Figure 4 The schematic cross-sectional view of the structure corresponding to step S12 along the vertical direction.

[0028] Figure 8 for Figure 4 Step S13 is a schematic cross-sectional view of the corresponding structure along the vertical direction.

[0029] Figure 9 for Figure 4 The schematic cross-sectional view of the structure corresponding to step S14 along the vertical direction.

[0030] Figure 10 for Figure 4 Step S15 is a schematic cross-sectional view of the corresponding structure along the vertical direction.

[0031] Description of main component symbols

[0032] Semiconductor device 1

[0033] Storage unit 10

[0034] Stacked structure ST

[0035] Dielectric layer 11

[0036] Insulation layer 12

[0037] Control layer 13

[0038] Erasure layer 112

[0039] Barrier layer 14

[0040] Floating gate layer 15

[0041] Tunnel dielectric layer 16

[0042] Channel layer 17

[0043] Filling layer 18

[0044] Containment Space OP

[0045] First storage unit op1

[0046] Second storage unit op2

[0047] Memory cell area 101

[0048] Specify pattern P

[0049] Part 1 P1

[0050] Part 2 P2

[0051] First sacrificial layer 19a

[0052] Second sacrificial layer 19b

[0053] Write path path-A

[0054] Erase path path-B

[0055] Semiconductor device manufacturing method S10-S16

[0056] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0057] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0058] The terms "first," "second," and "third," etc., in the present description and accompanying drawings are used to distinguish between different items, not to describe a specific order. Furthermore, the terms "comprise," "comprising," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or apparatus.

[0059] The specific embodiments of the semiconductor device manufacturing method of the present invention are described below with reference to the accompanying drawings.

[0060] Please refer to Figure 1 as well as Figure 2The present invention provides a schematic cross-sectional view of a semiconductor device 1 along a horizontal direction and a schematic cross-sectional view along a vertical direction. The semiconductor device 1 is a stacked structure, which is composed of a plurality of memory cells 10. Figure 1 FIG. 1 is a schematic diagram showing only one storage unit 10 in the horizontal direction. Figure 2 Schematic diagram of a vertical cross-section of two adjacent storage units 10. In at least one embodiment of the present invention, the semiconductor device 1 may be a three-dimensional flash memory. Each storage unit 10 may be capable of performing data write and data erase operations.

[0061] Each of the storage units 10 includes a stacked structure ST, a receiving space op (such as Figure 6 As shown), an insulating layer 12, a floating gate layer 15, a blocking layer 14, a tunnel dielectric layer 16, a channel layer 17 and a filling layer 18.

[0062] The stacked structure ST includes a plurality of control layers 13, a plurality of dielectric layers 11, and a plurality of erase layers 112. Figure 2 As shown in FIG. 1 , the stacked structure ST includes two control layers 13, three dielectric layers 11, and three erase layers 112. Two of the dielectric layers 11 serve as the bottom and top layers, respectively, and the other dielectric layer 11 serves as the middle layer. The control layer 13 is sandwiched between two adjacent dielectric layers 11, and the erase layer 112 is isolated from the control layer 13 by the dielectric layer 11. The erase layer 112 is isolated from the floating gate layer 15 by the dielectric layer 11 and the barrier layer 14.

[0063] The barrier layer 14, the tunnel dielectric layer 16, the channel layer 17 and the filling layer 18 in the control layer 13 are generally annular structures (eg Figure 1 In at least one embodiment of the present invention, the control layer 13 is made of a conductive material.

[0064] In the first direction X, the erase layer 112 is insulated from the corresponding control layer 13 by the dielectric layer 11. The erase layer 112 is insulated from the floating gate layer 15 by the dielectric layer 11 and the barrier layer 14. The erase layer 112 is insulated from the channel layer 17 located within the receiving space op by the dielectric layer 11 and the barrier layer 14. The filling layer 18 itself is mostly composed of a dielectric material and is insulated from the adjacent channel layer 17.

[0065] Please also refer to Figure 3 , Figure 3The diagram illustrates the erase layers 112 of the memory cells 10 arranged in a 2x2 matrix. In other embodiments, the first portion P1 can be divided to form the erase layers 112 within more memory cells 10. In the second direction Y, the erase layer 112 is interconnected with adjacent erase layers 112 coplanarly arranged within another memory cell 10 and formed integrally. The second direction Y is perpendicular to the first direction X and is horizontal. In other words, the erase layer 112 is interconnected with the erase layers 112 coplanarly arranged along the second direction Y within adjacent memory cells 10 to form a designated pattern P. Viewed from the first direction X, the designated pattern P includes two first portions P1 arranged parallel to the second direction Y and at least two second portions P2 arranged parallel to a third direction Z. The first direction X, the second direction Y, and the third direction Z are mutually perpendicular to each other to form a three-dimensional coordinate system. The second portion P2 is connected to the first portion P1. At least one end of the second portion P2 is connected to the first portion P1. In at least one embodiment of the present invention, both ends of the second portion P2 are connected to the first portion P1. The first portion P1 is used to electrically connect the memory cell 10 corresponding to the erase layer 112 to an external circuit. In at least one embodiment of the present invention, the erase layer 112 is made of a low-resistance conductive material, such as a metal or silicide; and the dielectric layer 11 is made of an insulating material.

[0066] Please also refer to Figure 6 , the receiving space op passes through the center of the stacked structure ST. In at least one embodiment of the present invention, the receiving space op is roughly non-letter-shaped. The receiving space op includes a first receiving portion op1 and a plurality of second receiving portions op2. The first receiving portion op1 penetrates the stacked structure ST along the first direction X. The second receiving portion op2 is connected to the first receiving portion op1. The second receiving portion op2 extends from the first receiving portion op1 into the control layer 13 along the second direction Y. In at least one embodiment of the present invention, the receiving space op includes four second receiving portions op2. The four second receiving portions op2 are symmetrically arranged on both sides of the first receiving portion op1.

[0067] The barrier layer 14 is partially contained within the second receiving portion op2 and partially contained within the first receiving portion op1, and is coplanar with the control layer 13. In the first direction X, the thickness of the barrier layer 14 is twice less than the thickness of the control layer 13, so that the barrier layer 14 is completely contained within the second receiving portion op2, forming a receiving portion (not shown) to accommodate the floating gate layer 15. The barrier layer 14 within the first receiving portion op1 is arranged parallel to the first direction X.

[0068] The floating gate layer 15 is accommodated in the receiving portion of the barrier layer 14 and is located in the second receiving portion op2. In the second direction Y, the floating gate layer 15 and the control layer 13 are arranged on the same plane. The floating gate layer 15 is a semi-annular structure (eg Figure 1 In the first direction X, the floating gate layer 15 partially overlaps the erase layer 112. In at least one embodiment of the present invention, the floating gate layer 15 is made of silicide or other materials with good conductivity. The floating gate layer 15 is used to store data.

[0069] The tunnel dielectric layer 16 is contained in the first containing portion op1 and covers the barrier layer 14 and the sidewalls of the floating gate layer 15 along the first direction X. The tunnel dielectric layer 16 is substantially annular in shape (eg Figure 1 shown).

[0070] The channel layer 17 is disposed in the first receiving portion op1 and is located between the tunnel dielectric layer 16 and the filling layer 18. The channel layer 17 is substantially annular in structure (eg Figure 1 In at least one embodiment of the present invention, the channel layer 17 is made of a semiconductor material, such as silicon.

[0071] The filling layer 18 is used to fill the remaining first receiving portion op1. In at least one embodiment of the present invention, the filling layer 18 is made of insulating material.

[0072] Please refer again Figure 1 The memory cell 10 further includes an insulating layer 12. The insulating layer 12 insulates and isolates the barrier layer 14 located on both sides of the receiving space OP in the second direction Y, and insulates and isolates the tunnel dielectric layer 16 from the tunnel dielectric layer 16 in the adjacent memory cell 10 in the third direction Z. In at least one embodiment of the present invention, the insulating layer 12 is made of silicon oxide.

[0073] The data writing operation performed by the memory cell 10 is consistent with the process of conventional semiconductor devices and will not be further described here. For example, a corresponding voltage is applied to the control layer 13, causing electrons to flow along the write path path-A from the channel layer 17 through the tunnel dielectric layer 16 into the floating gate layer 15, thereby achieving data storage.

[0074] When the memory cell 10 performs a data erase operation, a forward voltage is applied to the erase layer 112, causing the floating gate layer 15 to float. A voltage less than the forward voltage is applied to the control layer 13 to prevent breakdown between the erase layer 112 and the control layer 13. Simultaneously, a ground voltage or a negative voltage is applied to the channel layer 17, causing electrons to flow from the floating gate layer 15 along an erase path-B, through the dielectric layer 11 and the sidewalls of the barrier layer 14 located at the overlapped portion of the erase layer 112 and the floating gate layer 15, and into the erase layer 112, rather than through the tunnel dielectric layer 16. In at least one embodiment of the present invention, the forward voltage is 10-15 volts.

[0075] The semiconductor device 1 is provided with the erase layer 112, and the erase layer 112 and the floating gate layer 15 partially overlap in the first direction X, so that during an erase operation, electrons flow from the floating gate layer 15 through the sidewall located at the overlapping portion of the erase layer 112 and the floating gate layer 15 into the erase layer 112, thereby avoiding data writing and data erasure through the same path, reducing the loss of the tunnel dielectric layer 16 caused by repeated erase operations, and improving the service life of the semiconductor device 1.

[0076] See also Figure 4 , which is a flow chart of a method for manufacturing a semiconductor device provided by the present invention. The method for manufacturing a semiconductor device is used to manufacture the semiconductor device 1 described above. The method for manufacturing a semiconductor device comprises the following steps:

[0077] S10 , providing a stacked structure ST consisting of a first sacrificial layer 19 a , a dielectric layer 11 , and a second sacrificial layer 19 b .

[0078] Please also refer to Figure 5In at least one embodiment of the present invention, the stacked structure ST includes two first sacrificial layers 19a, three dielectric layers 11, and three second sacrificial layers 19b. The two first sacrificial layers 19a are separated by the dielectric layer 11. The dielectric layer 11 is formed by multiple deposition and planarization steps. During the deposition of the dielectric layer 11, etching and patterning are performed to form the second sacrificial layer 19b composed of the first material. After the second sacrificial layer 19b is formed, the dielectric layer 11 is deposited again to insulate and isolate the second sacrificial layer 19b from the first sacrificial layer 19a. Next, the first sacrificial layer 19a composed of the first material is deposited over the dielectric layer 11. These steps are repeated to form the stacked structure ST. Two dielectric layers 11 serve as the bottom and top layers, respectively, and another dielectric layer 11 serves as the middle layer. The control layer 13 is sandwiched between two adjacent dielectric layers 11. The second sacrificial layer 19b is separated from the first sacrificial layer 19a by the dielectric layer 11. Each second sacrificial layer 19 b is arranged in a designated pattern P. Figure 3 The diagram illustrates the second sacrificial layer 19b of the memory cells 10 arranged in a 2x2 matrix. In other embodiments, the first portion P1 can be divided to form the second sacrificial layer 19b in more memory cells 10. In at least one embodiment of the present invention, the designated pattern P includes two first portions P1 arranged in parallel along a second direction Y and at least two second portions P2 arranged in parallel along a third direction Z. The second portion P2 is connected to the first portion P1. Particularly, at least one end of the second portion P2 is connected to the first portion P1. In at least one embodiment of the present invention, both ends of the second portion P2 are connected to the first portion P1. The first portion P1 is used to electrically connect the memory cell 10 corresponding to the erase layer 112 to an external circuit. In at least one embodiment of the present invention, the first material may be a silicon nitride material; and the dielectric layer 11 is made of an insulating material.

[0079] S11 , etching the stacked structure ST to form a receiving space op.

[0080] Please also refer to Figure 6, the stacked structure ST can be divided into a plurality of equally sized memory cell regions 101, each of which corresponds to a memory cell 10. The receiving space op penetrates the center of the corresponding stacked structure ST. In at least one embodiment of the present invention, the receiving space op is roughly non-letter-shaped. The receiving space op may include a first receiving portion op1 and a plurality of second receiving portions op2. The first receiving portion op1 penetrates the corresponding stacked structure ST along the first direction X. The second receiving portion op2 is connected to the first receiving portion op1. The second receiving portion op2 extends from the first receiving portion op1 in the second direction Y and is arranged coplanar with the control layer 13. In at least one embodiment of the present invention, the receiving space op includes four second receiving portions op2. The four second receiving portions op2 are symmetrically arranged on both sides of the first receiving portion op1. In the first direction X, the second receiving portion op2 overlaps with a portion of the second sacrificial layer 19b. In the first direction X, the second sacrificial layer 19b and the first sacrificial layer 19a partially overlap.

[0081] S12 , forming a barrier layer 14 and a floating gate layer 15 in sequence in the receiving space op.

[0082] Please also refer to Figure 7 , a portion of the barrier layer 14 is accommodated in the second receiving portion op2 and is coplanar with the first sacrificial layer 19a to cover the sidewalls of the first sacrificial layer 19a. The barrier layer 14 also has a portion arranged parallel to the first direction X. In the first direction X, the barrier layer 14 partially overlaps with the second sacrificial layer 19b. The floating gate layer 15 is accommodated in the barrier layer 14 located in the second receiving portion op2 and is located in the second receiving portion op2. In the second direction Y, the floating gate layer 15 is coplanar with the control layer 13. The floating gate layer 15 also includes a portion arranged parallel to the first direction. In at least one embodiment of the present invention, the floating gate layer 15 is made of silicide or other materials with good conductive properties.

[0083] Please refer again Figure 8 In step S13 , the portion of the floating gate layer 15 located in the first receiving portion op1 is removed, so that the floating gate layer 15 is completely received in the second receiving portion op2 .

[0084] Please also refer to Figure 9 In step S14 , a tunnel dielectric layer 16 , a channel layer 17 and a filling layer 18 are sequentially formed in the first receiving portion op1 .

[0085] Please also refer to Figure 2In at least one embodiment of the present invention, the tunnel dielectric layer 16 is housed in the first housing portion op1 and covers the sidewalls of the barrier layer 14 and the floating gate layer 15 along the first direction X. The channel layer 17 is disposed in the first housing portion op1. The channel layer 17 is disposed inside the tunnel dielectric layer 16. In at least one embodiment of the present invention, the channel layer 17 is made of a semiconductor material, such as silicon. The filling layer 18 is used to fill the remaining first housing portion op1. In at least one embodiment of the present invention, the filling layer 18 is made of an insulating material.

[0086] Please also refer to Figure 10 , step S15, removing the first sacrificial layer 19a and the second sacrificial layer 19b.

[0087] Please also refer to Figure 2 , step S16, forming the control layer 13 at the position after removing the first sacrificial layer 19a, and forming the erase layer 112 at the position after removing the second sacrificial layer 19b, to form the semiconductor device 1.

[0088] In at least one embodiment of the present invention, the erase layer 112 and the control layer 13 are formed by filling a second material, wherein the second material is made of a low-resistance conductive material, such as metal, silicide, etc.

[0089] When performing a data writing operation, a corresponding voltage is applied to the control layer 13 so that electrons pass from the channel layer 17 through the tunnel dielectric layer 16 into the floating gate layer 15 , thereby realizing data storage.

[0090] During a data erase operation, a forward voltage is applied to the erase layer 112, causing the floating gate layer 15 to float. A voltage less than the forward voltage is applied to the control layer 13 to prevent breakdown between the erase layer 112 and the control layer 13. Simultaneously, a ground voltage or a negative voltage is applied to the channel layer 17, allowing electrons to flow from the floating gate layer 15 through the dielectric layer 11 and the sidewalls of the barrier layer 14 at the overlapping portion of the erase layer 112 and the floating gate layer 15, into the erase layer 112, rather than through the tunnel dielectric layer 16. In at least one embodiment of the present invention, the forward voltage is 10-15 volts.

[0091] In the semiconductor device manufacturing method, the erase layer 112 is provided, and the erase layer 112 and the floating gate layer 15 partially overlap in the first direction X, so that during an erase operation, electrons flow from the floating gate layer 15 through the sidewall located at the overlapping portion of the erase layer 112 and the floating gate layer 15 into the erase layer 112, thereby avoiding data writing and data erasure through the same path, reducing the loss of the tunnel dielectric layer 16 caused by repeated erase operations, and improving the service life of the semiconductor device 1.

[0092] It should be noted that, for the sake of simplicity, the aforementioned method embodiments are all expressed as a series of action combinations. However, those skilled in the art should know that the present invention is not limited to the described order of actions, because according to the present invention, certain steps can be performed in other orders or simultaneously.

[0093] It should also be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0094] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device comprising a plurality of memory cells; each of the memory cells comprising: A stacked structure comprising at least one control layer, at least two dielectric layers, and at least one erase layer; wherein the erase layer and the control layer are isolated by the dielectric layer; A receiving space penetrating the stacked structure; the receiving space includes a first receiving portion and a plurality of second receiving portions communicating with the first receiving portion; the first receiving portion penetrates the stacked structure; the second receiving portion is coplanar with the control layer; a barrier layer received in the second receiving portion; a floating gate layer, housed in the second housing portion and insulated from the control layer by the barrier layer; a channel layer, housed in the first housing portion; When the semiconductor device performs a data erasing operation, a forward voltage is applied to the erase layer, the floating gate layer is floated, a voltage less than the forward voltage is applied to the control layer, and electrons flow from the floating gate layer through the dielectric layer located at the overlapping portion of the erase layer and the floating gate layer and the sidewall of the blocking layer into the erase layer, and the erase layer and the floating gate layer cooperate to form an electron flow path.

2. The semiconductor device according to claim 1, wherein In a direction parallel to the control layer, the erase layer is insulated from the channel layer located in the receiving space by the dielectric layer and the barrier layer.

3. The semiconductor device according to claim 1, wherein The erasing layer and the adjacent erasing layer in another storage unit are coplanarly arranged and connected to each other and are integrally formed.

4. The semiconductor device according to claim 1, wherein In a direction perpendicular to the stacked structure, the erase layer partially overlaps with the floating gate layer.

5. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device manufacturing method comprises the following steps: Providing a stacked structure consisting of at least one first sacrificial layer, at least two dielectric layers, and at least one second sacrificial layer; wherein the second sacrificial layer is isolated from the first sacrificial layer by the dielectric layer; Etching the stacked structure to form a receiving space; wherein the receiving space includes a first receiving portion and a plurality of second receiving portions communicating with the first receiving portion; the first receiving portion penetrates the corresponding stacked structure; and the second receiving portion is coplanar with the first sacrificial layer; forming a barrier layer and a floating gate layer in sequence in the receiving space; removing the portion of the floating gate layer located in the first receiving space so that the barrier layer and the floating gate layer are completely received in the second receiving portion; forming a tunnel dielectric layer, a channel layer and a filling layer in sequence in the first receiving portion; removing the first sacrificial layer and the second sacrificial layer; A control layer is formed at a position after the first sacrificial layer is removed, and an erase layer is formed at a position after the second sacrificial layer is removed, so as to constitute the semiconductor device. When the semiconductor device performs a data erasing operation, a forward voltage is applied to the erase layer, the floating gate layer is floated, a voltage less than the forward voltage is applied to the control layer, and electrons flow from the floating gate layer through the dielectric layer located at the overlapping portion of the erase layer and the floating gate layer and the sidewall of the blocking layer into the erase layer. The erase layer and the floating gate layer cooperate to form an electron flow path.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: In a direction parallel to the control layer, the erase layer is insulated from the channel layer located in the receiving space by the dielectric layer and the barrier layer.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The stacked structure can be divided into a plurality of storage units; the erasing layer is coplanar with another storage unit, and the adjacent erasing layers are interconnected and integrally formed.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: In a direction perpendicular to the stacked structure, the erase layer partially overlaps with the floating gate layer.

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