Array substrate and manufacturing method thereof, and display panel

Abstract

The present application discloses an array substrate and a manufacturing method thereof, and a display panel. The array substrate comprises a substrate and an active layer; the active layer comprises a channel portion and an active portion, the active portion comprises a first doping portion and a second doping portion, the second doping portion connects the first doping portion and the channel portion, the ion concentration of the first doping portion is greater than the ion concentration of the second doping portion; and in the direction from the substrate to the active layer, the thickness dimension of the first doping portion is greater than the thickness dimension of the second doping portion; the present application adds ions to the first active layer material in advance, and sets the thickness dimension of the position corresponding to the first doping portion in the first active layer to be greater than the thickness dimension of the position corresponding to the second doping portion, and then deposits the second active layer, so that the two active layers are crystallized during laser annealing, and different ion concentrations are formed by means of the thickness difference between the first doping portion and the second doping portion, thereby solving the technical problem that the array substrate using high-temperature diffusion doping cannot realize the LDD structure.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] LTPS TFT (Low Temperature Poly-Silicon Thin Film Transistor) has the advantages of high mobility and good stability, and has broad prospects in the field of display panels.

[0003] In the manufacturing process of the array substrate of the display panel, high-temperature diffusion doping can be used to realize the conductorization of the active layer of the thin film transistor. In the prior art, in order to compensate for the mask alignment deviation during the gate patterning of the thin film transistor, the gate and the doping area are overlapped. Since the gate directly overlaps the doping area, it is impossible to set the LDD (light dopping drain) structure at the junction of the gate and the doping area. The thin film transistor device is easily damaged by the hot carrier effect. Therefore, it is urgent to solve the technical problem that the array substrate using high-temperature diffusion doping cannot realize the LDD structure. Summary of the invention

[0004] The present application provides an array substrate and a manufacturing method thereof, and a display panel, so as to solve the technical problem that an array substrate using high-temperature diffusion doping cannot realize an LDD structure.

[0005] To solve the above-mentioned problems, the technical solutions provided by this application are as follows:

[0006] The present application provides an array substrate, the array substrate comprising a substrate and an active layer disposed on the substrate; wherein the active layer comprises:

[0007] Channel Department;

[0008] an active portion disposed on both sides of the channel portion, the active portion comprising a first doping portion and a second doping portion, the second doping portion being located between the first doping portion and the channel portion, and the second doping portion being connected to the channel portion and the first doping portion, and the ion concentration of the first doping portion being greater than the ion concentration of the second doping portion;

[0009] Wherein, in the direction from the substrate to the active layer, the thickness of the first doped portion is greater than the thickness of the second doped portion.

[0010] In the array substrate of the present application, the array substrate further includes:

[0011] A gate, disposed on the active layer;

[0012] Wherein, in the top view direction of the array substrate, the gate covers the channel portion, the gate and the second doping portion at least partially overlap, and the gate and the first doping portion are arranged non-overlappingly.

[0013] In the array substrate of the present application, in the direction from the substrate to the active layer, the thickness of the channel portion is smaller than the thickness of the second doping portion.

[0014] In the array substrate of the present application, in the direction from the substrate to the active layer, the ion concentration of the second doping part gradually decreases.

[0015] In the array substrate of the present application, the second doping portion is arranged around the first doping portion.

[0016] In the array substrate of the present application, a step structure is provided between the first doping portion and the second doping portion, and a surface of the first doping portion away from the substrate is arranged in parallel with a surface of the second doping portion away from the substrate.

[0017] The present application also provides a method for manufacturing an array substrate, comprising:

[0018] providing a substrate;

[0019] forming a first active material layer doped with ions on the substrate;

[0020] Performing patterning on the first active material layer so that the active material layer forms a plurality of active doping portions in a stepped shape, wherein the plurality of active doping portions are separately arranged;

[0021] forming a second active material layer on the plurality of active doping portions;

[0022] Performing a preset process on the second active material layer and the plurality of active doping portions to form an active portion including a channel portion and active portions disposed on both sides of the channel portion;

[0023] The active portion includes a first doping portion and a second doping portion, the second doping portion is located between the first doping portion and the channel portion, and the second doping portion is connected to the channel portion and the first doping portion, and the ion concentration of the first doping portion is greater than the ion concentration of the second doping portion;

[0024] Wherein, in the direction from the substrate to the active layer, the thickness of the first doped portion is greater than the thickness of the second doped portion.

[0025] In the method for manufacturing the array substrate of the present application, the step of patterning the first active material layer so as to form a plurality of stepped active doping portions in the active material layer includes:

[0026] A first yellow light process and an etching process are used to form a plurality of active doping parts, and a second yellow light process and an etching process are performed on the active doping parts to form a plurality of active doping parts in a stepped shape; or, a first yellow light process and an etching process are used to form a plurality of active doping parts, an ashing process is used to degrade the first photoresist in the yellow light process, and a second etching process is used to form a plurality of active doping parts in a stepped shape.

[0027] In the manufacturing method of the array substrate of the present application, the step of performing a preset process on the second active material layer and the plurality of active doping portions to form an active portion including a channel portion and active portions arranged on both sides of the channel portion includes:

[0028] Laser annealing is performed on the second active material layer and the plurality of active doping parts to diffuse ions in the active doping parts into the second active material layer, and to crystallize the active doping parts and the second active material layer to form an active part including a channel part and active parts arranged on both sides of the channel part.

[0029] The present application also provides a display panel, which includes a panel body and the above-mentioned array substrate, and the panel body and the array substrate are combined into one.

[0030] Beneficial effects: The present application provides an array substrate and a manufacturing method thereof, and a display panel, wherein the array substrate comprises a substrate and an active layer arranged on the substrate; wherein the active layer comprises a channel portion and active portions arranged on both sides of the channel portion, the active portion comprises a first doping portion and a second doping portion, the second doping portion is located between the first doping portion and the channel portion, and the second doping portion is connected to the channel portion and the first doping portion, the ion concentration of the first doping portion is greater than the ion concentration of the second doping portion; and in the direction from the substrate to the active layer, the thickness dimension of the first doping portion is greater than the thickness dimension of the second doping portion; the present application adds ions to the first active layer material in advance, sets the thickness dimension of the position corresponding to the first doping portion in the first active layer to be greater than the thickness dimension of the position corresponding to the second doping portion, and then deposits the second active layer, so that the two active layers are crystallized during laser annealing, and different ion concentrations are formed by means of the thickness difference between the first doping portion and the second doping portion, thereby solving the technical problem that the array substrate using high-temperature diffusion doping cannot realize the LDD structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0032] Figure 1 It is a thin film transistor structure in the prior art;

[0033] Figure 2A A cross-sectional view of a first thin film transistor of the present application;

[0034] Figure 2B A top view of the first thin film transistor of the present application;

[0035] Figure 3A is a cross-sectional view of a second thin film transistor of the present application;

[0036] Figure 3B A top view of a second thin film transistor of the present application;

[0037] Figures 4A-4E This is a process flow chart of the first thin film transistor of the present application;

[0038] Figures 5A-5F This is a process flow chart of the second thin film transistor of the present application.

[0039] Description of reference numerals:

[0040] Substrate 101 , interlayer insulating layer 102 , channel portion 220 , active portion 210 , first doped portion 211 , second doped portion 212 , gate 300 , source-drain layer 400 , source 401 , drain 402 , first active material layer 221 , active doped portion 213 , second active material layer 222 , first photoresist 411 , second photoresist 412 . DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; and "inside" and "outside" refer to the outline of the device.

[0042] The array substrate of the display panel includes a plurality of thin film transistors distributed in an array. In the manufacturing process of the thin film transistor, high temperature diffusion doping can be used to realize the conductor of the active layer of the thin film transistor. In the prior art, in order to compensate for the mask alignment deviation during the gate patterning of the thin film transistor, the gate and the doping area are overlapped. Figure 1 , the gate 300 and the first doped portion 211 partially overlap on the orthographic projection of the substrate 101. Since the gate 300 directly overlaps the first doped portion 211, it is impossible to set the LDD structure at the intersection of the orthographic projection of the gate 300 and the first doped portion 211, and the thin film transistor device is easily damaged by the hot carrier effect. Therefore, it is urgent to solve the technical problem that the array substrate using high temperature diffusion doping cannot realize the LDD structure.

[0043] Therefore, this application proposes the following technical solutions based on the above technical problems.

[0044] See also Figure 2A and Figure 3A The present application provides an array substrate, which includes a substrate 101 and an active layer arranged on the substrate 101; wherein the active layer includes a channel portion 220 and active portions 210 arranged on both sides of the channel portion 220, the active portion 210 includes a first doping portion 211 and a second doping portion 212, the second doping portion 212 is located between the first doping portion 211 and the channel portion 220, and the second doping portion 212 is connected to the channel portion 220 and the first doping portion 211, and the ion concentration of the first doping portion 211 is greater than the ion concentration of the second doping portion 212; wherein in the direction from the substrate 101 to the active layer, the thickness dimension of the first doping portion 211 is greater than the thickness dimension of the second doping portion 212.

[0045] In this embodiment, the substrate 101 may include a glass substrate and a buffer layer stacked together, and the buffer layer is arranged close to the source layer. The buffer layer is composed of a film layer with heat insulation capability, for example, a single-layer film composed of any one of silicon oxide, silicon nitride, silicon oxynitride, etc., or a composite film composed of multiple compositions.

[0046] In this embodiment, the active layer may be low temperature polysilicon.

[0047] In this embodiment, the ions doped in the first doping portion 211 and the second doping portion 212 may be group V elements, such as nitrogen, phosphorus, and the like.

[0048] In this embodiment, the concentration of ions doped in the first doping portion 211 is greater than the concentration of ions doped in the second doping portion 212, that is, the first doping portion 211 is heavily doped and the second doping portion 212 is lightly doped. By arranging the second doping portion 212 on both sides of the communication portion, the hot carrier effect can be improved.

[0049] In this example, see Figure 2A and Figure 3A In the direction from the substrate 101 to the active layer, the thickness of the first doping portion 211 is greater than the thickness of the second doping portion 212. Through the above arrangement, the proportion of ions in the first doping portion 211 diffusing laterally to the second doping portion 212 during the high-temperature diffusion doping process can be reduced, thereby improving the degree of conductorization of the first doping portion 211 and preventing the ion concentration in the second doping portion 212 from being too high, thereby failing to effectively weaken the drain electric field and thereby failing to improve the consequences of the hot carrier effect.

[0050] The technical solution of the present application is now described in conjunction with specific embodiments.

[0051] In the array substrate of the present application, the array substrate further comprises a gate 300 disposed on the active layer; in the top view direction of the array substrate, refer to Figure 2B and Figure 3B The gate 300 covers the channel portion 220 , the gate 300 and the second doped portion 212 at least partially overlap, and the gate 300 and the first doped portion 211 are arranged non-overlappingly.

[0052] In this embodiment, the orthographic projection of the second doped portion 212 of the gate 300 on the substrate 101 may be at a critical contact position, that is, a boundary of the gate 300 close to the second doped portion 212 coincides with a boundary of the second doped portion 212 close to the gate 300 .

[0053] In this example, see Figure 2B and Figure 3B The gate 300 and the orthographic projection of the first doped portion 211 on the substrate 101 do not overlap, and the gate 300 and the orthographic projection of the second doped portion 212 on the substrate 101 partially overlap, and the gate 300 completely covers the channel portion 220. Through the above arrangement, the parasitic capacitance formed by the overlap of the gate 300 and the first doped portion 211 in the active portion 210 can be further reduced, thereby reducing the influence of the parasitic capacitance on the circuit.

[0054] In this embodiment, a gate insulating layer is further disposed between the gate 300 and the active layer.

[0055] In this embodiment, the gate 300 covers the channel portion 220, the gate 300 and the second doped portion 212 are at least partially overlapped, and the gate 300 and the first doped portion 211 are non-overlappingly arranged, thereby avoiding parasitic capacitance formed by the overlap of the gate 300 and the first doped portion 211, thereby reducing the influence of parasitic capacitance on the circuit.

[0056] In the array substrate of this application, please refer to Figure 2A and Figure 3A In the direction from the substrate 101 to the active layer, the thickness of the channel portion 220 is smaller than the thickness of the second doping portion 212 .

[0057] In this embodiment, by setting the thickness of the channel portion 220 to be smaller than the thickness of the second doped portion 212, the hot carrier effect can be further reduced, reducing the risk of hot carriers impacting the gate insulating layer, thereby increasing the life of the thin film transistor.

[0058] In the array substrate of the present application, in the direction from the substrate 101 to the active layer, the ion concentration of the second doping part 212 gradually decreases.

[0059] In this embodiment, the ion concentration of the second doping portion 212 changes in a gradient, and the ion concentration in the second doping portion 212 gradually decreases in a direction from the substrate 101 to the active layer.

[0060] Through the above arrangement, the present embodiment makes the ion concentration in the second doped portion 212 close to the gate 300 smaller, thereby better realizing the LDD structure, further weakening the drain region electric field, and improving the hot carrier effect.

[0061] In the array substrate of this application, please refer to Figure 3A and Figure 3B The second doping portion 212 is arranged around the first doping portion 211.

[0062] In this embodiment, the second doping portion 212 can be arranged around the first doping portion 211. Through the above arrangement, one photomask can be saved. Specifically, after the active doping portion 213 is formed, the first photoresist 411 is subjected to an ashing process to shrink the photoresist to form the second photoresist 412, and then an etching process is used to form a plurality of active doping portions 213 in a stepped shape. In this embodiment, the second photoresist 412 is formed by an ashing process, and there is no need to re-make a photomask to form the second photoresist 412, thereby saving production costs and simplifying the process.

[0063] In the array substrate of this application, please refer to FIG. 2A to FIG. 3BA step structure is provided between the first doping portion 211 and the second doping portion 212 , and a surface of the first doping portion 211 away from the substrate 101 is arranged in parallel with a surface of the second doping portion 212 away from the substrate 101 .

[0064] In this embodiment, an uneven step structure is arranged between the first doping portion 211 and the second doping portion 212 , and an upper surface of the step structure is arranged parallel to the surface of the substrate 101 .

[0065] Through the above arrangement, this embodiment can reduce the proportion of ions in the first doping portion 211 diffusing laterally to the second doping portion 212 during the high-temperature diffusion doping process, thereby improving the degree of conductivity of the first doping portion 211 and preventing the ion concentration in the second doping portion 212 from being too high. If the ion concentration in the second doping portion 212 is too high, the hot carrier effect cannot be effectively reduced.

[0066] In the array substrate of this application, please refer to Figure 2A and Figure 3A The array substrate also includes an inter-insulating layer 102 disposed on the gate 300 layer and a source-drain layer 400 disposed on the inter-insulating layer 102, the source-drain layer 400 includes a source 401 and a drain 402, and the source 401 and the drain 402 are electrically connected to the corresponding first doped portion 211 respectively.

[0067] The present application also provides a method for manufacturing an array substrate, comprising:

[0068] Providing a substrate 101;

[0069] See also Figure 4A and Figure 5A , forming a first active material layer 221 doped with ions on the substrate 101;

[0070] See also FIG. 4B to FIG. 4C , FIG. 5B to FIG. 5D , patterning the first active material layer 221 so that the active material layer forms a plurality of active doping portions 213 in a stepped shape, wherein the plurality of active doping portions 213 are separately arranged;

[0071] See also Figure 4D and Figure 5E , forming a second active material layer 222 on the plurality of active doping parts 213;

[0072] See also Figure 4E and Fig. 5F, performing a preset process on the second active material layer 222 and the plurality of active doping portions 213 to form an active portion 210 including a channel portion 220 and disposed on both sides of the channel portion 220;

[0073] The active portion 210 includes a first doping portion 211 and a second doping portion 212, the second doping portion 212 is located between the first doping portion 211 and the channel portion 220, and the second doping portion 212 is connected to the channel portion 220 and the first doping portion 211, and the ion concentration of the first doping portion 211 is greater than the ion concentration of the second doping portion 212;

[0074] In the direction from the substrate 101 to the active layer, the thickness of the first doping portion 211 is greater than the thickness of the second doping portion 212 .

[0075] In this embodiment, the ions doped in the first active material layer 221 may be group V elements, such as nitrogen, phosphorus, etc. For example, when phosphorus is doped in the first active material layer 221, the first active material layer containing doped ions may be formed by depositing a material including silane, phosphine and hydrogen. The thickness of the first active material layer 221 may be 400 angstroms to 1000 angstroms.

[0076] In this embodiment, the first active material layer 221 can be realized by using a process such as PECVD, which is not limited here.

[0077] In this embodiment, the substrate 101 includes a glass substrate and a buffer layer, and the buffer layer can be a single layer film or a composite film composed of any one of silicon oxide, silicon nitride, silicon oxynitride, etc. The deposition thickness of the buffer layer can be 1500 angstroms to 4000 angstroms.

[0078] In this embodiment, the first active material layer 221 may be an amorphous silicon layer.

[0079] In this embodiment, the second active material layer 222 may be an amorphous silicon layer.

[0080] In this embodiment, the patterning method of the first active material layer 221 is a conventional process in the art, including coating photoresist, mask exposure and development, etching, etc., which is not limited here.

[0081] In this embodiment, the process of forming the first active material layer 221 and the second active material layer 222 is a conventional process in the art, including a film forming process such as CVD, which is not limited here.

[0082] In this embodiment, the method for manufacturing the array substrate also includes etching the excess second active material layer 222 after the step of forming a channel portion 220 and an active portion 210 arranged on both sides of the channel portion 220, so as to remove the portion of the second active material layer 222 located outside the active portion 210 and the channel portion 220.

[0083] In this embodiment, the method for manufacturing the array substrate further includes forming an inter-insulating layer 102 on the gate 300 and a source-drain electrode layer 400 disposed on the inter-insulating layer 102, and making vias on the inter-insulating layer 102 to electrically connect the source-drain electrode layer 400 to the first doped portion 211. The process after forming the inter-insulating layer 102 is a conventional manufacturing process of a thin film transistor and is not limited here.

[0084] In the method for manufacturing the array substrate of the present application, the step of patterning the first active material layer 221 so as to form a plurality of stepped active doping portions 213 on the active material layer includes:

[0085] See also Figure 4B , a plurality of active doping parts 213 are formed by a first yellow light process and an etching process, see Figure 4C , performing a second yellow light process and an etching process on the active doping portion 213 to form a plurality of active doping portions 213 in a stepped shape; or, refer to Figure 5B , a plurality of active doping parts 213 are formed by a first yellow light process and an etching process, see Figure 5C , the first photoresist 411 in the yellow light process is degraded by an ashing process to form a second photoresist 412, see Figure 5D , a second etching process is used to form a plurality of active doping portions 213 in a stepped shape.

[0086] In this embodiment, the yellow light process, the etching process, and the ashing process are conventional processes in the art and are not limited here.

[0087] In this example, see FIG. 4B to FIG. 4C The first yellow light process uses the first photoresist 411, and the second yellow light process uses the second photoresist 412. The second photoresist 412 can be formed by a mask different from that used for the first photoresist 411, or by degrading the first photoresist 411 through an ashing process. FIG. 4B to FIG. 4C When the second photoresist 412 is formed using a mask different from that used for the first photoresist 411, the second doped portion 212 finally formed is located between the first doped portion 211 and the channel portion 220; see FIG. 5B to FIG. 5DWhen the second photoresist 412 is formed by an ashing process, the second doping portion 212 finally formed is arranged around the first doping portion 211. At this time, only the second doping portion 212 located between the first doping portion 211 and the channel portion 220 can achieve the LDD effect.

[0088] In this example, see Figure 4C , Figure 5C and Figure 5D When the active doping portion 213 is subjected to a second yellow light process and an etching process to form a plurality of active doping portions 213 in a stepped shape, the outer dimension of the positive projection of the second photoresist 412 on the substrate 101 is reduced by 1 micron to 3 microns on a single side inward relative to the first photoresist 411, and then a plurality of active doping portions 213 in a stepped shape are formed by performing exposure, development, etching and other processes using the second photoresist 412.

[0089] In this example, see Figure 5C and Figure 5D When the first photoresist 411 in the yellow light process is degraded by an ashing process, the size of the first photoresist 411 can be reduced inward by 1 micron to 3 microns, thereby forming a second photoresist 412, and then the second photoresist 412 is used to perform exposure, development, and etching processes to form a plurality of active doping portions 213 in a stepped shape. In the direction of the top view of the active doping portion 213, the middle thickness of the active doping portion 213 is greater than the edge thickness, and the portion with a smaller edge thickness is arranged around the portion with a larger middle thickness.

[0090] In this example, see Figure 4C and Figure 5D The active doping portion 213 is in a stepped shape, wherein the thickness of the region with a smaller thickness is 20% to 70% of the thickness of the region with a larger thickness.

[0091] In the method for manufacturing the array substrate of the present application, the step of performing a preset process on the second active material layer 222 and the plurality of active doping portions 213 to form an active portion 210 including a channel portion 220 and disposed on both sides of the channel portion 220 includes:

[0092] Laser annealing is performed on the second active material layer 222 and the plurality of active doping portions 213 to diffuse ions in the active doping portions 213 into the second active material layer 222 and to crystallize the active doping portions 213 and the second active material layer 222 to form an active portion 210 including a channel portion 220 and disposed on both sides of the channel portion 220 .

[0093] In this embodiment, the step before laser annealing the second active material layer 222 and the plurality of active doping parts 213 further includes annealing the second active layer to remove hydrogen, the annealing temperature range is 450 degrees Celsius to 600 degrees Celsius, and the annealing time is 0.5 to 2 hours. After the dehydrogenation process, the atomic percentage of hydrogen in the second active material layer 222 is less than 0.5%.

[0094] In this embodiment, the laser annealing process for the second active material layer 222 and the plurality of active doping parts 213 may be a BLA (Blue Laser Annealing) technology, and the scanning direction of the laser annealing is vertical channel scanning or parallel channel scanning. Through laser annealing, the second active layer material is crystallized, and at the same time, the doping ions in the first active material layer 221 diffuse under high temperature, that is, high-temperature diffusion doping is achieved. Please refer to Figure 4D , Figure 4E , Figure 5E and Fig. 5F Since the thicknesses of the multiple stepped active doping parts 213 are different, a first doping part 211 with a higher ion doping concentration is formed in a thicker area, and a second doping part 212 with a lower ion doping concentration is formed in a thinner area.

[0095] The present application also provides a display panel, which includes a panel body and the above-mentioned array substrate, and the panel body and the array substrate are combined into one.

[0096] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] The above is a detailed introduction to a display panel and a mobile terminal provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: The invention comprises a substrate and an active layer arranged on the substrate; wherein the active layer comprises: Channel Department; an active portion disposed on both sides of the channel portion, the active portion comprising a first doping portion and a second doping portion, the second doping portion being located between the first doping portion and the channel portion, and the second doping portion being connected to the channel portion and the first doping portion, and the ion concentration of the first doping portion being greater than the ion concentration of the second doping portion; Wherein, in the direction from the substrate to the active layer, the thickness of the first doped portion is greater than the thickness of the second doped portion, and the thickness of the channel portion is less than the thickness of the second doped portion.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes: A gate is disposed on the active layer; Wherein, in the top view direction of the array substrate, the gate covers the channel portion, the gate and the second doping portion at least partially overlap, and the gate and the first doping portion are arranged non-overlappingly.

3. The array substrate according to claim 1, characterized in that: In a direction from the substrate to the active layer, the ion concentration of the second doping part gradually decreases.

4. The array substrate according to claim 1, characterized in that: The second doping portion is arranged around the first doping portion.

5. The array substrate according to claim 1, characterized in that: A step structure is provided between the first doping portion and the second doping portion, and a surface of the first doping portion away from the substrate is arranged in parallel with a surface of the second doping portion away from the substrate.

6. A method for manufacturing an array substrate, characterized in that: include: providing a substrate; forming a first active material layer doped with ions on the substrate; Performing patterning on the first active material layer so that the active material layer forms a plurality of active doping portions in a stepped shape, wherein the plurality of active doping portions are separately arranged; forming a second active material layer on the plurality of active doping portions; Performing a preset process on the second active material layer and the plurality of active doping portions to form an active portion including a channel portion and active portions disposed on both sides of the channel portion; The active portion includes a first doping portion and a second doping portion, the second doping portion is located between the first doping portion and the channel portion, and the second doping portion is connected to the channel portion and the first doping portion, and the ion concentration of the first doping portion is greater than the ion concentration of the second doping portion; Wherein, in a direction from the substrate to the active portion, a thickness dimension of the first doped portion is greater than a thickness dimension of the second doped portion, and a thickness dimension of the channel portion is smaller than a thickness dimension of the second doped portion.

7. The method for manufacturing an array substrate according to claim 6, characterized in that: The step of patterning the first active material layer to form a plurality of stepped active doping portions on the active material layer comprises: A first yellow light process and an etching process are used to form a plurality of the active doping parts, and a second yellow light process and an etching process are performed on the active doping parts to form a plurality of the active doping parts in a stepped shape; or, a first yellow light process and an etching process are used to form a plurality of the active doping parts, an ashing process is used to degrade the first photoresist in the yellow light process, and a second etching process is used to form a plurality of the active doping parts in a stepped shape.

8. The method for manufacturing an array substrate according to claim 6, characterized in that: The step of performing a preset process on the second active material layer and the plurality of active doping portions to form a channel portion and an active portion disposed on both sides of the channel portion comprises: Laser annealing is performed on the second active material layer and the plurality of active doping parts to diffuse ions in the active doping parts into the second active material layer, and to crystallize the active doping parts and the second active material layer to form the channel part and the active part disposed on both sides of the channel part.

9. A display panel, characterized in that: The display panel comprises a panel body and the array substrate according to any one of claims 1 to 5, wherein the panel body and the array substrate are combined into one body.

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