Increase the LUT splitting degree of the FPGA 4-LUT using existing adder circuitry.

Abstract

This invention relates to a field-programmable gate array (FPGA) having a 4-LUT (lookup table) with four stages of multiplexing. The 4-LUT is splittable. A splittable 4-LUT includes the ability to implement multiple LUTs in an FPGA-programmed application as functions within a group including adder functions and other functions. The outputs of the 4-LUT are exposed to programmable connections according to FPGA programming. The outputs of the 4-LUT include the output of a first multiplexer in the third stage of the 4-LUT, the output of a multiplexer in the second stage, and the output of a multiplexer in either the second or third stage.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 144,879, filed February 2, 2021, entitled “Adding LUT FRACTURABILIY TO FPGA 4-LUTS USING EXISTING ADDERCIRCUITRY”, which is incorporated herein by reference. Technical Field

[0003] The technical field of this disclosure is broadly related to field-programmable gate arrays (FPGAs), and more specifically, to FPGAs having splittable components. Background Technology

[0004] Modern FPGAs based on 6-LUTs typically include "fracturability," which allows a LUT to be used as two or more LUTs with fewer inputs. For example, a 5-LUT can be used as two 4-LUTs, provided all inputs are identical. It's important to note that additional outputs must be routed from the 5th stage of the 6-LUT, adding extra load and slowing down the LUT. This fracturability is common in 6-LUT architectures because circuits typically do not synthesize many 6-input functions. Often, synthesis establishes many functions that will be implemented using fewer LUTs. For this reason, increasing the fracturability of the 6-LUT architecture significantly improves area efficiency.

[0005] Typically, 4-LUT FPGA architectures do not have splitting capability. The cost of using a 4-LUT with 2 or 3 input functions is not as prohibitively high as the cost of using a 6-LUT. It may not be worthwhile to slow down the third stage of a 4-LUT to implement 3-3 splitting capability.

[0006] Another common approach to splitting a 4-LUT is to implement an adder. Adders are sometimes implemented on an FPGA using a 4-LUT to implement propagate, generate, and sum functions. Essentially, this splits the 4-LUT into two 2-input and one 3-input function. The propagate is a function of A and B, the generate function is also a function of A and B, and the sum function is A, B, and C. in The function. Summary of the Invention

[0007] The embodiments described herein include field-programmable gate arrays (FPGAs), lookup tables (LUTs), splittable components, splittable LUTs, splittable 4-LUTs, adder circuits, computer-aided design (CAD) tools and systems, various devices and related methods.

[0008] One embodiment is a field-programmable gate array (FPGA) including a 4-LUT. The 4-LUT has first, second, third, and fourth stages of multiplexers. The 4-LUT is splittable to implement multiple LUTs in FPGA-programmed applications as functions within a group including adder functions and other functions. The outputs of the 4-LUT are exposed to connections and general routing programmable according to FPGA programming. These outputs include the output of the first multiplexer in the third stage, the output of the first multiplexer in the second stage, and the output of the multiplexer in the second or third stage.

[0009] One embodiment is a method of operating a field-programmable gate array (FPGA). The method includes splitting a 4-LUT having first, second, third, and fourth stages of multiplexers to implement multiple LUTs, each having fewer than four stages of multiplexers. Splitting and implementing multiple LUTs is for functions in a group including adder functions and other functions. The method includes programming connections of at least two of the multiple outputs of the 4-LUTs to further implement multiple LUTs based on the 4-LUTs in FPGA programming applications. The multiple outputs of the 4-LUTs used for programming connections include: the output of the first multiplexer in the third stage of the 4-LUT, the output of the first multiplexer in the second stage of the 4-LUT, and the output of a multiplexer in the second or third stage of the 4-LUT.

[0010] One embodiment is a tangible, non-transitory computer-readable medium having instructions. When executed by a processor, the instructions cause the processor to perform a method. The method includes splitting a 4-LUT having first, second, third, and fourth stages of multiplexing to implement multiple LUTs, each having fewer than four stages of multiplexing. Splitting and implementing the multiple LUTs are for functions in a group including adder functions and other functions. The 4-LUT is splittable and is located in a field-programmable gate array (FPGA). The method includes programming connections of at least two of the multiple outputs of the 4-LUT to further implement multiple LUTs according to the 4-LUT in an FPGA-programmed application. The multiple outputs of the 4-LUT include: the output of the first multiplexer in the third stage of the 4-LUT, the output of the first multiplexer in the second stage of the 4-LUT, and the output of the multiplexer in the second or third stage of the 4-LUT. Attached Figure Description

[0011] The embodiments described herein can be more fully understood through the detailed descriptions given below and the accompanying drawings of various embodiments according to the invention. However, this should not be construed as limiting the invention to the specific embodiments, but is only for explanation and understanding.

[0012] Figure 1 This illustrates a typical use of a 4-LUT to implement a full adder.

[0013] Figure 2 This demonstrates how to implement arbitrary 2-input and arbitrary 3-input functions that share 2 inputs by reusing the splitness of a 4-LUT adder.

[0014] Figure 3 This demonstrates how to implement two arbitrary 2-input and one arbitrary 3-input functions with two shared inputs by reusing the splitness of the 4-LUT adder.

[0015] Figure 4 This demonstrates the implementation of 3 / 3 divisibility using the bottom of the third level of a LUT.

[0016] Figure 5 Other embodiments of implementing a full adder using a 4-LUT are shown.

[0017] Figure 6 A CAD system for programming an FPGA with a splittable LUT is shown.

[0018] Figure 7 This is a flowchart of the operation method of an FPGA with a splittable LUT. Detailed Implementation

[0019] In the following description, numerous details are set forth to provide a more thorough explanation of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without these specific details. In other instances, well-known structures and apparatuses are shown in block diagram form rather than in detail to avoid obscuring the invention.

[0020] Regarding terminology, the terms "multiplexer," "multiplexer," and "multiplexer" are used interchangeably herein to describe circuitry that selects from multiplexer inputs to drive the multiplexer output. A LUT (Look-Up Table), as a component in an FPGA, can be described based on the multiplexer's level (i.e., grade or layer) and the multiplexing within the LUT; for example, a 4-LUT is a look-up table with four multiplexer levels. The splittability of a LUT can be described using commas, forward slashes, or hyphens as separators in the naming convention, based on one or more LUTs implemented using splittable LUTs. Each stage of the multiplexer is operated by a selector or selection input, and the splittability of a LUT can be described based on the levels of multiple LUTs implemented through the LUT's splittability, the function of the selection input, or other aspects. For example, 2 / 3 splittability represents the ability to implement 2-LUTs and 3-LUTs, and it can also be called "3 / 2 splittability", "2-3 splittability", "3-2 splittability", "3,2 splittability" or "2,3 splittability".

[0021] One embodiment described herein is a method for reusing adder circuitry in a 4-LUT to implement splittability, allowing one or two 2-input functions and one 3-input function to be implemented without additional LUT circuitry. Various implementations of individual LUTs using the splittability of a 4-LUT are described herein. The embodiments described herein include novel reuse of adder-specific 4-LUT splittability to implement any two 2-input and 3-input functions with two shared inputs. In some embodiments, the adder is implemented at the latency penalty of the additional load of the second and third stages of the LUT, so there is no additional cost in using that load to implement 2 / 3 splittability. In various embodiments, different functions are implemented through different programming of the programmable connections, such as adder functions for implementing adders from LUTs with adders from the splittable LUT and other functions for implementing other LUTs from the same splittable LUT. In other words, the splittable LUT has circuitry and programmable connections that support the implementation of multiple LUTs and multiple functions in an FPGA programming application. With different programming using programmable connections, different functions can be implemented for different FPGA programming applications.

[0022] Figure 1 The 4-LUT 102 is shown, which is split into one 3-input and two 2-input functions to implement these three functions (pass or carry pass, generate or carry generate, and sum) in a full adder. (See reference...) Figure 1 Because of passing (two-input functions of A and B), generating (different two-input functions of A and B), and summing (A, B, and C) inSince the 3-input function (or carry-in) shares two inputs (A and B), the only modification required to implement a full adder in the 4-LUT 102 is to tap the second stage of the lower half of the LUT and the third stage of the upper half. Then, the transmitted and generated signals are connected to C. in The carry input, along with the input to the hardened mux 134, is used to complete the C function of the full adder. out Or carry-out output.

[0023] like Figure 1 As shown, an embodiment of the 4-LUT 102 with divisibility for implementing a full adder has four stages of multiplexers 104, 106, 108, and 110. Each stage of the multiplexer has selection inputs 118, 120, and 122 (the selection inputs of the individual multiplexers in the fourth stage 110 are not shown in the figure and are, for example, related to a known state or implemented as unrelated but not additionally used for implementing a full adder). When programmed according to FPGA programming to implement a full adder, 4-LUT 102 is split into 3-LUT, 2-LUT, and another 2-LUT to operate. The 3-LUT produces a sum as the output 124 of multiplexer 112 in stage 3 108, the 2-LUT produces a generate or carry generate as the output 126 of multiplexer 114 in stage 2 106, and the other 2-LUT produces a propagate or carry pass as the output 128 of another multiplexer 116 in stage 2 106. To further implement the full adder, FPGA programming programs the output of 4-LUT 102 to connect the sum, which is the output 124 of multiplexer 112 in stage 3 108, to a common route. FPGA programming programs the output of 4-LUT 102 to connect the generation or carry generation of the intermediate signal as an adder and the output 126 of multiplexer 114 in second stage 106 to multiplexer 134 located outside LUT 102 but inside the FPGA. FPGA programming also programs the output of 4-LUT 102 to connect the pass or carry pass of another intermediate signal as an adder and the output 128 of multiplexer 116 in second stage 106 to multiplexer 134. FPGA programming also programs the C input 130 of external multiplexer 134. in Or program the carry input, and program the C of the output 132 of the external multiplexer 134. out Alternatively, it can be programmed using carry-out output.

[0024] Figure 2 An example of implementing two arbitrary functions is shown. Figure 1Same LUT level. Instead of performing a summation (which is A, B, and C), perform a summation. in The function (of which) can be split into two LUTs, each implementing an arbitrary function 204 of A, B, and C, is described as F(A,B,C). Only one of the two bottom 2-LUT levels is used to implement the other function 208G(A,B).

[0025] The embodiment of 4-LUT 102 has the following characteristics: Figure 1 The divisibility shown in this paper implements a full adder with 2 / 3 divisibility to implement a 2-LUT for a 2-input function 208 (e.g., G(A,B)) having the output 128 of multiplexer 116 in the second stage 106; and a 3-LUT for a 3-input function 204 (e.g., F(A,B,C)) having the output 124 of multiplexer 112 in the third stage 108. These two functions 204, 208 share inputs A and B, but are otherwise independent because they use different, non-overlapping groups 202, 206 of multiplexer 102 for the 4-LUT 102. It should be understood that the generalized 2 / 3 divisibility includes the ability to implement adder functions (see [link to documentation]). Figure 1 ) and the ability to implement other functions (see Figure 2 ).

[0026] Figure 3 The complete divisibility of an adder for implementing a 3-input and two 2-input functions (as long as they share two inputs) is shown according to one embodiment. Note that in one embodiment, all three outputs are routed outside the LUT in this case.

[0027] The embodiment of 4-LUT 102 has the following characteristics: Figure 1 The divisibility of the implementation of the full adder shown herein includes, and uses 2 / 2 / 3 divisibility to implement a 2-LUT for a 2-input function 208 (e.g., G(A,B)), having the output 128 of multiplexer 116 in the second stage 106; another 2-LUT for a 2-input function 308 (e.g., H(A,B)), having the output 310 of another multiplexer 114 in the second stage 106; and a 3-LUT for a 3-input function 204 (e.g., F(A,B,C)), having the output 124 of multiplexer 112 in the third stage 108. These three functions 204, 208, and 308 share inputs A and B, but are otherwise independent because they use different, non-overlapping groups 302, 304, and 306 of multiplexers in the 4-LUT 102. It should be understood that the generalized 2 / 2 / 3 splittability includes the ability to implement adder functions (see [link]). Figure 1 ) and the ability to implement other functions (see Figure 3 ).

[0028] Figure 4 This demonstrates routing the lower half of the third stage of the LUT to implement two 3-input functions. This reuses some of the splittability necessary to implement the adder, but also requires adding some load.

[0029] The embodiment of 4-LUT 102 has the following characteristics: Figure 1 The divisibility of the full adder shown herein is used to implement a 3-LUT for a 3-input function 406 (e.g., G(A,B,C)) with output 408 of multiplexer 410 in third stage 108, and a 3-LUT for a 3-input function 204 (e.g., F(A,B,C)) with output 124 of another multiplexer 112 in third stage 108. These two functions 204 and 406 share inputs A, B, and C, but are otherwise independent because they use different, non-overlapping groups 402 and 404 of multiplexers in 4-LUT 102.

[0030] Figure 5 Another embodiment of implementing a full adder using a 4-LUT is shown. In this embodiment, the pass or carry pass is generated in the third stage 108 of the 4-LUT 102, rather than in... Figure 1 This is generated in the second stage 106 shown. By making the outputs 124, 408 of the multiplexers 112, 410 in the third stage 108 available for programmable connections to a general route in the FPGA, this embodiment directly supports, for example... Figure 4 The 3 / 3 splittability of the 4-LUT shown.

[0031] Continue to refer to Figure 5 The 4-LUT 102 is split into one 3-input and two 2-input functions to implement these three functions (pass or carry pass, generate or carry generate, and sum) in the full adder. When programmed according to the FPGA programming for implementing the full adder, the 4-LUT 102 is split into a 3-LUT, a 2-LUT, and another 2-LUT to operate. The 3-LUT produces a sum as the output 124 of multiplexer 112 in stage 3 108, the 2-LUT produces a generate or carry generate as the output 126 of multiplexer 114 in stage 2 106, and the other 2-LUT produces a pass or carry pass as the output 408 of another multiplexer 410 in stage 3 108. Typically, the carry pass is a 2-input function, i.e., a function of inputs A and B, and utilizes... Figure 1 The output 128 of the multiplexer 116 in the second stage 106 of LUT 102 is used for implementation. Here, in Figure 5In this context, using the same multiplexer group 206 within the larger group 508, carry passing utilizes the output of multiplexer 410 in the third stage 108 of the multiplexer, along with the function-independent carry input or C. in To further implement the full adder, the FPGA programming program the output of the 4-LUT 102 to connect the summation, which is the output 124 of the multiplexer 112 in the third stage 108, to a general route; to connect the generation or carry generation, which is the intermediate signal of the adder and the output 126 of the multiplexer 114 in the second stage 106, to a multiplexer 134 located outside the LUT 102 but inside the FPGA; and to connect the pass or carry pass, which is another intermediate signal of the adder and the output 408 of the multiplexer 410 in the third stage 108, to the multiplexer 134. The FPGA programming program the C input 132 of the external multiplexer 134. in Or program the carry input, and program the C of the output 132 of the external multiplexer 134. out Or programmable with carry output. Although the functions used for summation, generation or carry generation, and pass or carry pass share inputs A and B, they are otherwise independent because they are generated by different groups 202, 506, and 508 of the splittable 4-LUT 102 multiplexer. This, in turn, supports other degrees of splittability (see...). Figure 5 ).

[0032] Figure 6 A CAD system 606 is illustrated for programming an FPGA having a splittable LUT 604. A user 612 interacts with the CAD system 606, which has a processor 610 running, for example, a CAD tool 608 implemented in computer programming. The CAD tool 608 and the CAD system 606 are used to program the FPGA 602, which includes actions of splitting the splittable LUT 604 614 and programming the programmable connections 616 of the splittable LUT 604 and the remainder of the FPGA circuitry. In various embodiments, the FPGA may have one or more splittable LUTs as well as other programmable circuitry and general routing, and the embodiments and variations of the LUTs described herein are applicable to embodiments for programming the FPGA.

[0033] Figure 7 This is a flowchart illustrating the operation method of an FPGA 602 with a splittable LUT 604. This method can be referenced above. Figure 6 The CAD tool 608 and CAD system 606 described above are referenced. Figures 1 to 5The described splittable LUT or a variant thereof is executed. The method can be executed on an FPGA via a processor. The method can be implemented as instructions for a processor, located in a tangible, non-transitory computer-readable medium.

[0034] In action 702, the 4-LUT is split to define multiple LUTs. In various embodiments, this is part of defining the overall functionality of the programmable FPGA. Splitting defines one or more LUTs among the possible splittable LUTs for a specific implementation and application of FPGA programming. In FPGA programming applications, a single LUT or multiple LUTs can be defined based on the splittable LUTs.

[0035] In action 704, the connections of the 4-LUT outputs are programmed. For example, the outputs of the splittable 4-LUT are exposed for programmable connections to a general route, and thus to other circuitry within the FPGA. Utilizing the splittable nature of the 4-LUT, multiple LUTs are defined in action 702, and the connections of the 4-LUT outputs are programmed in action 704.

[0036] It should be understood that a specific set of LUTs and a specific set of programming connections are configured for a specific splittable LUT in a specific application of FPGA programming, and another FPGA programming application can produce a different set of LUTs and a different set of programming connections. Different embodiments of the LUT can have different LUTs that can be implemented, different outputs exposed for programmable connections, and different degrees of splittability. By using "irrelevant" as one of the inputs to the function being implemented, a LUT with fewer feature levels can be implemented from a LUT with more feature levels. For example, a 2 / 3 splittable LUT (see...) Figure 2 ), 2 / 2 / 3 splittable LUTs (see) Figure 3 ) or 3 / 3 splittable LUT (see Figure 4 It also has 2 / 2 splittability to implement two 2-input LUTs by using the "irrelevant" principle above. This principle applies to... Figure 5 The adder implementation in the example is, and vice versa.

[0037] Some of the parts described in detail above are presented in terms of algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Furthermore, the algorithms described here are generally considered to be a self-consistent sequence of steps that produce the desired result. These steps are those that require physical manipulation of physical quantities. Although not necessary, these quantities are often in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has been found that, conveniently, and primarily for common use, these signals are sometimes referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0038] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels for those quantities. Unless otherwise explicitly stated, it will be apparent from the following discussion that, throughout this specification, discussions using terms such as “processing” or “operation” or “calculation” or “determining” or “displaying” refer to the operation and processing of a computer system or similar electronic computing device, which manipulates data represented as physical (electronic) quantities in the registers and memories of the computer system and converts it into other data represented as physical quantities in the computer system’s memory or registers or other such information storage, transmission, or display devices.

[0039] This specification also relates to a device for performing the operations described herein. Such a device may be specifically constructed for the desired purpose, or it may comprise a general-purpose computer that can be selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, and each is connected to a computer system bus.

[0040] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the required method steps. The necessary structures for various such systems will become apparent from the description. Furthermore, this invention is described without reference to any particular programming language. It should be understood that the teachings of this invention as described herein can be implemented using various programming languages.

[0041] Machine-readable media include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media include: read-only memory (“ROM”); random access memory (“RAM”); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of signal transmission (e.g., carrier waves, infrared signals, digital signals, etc.); and so on.

[0042] While many changes and modifications to the invention will undoubtedly become apparent to those skilled in the art upon reading the above description, it should be understood that any particular embodiment shown and described by way of illustration is by no means intended to be limiting. Therefore, reference to details of the various embodiments is not intended to limit the scope of the claims, which themselves only enumerate those features deemed essential to the invention.

Claims

1. A field-programmable gate array, i.e., an FPGA, comprising: 4-Lookup Table, or 4-LUT, includes the first, second, third, and fourth stages of the multiplexer; The 4-LUT is divisible to allow for the implementation of multiple LUTs in FPGA programming applications, serving as functions within a group that includes adder functions and other functions; and The outputs of the 4-LUT are exposed to programmable connections programmed according to the FPGA, including the outputs of the first multiplexer in the third stage, the first multiplexer in the second stage, and the multiplexers in the second or third stage. The 4-LUT has a splittability including circuitry and programmable connections to implement a full adder. The full adder has the adder function and has a 2 / 3 splittability, which is the ability to implement 2-LUTs and 3-LUTs, having other functions using the same circuitry and programmable connections. The 4-LUT is splittable to implement a full adder using the 4-LUT and an external multiplexer located outside the 4-LUT and inside the FPGA. The 4-LUT has selection inputs, including a first operand input to the first stage of the multiplexer, a second operand input to the second stage of the multiplexer, and a carry input to the third stage of the multiplexer. The output of the full adder includes the summation of the output of the first multiplexer in the third stage and the carry output of the output of the external multiplexer, the input of which includes a carry input and a carry generation, and the selection input of which includes a carry pass.

2. The FPGA according to claim 1, in, The full adder has an intermediate signal line that includes a generated carry from the output of a first multiplexer in the second stage and a passed carry from the output of a second multiplexer in the second stage, which serves as the output of a multiplexer in the second or third stage.

3. The FPGA according to claim 1, in, The full adder has an intermediate signal line that includes a generated carry from the output of a first multiplexer in the second stage and a passed carry from the output of a second multiplexer in the third stage, which serves as the output of the multiplexer in the second or third stage.

4. The FPGA according to claim 1, wherein: The 4-LUT has a 2 / 3 splitting degree to implement a 2-LUT for a 2-input function and a 3-LUT for a 3-input function, the 2-LUT having the output of the first multiplexer in the second stage, and the 3-LUT having the output of the first multiplexer in the third stage.

5. The FPGA according to claim 1, wherein: The 4-LUT has a 2 / 3 splitting degree to implement a 2-LUT for a 2-input function and a 3-LUT for a 3-input function, the 2-LUT having the output of a second multiplexer in the second stage as the output of a multiplexer in the second stage or the third stage, and the 3-LUT having the output of a first multiplexer in the third stage.

6. The FPGA according to claim 1, wherein: The 4-LUT has a 3 / 3 splitting degree to implement a 3-LUT for a 3-input function and another 3-LUT for another 3-input function, the 3-LUT having the output of the first multiplexer in the third stage, and the other 3-LUT having the output of the second multiplexer in the third stage as the output of the multiplexer in the second stage or the third stage.

7. The FPGA according to claim 1, wherein: The 4-LUT has 2 / 2 / 3 splitting degree to implement a 2-LUT for a 2-input function, another 2-LUT for another 2-input function, and a 3-LUT for a 3-input function. The 2-LUT has the output of a first multiplexer in the second stage, the other 2-LUT has the output of a second multiplexer in the second stage as the output of a multiplexer in the second stage or the third stage, and the 3-LUT has the output of a first multiplexer in the third stage.

8. The FPGA according to claim 1, wherein: The 4-LUT has a 2 / 2 splittability to implement a 2-LUT for a 2-input function and another 2-LUT for a 3-input function by making one of the three inputs independent. The 2-LUT has the output of the first multiplexer in the second stage, and the other 2-LUT has the output of the first multiplexer in the third stage.

9. A method for operating a field-programmable gate array (FPGA), comprising: For functions in a group including adder functions and other functions, a 4-LUT with first, second, third, and fourth stages of multiplexing is split to implement multiple LUTs, each of which has fewer than four stages of multiplexing; and The connections of at least two of the multiple outputs of the 4-LUT are programmed to further implement the multiple LUTs according to the 4-LUT in FPGA programming applications, wherein the multiple outputs of the 4-LUT include the output of the first multiplexer in the third stage of the 4-LUT, the output of the first multiplexer in the second stage of the 4-LUT, and the output of the multiplexer in the second or third stage of the 4-LUT. The 4-LUT has a splittability including circuitry and programmable connections to implement a full adder. The full adder has the adder function and has a 2 / 3 splittability, which is the ability to implement 2-LUTs and 3-LUTs, having other functions using the same circuitry and programmable connections. The programming of the connection of at least two outputs of the 4-LUT includes: A full adder is implemented using a 4-LUT and an external multiplexer located outside the 4-LUT and inside the FPGA. The 4-LUT has selection inputs, which include a first operand input to a first stage of the multiplexer, a second operand input to a second stage of the multiplexer, and a carry input to a third stage of the multiplexer. The output of the full adder includes the summation of the output of the first multiplexer in the third stage and the carry output of the output of the external multiplexer, wherein the input of the external multiplexer includes a carry input and a carry generation input, and the selection input of the external multiplexer includes a carry transfer input.

10. The operating method according to claim 9, The programming of the connection of at least two outputs of the 4-LUT further includes: The full adder has an intermediate signal line that includes a generated carry from the output of a first multiplexer in the second stage and a passed carry from the output of a second multiplexer in the second stage, which serves as the output of a multiplexer in the second or third stage.

11. The method of claim 9, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT comprises: The 4-LUT is implemented using 2 / 3 of its splittability to create a 2-LUT for a 2-input function and a 3-LUT for a 3-input function, the 2-LUT having the output of the first multiplexer in the second stage and the 3-LUT having the output of the first multiplexer in the third stage.

12. The method of claim 9, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT comprises: The 3 / 3 splittability of the 4-LUT is used to implement a 3-LUT for a 3-input function and another 3-LUT for another 3-input function, the 3-LUT having the output of the first multiplexer in the third stage, and the other 3-LUT having the output of the second multiplexer in the third stage as the output of the multiplexer in the second stage or the third stage.

13. The method of claim 9, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT comprises: The 4-LUT is implemented using a 2 / 2 / 3 splittability to create a 2-LUT for a 2-input function, another 2-LUT for another 2-input function, and a 3-LUT for a 3-input function. The 2-LUT has the output of a first multiplexer in the second stage, the other 2-LUT has the output of a second multiplexer in the second stage as the output of a multiplexer in the second or third stage, and the 3-LUT has the output of a first multiplexer in the third stage.

14. The method of claim 9, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT comprises: The 4-LUT is splittable by 2 / 2 to implement a 2-LUT for a 2-input function and another 2-LUT for a 3-input function by making one of the three inputs independent. The 2-LUT has the output of the first multiplexer in the second stage, and the other 2-LUT has the output of the first multiplexer in the third stage.

15. A tangible, non-transitory computer-readable medium having instructions thereon that, when executed by a processor, cause the processor to perform a method, the method comprising: For functions in a group including adder functions and other functions, a 4-LUT with first, second, third, and fourth stages of multiplexing is split to implement multiple LUTs, each of which has fewer than four stages of multiplexing. The 4-LUTs are splittable and located in a Field-Programmable Gate Array (FPGA). The connection of at least two of the multiple outputs of the 4-LUT is programmed to further implement the multiple LUTs according to the 4-LUT in FPGA programming applications, wherein the multiple outputs of the 4-LUT include the output of the first multiplexer in the third stage of the 4-LUT, the output of the first multiplexer in the second stage of the 4-LUT, and the output of the multiplexer in the second or third stage of the 4-LUT. The 4-LUT has a splittability that includes circuitry and programmable connections to implement a full adder, the full adder having the adder function and having a 2 / 3 splittability, which is the ability to implement 2-LUTs and 3-LUTs with other functions using the same circuitry and the same programmable connections.

16. The computer-readable medium according to claim 15, The programming of the connection of at least two outputs of the 4-LUT further includes: The full adder has an intermediate signal line that includes a generated carry from the output of a first multiplexer in the second stage and a passed carry from the output of a second multiplexer in the second stage, which serves as the output of a multiplexer in the second or third stage.

17. The computer-readable medium of claim 15, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT comprises: The 4-LUT is implemented using 2 / 3 of its splittability to create a 2-LUT for a 2-input function and a 3-LUT for a 3-input function, the 2-LUT having the output of the first multiplexer in the second stage and the 3-LUT having the output of the first multiplexer in the third stage.

18. The computer-readable medium of claim 15, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT to a common route comprises: The 3 / 3 splittability of the 4-LUT is used to implement a 3-LUT for a 3-input function and another 3-LUT for another 3-input function, the 3-LUT having the output of the first multiplexer in the third stage, and the other 3-LUT having the output of the second multiplexer in the third stage as the output of the multiplexer in the second stage or the third stage.

19. The computer-readable medium of claim 15, wherein programming the connection of at least two of the plurality of outputs of the 4-LUT to a common route comprises: The 4-LUT is implemented using a 2 / 2 / 3 splittability to create a 2-LUT for a 2-input function, another 2-LUT for another 2-input function, and a 3-LUT for a 3-input function. The 2-LUT has the output of a first multiplexer in the second stage, the other 2-LUT has the output of a second multiplexer in the second stage as the output of a multiplexer in the second or third stage, and the 3-LUT has the output of a first multiplexer in the third stage.

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